java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 20:01:58,403 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 20:01:58,431 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 20:01:58,445 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 20:01:58,445 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 20:01:58,446 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 20:01:58,447 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 20:01:58,449 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 20:01:58,451 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 20:01:58,452 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 20:01:58,453 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 20:01:58,453 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 20:01:58,453 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 20:01:58,455 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 20:01:58,456 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 20:01:58,458 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 20:01:58,460 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 20:01:58,462 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 20:01:58,464 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 20:01:58,465 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 20:01:58,467 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 20:01:58,467 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 20:01:58,468 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 20:01:58,469 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 20:01:58,469 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 20:01:58,471 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 20:01:58,471 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 20:01:58,471 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 20:01:58,472 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 20:01:58,472 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 20:01:58,472 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 20:01:58,473 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf [2018-01-24 20:01:58,483 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 20:01:58,483 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 20:01:58,484 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 20:01:58,484 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 20:01:58,484 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 20:01:58,484 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 20:01:58,485 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 20:01:58,485 INFO L133 SettingsManager]: * Precise comparison operator=true [2018-01-24 20:01:58,485 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 20:01:58,486 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 20:01:58,486 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 20:01:58,486 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 20:01:58,486 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 20:01:58,486 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 20:01:58,487 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 20:01:58,487 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 20:01:58,487 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 20:01:58,487 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 20:01:58,487 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 20:01:58,487 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 20:01:58,488 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 20:01:58,488 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 20:01:58,488 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 20:01:58,488 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 20:01:58,488 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 20:01:58,489 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:01:58,489 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 20:01:58,489 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 20:01:58,489 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 20:01:58,489 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 20:01:58,490 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 20:01:58,490 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 20:01:58,490 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 20:01:58,490 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 20:01:58,490 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 20:01:58,491 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 20:01:58,491 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 20:01:58,525 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 20:01:58,538 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 20:01:58,542 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 20:01:58,544 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 20:01:58,544 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 20:01:58,545 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i [2018-01-24 20:01:58,674 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 20:01:58,680 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 20:01:58,681 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 20:01:58,681 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 20:01:58,689 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 20:01:58,690 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,693 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29a4c9af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58, skipping insertion in model container [2018-01-24 20:01:58,693 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,711 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:01:58,725 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:01:58,829 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:01:58,840 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:01:58,844 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58 WrapperNode [2018-01-24 20:01:58,844 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 20:01:58,845 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 20:01:58,845 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 20:01:58,845 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 20:01:58,855 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,856 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,862 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,862 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,863 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,866 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,867 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... [2018-01-24 20:01:58,868 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 20:01:58,868 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 20:01:58,868 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 20:01:58,868 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 20:01:58,869 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:01:58,912 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 20:01:58,912 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 20:01:58,912 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 20:01:58,912 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 20:01:58,913 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 20:01:58,913 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 20:01:58,913 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 20:01:58,913 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 20:01:58,913 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 20:01:59,029 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 20:01:59,030 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:01:59 BoogieIcfgContainer [2018-01-24 20:01:59,030 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 20:01:59,031 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 20:01:59,031 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 20:01:59,032 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 20:01:59,033 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 08:01:58" (1/3) ... [2018-01-24 20:01:59,033 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5431e13c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:01:59, skipping insertion in model container [2018-01-24 20:01:59,034 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:01:58" (2/3) ... [2018-01-24 20:01:59,034 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5431e13c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:01:59, skipping insertion in model container [2018-01-24 20:01:59,034 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:01:59" (3/3) ... [2018-01-24 20:01:59,035 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_false-valid-deref_ground.i [2018-01-24 20:01:59,043 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 20:01:59,050 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 5 error locations. [2018-01-24 20:01:59,093 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 20:01:59,094 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 20:01:59,094 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 20:01:59,094 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 20:01:59,094 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 20:01:59,094 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 20:01:59,095 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 20:01:59,095 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 20:01:59,096 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 20:01:59,117 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-01-24 20:01:59,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 20:01:59,124 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:59,125 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:59,125 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:59,132 INFO L82 PathProgramCache]: Analyzing trace with hash -42218404, now seen corresponding path program 1 times [2018-01-24 20:01:59,134 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:59,188 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:59,188 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:59,188 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:59,189 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:59,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:59,235 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:59,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:59,323 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:01:59,323 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 20:01:59,323 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:01:59,325 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 20:01:59,336 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 20:01:59,336 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 20:01:59,338 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 3 states. [2018-01-24 20:01:59,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:01:59,394 INFO L93 Difference]: Finished difference Result 71 states and 84 transitions. [2018-01-24 20:01:59,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 20:01:59,396 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 20:01:59,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:01:59,404 INFO L225 Difference]: With dead ends: 71 [2018-01-24 20:01:59,404 INFO L226 Difference]: Without dead ends: 40 [2018-01-24 20:01:59,409 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 20:01:59,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-01-24 20:01:59,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 31. [2018-01-24 20:01:59,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 20:01:59,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2018-01-24 20:01:59,503 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 33 transitions. Word has length 7 [2018-01-24 20:01:59,503 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:01:59,503 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 33 transitions. [2018-01-24 20:01:59,503 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 20:01:59,503 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 33 transitions. [2018-01-24 20:01:59,504 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 20:01:59,504 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:01:59,504 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:01:59,504 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:01:59,504 INFO L82 PathProgramCache]: Analyzing trace with hash -207595369, now seen corresponding path program 1 times [2018-01-24 20:01:59,504 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:01:59,505 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:59,505 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:59,505 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:01:59,505 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:01:59,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:59,515 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:01:59,569 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:59,569 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:59,569 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:01:59,570 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-01-24 20:01:59,572 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [10], [11], [16], [18], [20], [56], [57], [58] [2018-01-24 20:01:59,617 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:01:59,617 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:01:59,909 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:01:59,910 INFO L268 AbstractInterpreter]: Visited 11 different actions 23 times. Merged at 6 different actions 12 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-01-24 20:01:59,924 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:01:59,924 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:01:59,924 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:01:59,938 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:01:59,939 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:01:59,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:01:59,966 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:01:59,983 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:01:59,983 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:00,034 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,057 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:00,058 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:00,062 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:00,062 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:00,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:00,075 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:00,082 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,082 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:00,102 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,104 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:00,104 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 20:02:00,105 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:00,106 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:02:00,106 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:02:00,106 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:02:00,106 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. Second operand 4 states. [2018-01-24 20:02:00,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:00,163 INFO L93 Difference]: Finished difference Result 57 states and 62 transitions. [2018-01-24 20:02:00,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:02:00,164 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 20:02:00,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:00,165 INFO L225 Difference]: With dead ends: 57 [2018-01-24 20:02:00,165 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 20:02:00,166 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:02:00,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 20:02:00,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 36. [2018-01-24 20:02:00,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 20:02:00,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 39 transitions. [2018-01-24 20:02:00,173 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 39 transitions. Word has length 12 [2018-01-24 20:02:00,174 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:00,174 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 39 transitions. [2018-01-24 20:02:00,174 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:02:00,174 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 39 transitions. [2018-01-24 20:02:00,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 20:02:00,175 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:00,175 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:00,175 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:00,176 INFO L82 PathProgramCache]: Analyzing trace with hash -209255178, now seen corresponding path program 1 times [2018-01-24 20:02:00,176 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:00,177 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,177 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:00,178 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,178 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:00,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:00,183 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:00,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,246 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:02:00,247 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 20:02:00,247 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:02:00,247 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:02:00,247 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:02:00,247 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 20:02:00,248 INFO L87 Difference]: Start difference. First operand 36 states and 39 transitions. Second operand 4 states. [2018-01-24 20:02:00,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:00,288 INFO L93 Difference]: Finished difference Result 51 states and 54 transitions. [2018-01-24 20:02:00,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:02:00,288 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 20:02:00,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:00,289 INFO L225 Difference]: With dead ends: 51 [2018-01-24 20:02:00,289 INFO L226 Difference]: Without dead ends: 36 [2018-01-24 20:02:00,290 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 20:02:00,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-01-24 20:02:00,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-01-24 20:02:00,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 20:02:00,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-01-24 20:02:00,295 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 12 [2018-01-24 20:02:00,295 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:00,296 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-01-24 20:02:00,296 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:02:00,296 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-01-24 20:02:00,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 20:02:00,297 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:00,297 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:00,297 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:00,297 INFO L82 PathProgramCache]: Analyzing trace with hash 2132883772, now seen corresponding path program 2 times [2018-01-24 20:02:00,298 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:00,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,299 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:00,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,299 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:00,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:00,308 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:00,353 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,354 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:00,354 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:00,354 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:00,354 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:00,354 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:00,354 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:00,360 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:00,360 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:00,364 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:00,367 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:00,367 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:00,368 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:00,385 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,385 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:00,452 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,487 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:00,487 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:00,491 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:00,492 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:00,497 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:00,501 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:00,505 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:00,509 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:00,516 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,517 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:00,526 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,527 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:00,528 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 20:02:00,528 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:00,528 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 20:02:00,528 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 20:02:00,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:02:00,529 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 5 states. [2018-01-24 20:02:00,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:00,583 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions. [2018-01-24 20:02:00,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 20:02:00,584 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 20:02:00,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:00,585 INFO L225 Difference]: With dead ends: 62 [2018-01-24 20:02:00,585 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 20:02:00,585 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:02:00,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 20:02:00,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 41. [2018-01-24 20:02:00,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-01-24 20:02:00,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 44 transitions. [2018-01-24 20:02:00,592 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 44 transitions. Word has length 17 [2018-01-24 20:02:00,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:00,592 INFO L432 AbstractCegarLoop]: Abstraction has 41 states and 44 transitions. [2018-01-24 20:02:00,592 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 20:02:00,593 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 44 transitions. [2018-01-24 20:02:00,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 20:02:00,593 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:00,593 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:00,593 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:00,594 INFO L82 PathProgramCache]: Analyzing trace with hash 2131223963, now seen corresponding path program 1 times [2018-01-24 20:02:00,594 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:00,594 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,595 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:00,595 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,595 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:00,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:00,599 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:00,659 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:00,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:00,659 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:00,659 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 18 with the following transitions: [2018-01-24 20:02:00,660 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [14], [16], [18], [20], [24], [28], [33], [34], [56], [57], [58] [2018-01-24 20:02:00,661 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:02:00,661 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:02:00,877 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:02:00,877 INFO L268 AbstractInterpreter]: Visited 15 different actions 35 times. Merged at 10 different actions 20 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 4 variables. [2018-01-24 20:02:00,879 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:02:00,879 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:00,879 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:00,900 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:00,900 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:00,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:00,917 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:00,919 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:02:00,919 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:00,938 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 20:02:00,959 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 20:02:00,959 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2, 2] imperfect sequences [5] total 6 [2018-01-24 20:02:00,959 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:02:00,959 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 20:02:00,960 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 20:02:00,960 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 20:02:00,960 INFO L87 Difference]: Start difference. First operand 41 states and 44 transitions. Second operand 3 states. [2018-01-24 20:02:00,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:00,973 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-01-24 20:02:00,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 20:02:00,973 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-01-24 20:02:00,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:00,974 INFO L225 Difference]: With dead ends: 49 [2018-01-24 20:02:00,974 INFO L226 Difference]: Without dead ends: 47 [2018-01-24 20:02:00,974 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 20:02:00,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-01-24 20:02:00,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2018-01-24 20:02:00,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 20:02:00,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 48 transitions. [2018-01-24 20:02:00,978 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 48 transitions. Word has length 17 [2018-01-24 20:02:00,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:00,978 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 48 transitions. [2018-01-24 20:02:00,978 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 20:02:00,978 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 48 transitions. [2018-01-24 20:02:00,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 20:02:00,979 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:00,979 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:00,979 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:00,979 INFO L82 PathProgramCache]: Analyzing trace with hash 2059138999, now seen corresponding path program 3 times [2018-01-24 20:02:00,979 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:00,980 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,980 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:00,980 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:00,980 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:00,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:00,986 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:01,081 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,081 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:01,082 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:01,082 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:01,082 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:01,082 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:01,082 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:01,088 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:01,089 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:01,092 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,094 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,100 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:01,101 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:01,115 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,115 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:01,188 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,216 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:01,217 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:01,225 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:01,225 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:01,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,231 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,235 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,240 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:01,243 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:01,246 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:01,252 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,252 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:01,261 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,263 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:01,263 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 20:02:01,263 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:01,263 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 20:02:01,263 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 20:02:01,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 20:02:01,264 INFO L87 Difference]: Start difference. First operand 45 states and 48 transitions. Second operand 6 states. [2018-01-24 20:02:01,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:01,332 INFO L93 Difference]: Finished difference Result 92 states and 99 transitions. [2018-01-24 20:02:01,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 20:02:01,332 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 20:02:01,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:01,333 INFO L225 Difference]: With dead ends: 92 [2018-01-24 20:02:01,334 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 20:02:01,334 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 20:02:01,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 20:02:01,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 50. [2018-01-24 20:02:01,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 20:02:01,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 20:02:01,343 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 22 [2018-01-24 20:02:01,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:01,344 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 20:02:01,344 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 20:02:01,344 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 20:02:01,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 20:02:01,345 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:01,345 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:01,345 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:01,345 INFO L82 PathProgramCache]: Analyzing trace with hash -6617899, now seen corresponding path program 1 times [2018-01-24 20:02:01,345 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:01,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:01,346 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:01,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:01,346 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:01,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:01,356 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:01,402 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,402 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:01,402 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:01,402 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 28 with the following transitions: [2018-01-24 20:02:01,403 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [14], [16], [18], [20], [24], [28], [33], [34], [35], [37], [40], [46], [53], [55], [56], [57], [58], [60], [61] [2018-01-24 20:02:01,404 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:02:01,404 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:02:01,777 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:02:01,777 INFO L268 AbstractInterpreter]: Visited 23 different actions 81 times. Merged at 14 different actions 39 times. Never widened. Found 5 fixpoints after 3 different actions. Largest state had 5 variables. [2018-01-24 20:02:01,793 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:02:01,793 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:01,794 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:01,802 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:01,802 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:01,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:01,816 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:01,858 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,858 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:01,883 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,916 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:01,916 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:01,929 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:01,929 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:01,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:01,946 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:01,953 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,953 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:01,973 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:01,975 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:01,975 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 9 [2018-01-24 20:02:01,975 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:01,975 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 20:02:01,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 20:02:01,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 20:02:01,976 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 8 states. [2018-01-24 20:02:02,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:02,059 INFO L93 Difference]: Finished difference Result 71 states and 76 transitions. [2018-01-24 20:02:02,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 20:02:02,059 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-01-24 20:02:02,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:02,060 INFO L225 Difference]: With dead ends: 71 [2018-01-24 20:02:02,062 INFO L226 Difference]: Without dead ends: 50 [2018-01-24 20:02:02,062 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 101 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 20:02:02,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-24 20:02:02,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-01-24 20:02:02,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 20:02:02,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 53 transitions. [2018-01-24 20:02:02,069 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 53 transitions. Word has length 27 [2018-01-24 20:02:02,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:02,069 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 53 transitions. [2018-01-24 20:02:02,070 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 20:02:02,070 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 53 transitions. [2018-01-24 20:02:02,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 20:02:02,071 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:02,071 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:02,071 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:02,071 INFO L82 PathProgramCache]: Analyzing trace with hash -1173615076, now seen corresponding path program 4 times [2018-01-24 20:02:02,071 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:02,072 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:02,073 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:02,073 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:02,073 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:02,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:02,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:02,224 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,225 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,225 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:02,225 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:02,225 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:02,225 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,225 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:02,232 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:02,232 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:02,238 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:02,239 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:02,246 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,247 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:02,350 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,369 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,369 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:02,372 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:02,372 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:02,385 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:02,387 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:02,395 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,396 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:02,411 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,413 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:02,413 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 20:02:02,413 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:02,413 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 20:02:02,413 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 20:02:02,413 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:02:02,414 INFO L87 Difference]: Start difference. First operand 50 states and 53 transitions. Second operand 7 states. [2018-01-24 20:02:02,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:02,557 INFO L93 Difference]: Finished difference Result 97 states and 104 transitions. [2018-01-24 20:02:02,558 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 20:02:02,558 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 20:02:02,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:02,559 INFO L225 Difference]: With dead ends: 97 [2018-01-24 20:02:02,559 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 20:02:02,559 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:02:02,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 20:02:02,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 55. [2018-01-24 20:02:02,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 20:02:02,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 59 transitions. [2018-01-24 20:02:02,565 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 59 transitions. Word has length 27 [2018-01-24 20:02:02,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:02,566 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 59 transitions. [2018-01-24 20:02:02,566 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 20:02:02,566 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 59 transitions. [2018-01-24 20:02:02,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 20:02:02,567 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:02,567 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:02,567 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:02,567 INFO L82 PathProgramCache]: Analyzing trace with hash 155329936, now seen corresponding path program 2 times [2018-01-24 20:02:02,567 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:02,568 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:02,568 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:02,568 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:02,568 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:02,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:02,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:02,639 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,640 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,640 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:02,640 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:02,640 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:02,640 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,640 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:02,648 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:02,649 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:02,653 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:02,656 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:02,657 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:02,659 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:02,676 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,677 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:02,752 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,771 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,771 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:02,774 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:02,774 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:02,778 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:02,782 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:02,786 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:02,788 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:02,793 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,793 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:02,805 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,807 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:02,807 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 14 [2018-01-24 20:02:02,807 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:02,808 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 20:02:02,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 20:02:02,808 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2018-01-24 20:02:02,808 INFO L87 Difference]: Start difference. First operand 55 states and 59 transitions. Second operand 9 states. [2018-01-24 20:02:02,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:02,889 INFO L93 Difference]: Finished difference Result 72 states and 78 transitions. [2018-01-24 20:02:02,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 20:02:02,890 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 32 [2018-01-24 20:02:02,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:02,890 INFO L225 Difference]: With dead ends: 72 [2018-01-24 20:02:02,890 INFO L226 Difference]: Without dead ends: 55 [2018-01-24 20:02:02,891 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:02:02,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-01-24 20:02:02,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-01-24 20:02:02,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 20:02:02,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 58 transitions. [2018-01-24 20:02:02,894 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 58 transitions. Word has length 32 [2018-01-24 20:02:02,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:02,894 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 58 transitions. [2018-01-24 20:02:02,895 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 20:02:02,895 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 58 transitions. [2018-01-24 20:02:02,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 20:02:02,895 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:02,895 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:02,896 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:02,896 INFO L82 PathProgramCache]: Analyzing trace with hash -1011667241, now seen corresponding path program 5 times [2018-01-24 20:02:02,896 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:02,897 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:02,897 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:02,897 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:02,897 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:02,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:02,902 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:02,977 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:02,977 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,977 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:02,977 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:02,978 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:02,978 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:02,978 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:02,983 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:02,983 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:02,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,014 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,015 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,016 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,018 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,025 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:03,027 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:03,034 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,035 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:03,093 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,112 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,112 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:03,115 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:03,115 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:03,118 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,120 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,129 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,134 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,140 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:03,143 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:03,147 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:03,153 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,153 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:03,160 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,162 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:03,162 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 20:02:03,163 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:03,163 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 20:02:03,163 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 20:02:03,163 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 20:02:03,163 INFO L87 Difference]: Start difference. First operand 55 states and 58 transitions. Second operand 8 states. [2018-01-24 20:02:03,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:03,255 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-01-24 20:02:03,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 20:02:03,255 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 20:02:03,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:03,256 INFO L225 Difference]: With dead ends: 102 [2018-01-24 20:02:03,256 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 20:02:03,256 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 20:02:03,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 20:02:03,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 60. [2018-01-24 20:02:03,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 20:02:03,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2018-01-24 20:02:03,261 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 32 [2018-01-24 20:02:03,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:03,262 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2018-01-24 20:02:03,262 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 20:02:03,262 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2018-01-24 20:02:03,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 20:02:03,263 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:03,263 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:03,263 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:03,263 INFO L82 PathProgramCache]: Analyzing trace with hash -903265867, now seen corresponding path program 3 times [2018-01-24 20:02:03,263 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:03,264 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:03,264 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:03,264 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:03,265 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:03,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:03,272 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:03,329 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,330 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,330 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:03,330 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:03,330 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:03,330 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,330 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:03,342 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:03,342 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:03,345 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:03,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:03,348 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:03,350 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:03,366 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:02:03,366 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:03,402 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:02:03,434 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,434 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:03,440 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:03,440 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:03,445 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:03,449 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:03,453 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:03,456 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:03,459 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:02:03,459 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:03,478 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:02:03,480 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:03,480 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 3, 3, 3, 3] total 12 [2018-01-24 20:02:03,480 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:03,480 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 20:02:03,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 20:02:03,481 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2018-01-24 20:02:03,481 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 11 states. [2018-01-24 20:02:03,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:03,565 INFO L93 Difference]: Finished difference Result 97 states and 113 transitions. [2018-01-24 20:02:03,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 20:02:03,567 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2018-01-24 20:02:03,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:03,568 INFO L225 Difference]: With dead ends: 97 [2018-01-24 20:02:03,568 INFO L226 Difference]: Without dead ends: 74 [2018-01-24 20:02:03,569 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-01-24 20:02:03,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-01-24 20:02:03,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 72. [2018-01-24 20:02:03,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-01-24 20:02:03,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 77 transitions. [2018-01-24 20:02:03,576 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 77 transitions. Word has length 37 [2018-01-24 20:02:03,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:03,576 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 77 transitions. [2018-01-24 20:02:03,576 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 20:02:03,576 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 77 transitions. [2018-01-24 20:02:03,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 20:02:03,578 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:03,579 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:03,579 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:03,579 INFO L82 PathProgramCache]: Analyzing trace with hash -2070263044, now seen corresponding path program 6 times [2018-01-24 20:02:03,579 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:03,580 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:03,580 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:03,580 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:03,580 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:03,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:03,587 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:03,680 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,680 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,680 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:03,680 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:03,680 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:03,680 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,680 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:03,686 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:03,686 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:03,688 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,689 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,690 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,691 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,692 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,693 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,694 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,694 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:03,695 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:03,702 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,702 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:03,774 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,795 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:03,795 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:03,798 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:03,798 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:03,801 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,807 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,811 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,817 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:03,836 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:03,839 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:03,847 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,848 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:03,857 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:03,858 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:03,858 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 20:02:03,858 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:03,858 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 20:02:03,859 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 20:02:03,859 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:02:03,859 INFO L87 Difference]: Start difference. First operand 72 states and 77 transitions. Second operand 9 states. [2018-01-24 20:02:03,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:03,972 INFO L93 Difference]: Finished difference Result 155 states and 170 transitions. [2018-01-24 20:02:03,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 20:02:03,972 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 20:02:03,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:03,974 INFO L225 Difference]: With dead ends: 155 [2018-01-24 20:02:03,974 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 20:02:03,974 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:02:03,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 20:02:03,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 77. [2018-01-24 20:02:03,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 20:02:03,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 20:02:03,982 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 37 [2018-01-24 20:02:03,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:03,982 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 20:02:03,982 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 20:02:03,983 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 20:02:03,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 20:02:03,984 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:03,984 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:03,984 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:03,984 INFO L82 PathProgramCache]: Analyzing trace with hash 1122500087, now seen corresponding path program 7 times [2018-01-24 20:02:03,984 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:03,985 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:03,985 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:03,985 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:03,986 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:03,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:03,993 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:04,072 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,072 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:04,072 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:04,072 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:04,072 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:04,072 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:04,072 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:04,078 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:04,078 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:04,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:04,086 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:04,098 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,098 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:04,243 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,263 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:04,264 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:04,267 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:04,267 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:04,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:04,280 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:04,288 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,289 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:04,299 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,301 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:04,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 20:02:04,301 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:04,301 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 20:02:04,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 20:02:04,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 20:02:04,302 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 10 states. [2018-01-24 20:02:04,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:04,423 INFO L93 Difference]: Finished difference Result 185 states and 204 transitions. [2018-01-24 20:02:04,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 20:02:04,423 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 20:02:04,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:04,425 INFO L225 Difference]: With dead ends: 185 [2018-01-24 20:02:04,425 INFO L226 Difference]: Without dead ends: 182 [2018-01-24 20:02:04,426 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 20:02:04,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-01-24 20:02:04,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 82. [2018-01-24 20:02:04,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 20:02:04,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 20:02:04,436 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 42 [2018-01-24 20:02:04,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:04,437 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 20:02:04,437 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 20:02:04,437 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 20:02:04,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 20:02:04,438 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:04,439 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:04,439 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:04,439 INFO L82 PathProgramCache]: Analyzing trace with hash -676728868, now seen corresponding path program 8 times [2018-01-24 20:02:04,439 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:04,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:04,440 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:04,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:04,440 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:04,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:04,448 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:04,594 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,594 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:04,594 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:04,595 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:04,595 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:04,595 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:04,595 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:04,602 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:04,602 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:04,606 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:04,616 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:04,619 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:04,620 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:04,631 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,631 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:04,784 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,804 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:04,804 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:04,807 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:04,807 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:04,810 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:04,817 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:04,822 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:04,825 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:04,832 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,833 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:04,842 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:04,844 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:04,844 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 20:02:04,844 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:04,844 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 20:02:04,844 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 20:02:04,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 20:02:04,845 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 11 states. [2018-01-24 20:02:04,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:04,998 INFO L93 Difference]: Finished difference Result 215 states and 238 transitions. [2018-01-24 20:02:04,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 20:02:04,999 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 20:02:04,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:05,001 INFO L225 Difference]: With dead ends: 215 [2018-01-24 20:02:05,001 INFO L226 Difference]: Without dead ends: 212 [2018-01-24 20:02:05,002 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 20:02:05,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-01-24 20:02:05,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 87. [2018-01-24 20:02:05,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 20:02:05,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 95 transitions. [2018-01-24 20:02:05,019 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 95 transitions. Word has length 47 [2018-01-24 20:02:05,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:05,020 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 95 transitions. [2018-01-24 20:02:05,020 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 20:02:05,020 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 95 transitions. [2018-01-24 20:02:05,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 20:02:05,021 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:05,021 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:05,021 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:05,022 INFO L82 PathProgramCache]: Analyzing trace with hash -633576169, now seen corresponding path program 9 times [2018-01-24 20:02:05,022 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:05,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:05,023 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:05,023 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:05,023 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:05,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:05,031 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:05,142 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,142 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:05,142 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:05,142 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:05,142 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:05,143 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:05,143 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:05,150 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:05,150 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:05,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,159 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,160 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,162 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,164 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,166 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,167 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,170 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,172 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,173 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:05,174 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:05,184 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,184 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:05,399 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,432 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:05,432 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:05,437 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:05,437 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:05,442 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,447 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,452 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,458 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,465 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,473 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,483 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,512 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:05,519 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:05,523 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:05,544 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,544 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:05,558 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,560 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:05,560 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 20:02:05,560 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:05,561 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 20:02:05,561 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 20:02:05,561 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:02:05,561 INFO L87 Difference]: Start difference. First operand 87 states and 95 transitions. Second operand 12 states. [2018-01-24 20:02:05,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:05,855 INFO L93 Difference]: Finished difference Result 245 states and 272 transitions. [2018-01-24 20:02:05,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 20:02:05,856 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 20:02:05,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:05,858 INFO L225 Difference]: With dead ends: 245 [2018-01-24 20:02:05,858 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 20:02:05,859 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:02:05,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 20:02:05,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 92. [2018-01-24 20:02:05,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 20:02:05,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 101 transitions. [2018-01-24 20:02:05,871 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 101 transitions. Word has length 52 [2018-01-24 20:02:05,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:05,871 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 101 transitions. [2018-01-24 20:02:05,872 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 20:02:05,872 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 101 transitions. [2018-01-24 20:02:05,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 20:02:05,873 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:05,873 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:05,873 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:05,873 INFO L82 PathProgramCache]: Analyzing trace with hash -1365705540, now seen corresponding path program 10 times [2018-01-24 20:02:05,873 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:05,874 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:05,874 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:05,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:05,875 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:05,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:05,884 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:05,995 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,995 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:05,995 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:05,995 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:05,996 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:05,996 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:05,996 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:06,001 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:06,001 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:06,011 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:06,012 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,022 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,022 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,177 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,197 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,197 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:06,200 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:06,200 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:06,231 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:06,234 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,243 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,243 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,263 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,264 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:06,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 20:02:06,265 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:06,265 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 20:02:06,265 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 20:02:06,265 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 20:02:06,265 INFO L87 Difference]: Start difference. First operand 92 states and 101 transitions. Second operand 13 states. [2018-01-24 20:02:06,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:06,503 INFO L93 Difference]: Finished difference Result 275 states and 306 transitions. [2018-01-24 20:02:06,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 20:02:06,503 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 20:02:06,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:06,505 INFO L225 Difference]: With dead ends: 275 [2018-01-24 20:02:06,505 INFO L226 Difference]: Without dead ends: 272 [2018-01-24 20:02:06,506 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 20:02:06,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-01-24 20:02:06,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 97. [2018-01-24 20:02:06,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 20:02:06,519 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 107 transitions. [2018-01-24 20:02:06,519 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 107 transitions. Word has length 57 [2018-01-24 20:02:06,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:06,519 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 107 transitions. [2018-01-24 20:02:06,519 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 20:02:06,519 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 107 transitions. [2018-01-24 20:02:06,520 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 20:02:06,520 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:06,520 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:06,520 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:06,520 INFO L82 PathProgramCache]: Analyzing trace with hash -1933470172, now seen corresponding path program 4 times [2018-01-24 20:02:06,520 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:06,521 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:06,521 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:06,521 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:06,521 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:06,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:06,528 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:06,637 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 10 proven. 59 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-24 20:02:06,637 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,637 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:06,637 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:06,637 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:06,637 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,637 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:06,642 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:06,643 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:06,652 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:06,654 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,679 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:02:06,680 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,737 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:02:06,758 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,758 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:06,761 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:06,761 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:06,790 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:06,793 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,805 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:02:06,806 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,817 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 20:02:06,819 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:06,819 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 5, 5, 5, 5] total 18 [2018-01-24 20:02:06,820 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:06,820 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 20:02:06,820 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 20:02:06,820 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2018-01-24 20:02:06,820 INFO L87 Difference]: Start difference. First operand 97 states and 107 transitions. Second operand 15 states. [2018-01-24 20:02:07,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:07,050 INFO L93 Difference]: Finished difference Result 134 states and 152 transitions. [2018-01-24 20:02:07,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 20:02:07,050 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 62 [2018-01-24 20:02:07,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:07,052 INFO L225 Difference]: With dead ends: 134 [2018-01-24 20:02:07,052 INFO L226 Difference]: Without dead ends: 105 [2018-01-24 20:02:07,052 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 238 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:02:07,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-01-24 20:02:07,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 103. [2018-01-24 20:02:07,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 20:02:07,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 113 transitions. [2018-01-24 20:02:07,061 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 113 transitions. Word has length 62 [2018-01-24 20:02:07,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:07,061 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 113 transitions. [2018-01-24 20:02:07,062 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 20:02:07,062 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 113 transitions. [2018-01-24 20:02:07,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 20:02:07,062 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:07,062 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:07,062 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:07,062 INFO L82 PathProgramCache]: Analyzing trace with hash -116235209, now seen corresponding path program 11 times [2018-01-24 20:02:07,062 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:07,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,063 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:07,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,063 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:07,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:07,070 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:07,269 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,270 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,270 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:07,270 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:07,270 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:07,270 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,270 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:07,277 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:07,277 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:07,280 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,286 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,295 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,297 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,302 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,306 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,311 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,313 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,320 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,324 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,341 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:07,343 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:07,356 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,356 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:07,672 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,693 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,693 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:07,696 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:07,696 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:07,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,706 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,711 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,717 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,723 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,732 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,743 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:07,817 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:07,820 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:07,831 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,831 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:07,850 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,851 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:07,851 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 20:02:07,851 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:07,852 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 20:02:07,852 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 20:02:07,852 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:02:07,852 INFO L87 Difference]: Start difference. First operand 103 states and 113 transitions. Second operand 14 states. [2018-01-24 20:02:08,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:08,092 INFO L93 Difference]: Finished difference Result 328 states and 367 transitions. [2018-01-24 20:02:08,093 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 20:02:08,093 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 20:02:08,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:08,095 INFO L225 Difference]: With dead ends: 328 [2018-01-24 20:02:08,095 INFO L226 Difference]: Without dead ends: 325 [2018-01-24 20:02:08,095 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:02:08,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2018-01-24 20:02:08,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 108. [2018-01-24 20:02:08,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 20:02:08,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 119 transitions. [2018-01-24 20:02:08,111 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 119 transitions. Word has length 62 [2018-01-24 20:02:08,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:08,111 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 119 transitions. [2018-01-24 20:02:08,111 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 20:02:08,111 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 119 transitions. [2018-01-24 20:02:08,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 20:02:08,112 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:08,112 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:08,112 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:08,113 INFO L82 PathProgramCache]: Analyzing trace with hash -414879332, now seen corresponding path program 12 times [2018-01-24 20:02:08,113 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:08,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:08,114 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:08,114 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:08,114 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:08,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:08,123 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:08,291 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,291 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,291 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:08,291 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:08,291 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:08,291 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,292 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:08,296 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:08,296 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:08,299 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,300 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,301 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,302 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,303 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,304 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,305 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,306 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,307 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,308 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,311 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,312 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,313 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:08,314 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:08,328 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,329 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:08,533 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,553 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,553 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:08,556 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:08,556 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:08,560 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,565 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,574 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,580 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,599 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,614 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,648 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,672 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,701 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,708 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:08,712 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:08,731 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,731 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:08,756 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,758 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:08,758 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 20:02:08,758 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:08,758 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 20:02:08,758 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 20:02:08,759 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:02:08,759 INFO L87 Difference]: Start difference. First operand 108 states and 119 transitions. Second operand 15 states. [2018-01-24 20:02:09,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:09,038 INFO L93 Difference]: Finished difference Result 364 states and 408 transitions. [2018-01-24 20:02:09,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 20:02:09,038 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 20:02:09,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:09,040 INFO L225 Difference]: With dead ends: 364 [2018-01-24 20:02:09,040 INFO L226 Difference]: Without dead ends: 361 [2018-01-24 20:02:09,041 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:02:09,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2018-01-24 20:02:09,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 113. [2018-01-24 20:02:09,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 20:02:09,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 125 transitions. [2018-01-24 20:02:09,052 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 125 transitions. Word has length 67 [2018-01-24 20:02:09,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:09,052 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 125 transitions. [2018-01-24 20:02:09,052 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 20:02:09,052 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 125 transitions. [2018-01-24 20:02:09,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 20:02:09,053 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:09,053 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:09,053 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:09,053 INFO L82 PathProgramCache]: Analyzing trace with hash -1135871145, now seen corresponding path program 13 times [2018-01-24 20:02:09,053 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:09,054 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,054 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:09,054 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,054 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:09,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,062 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:09,236 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,236 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,237 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:09,237 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:09,237 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:09,237 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,237 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:09,242 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:09,242 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:09,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,252 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:09,263 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,263 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:09,498 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,518 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,518 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:09,521 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:09,521 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:09,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,542 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:09,553 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,553 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:09,570 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,571 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:09,571 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 20:02:09,571 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:09,572 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 20:02:09,572 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 20:02:09,572 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 20:02:09,572 INFO L87 Difference]: Start difference. First operand 113 states and 125 transitions. Second operand 16 states. [2018-01-24 20:02:09,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:09,918 INFO L93 Difference]: Finished difference Result 400 states and 449 transitions. [2018-01-24 20:02:09,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 20:02:09,919 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 20:02:09,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:09,921 INFO L225 Difference]: With dead ends: 400 [2018-01-24 20:02:09,921 INFO L226 Difference]: Without dead ends: 397 [2018-01-24 20:02:09,922 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 20:02:09,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2018-01-24 20:02:09,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 118. [2018-01-24 20:02:09,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 20:02:09,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 131 transitions. [2018-01-24 20:02:09,939 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 131 transitions. Word has length 72 [2018-01-24 20:02:09,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:09,940 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 131 transitions. [2018-01-24 20:02:09,940 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 20:02:09,940 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 131 transitions. [2018-01-24 20:02:09,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 20:02:09,941 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:09,941 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:09,941 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:09,941 INFO L82 PathProgramCache]: Analyzing trace with hash 1226682691, now seen corresponding path program 5 times [2018-01-24 20:02:09,942 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:09,942 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,942 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:09,943 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,943 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:09,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:10,050 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 24 proven. 89 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 20:02:10,050 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,050 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:10,050 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:10,050 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:10,050 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,050 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:10,056 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:10,056 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:10,060 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,065 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,067 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,071 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,075 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:10,077 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:10,115 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 20:02:10,115 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:10,177 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 20:02:10,197 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,198 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:10,200 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:10,200 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:10,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,207 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,214 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,224 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,235 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,253 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,261 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:10,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:10,280 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 20:02:10,281 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:10,297 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 20:02:10,298 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:10,298 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 22 [2018-01-24 20:02:10,298 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:10,298 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 20:02:10,298 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 20:02:10,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-01-24 20:02:10,299 INFO L87 Difference]: Start difference. First operand 118 states and 131 transitions. Second operand 18 states. [2018-01-24 20:02:10,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:10,446 INFO L93 Difference]: Finished difference Result 161 states and 183 transitions. [2018-01-24 20:02:10,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 20:02:10,446 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 77 [2018-01-24 20:02:10,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:10,447 INFO L225 Difference]: With dead ends: 161 [2018-01-24 20:02:10,447 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 20:02:10,447 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 296 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=556, Unknown=0, NotChecked=0, Total=702 [2018-01-24 20:02:10,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 20:02:10,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-01-24 20:02:10,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-01-24 20:02:10,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 137 transitions. [2018-01-24 20:02:10,456 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 137 transitions. Word has length 77 [2018-01-24 20:02:10,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:10,457 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 137 transitions. [2018-01-24 20:02:10,457 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 20:02:10,457 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 137 transitions. [2018-01-24 20:02:10,457 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 20:02:10,457 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:10,457 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:10,457 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:10,458 INFO L82 PathProgramCache]: Analyzing trace with hash 571297404, now seen corresponding path program 14 times [2018-01-24 20:02:10,458 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:10,458 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:10,458 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:10,458 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:10,458 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:10,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:10,466 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:10,657 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,657 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,657 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:10,658 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:10,658 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:10,658 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,658 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:10,664 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:10,664 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:10,667 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,673 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,674 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:10,675 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:10,692 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,692 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:10,973 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,993 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,993 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:10,996 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:10,997 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:11,000 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:11,010 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:11,017 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:11,021 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:11,033 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,033 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:11,050 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,052 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:11,052 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 20:02:11,052 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:11,052 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 20:02:11,052 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 20:02:11,052 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:02:11,053 INFO L87 Difference]: Start difference. First operand 124 states and 137 transitions. Second operand 17 states. [2018-01-24 20:02:11,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:11,429 INFO L93 Difference]: Finished difference Result 465 states and 524 transitions. [2018-01-24 20:02:11,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 20:02:11,430 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 20:02:11,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:11,432 INFO L225 Difference]: With dead ends: 465 [2018-01-24 20:02:11,432 INFO L226 Difference]: Without dead ends: 462 [2018-01-24 20:02:11,433 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:02:11,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-24 20:02:11,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 129. [2018-01-24 20:02:11,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-01-24 20:02:11,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 143 transitions. [2018-01-24 20:02:11,453 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 143 transitions. Word has length 77 [2018-01-24 20:02:11,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:11,453 INFO L432 AbstractCegarLoop]: Abstraction has 129 states and 143 transitions. [2018-01-24 20:02:11,454 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 20:02:11,454 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 143 transitions. [2018-01-24 20:02:11,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 20:02:11,455 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:11,455 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:11,455 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:11,455 INFO L82 PathProgramCache]: Analyzing trace with hash 239807095, now seen corresponding path program 15 times [2018-01-24 20:02:11,455 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:11,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:11,456 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:11,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:11,457 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:11,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:11,465 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:11,714 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,714 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:11,714 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:11,714 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:11,714 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:11,714 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:11,714 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:11,721 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:11,722 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:11,726 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,730 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,731 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,744 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,745 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,746 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,748 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,749 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,751 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,760 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,769 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,778 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,781 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,785 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:11,786 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:11,788 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:11,812 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,812 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:12,103 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,123 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:12,123 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:12,126 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:12,126 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:12,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,139 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,158 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,167 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,178 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,193 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,212 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,232 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,375 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:12,384 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:12,388 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:12,400 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,401 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:12,415 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,416 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:12,417 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 20:02:12,417 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:12,417 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 20:02:12,417 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 20:02:12,418 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 20:02:12,418 INFO L87 Difference]: Start difference. First operand 129 states and 143 transitions. Second operand 18 states. [2018-01-24 20:02:12,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:12,896 INFO L93 Difference]: Finished difference Result 507 states and 572 transitions. [2018-01-24 20:02:12,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 20:02:12,896 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 20:02:12,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:12,898 INFO L225 Difference]: With dead ends: 507 [2018-01-24 20:02:12,898 INFO L226 Difference]: Without dead ends: 504 [2018-01-24 20:02:12,898 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 20:02:12,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-01-24 20:02:12,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 134. [2018-01-24 20:02:12,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 20:02:12,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 149 transitions. [2018-01-24 20:02:12,917 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 149 transitions. Word has length 82 [2018-01-24 20:02:12,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:12,917 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 149 transitions. [2018-01-24 20:02:12,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 20:02:12,918 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 149 transitions. [2018-01-24 20:02:12,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 20:02:12,919 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:12,919 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:12,919 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:12,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1580297380, now seen corresponding path program 16 times [2018-01-24 20:02:12,919 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:12,920 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:12,920 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:12,920 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:12,920 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:12,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:12,929 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:13,236 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,236 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:13,236 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:13,236 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:13,236 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:13,236 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:13,236 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:13,242 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:13,242 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:13,259 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:13,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:13,275 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,276 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:13,665 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,685 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:13,685 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:13,687 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:13,688 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:13,752 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:13,756 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:13,772 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,772 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:13,793 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,794 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:13,794 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 20:02:13,794 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:13,795 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 20:02:13,795 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 20:02:13,795 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:02:13,795 INFO L87 Difference]: Start difference. First operand 134 states and 149 transitions. Second operand 19 states. [2018-01-24 20:02:14,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:14,275 INFO L93 Difference]: Finished difference Result 549 states and 620 transitions. [2018-01-24 20:02:14,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 20:02:14,275 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 20:02:14,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:14,278 INFO L225 Difference]: With dead ends: 549 [2018-01-24 20:02:14,278 INFO L226 Difference]: Without dead ends: 546 [2018-01-24 20:02:14,279 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:02:14,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-24 20:02:14,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 139. [2018-01-24 20:02:14,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 20:02:14,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 155 transitions. [2018-01-24 20:02:14,306 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 155 transitions. Word has length 87 [2018-01-24 20:02:14,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:14,306 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 155 transitions. [2018-01-24 20:02:14,307 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 20:02:14,307 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 155 transitions. [2018-01-24 20:02:14,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 20:02:14,308 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:14,308 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:14,308 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:14,308 INFO L82 PathProgramCache]: Analyzing trace with hash 677887160, now seen corresponding path program 6 times [2018-01-24 20:02:14,308 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:14,309 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:14,309 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:14,309 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:14,309 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:14,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:14,318 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:14,478 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 44 proven. 124 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-01-24 20:02:14,478 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:14,478 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:14,478 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:14,478 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:14,479 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:14,479 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:14,485 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:14,485 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:14,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,497 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,499 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,502 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,504 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,507 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,510 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,511 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:14,513 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:14,570 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 20:02:14,571 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:14,723 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 20:02:14,744 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:14,744 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:14,753 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:14,753 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:14,758 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,775 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,802 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:14,836 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:14,841 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:14,863 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 20:02:14,863 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:14,880 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 20:02:14,882 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:14,882 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 7, 7, 7, 7] total 26 [2018-01-24 20:02:14,882 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:14,882 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 20:02:14,882 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 20:02:14,882 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=571, Unknown=0, NotChecked=0, Total=702 [2018-01-24 20:02:14,883 INFO L87 Difference]: Start difference. First operand 139 states and 155 transitions. Second operand 21 states. [2018-01-24 20:02:15,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:15,062 INFO L93 Difference]: Finished difference Result 188 states and 214 transitions. [2018-01-24 20:02:15,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 20:02:15,062 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 92 [2018-01-24 20:02:15,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:15,063 INFO L225 Difference]: With dead ends: 188 [2018-01-24 20:02:15,063 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 20:02:15,064 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 354 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 238 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=196, Invalid=796, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:02:15,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 20:02:15,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-01-24 20:02:15,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-01-24 20:02:15,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 161 transitions. [2018-01-24 20:02:15,076 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 161 transitions. Word has length 92 [2018-01-24 20:02:15,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:15,077 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 161 transitions. [2018-01-24 20:02:15,077 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 20:02:15,077 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 161 transitions. [2018-01-24 20:02:15,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 20:02:15,077 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:15,077 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:15,077 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:15,078 INFO L82 PathProgramCache]: Analyzing trace with hash -957222505, now seen corresponding path program 17 times [2018-01-24 20:02:15,078 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:15,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:15,078 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:15,078 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:15,078 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:15,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:15,084 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:15,327 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:15,327 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:15,327 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:15,327 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:15,328 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:15,328 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:15,328 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:15,334 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:15,334 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:15,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,342 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,343 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,344 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,346 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,348 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,350 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,352 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,354 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,356 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,381 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:15,383 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:15,401 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:15,401 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:15,825 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:15,845 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:15,845 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:15,848 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:15,848 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:15,851 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,868 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,875 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,883 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,893 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,926 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,022 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,064 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,100 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,142 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,189 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,200 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:16,204 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:16,221 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,221 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:16,243 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,244 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:16,245 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 20:02:16,245 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:16,245 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 20:02:16,245 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 20:02:16,246 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:02:16,246 INFO L87 Difference]: Start difference. First operand 145 states and 161 transitions. Second operand 20 states. [2018-01-24 20:02:16,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:16,784 INFO L93 Difference]: Finished difference Result 626 states and 709 transitions. [2018-01-24 20:02:16,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 20:02:16,784 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 20:02:16,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:16,786 INFO L225 Difference]: With dead ends: 626 [2018-01-24 20:02:16,787 INFO L226 Difference]: Without dead ends: 623 [2018-01-24 20:02:16,787 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:02:16,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states. [2018-01-24 20:02:16,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 150. [2018-01-24 20:02:16,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-24 20:02:16,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 167 transitions. [2018-01-24 20:02:16,804 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 167 transitions. Word has length 92 [2018-01-24 20:02:16,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:16,805 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 167 transitions. [2018-01-24 20:02:16,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 20:02:16,805 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 167 transitions. [2018-01-24 20:02:16,805 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 20:02:16,805 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:16,805 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:16,805 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:16,806 INFO L82 PathProgramCache]: Analyzing trace with hash 736575548, now seen corresponding path program 18 times [2018-01-24 20:02:16,806 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:16,806 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:16,806 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:16,806 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:16,806 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:16,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:16,812 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:17,119 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:17,120 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:17,120 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:17,120 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:17,120 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:17,120 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:17,120 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:17,127 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:17,127 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:17,131 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,132 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,133 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,134 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,135 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,138 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,140 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,141 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,143 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,145 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,147 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,150 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,154 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,159 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,159 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:17,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:17,178 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:17,178 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:17,649 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:17,668 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:17,669 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:17,671 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:17,671 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:17,675 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,676 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,680 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,683 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,688 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,693 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,699 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,708 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,758 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,778 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,849 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,918 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:17,963 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:18,078 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:18,088 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:18,092 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:18,110 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:18,110 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:18,129 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:18,130 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:18,130 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 20:02:18,130 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:18,130 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 20:02:18,131 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 20:02:18,131 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 20:02:18,131 INFO L87 Difference]: Start difference. First operand 150 states and 167 transitions. Second operand 21 states. [2018-01-24 20:02:18,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:18,748 INFO L93 Difference]: Finished difference Result 674 states and 764 transitions. [2018-01-24 20:02:18,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 20:02:18,749 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 20:02:18,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:18,751 INFO L225 Difference]: With dead ends: 674 [2018-01-24 20:02:18,751 INFO L226 Difference]: Without dead ends: 671 [2018-01-24 20:02:18,752 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 20:02:18,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 671 states. [2018-01-24 20:02:18,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 671 to 155. [2018-01-24 20:02:18,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-24 20:02:18,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 173 transitions. [2018-01-24 20:02:18,785 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 173 transitions. Word has length 97 [2018-01-24 20:02:18,785 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:18,785 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 173 transitions. [2018-01-24 20:02:18,785 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 20:02:18,786 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 173 transitions. [2018-01-24 20:02:18,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 20:02:18,786 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:18,787 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:18,787 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:18,787 INFO L82 PathProgramCache]: Analyzing trace with hash -891985897, now seen corresponding path program 7 times [2018-01-24 20:02:18,787 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:18,788 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:18,788 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:18,788 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:18,788 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:18,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:18,798 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:19,169 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 70 proven. 164 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 20:02:19,169 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:19,169 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:19,170 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:19,170 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:19,170 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:19,170 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:19,178 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:19,179 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:19,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:19,201 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:19,401 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 20:02:19,401 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:19,604 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 20:02:19,634 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:19,635 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:19,639 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:19,640 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:19,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:19,681 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:19,705 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 20:02:19,705 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:19,763 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 20:02:19,764 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:19,764 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 8, 8, 8, 8] total 30 [2018-01-24 20:02:19,765 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:19,765 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 20:02:19,765 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 20:02:19,765 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=764, Unknown=0, NotChecked=0, Total=930 [2018-01-24 20:02:19,765 INFO L87 Difference]: Start difference. First operand 155 states and 173 transitions. Second operand 24 states. [2018-01-24 20:02:20,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:20,020 INFO L93 Difference]: Finished difference Result 210 states and 239 transitions. [2018-01-24 20:02:20,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 20:02:20,020 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-01-24 20:02:20,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:20,021 INFO L225 Difference]: With dead ends: 210 [2018-01-24 20:02:20,021 INFO L226 Difference]: Without dead ends: 163 [2018-01-24 20:02:20,022 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 412 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=253, Invalid=1079, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 20:02:20,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-01-24 20:02:20,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 161. [2018-01-24 20:02:20,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-01-24 20:02:20,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 179 transitions. [2018-01-24 20:02:20,050 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 179 transitions. Word has length 107 [2018-01-24 20:02:20,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:20,051 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 179 transitions. [2018-01-24 20:02:20,051 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 20:02:20,051 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 179 transitions. [2018-01-24 20:02:20,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 20:02:20,051 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:20,052 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:20,052 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:20,052 INFO L82 PathProgramCache]: Analyzing trace with hash -878554953, now seen corresponding path program 19 times [2018-01-24 20:02:20,052 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:20,052 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:20,052 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:20,052 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:20,053 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:20,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:20,059 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:20,351 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,351 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:20,351 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:20,351 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:20,351 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:20,351 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:20,351 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:20,356 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:20,356 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:20,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:20,368 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:20,385 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,385 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:20,839 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,871 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:20,872 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:20,874 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:20,875 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:20,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:20,902 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:20,919 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,919 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:20,939 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,940 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:20,940 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 20:02:20,940 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:20,941 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 20:02:20,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 20:02:20,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:02:20,941 INFO L87 Difference]: Start difference. First operand 161 states and 179 transitions. Second operand 22 states. [2018-01-24 20:02:21,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:21,602 INFO L93 Difference]: Finished difference Result 757 states and 860 transitions. [2018-01-24 20:02:21,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 20:02:21,603 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 20:02:21,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:21,605 INFO L225 Difference]: With dead ends: 757 [2018-01-24 20:02:21,605 INFO L226 Difference]: Without dead ends: 754 [2018-01-24 20:02:21,606 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:02:21,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states. [2018-01-24 20:02:21,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 166. [2018-01-24 20:02:21,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-24 20:02:21,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 185 transitions. [2018-01-24 20:02:21,629 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 185 transitions. Word has length 102 [2018-01-24 20:02:21,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:21,629 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 185 transitions. [2018-01-24 20:02:21,629 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 20:02:21,629 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 185 transitions. [2018-01-24 20:02:21,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 20:02:21,629 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:21,630 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:21,630 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:21,630 INFO L82 PathProgramCache]: Analyzing trace with hash -399157988, now seen corresponding path program 20 times [2018-01-24 20:02:21,630 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:21,630 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:21,631 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:21,631 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:21,631 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:21,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:21,637 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:21,998 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:21,998 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:21,998 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:21,998 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:21,998 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:21,998 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:21,999 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:22,006 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:22,006 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:22,010 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:22,020 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:22,023 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:22,026 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:22,044 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:22,044 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:22,859 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:22,879 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:22,879 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:22,882 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:22,882 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:22,887 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:22,902 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:22,913 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:22,916 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:22,946 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:22,946 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:22,992 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:22,993 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:22,993 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 20:02:22,993 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:22,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 20:02:22,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 20:02:22,994 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:02:22,995 INFO L87 Difference]: Start difference. First operand 166 states and 185 transitions. Second operand 23 states. [2018-01-24 20:02:23,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:23,854 INFO L93 Difference]: Finished difference Result 811 states and 922 transitions. [2018-01-24 20:02:23,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 20:02:23,854 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 20:02:23,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:23,857 INFO L225 Difference]: With dead ends: 811 [2018-01-24 20:02:23,857 INFO L226 Difference]: Without dead ends: 808 [2018-01-24 20:02:23,858 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:02:23,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-01-24 20:02:23,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 171. [2018-01-24 20:02:23,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-01-24 20:02:23,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 191 transitions. [2018-01-24 20:02:23,884 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 191 transitions. Word has length 107 [2018-01-24 20:02:23,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:23,884 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 191 transitions. [2018-01-24 20:02:23,884 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 20:02:23,884 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 191 transitions. [2018-01-24 20:02:23,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 20:02:23,885 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:23,885 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:23,885 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:23,885 INFO L82 PathProgramCache]: Analyzing trace with hash 792610775, now seen corresponding path program 21 times [2018-01-24 20:02:23,885 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:23,886 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:23,886 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:23,886 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:23,886 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:23,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:23,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:24,271 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:24,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:24,271 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:24,271 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:24,271 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:24,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:24,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:24,276 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:24,276 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:24,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,290 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,291 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,292 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,294 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,296 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,299 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,301 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,306 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,308 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,315 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,319 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,323 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,338 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,345 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,351 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:24,352 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:24,354 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:24,375 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:24,375 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:24,987 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,007 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:25,008 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:25,011 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:25,011 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:25,015 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,024 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,029 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,064 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,080 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,118 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,142 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,170 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,211 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,355 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,416 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,598 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,692 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:25,704 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:25,708 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:25,731 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,731 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:25,753 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,755 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:25,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 20:02:25,755 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:25,755 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 20:02:25,755 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 20:02:25,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 20:02:25,756 INFO L87 Difference]: Start difference. First operand 171 states and 191 transitions. Second operand 24 states. [2018-01-24 20:02:26,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:26,638 INFO L93 Difference]: Finished difference Result 865 states and 984 transitions. [2018-01-24 20:02:26,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 20:02:26,638 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 20:02:26,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:26,641 INFO L225 Difference]: With dead ends: 865 [2018-01-24 20:02:26,641 INFO L226 Difference]: Without dead ends: 862 [2018-01-24 20:02:26,642 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 20:02:26,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2018-01-24 20:02:26,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 176. [2018-01-24 20:02:26,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-24 20:02:26,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 197 transitions. [2018-01-24 20:02:26,670 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 197 transitions. Word has length 112 [2018-01-24 20:02:26,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:26,671 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 197 transitions. [2018-01-24 20:02:26,671 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 20:02:26,671 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 197 transitions. [2018-01-24 20:02:26,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 20:02:26,671 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:26,671 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:26,672 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:26,672 INFO L82 PathProgramCache]: Analyzing trace with hash -600860340, now seen corresponding path program 8 times [2018-01-24 20:02:26,672 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:26,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:26,673 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:26,673 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:26,673 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:26,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:26,680 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:26,892 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 102 proven. 209 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 20:02:26,893 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:26,893 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:26,893 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:26,893 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:26,893 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:26,893 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:26,898 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:26,898 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:26,902 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:26,910 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:26,912 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:26,914 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:26,992 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 20:02:26,992 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:27,127 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 20:02:27,147 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:27,148 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:27,150 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:27,151 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:27,156 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:27,174 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:27,188 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:27,192 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:27,234 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 140 proven. 171 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 20:02:27,235 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:27,743 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 126 proven. 185 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 20:02:27,744 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:27,744 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 9, 9, 19, 19] total 52 [2018-01-24 20:02:27,744 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:27,745 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 20:02:27,745 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 20:02:27,745 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=550, Invalid=2206, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 20:02:27,745 INFO L87 Difference]: Start difference. First operand 176 states and 197 transitions. Second operand 27 states. [2018-01-24 20:02:28,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:28,079 INFO L93 Difference]: Finished difference Result 237 states and 270 transitions. [2018-01-24 20:02:28,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 20:02:28,079 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-24 20:02:28,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:28,080 INFO L225 Difference]: With dead ends: 237 [2018-01-24 20:02:28,080 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 20:02:28,081 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 453 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 951 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=788, Invalid=2752, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 20:02:28,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 20:02:28,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 182. [2018-01-24 20:02:28,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 20:02:28,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 203 transitions. [2018-01-24 20:02:28,110 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 203 transitions. Word has length 122 [2018-01-24 20:02:28,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:28,111 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 203 transitions. [2018-01-24 20:02:28,111 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 20:02:28,111 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 203 transitions. [2018-01-24 20:02:28,112 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 20:02:28,112 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:28,112 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:28,112 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:28,112 INFO L82 PathProgramCache]: Analyzing trace with hash 1092014588, now seen corresponding path program 22 times [2018-01-24 20:02:28,112 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:28,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:28,113 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:28,113 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:28,113 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:28,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:28,122 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:28,865 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:28,865 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:28,865 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:28,865 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:28,865 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:28,865 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:28,865 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:28,870 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:28,870 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:28,894 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:28,896 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:28,916 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:28,916 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:29,467 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:29,487 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:29,487 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:29,490 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:29,490 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:29,608 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:29,612 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:29,633 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:29,634 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:29,661 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:29,662 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:29,663 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 20:02:29,663 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:29,663 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 20:02:29,663 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 20:02:29,664 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 20:02:29,664 INFO L87 Difference]: Start difference. First operand 182 states and 203 transitions. Second operand 25 states. [2018-01-24 20:02:30,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:30,601 INFO L93 Difference]: Finished difference Result 960 states and 1094 transitions. [2018-01-24 20:02:30,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 20:02:30,601 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 20:02:30,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:30,604 INFO L225 Difference]: With dead ends: 960 [2018-01-24 20:02:30,604 INFO L226 Difference]: Without dead ends: 957 [2018-01-24 20:02:30,605 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 20:02:30,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states. [2018-01-24 20:02:30,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 187. [2018-01-24 20:02:30,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-01-24 20:02:30,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 209 transitions. [2018-01-24 20:02:30,637 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 209 transitions. Word has length 117 [2018-01-24 20:02:30,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:30,637 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 209 transitions. [2018-01-24 20:02:30,637 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 20:02:30,637 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 209 transitions. [2018-01-24 20:02:30,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 20:02:30,638 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:30,638 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:30,638 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:30,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1378342647, now seen corresponding path program 23 times [2018-01-24 20:02:30,638 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:30,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:30,639 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:30,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:30,639 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:30,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:30,647 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:31,056 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:31,056 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:31,056 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:31,056 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:31,056 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:31,057 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:31,057 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:31,063 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:31,063 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:31,067 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,069 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,070 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,072 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,073 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,077 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,085 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,087 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,091 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,095 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,099 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,103 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,108 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,112 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,119 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,131 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,138 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,146 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,155 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,164 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,171 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,179 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,180 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:31,182 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:31,205 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:31,205 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:31,804 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:31,824 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:31,824 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:31,827 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:31,827 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:31,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,841 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,872 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,884 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:31,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,034 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,083 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,124 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,171 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,227 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,314 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,417 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,495 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,581 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:32,703 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:32,707 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:32,732 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:32,732 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:32,761 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:32,763 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:32,763 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 20:02:32,763 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:32,763 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 20:02:32,763 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 20:02:32,764 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 20:02:32,764 INFO L87 Difference]: Start difference. First operand 187 states and 209 transitions. Second operand 26 states. [2018-01-24 20:02:33,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:33,852 INFO L93 Difference]: Finished difference Result 1020 states and 1163 transitions. [2018-01-24 20:02:33,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 20:02:33,853 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 20:02:33,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:33,856 INFO L225 Difference]: With dead ends: 1020 [2018-01-24 20:02:33,856 INFO L226 Difference]: Without dead ends: 1017 [2018-01-24 20:02:33,857 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 20:02:33,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017 states. [2018-01-24 20:02:33,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017 to 192. [2018-01-24 20:02:33,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-01-24 20:02:33,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 215 transitions. [2018-01-24 20:02:33,922 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 215 transitions. Word has length 122 [2018-01-24 20:02:33,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:33,922 INFO L432 AbstractCegarLoop]: Abstraction has 192 states and 215 transitions. [2018-01-24 20:02:33,922 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 20:02:33,922 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 215 transitions. [2018-01-24 20:02:33,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 20:02:33,923 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:33,923 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:33,923 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:33,923 INFO L82 PathProgramCache]: Analyzing trace with hash -1016482084, now seen corresponding path program 24 times [2018-01-24 20:02:33,923 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:33,924 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:33,924 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:33,924 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:33,924 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:33,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:33,933 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:34,376 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:34,376 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:34,376 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:34,376 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:34,376 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:34,377 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:34,377 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:34,381 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:34,382 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:34,385 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,386 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,388 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,389 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,389 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,390 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,391 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,394 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,395 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,396 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,398 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,401 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,405 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,407 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,409 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,411 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,413 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,417 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,420 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,424 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:34,428 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:34,430 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:34,453 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:34,453 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:35,102 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:35,122 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:35,122 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:35,124 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:35,125 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:35,130 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,131 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,135 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,139 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,165 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,189 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,210 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,230 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,312 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,343 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,381 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,481 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:35,830 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:36,050 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:36,298 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:36,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:36,539 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:36,543 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:36,568 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:36,568 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:36,603 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:36,604 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:36,604 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 20:02:36,604 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:36,605 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 20:02:36,605 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 20:02:36,605 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 20:02:36,606 INFO L87 Difference]: Start difference. First operand 192 states and 215 transitions. Second operand 27 states. [2018-01-24 20:02:38,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:38,165 INFO L93 Difference]: Finished difference Result 1080 states and 1232 transitions. [2018-01-24 20:02:38,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 20:02:38,165 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 20:02:38,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:38,168 INFO L225 Difference]: With dead ends: 1080 [2018-01-24 20:02:38,168 INFO L226 Difference]: Without dead ends: 1077 [2018-01-24 20:02:38,169 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 20:02:38,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1077 states. [2018-01-24 20:02:38,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1077 to 197. [2018-01-24 20:02:38,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-01-24 20:02:38,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 221 transitions. [2018-01-24 20:02:38,211 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 221 transitions. Word has length 127 [2018-01-24 20:02:38,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:38,212 INFO L432 AbstractCegarLoop]: Abstraction has 197 states and 221 transitions. [2018-01-24 20:02:38,212 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 20:02:38,212 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 221 transitions. [2018-01-24 20:02:38,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 20:02:38,212 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:38,212 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:38,213 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:38,213 INFO L82 PathProgramCache]: Analyzing trace with hash 795448555, now seen corresponding path program 9 times [2018-01-24 20:02:38,213 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:38,213 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:38,213 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:38,213 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:38,213 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:38,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:38,221 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:38,479 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 140 proven. 259 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-01-24 20:02:38,480 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:38,480 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:38,480 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:38,480 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:38,480 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:38,480 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:38,485 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:38,485 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:38,489 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,492 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,496 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,499 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,510 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:38,512 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:38,604 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 20:02:38,604 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:38,776 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 20:02:38,795 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:38,796 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:38,798 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:38,799 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:38,804 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,807 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,814 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,874 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,913 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:38,971 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:38,976 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:39,021 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 20:02:39,021 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:39,058 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 20:02:39,059 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:39,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10, 10, 10, 10] total 38 [2018-01-24 20:02:39,059 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:39,060 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 20:02:39,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 20:02:39,060 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1234, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 20:02:39,060 INFO L87 Difference]: Start difference. First operand 197 states and 221 transitions. Second operand 30 states. [2018-01-24 20:02:39,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:39,468 INFO L93 Difference]: Finished difference Result 264 states and 301 transitions. [2018-01-24 20:02:39,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 20:02:39,468 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 137 [2018-01-24 20:02:39,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:39,469 INFO L225 Difference]: With dead ends: 264 [2018-01-24 20:02:39,469 INFO L226 Difference]: Without dead ends: 205 [2018-01-24 20:02:39,470 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 528 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=388, Invalid=1774, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 20:02:39,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-01-24 20:02:39,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 203. [2018-01-24 20:02:39,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-01-24 20:02:39,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 227 transitions. [2018-01-24 20:02:39,501 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 227 transitions. Word has length 137 [2018-01-24 20:02:39,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:39,501 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 227 transitions. [2018-01-24 20:02:39,501 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 20:02:39,501 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 227 transitions. [2018-01-24 20:02:39,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 20:02:39,502 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:39,502 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:39,502 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:39,502 INFO L82 PathProgramCache]: Analyzing trace with hash 37813783, now seen corresponding path program 25 times [2018-01-24 20:02:39,503 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:39,503 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:39,503 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:39,503 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:39,503 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:39,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:39,512 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:39,928 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:39,928 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:39,928 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:39,928 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:39,928 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:39,928 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:39,929 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:39,933 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:39,933 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:39,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:39,948 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:39,988 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:39,988 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:40,652 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:40,671 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:40,672 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:40,674 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:40,674 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:40,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:40,718 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:40,767 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:40,767 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:40,815 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:40,817 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:40,817 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 20:02:40,817 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:40,817 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 20:02:40,818 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 20:02:40,818 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 20:02:40,818 INFO L87 Difference]: Start difference. First operand 203 states and 227 transitions. Second operand 28 states. [2018-01-24 20:02:42,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:42,346 INFO L93 Difference]: Finished difference Result 1187 states and 1356 transitions. [2018-01-24 20:02:42,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 20:02:42,346 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 20:02:42,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:42,351 INFO L225 Difference]: With dead ends: 1187 [2018-01-24 20:02:42,352 INFO L226 Difference]: Without dead ends: 1184 [2018-01-24 20:02:42,352 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 20:02:42,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states. [2018-01-24 20:02:42,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 208. [2018-01-24 20:02:42,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208 states. [2018-01-24 20:02:42,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 233 transitions. [2018-01-24 20:02:42,400 INFO L78 Accepts]: Start accepts. Automaton has 208 states and 233 transitions. Word has length 132 [2018-01-24 20:02:42,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:42,401 INFO L432 AbstractCegarLoop]: Abstraction has 208 states and 233 transitions. [2018-01-24 20:02:42,401 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 20:02:42,401 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 233 transitions. [2018-01-24 20:02:42,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 20:02:42,402 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:42,402 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:42,402 INFO L371 AbstractCegarLoop]: === Iteration 38 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:42,403 INFO L82 PathProgramCache]: Analyzing trace with hash -24378436, now seen corresponding path program 26 times [2018-01-24 20:02:42,403 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:42,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:42,403 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:42,403 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:42,404 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:42,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:42,411 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:42,982 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:42,982 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:42,982 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:42,982 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:42,983 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:42,983 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:42,983 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:42,987 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:42,987 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:42,991 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:43,001 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:43,003 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:43,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:43,047 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,047 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:43,861 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,880 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:43,880 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 72 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:43,883 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:43,883 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:43,888 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:43,904 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:43,916 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:43,920 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:43,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,950 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:43,981 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,982 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:44,019 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 20:02:44,019 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:44,020 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 20:02:44,020 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 20:02:44,020 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 20:02:44,020 INFO L87 Difference]: Start difference. First operand 208 states and 233 transitions. Second operand 29 states. [2018-01-24 20:02:45,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:45,546 INFO L93 Difference]: Finished difference Result 1253 states and 1432 transitions. [2018-01-24 20:02:45,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 20:02:45,546 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 137 [2018-01-24 20:02:45,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:45,550 INFO L225 Difference]: With dead ends: 1253 [2018-01-24 20:02:45,550 INFO L226 Difference]: Without dead ends: 1250 [2018-01-24 20:02:45,551 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 574 GetRequests, 518 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 20:02:45,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1250 states. [2018-01-24 20:02:45,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1250 to 213. [2018-01-24 20:02:45,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-01-24 20:02:45,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 239 transitions. [2018-01-24 20:02:45,597 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 239 transitions. Word has length 137 [2018-01-24 20:02:45,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:45,598 INFO L432 AbstractCegarLoop]: Abstraction has 213 states and 239 transitions. [2018-01-24 20:02:45,598 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 20:02:45,598 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 239 transitions. [2018-01-24 20:02:45,598 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 20:02:45,598 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:45,598 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:45,599 INFO L371 AbstractCegarLoop]: === Iteration 39 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:45,599 INFO L82 PathProgramCache]: Analyzing trace with hash -1695826633, now seen corresponding path program 27 times [2018-01-24 20:02:45,599 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:45,599 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:45,599 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:45,599 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:45,599 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:45,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:45,605 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:46,196 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:46,196 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:46,196 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:46,196 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:46,196 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:46,196 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:46,196 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:46,201 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:46,201 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:46,205 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,205 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,206 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,207 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,208 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,209 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,210 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,211 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,212 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,213 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,215 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,216 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,218 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,220 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,222 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,227 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command Received shutdown request... [2018-01-24 20:02:46,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,234 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,237 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,242 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,246 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,255 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,271 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,278 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:46,279 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:46,281 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:46,283 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 20:02:46,283 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 20:02:46,286 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 20:02:46,286 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 08:02:46 BoogieIcfgContainer [2018-01-24 20:02:46,286 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 20:02:46,287 INFO L168 Benchmark]: Toolchain (without parser) took 47612.78 ms. Allocated memory was 308.8 MB in the beginning and 770.2 MB in the end (delta: 461.4 MB). Free memory was 268.1 MB in the beginning and 588.4 MB in the end (delta: -320.3 MB). Peak memory consumption was 141.1 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:46,287 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 308.8 MB. Free memory is still 273.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 20:02:46,288 INFO L168 Benchmark]: CACSL2BoogieTranslator took 163.06 ms. Allocated memory is still 308.8 MB. Free memory was 267.1 MB in the beginning and 260.1 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:46,288 INFO L168 Benchmark]: Boogie Preprocessor took 23.32 ms. Allocated memory is still 308.8 MB. Free memory was 260.1 MB in the beginning and 258.1 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:46,288 INFO L168 Benchmark]: RCFGBuilder took 161.96 ms. Allocated memory is still 308.8 MB. Free memory was 258.1 MB in the beginning and 246.5 MB in the end (delta: 11.6 MB). Peak memory consumption was 11.6 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:46,288 INFO L168 Benchmark]: TraceAbstraction took 47255.71 ms. Allocated memory was 308.8 MB in the beginning and 770.2 MB in the end (delta: 461.4 MB). Free memory was 246.5 MB in the beginning and 588.4 MB in the end (delta: -341.9 MB). Peak memory consumption was 119.4 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:46,290 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 308.8 MB. Free memory is still 273.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 163.06 ms. Allocated memory is still 308.8 MB. Free memory was 267.1 MB in the beginning and 260.1 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 23.32 ms. Allocated memory is still 308.8 MB. Free memory was 260.1 MB in the beginning and 258.1 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 161.96 ms. Allocated memory is still 308.8 MB. Free memory was 258.1 MB in the beginning and 246.5 MB in the end (delta: 11.6 MB). Peak memory consumption was 11.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 47255.71 ms. Allocated memory was 308.8 MB in the beginning and 770.2 MB in the end (delta: 461.4 MB). Free memory was 246.5 MB in the beginning and 588.4 MB in the end (delta: -341.9 MB). Peak memory consumption was 119.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 3.323116 RENAME_VARIABLES(MILLISECONDS) : 0.321325 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 3.251263 PROJECTAWAY(MILLISECONDS) : 6.032377 ADD_WEAK_EQUALITY(MILLISECONDS) : 2.141884 DISJOIN(MILLISECONDS) : 0.214629 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.349183 ADD_EQUALITY(MILLISECONDS) : 3.995942 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.745304 #CONJOIN_DISJUNCTIVE : 36 #RENAME_VARIABLES : 82 #UNFREEZE : 0 #CONJOIN : 48 #PROJECTAWAY : 57 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 77 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 14 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 9 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -28 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 19 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 7 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 20 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.637545 RENAME_VARIABLES(MILLISECONDS) : 0.389541 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.240788 PROJECTAWAY(MILLISECONDS) : 0.045670 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.361590 DISJOIN(MILLISECONDS) : 0.181227 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.420106 ADD_EQUALITY(MILLISECONDS) : 0.033326 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.327528 #CONJOIN_DISJUNCTIVE : 56 #RENAME_VARIABLES : 122 #UNFREEZE : 0 #CONJOIN : 68 #PROJECTAWAY : 81 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 14 #RENAME_VARIABLES_DISJUNCTIVE : 117 #ADD_EQUALITY : 7 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 21 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 11 LocStat_NO_SUPPORTING_DISEQUALITIES : 7 LocStat_NO_DISJUNCTIONS : -42 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 29 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 10 TransStat_NO_SUPPORTING_DISEQUALITIES : 2 TransStat_NO_DISJUNCTIONS : 30 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.138280 RENAME_VARIABLES(MILLISECONDS) : 0.143785 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.097972 PROJECTAWAY(MILLISECONDS) : 0.132013 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.285076 DISJOIN(MILLISECONDS) : 0.154223 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.166602 ADD_EQUALITY(MILLISECONDS) : 0.046985 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.013846 #CONJOIN_DISJUNCTIVE : 121 #RENAME_VARIABLES : 295 #UNFREEZE : 0 #CONJOIN : 184 #PROJECTAWAY : 191 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 26 #RENAME_VARIABLES_DISJUNCTIVE : 287 #ADD_EQUALITY : 10 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 30 known predicates. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 30 known predicates. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 30 known predicates. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 30 known predicates. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 143 with TraceHistMax 28, while TraceCheckSpWp was constructing forward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 30 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 32 locations, 5 error locations. TIMEOUT Result, 47.2s OverallTime, 39 OverallIterations, 28 TraceHistogramMax, 15.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4036 SDtfs, 2569 SDslu, 59587 SDs, 0 SdLazy, 30837 SolverSat, 230 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 11050 GetRequests, 9973 SyntacticMatches, 68 SemanticMatches, 1009 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2796 ImplicationChecksByTransitivity, 16.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=213occurred in iteration=38, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.9s AbstIntTime, 3 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 38 MinimizatonAttempts, 10045 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 6.2s SatisfiabilityAnalysisTime, 20.6s InterpolantComputationTime, 7943 NumberOfCodeBlocks, 7913 NumberOfCodeBlocksAsserted, 501 NumberOfCheckSat, 13040 ConstructedInterpolants, 0 QuantifiedInterpolants, 7741836 SizeOfPredicates, 7 NumberOfNonLiveVariables, 7716 ConjunctsInSsa, 1767 ConjunctsInUnsatCore, 180 InterpolantComputations, 4 PerfectInterpolantSequences, 4895/85009 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-1-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-1-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-2-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-2-2018-01-24_20-02-46-300.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_20-02-46-300.csv Completed graceful shutdown