java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 20:02:04,837 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 20:02:04,839 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 20:02:04,854 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 20:02:04,855 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 20:02:04,856 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 20:02:04,857 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 20:02:04,858 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 20:02:04,860 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 20:02:04,861 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 20:02:04,862 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 20:02:04,862 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 20:02:04,863 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 20:02:04,864 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 20:02:04,865 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 20:02:04,868 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 20:02:04,870 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 20:02:04,872 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 20:02:04,873 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 20:02:04,875 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 20:02:04,877 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 20:02:04,877 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 20:02:04,878 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 20:02:04,879 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 20:02:04,879 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 20:02:04,881 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 20:02:04,881 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 20:02:04,882 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 20:02:04,882 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 20:02:04,882 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 20:02:04,883 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 20:02:04,883 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf [2018-01-24 20:02:04,892 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 20:02:04,892 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 20:02:04,893 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 20:02:04,893 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 20:02:04,893 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 20:02:04,893 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 20:02:04,893 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 20:02:04,893 INFO L133 SettingsManager]: * Precise comparison operator=true [2018-01-24 20:02:04,893 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 20:02:04,894 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 20:02:04,894 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 20:02:04,894 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 20:02:04,894 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 20:02:04,895 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 20:02:04,895 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 20:02:04,896 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 20:02:04,896 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 20:02:04,896 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 20:02:04,896 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 20:02:04,896 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:02:04,897 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 20:02:04,897 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 20:02:04,898 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 20:02:04,898 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 20:02:04,898 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 20:02:04,932 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 20:02:04,945 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 20:02:04,949 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 20:02:04,950 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 20:02:04,951 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 20:02:04,952 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i [2018-01-24 20:02:05,085 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 20:02:05,093 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 20:02:05,094 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 20:02:05,094 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 20:02:05,101 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 20:02:05,102 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,105 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@87bddd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05, skipping insertion in model container [2018-01-24 20:02:05,105 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,123 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:02:05,143 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 20:02:05,261 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:02:05,272 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 20:02:05,277 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05 WrapperNode [2018-01-24 20:02:05,277 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 20:02:05,278 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 20:02:05,278 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 20:02:05,278 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 20:02:05,290 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,290 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,297 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,297 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,298 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,301 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,302 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... [2018-01-24 20:02:05,303 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 20:02:05,303 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 20:02:05,304 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 20:02:05,304 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 20:02:05,304 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 20:02:05,353 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 20:02:05,354 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 20:02:05,354 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 20:02:05,354 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 20:02:05,354 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 20:02:05,354 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 20:02:05,354 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 20:02:05,355 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 20:02:05,355 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 20:02:05,501 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 20:02:05,501 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:02:05 BoogieIcfgContainer [2018-01-24 20:02:05,501 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 20:02:05,502 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 20:02:05,503 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 20:02:05,505 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 20:02:05,506 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 08:02:05" (1/3) ... [2018-01-24 20:02:05,507 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71ce0606 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:02:05, skipping insertion in model container [2018-01-24 20:02:05,507 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 08:02:05" (2/3) ... [2018-01-24 20:02:05,508 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@71ce0606 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 08:02:05, skipping insertion in model container [2018-01-24 20:02:05,508 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 08:02:05" (3/3) ... [2018-01-24 20:02:05,509 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_original_false-valid-deref.i [2018-01-24 20:02:05,516 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 20:02:05,524 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-01-24 20:02:05,562 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 20:02:05,562 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 20:02:05,562 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 20:02:05,562 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 20:02:05,562 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 20:02:05,563 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 20:02:05,563 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 20:02:05,563 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 20:02:05,564 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 20:02:05,586 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-01-24 20:02:05,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 20:02:05,593 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:05,594 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:05,594 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:05,600 INFO L82 PathProgramCache]: Analyzing trace with hash 1734695582, now seen corresponding path program 1 times [2018-01-24 20:02:05,602 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:05,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:05,654 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:05,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:05,654 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:05,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:05,696 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:05,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:05,763 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 20:02:05,763 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 20:02:05,763 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 20:02:05,765 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 20:02:05,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 20:02:05,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 20:02:05,780 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 3 states. [2018-01-24 20:02:05,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:05,900 INFO L93 Difference]: Finished difference Result 74 states and 90 transitions. [2018-01-24 20:02:05,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 20:02:05,902 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 20:02:05,903 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:05,911 INFO L225 Difference]: With dead ends: 74 [2018-01-24 20:02:05,911 INFO L226 Difference]: Without dead ends: 41 [2018-01-24 20:02:05,916 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 20:02:05,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-01-24 20:02:06,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 38. [2018-01-24 20:02:06,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-24 20:02:06,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-01-24 20:02:06,010 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 7 [2018-01-24 20:02:06,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:06,011 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-01-24 20:02:06,011 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 20:02:06,011 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-01-24 20:02:06,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 20:02:06,011 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:06,012 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:06,012 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:06,012 INFO L82 PathProgramCache]: Analyzing trace with hash 337601429, now seen corresponding path program 1 times [2018-01-24 20:02:06,012 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:06,013 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:06,013 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:06,013 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:06,013 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:06,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:06,022 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:06,073 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,073 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,073 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:06,074 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-01-24 20:02:06,075 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [10], [11], [16], [18], [20], [58], [59], [60] [2018-01-24 20:02:06,127 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 20:02:06,127 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 20:02:06,412 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 20:02:06,414 INFO L268 AbstractInterpreter]: Visited 11 different actions 23 times. Merged at 6 different actions 12 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-01-24 20:02:06,422 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 20:02:06,422 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,422 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:06,434 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:06,434 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:06,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:06,455 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,473 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,474 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,531 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,567 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,567 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:06,571 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:06,572 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:06,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:06,581 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,588 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,588 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,595 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,596 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:06,597 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 20:02:06,597 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:06,598 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 20:02:06,598 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 20:02:06,598 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:02:06,598 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 4 states. [2018-01-24 20:02:06,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:06,685 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2018-01-24 20:02:06,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 20:02:06,686 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 20:02:06,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:06,687 INFO L225 Difference]: With dead ends: 60 [2018-01-24 20:02:06,687 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 20:02:06,688 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 20:02:06,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 20:02:06,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 50. [2018-01-24 20:02:06,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 20:02:06,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 20:02:06,696 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 12 [2018-01-24 20:02:06,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:06,696 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 20:02:06,697 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 20:02:06,697 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 20:02:06,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 20:02:06,698 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:06,698 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:06,698 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:06,698 INFO L82 PathProgramCache]: Analyzing trace with hash -1746445058, now seen corresponding path program 2 times [2018-01-24 20:02:06,699 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:06,699 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:06,700 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:06,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:06,700 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:06,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:06,708 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:06,784 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,784 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,784 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:06,785 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:06,785 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:06,785 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,785 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:06,791 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:06,791 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:06,796 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:06,805 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:06,805 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:06,807 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,814 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,814 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,905 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,926 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:06,926 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:06,933 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:06,934 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:06,939 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:06,942 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:06,945 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:06,948 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:06,972 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,972 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:06,989 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:06,990 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:06,990 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 20:02:06,990 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:06,991 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 20:02:06,991 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 20:02:06,991 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:02:06,991 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 5 states. [2018-01-24 20:02:07,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:07,100 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2018-01-24 20:02:07,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 20:02:07,101 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 20:02:07,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:07,103 INFO L225 Difference]: With dead ends: 73 [2018-01-24 20:02:07,103 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 20:02:07,104 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 20:02:07,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 20:02:07,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2018-01-24 20:02:07,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 20:02:07,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 68 transitions. [2018-01-24 20:02:07,113 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 68 transitions. Word has length 17 [2018-01-24 20:02:07,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:07,113 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 68 transitions. [2018-01-24 20:02:07,113 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 20:02:07,113 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 68 transitions. [2018-01-24 20:02:07,114 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 20:02:07,114 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:07,114 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:07,114 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:07,115 INFO L82 PathProgramCache]: Analyzing trace with hash -228598475, now seen corresponding path program 3 times [2018-01-24 20:02:07,115 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:07,116 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,116 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:07,116 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,116 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:07,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:07,124 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:07,211 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,212 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,212 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:07,212 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:07,212 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:07,213 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,213 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:07,218 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:07,218 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:07,222 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,228 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,228 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:07,230 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:07,242 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,243 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:07,324 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,345 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,345 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:07,348 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:07,348 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:07,352 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,353 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,357 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,362 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:07,365 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:07,368 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:07,375 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,375 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:07,386 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,387 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:07,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 20:02:07,387 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:07,387 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 20:02:07,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 20:02:07,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 20:02:07,388 INFO L87 Difference]: Start difference. First operand 62 states and 68 transitions. Second operand 6 states. [2018-01-24 20:02:07,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:07,515 INFO L93 Difference]: Finished difference Result 86 states and 95 transitions. [2018-01-24 20:02:07,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 20:02:07,515 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 20:02:07,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:07,516 INFO L225 Difference]: With dead ends: 86 [2018-01-24 20:02:07,516 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 20:02:07,517 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 20:02:07,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 20:02:07,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 74. [2018-01-24 20:02:07,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 20:02:07,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 82 transitions. [2018-01-24 20:02:07,523 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 82 transitions. Word has length 22 [2018-01-24 20:02:07,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:07,524 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 82 transitions. [2018-01-24 20:02:07,524 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 20:02:07,524 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 82 transitions. [2018-01-24 20:02:07,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 20:02:07,525 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:07,525 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:07,525 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:07,525 INFO L82 PathProgramCache]: Analyzing trace with hash 756148062, now seen corresponding path program 4 times [2018-01-24 20:02:07,525 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:07,526 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,526 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:07,527 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,527 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:07,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:07,534 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:07,607 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,607 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,607 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:07,608 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:07,608 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:07,608 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,608 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:07,615 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:07,616 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:07,623 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:07,624 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:07,632 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,632 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:07,700 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,721 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:07,721 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:07,725 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:07,725 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:07,739 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:07,741 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:07,748 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,748 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:07,755 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:07,756 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:07,756 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 20:02:07,756 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:07,757 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 20:02:07,757 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 20:02:07,757 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:02:07,757 INFO L87 Difference]: Start difference. First operand 74 states and 82 transitions. Second operand 7 states. [2018-01-24 20:02:07,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:07,890 INFO L93 Difference]: Finished difference Result 99 states and 110 transitions. [2018-01-24 20:02:07,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 20:02:07,890 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 20:02:07,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:07,891 INFO L225 Difference]: With dead ends: 99 [2018-01-24 20:02:07,891 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 20:02:07,892 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 20:02:07,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 20:02:07,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 86. [2018-01-24 20:02:07,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 20:02:07,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 96 transitions. [2018-01-24 20:02:07,898 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 96 transitions. Word has length 27 [2018-01-24 20:02:07,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:07,898 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 96 transitions. [2018-01-24 20:02:07,898 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 20:02:07,898 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 96 transitions. [2018-01-24 20:02:07,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 20:02:07,899 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:07,899 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:07,899 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:07,899 INFO L82 PathProgramCache]: Analyzing trace with hash 671928021, now seen corresponding path program 5 times [2018-01-24 20:02:07,900 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:07,900 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,900 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:07,900 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:07,900 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:07,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:07,907 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:08,004 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,004 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:08,004 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:08,004 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:08,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,005 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:08,013 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:08,013 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:08,018 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,026 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,027 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,030 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,031 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:08,033 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:08,057 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,057 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:08,124 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,144 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,144 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:08,148 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:08,148 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:08,151 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,153 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,158 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,163 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,170 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,179 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:08,183 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:08,187 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:08,197 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,198 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:08,210 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,216 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:08,216 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 20:02:08,216 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:08,217 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 20:02:08,217 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 20:02:08,217 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 20:02:08,218 INFO L87 Difference]: Start difference. First operand 86 states and 96 transitions. Second operand 8 states. [2018-01-24 20:02:08,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:08,424 INFO L93 Difference]: Finished difference Result 112 states and 125 transitions. [2018-01-24 20:02:08,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 20:02:08,424 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 20:02:08,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:08,425 INFO L225 Difference]: With dead ends: 112 [2018-01-24 20:02:08,425 INFO L226 Difference]: Without dead ends: 106 [2018-01-24 20:02:08,425 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 20:02:08,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-01-24 20:02:08,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 98. [2018-01-24 20:02:08,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-01-24 20:02:08,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 110 transitions. [2018-01-24 20:02:08,432 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 110 transitions. Word has length 32 [2018-01-24 20:02:08,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:08,433 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 110 transitions. [2018-01-24 20:02:08,433 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 20:02:08,433 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 110 transitions. [2018-01-24 20:02:08,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 20:02:08,434 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:08,434 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:08,434 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:08,434 INFO L82 PathProgramCache]: Analyzing trace with hash -203753026, now seen corresponding path program 6 times [2018-01-24 20:02:08,434 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:08,454 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:08,454 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:08,454 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:08,455 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:08,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:08,464 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:08,584 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,584 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,585 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:08,585 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:08,585 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:08,585 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,585 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:08,595 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:08,595 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:08,600 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,603 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,604 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,606 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,607 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,607 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:08,609 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:08,623 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,624 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:08,820 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,853 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:08,853 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:08,865 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:08,866 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:08,870 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,880 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,886 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,903 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:08,907 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:08,911 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:08,923 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,923 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:08,941 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:08,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:08,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 20:02:08,943 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:08,943 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 20:02:08,943 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 20:02:08,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:02:08,944 INFO L87 Difference]: Start difference. First operand 98 states and 110 transitions. Second operand 9 states. [2018-01-24 20:02:09,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:09,120 INFO L93 Difference]: Finished difference Result 125 states and 140 transitions. [2018-01-24 20:02:09,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 20:02:09,120 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 20:02:09,120 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:09,121 INFO L225 Difference]: With dead ends: 125 [2018-01-24 20:02:09,121 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 20:02:09,122 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 20:02:09,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 20:02:09,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 110. [2018-01-24 20:02:09,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 20:02:09,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 124 transitions. [2018-01-24 20:02:09,130 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 124 transitions. Word has length 37 [2018-01-24 20:02:09,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:09,130 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 124 transitions. [2018-01-24 20:02:09,130 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 20:02:09,130 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 124 transitions. [2018-01-24 20:02:09,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 20:02:09,131 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:09,131 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:09,131 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:09,131 INFO L82 PathProgramCache]: Analyzing trace with hash -1846527883, now seen corresponding path program 7 times [2018-01-24 20:02:09,132 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:09,132 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,132 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:09,132 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,132 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:09,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,140 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:09,309 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,309 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,309 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:09,309 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:09,310 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:09,310 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,310 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:09,317 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:09,318 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:09,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,326 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:09,341 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,342 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:09,453 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,473 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,473 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:09,476 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:09,476 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:09,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,490 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:09,500 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,500 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:09,508 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,510 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:09,510 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 20:02:09,510 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:09,510 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 20:02:09,511 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 20:02:09,511 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 20:02:09,511 INFO L87 Difference]: Start difference. First operand 110 states and 124 transitions. Second operand 10 states. [2018-01-24 20:02:09,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:09,724 INFO L93 Difference]: Finished difference Result 138 states and 155 transitions. [2018-01-24 20:02:09,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 20:02:09,724 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 20:02:09,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:09,725 INFO L225 Difference]: With dead ends: 138 [2018-01-24 20:02:09,725 INFO L226 Difference]: Without dead ends: 132 [2018-01-24 20:02:09,725 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 20:02:09,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-24 20:02:09,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 122. [2018-01-24 20:02:09,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 20:02:09,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 138 transitions. [2018-01-24 20:02:09,736 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 138 transitions. Word has length 42 [2018-01-24 20:02:09,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:09,736 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 138 transitions. [2018-01-24 20:02:09,736 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 20:02:09,736 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 138 transitions. [2018-01-24 20:02:09,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 20:02:09,737 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:09,737 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:09,737 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:09,737 INFO L82 PathProgramCache]: Analyzing trace with hash 2109248542, now seen corresponding path program 8 times [2018-01-24 20:02:09,738 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:09,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,738 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:09,738 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:09,738 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:09,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:09,746 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:09,866 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,867 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,867 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:09,867 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:09,867 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:09,867 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:09,867 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:09,873 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:09,873 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:09,876 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:09,881 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:09,881 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:09,883 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:09,891 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:09,891 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:10,018 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,044 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,045 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:10,048 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:10,048 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:10,051 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,058 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:10,064 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:10,068 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:10,076 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,076 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:10,100 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,102 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:10,102 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 20:02:10,102 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:10,102 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 20:02:10,102 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 20:02:10,103 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 20:02:10,103 INFO L87 Difference]: Start difference. First operand 122 states and 138 transitions. Second operand 11 states. [2018-01-24 20:02:10,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:10,450 INFO L93 Difference]: Finished difference Result 151 states and 170 transitions. [2018-01-24 20:02:10,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 20:02:10,450 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 20:02:10,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:10,452 INFO L225 Difference]: With dead ends: 151 [2018-01-24 20:02:10,452 INFO L226 Difference]: Without dead ends: 145 [2018-01-24 20:02:10,452 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 20:02:10,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-01-24 20:02:10,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 134. [2018-01-24 20:02:10,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 20:02:10,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 152 transitions. [2018-01-24 20:02:10,462 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 152 transitions. Word has length 47 [2018-01-24 20:02:10,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:10,462 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 152 transitions. [2018-01-24 20:02:10,462 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 20:02:10,462 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 152 transitions. [2018-01-24 20:02:10,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 20:02:10,465 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:10,465 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:10,465 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:10,465 INFO L82 PathProgramCache]: Analyzing trace with hash 408164885, now seen corresponding path program 9 times [2018-01-24 20:02:10,465 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:10,466 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:10,466 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:10,466 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:10,467 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:10,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:10,476 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:10,599 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,599 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,599 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:10,600 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:10,600 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:10,600 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,600 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:10,608 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:10,608 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:10,611 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,612 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,613 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,617 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,618 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,619 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,621 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,623 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:10,625 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:10,639 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,640 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:10,879 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,899 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:10,900 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:10,902 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:10,903 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:10,907 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,915 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,919 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,924 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,931 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,938 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,947 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,973 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:10,978 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:10,981 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:10,991 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:10,991 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:11,003 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,005 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:11,005 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 20:02:11,005 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:11,006 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 20:02:11,006 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 20:02:11,007 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:02:11,007 INFO L87 Difference]: Start difference. First operand 134 states and 152 transitions. Second operand 12 states. [2018-01-24 20:02:11,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:11,359 INFO L93 Difference]: Finished difference Result 164 states and 185 transitions. [2018-01-24 20:02:11,359 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 20:02:11,359 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 20:02:11,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:11,361 INFO L225 Difference]: With dead ends: 164 [2018-01-24 20:02:11,361 INFO L226 Difference]: Without dead ends: 158 [2018-01-24 20:02:11,362 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 20:02:11,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-01-24 20:02:11,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 146. [2018-01-24 20:02:11,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-01-24 20:02:11,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 166 transitions. [2018-01-24 20:02:11,370 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 166 transitions. Word has length 52 [2018-01-24 20:02:11,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:11,371 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 166 transitions. [2018-01-24 20:02:11,371 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 20:02:11,371 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 166 transitions. [2018-01-24 20:02:11,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 20:02:11,373 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:11,373 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:11,373 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:11,373 INFO L82 PathProgramCache]: Analyzing trace with hash -2136951170, now seen corresponding path program 10 times [2018-01-24 20:02:11,373 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:11,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:11,374 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:11,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:11,374 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:11,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:11,384 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:11,540 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,541 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:11,541 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:11,541 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:11,541 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:11,541 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:11,541 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:11,549 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:11,549 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:11,561 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:11,563 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:11,572 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,573 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:11,732 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,752 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:11,753 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:11,755 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:11,756 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:11,788 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:11,792 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:11,803 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,804 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:11,814 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:11,816 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:11,816 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 20:02:11,816 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:11,817 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 20:02:11,817 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 20:02:11,817 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 20:02:11,818 INFO L87 Difference]: Start difference. First operand 146 states and 166 transitions. Second operand 13 states. [2018-01-24 20:02:12,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:12,200 INFO L93 Difference]: Finished difference Result 177 states and 200 transitions. [2018-01-24 20:02:12,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 20:02:12,201 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 20:02:12,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:12,202 INFO L225 Difference]: With dead ends: 177 [2018-01-24 20:02:12,202 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 20:02:12,203 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 20:02:12,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 20:02:12,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 20:02:12,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 20:02:12,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 180 transitions. [2018-01-24 20:02:12,216 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 180 transitions. Word has length 57 [2018-01-24 20:02:12,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:12,216 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 180 transitions. [2018-01-24 20:02:12,216 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 20:02:12,216 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 180 transitions. [2018-01-24 20:02:12,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 20:02:12,217 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:12,218 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:12,218 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:12,218 INFO L82 PathProgramCache]: Analyzing trace with hash 1325560757, now seen corresponding path program 11 times [2018-01-24 20:02:12,218 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:12,219 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:12,219 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:12,219 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:12,219 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:12,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:12,227 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:12,363 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:12,364 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:12,364 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:12,364 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:12,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:12,364 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:12,369 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:12,369 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:12,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,374 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,375 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,377 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,378 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,381 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,383 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,388 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,392 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,392 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:12,395 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:12,405 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,405 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:12,633 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,654 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:12,654 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:12,658 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:12,658 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:12,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,693 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,705 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,720 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,734 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,751 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,771 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:12,778 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:12,781 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:12,796 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,796 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:12,808 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:12,809 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:12,809 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 20:02:12,810 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:12,810 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 20:02:12,810 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 20:02:12,810 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:02:12,810 INFO L87 Difference]: Start difference. First operand 158 states and 180 transitions. Second operand 14 states. [2018-01-24 20:02:13,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:13,239 INFO L93 Difference]: Finished difference Result 190 states and 215 transitions. [2018-01-24 20:02:13,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 20:02:13,240 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 20:02:13,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:13,241 INFO L225 Difference]: With dead ends: 190 [2018-01-24 20:02:13,241 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 20:02:13,241 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 20:02:13,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 20:02:13,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 170. [2018-01-24 20:02:13,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-01-24 20:02:13,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 194 transitions. [2018-01-24 20:02:13,251 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 194 transitions. Word has length 62 [2018-01-24 20:02:13,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:13,251 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 194 transitions. [2018-01-24 20:02:13,251 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 20:02:13,251 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 194 transitions. [2018-01-24 20:02:13,253 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 20:02:13,253 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:13,253 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:13,253 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:13,253 INFO L82 PathProgramCache]: Analyzing trace with hash 923361502, now seen corresponding path program 12 times [2018-01-24 20:02:13,253 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:13,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:13,254 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:13,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:13,255 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:13,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:13,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:13,485 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,485 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:13,520 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:13,520 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:13,520 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:13,520 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:13,520 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:13,525 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:13,525 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:13,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,530 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,535 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,537 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,540 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,542 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:13,544 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:13,559 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,559 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:13,763 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,783 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:13,783 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:13,786 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:13,786 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:13,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,791 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,794 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,802 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,845 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,866 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,884 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,907 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,933 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:13,940 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:13,943 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:13,972 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,972 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:13,992 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:13,994 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:13,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 20:02:13,994 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:13,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 20:02:13,995 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 20:02:13,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:02:13,995 INFO L87 Difference]: Start difference. First operand 170 states and 194 transitions. Second operand 15 states. [2018-01-24 20:02:14,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:14,438 INFO L93 Difference]: Finished difference Result 203 states and 230 transitions. [2018-01-24 20:02:14,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 20:02:14,438 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 20:02:14,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:14,439 INFO L225 Difference]: With dead ends: 203 [2018-01-24 20:02:14,439 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 20:02:14,440 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 20:02:14,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 20:02:14,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 182. [2018-01-24 20:02:14,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 20:02:14,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 208 transitions. [2018-01-24 20:02:14,448 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 208 transitions. Word has length 67 [2018-01-24 20:02:14,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:14,449 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 208 transitions. [2018-01-24 20:02:14,449 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 20:02:14,449 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 208 transitions. [2018-01-24 20:02:14,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 20:02:14,449 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:14,449 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:14,449 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:14,450 INFO L82 PathProgramCache]: Analyzing trace with hash 356861269, now seen corresponding path program 13 times [2018-01-24 20:02:14,450 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:14,450 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:14,450 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:14,450 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:14,451 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:14,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:14,459 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:14,661 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:14,661 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:14,661 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:14,661 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:14,661 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:14,661 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:14,662 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:14,666 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:14,667 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:14,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:14,676 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:14,688 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:14,688 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:14,930 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:14,951 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:14,951 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:14,954 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:14,954 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:14,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:14,973 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:14,985 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:14,985 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:15,003 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:15,004 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:15,005 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 20:02:15,005 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:15,005 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 20:02:15,005 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 20:02:15,006 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 20:02:15,006 INFO L87 Difference]: Start difference. First operand 182 states and 208 transitions. Second operand 16 states. [2018-01-24 20:02:15,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:15,528 INFO L93 Difference]: Finished difference Result 216 states and 245 transitions. [2018-01-24 20:02:15,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 20:02:15,529 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 20:02:15,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:15,530 INFO L225 Difference]: With dead ends: 216 [2018-01-24 20:02:15,530 INFO L226 Difference]: Without dead ends: 210 [2018-01-24 20:02:15,530 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 20:02:15,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-24 20:02:15,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 194. [2018-01-24 20:02:15,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-01-24 20:02:15,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 222 transitions. [2018-01-24 20:02:15,540 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 222 transitions. Word has length 72 [2018-01-24 20:02:15,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:15,540 INFO L432 AbstractCegarLoop]: Abstraction has 194 states and 222 transitions. [2018-01-24 20:02:15,540 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 20:02:15,540 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 222 transitions. [2018-01-24 20:02:15,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 20:02:15,542 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:15,542 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:15,542 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:15,542 INFO L82 PathProgramCache]: Analyzing trace with hash -1075276994, now seen corresponding path program 14 times [2018-01-24 20:02:15,542 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:15,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:15,543 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:15,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:15,544 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:15,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:15,553 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:15,747 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:15,747 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:15,747 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:15,747 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:15,747 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:15,747 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:15,747 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:15,753 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:15,753 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:15,757 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,763 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:15,764 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:15,765 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:15,784 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:15,784 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:16,041 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,061 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:16,061 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:16,065 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:16,065 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:16,069 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,079 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:16,087 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:16,090 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:16,105 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,106 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:16,119 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,120 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:16,121 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 20:02:16,121 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:16,121 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 20:02:16,121 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 20:02:16,121 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:02:16,122 INFO L87 Difference]: Start difference. First operand 194 states and 222 transitions. Second operand 17 states. [2018-01-24 20:02:16,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:16,679 INFO L93 Difference]: Finished difference Result 229 states and 260 transitions. [2018-01-24 20:02:16,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 20:02:16,680 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 20:02:16,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:16,681 INFO L225 Difference]: With dead ends: 229 [2018-01-24 20:02:16,681 INFO L226 Difference]: Without dead ends: 223 [2018-01-24 20:02:16,682 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 20:02:16,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-01-24 20:02:16,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 206. [2018-01-24 20:02:16,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-01-24 20:02:16,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 236 transitions. [2018-01-24 20:02:16,690 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 236 transitions. Word has length 77 [2018-01-24 20:02:16,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:16,691 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 236 transitions. [2018-01-24 20:02:16,691 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 20:02:16,691 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 236 transitions. [2018-01-24 20:02:16,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 20:02:16,691 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:16,691 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:16,691 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:16,692 INFO L82 PathProgramCache]: Analyzing trace with hash 904302325, now seen corresponding path program 15 times [2018-01-24 20:02:16,692 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:16,692 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:16,692 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:16,692 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:16,693 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:16,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:16,700 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:16,882 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,882 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:16,882 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:16,882 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:16,883 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:16,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:16,883 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:16,887 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:16,888 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:16,891 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,892 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,893 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,894 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,895 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,896 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,897 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,898 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,899 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,900 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,902 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,904 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,905 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,908 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,912 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:16,913 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:16,915 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:16,935 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:16,935 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:17,292 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:17,312 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:17,312 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:17,315 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:17,315 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:17,320 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,321 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,325 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,329 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,334 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,341 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,349 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,358 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,369 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,385 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,403 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,446 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,474 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,561 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:17,570 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:17,574 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:17,590 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:17,590 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:17,616 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:17,617 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:17,617 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 20:02:17,617 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:17,618 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 20:02:17,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 20:02:17,618 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 20:02:17,618 INFO L87 Difference]: Start difference. First operand 206 states and 236 transitions. Second operand 18 states. [2018-01-24 20:02:18,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:18,252 INFO L93 Difference]: Finished difference Result 242 states and 275 transitions. [2018-01-24 20:02:18,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 20:02:18,252 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 20:02:18,253 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:18,254 INFO L225 Difference]: With dead ends: 242 [2018-01-24 20:02:18,254 INFO L226 Difference]: Without dead ends: 236 [2018-01-24 20:02:18,255 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 20:02:18,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-24 20:02:18,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 218. [2018-01-24 20:02:18,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-01-24 20:02:18,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-01-24 20:02:18,265 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 82 [2018-01-24 20:02:18,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:18,265 INFO L432 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-01-24 20:02:18,265 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 20:02:18,265 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-01-24 20:02:18,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 20:02:18,266 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:18,266 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:18,266 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:18,266 INFO L82 PathProgramCache]: Analyzing trace with hash 2125745566, now seen corresponding path program 16 times [2018-01-24 20:02:18,266 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:18,267 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:18,267 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:18,267 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:18,267 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:18,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:18,275 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:18,661 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:18,662 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:18,698 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:18,698 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:18,698 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:18,698 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:18,698 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:18,705 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:18,705 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:18,724 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:18,726 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:18,743 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:18,743 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:19,111 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:19,131 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:19,132 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:19,134 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:19,135 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:19,202 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:19,206 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:19,231 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:19,231 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:19,250 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:19,252 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:19,252 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 20:02:19,252 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:19,253 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 20:02:19,253 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 20:02:19,253 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:02:19,253 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 19 states. [2018-01-24 20:02:20,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:20,082 INFO L93 Difference]: Finished difference Result 255 states and 290 transitions. [2018-01-24 20:02:20,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 20:02:20,082 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 20:02:20,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:20,083 INFO L225 Difference]: With dead ends: 255 [2018-01-24 20:02:20,084 INFO L226 Difference]: Without dead ends: 249 [2018-01-24 20:02:20,084 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 20:02:20,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-01-24 20:02:20,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 230. [2018-01-24 20:02:20,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-24 20:02:20,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 264 transitions. [2018-01-24 20:02:20,096 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 264 transitions. Word has length 87 [2018-01-24 20:02:20,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:20,097 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 264 transitions. [2018-01-24 20:02:20,097 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 20:02:20,097 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 264 transitions. [2018-01-24 20:02:20,098 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 20:02:20,098 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:20,098 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:20,098 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:20,099 INFO L82 PathProgramCache]: Analyzing trace with hash 120606869, now seen corresponding path program 17 times [2018-01-24 20:02:20,099 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:20,099 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:20,099 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:20,100 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:20,100 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:20,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:20,109 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:20,312 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,312 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:20,312 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:20,312 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:20,312 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:20,312 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:20,313 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:20,317 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:20,317 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:20,321 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,322 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,323 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,324 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,325 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,326 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,329 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,330 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,332 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,334 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,342 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,353 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,358 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:20,360 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:20,375 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,375 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:20,724 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:20,743 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:20,744 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:20,746 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:20,746 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:20,750 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,752 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,756 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,761 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,767 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,774 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,885 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:20,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:21,002 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:21,043 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:21,090 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:21,101 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:21,104 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:21,119 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:21,120 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:21,137 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:21,138 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:21,139 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 20:02:21,139 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:21,139 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 20:02:21,139 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 20:02:21,140 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:02:21,140 INFO L87 Difference]: Start difference. First operand 230 states and 264 transitions. Second operand 20 states. [2018-01-24 20:02:21,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:21,927 INFO L93 Difference]: Finished difference Result 268 states and 305 transitions. [2018-01-24 20:02:21,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 20:02:21,927 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 20:02:21,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:21,928 INFO L225 Difference]: With dead ends: 268 [2018-01-24 20:02:21,928 INFO L226 Difference]: Without dead ends: 262 [2018-01-24 20:02:21,929 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 20:02:21,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states. [2018-01-24 20:02:21,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 242. [2018-01-24 20:02:21,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 20:02:21,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 278 transitions. [2018-01-24 20:02:21,938 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 278 transitions. Word has length 92 [2018-01-24 20:02:21,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:21,939 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 278 transitions. [2018-01-24 20:02:21,939 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 20:02:21,939 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 278 transitions. [2018-01-24 20:02:21,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 20:02:21,940 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:21,941 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:21,941 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:21,941 INFO L82 PathProgramCache]: Analyzing trace with hash 2070056958, now seen corresponding path program 18 times [2018-01-24 20:02:21,941 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:21,942 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:21,942 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:21,942 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:21,942 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:21,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:21,952 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:22,258 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:22,258 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:22,258 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:22,258 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:22,258 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:22,258 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:22,258 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:22,264 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:22,264 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:22,268 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,269 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,272 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,274 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,276 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,277 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,279 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,280 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,285 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,289 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,292 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,297 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:22,298 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:22,300 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:22,317 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:22,317 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:23,121 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:23,141 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:23,141 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:23,144 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:23,144 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:23,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,150 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,154 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,159 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,203 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,225 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,295 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,323 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,357 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:23,642 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:23,646 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:23,667 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:23,668 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:23,729 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:23,731 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:23,731 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 20:02:23,731 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:23,731 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 20:02:23,732 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 20:02:23,732 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 20:02:23,732 INFO L87 Difference]: Start difference. First operand 242 states and 278 transitions. Second operand 21 states. [2018-01-24 20:02:24,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:24,611 INFO L93 Difference]: Finished difference Result 281 states and 320 transitions. [2018-01-24 20:02:24,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 20:02:24,612 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 20:02:24,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:24,613 INFO L225 Difference]: With dead ends: 281 [2018-01-24 20:02:24,613 INFO L226 Difference]: Without dead ends: 275 [2018-01-24 20:02:24,614 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 20:02:24,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states. [2018-01-24 20:02:24,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 254. [2018-01-24 20:02:24,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-01-24 20:02:24,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 292 transitions. [2018-01-24 20:02:24,626 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 292 transitions. Word has length 97 [2018-01-24 20:02:24,626 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:24,626 INFO L432 AbstractCegarLoop]: Abstraction has 254 states and 292 transitions. [2018-01-24 20:02:24,626 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 20:02:24,626 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 292 transitions. [2018-01-24 20:02:24,627 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 20:02:24,627 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:24,628 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:24,628 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:24,628 INFO L82 PathProgramCache]: Analyzing trace with hash 183274037, now seen corresponding path program 19 times [2018-01-24 20:02:24,628 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:24,629 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:24,629 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:24,629 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:24,629 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:24,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:24,640 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:24,980 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:24,980 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:24,980 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:24,980 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:24,980 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:24,980 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:24,980 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:24,985 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:24,985 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:24,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:24,998 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:25,015 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,016 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:25,516 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,535 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:25,535 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:25,538 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:25,538 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:25,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:25,563 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:25,581 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,581 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:25,602 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:25,603 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:25,603 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 20:02:25,603 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:25,604 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 20:02:25,604 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 20:02:25,604 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:02:25,604 INFO L87 Difference]: Start difference. First operand 254 states and 292 transitions. Second operand 22 states. [2018-01-24 20:02:26,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:26,538 INFO L93 Difference]: Finished difference Result 294 states and 335 transitions. [2018-01-24 20:02:26,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 20:02:26,538 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 20:02:26,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:26,539 INFO L225 Difference]: With dead ends: 294 [2018-01-24 20:02:26,539 INFO L226 Difference]: Without dead ends: 288 [2018-01-24 20:02:26,540 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 20:02:26,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-01-24 20:02:26,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 266. [2018-01-24 20:02:26,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-24 20:02:26,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 306 transitions. [2018-01-24 20:02:26,548 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 306 transitions. Word has length 102 [2018-01-24 20:02:26,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:26,548 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 306 transitions. [2018-01-24 20:02:26,548 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 20:02:26,548 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 306 transitions. [2018-01-24 20:02:26,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 20:02:26,550 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:26,550 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:26,550 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:26,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1033282978, now seen corresponding path program 20 times [2018-01-24 20:02:26,550 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:26,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:26,551 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:26,551 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:26,551 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:26,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:26,561 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:27,244 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:27,244 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:27,244 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:27,245 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:27,245 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:27,245 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:27,245 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:27,251 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:27,252 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:27,257 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:27,265 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:27,268 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:27,270 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:27,289 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:27,289 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:27,857 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:27,889 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:27,889 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:27,892 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:27,893 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:27,898 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:27,913 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:27,923 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:27,928 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:27,962 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:27,962 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:27,999 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:28,000 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:28,000 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 20:02:28,001 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:28,001 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 20:02:28,001 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 20:02:28,002 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:02:28,002 INFO L87 Difference]: Start difference. First operand 266 states and 306 transitions. Second operand 23 states. [2018-01-24 20:02:29,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:29,083 INFO L93 Difference]: Finished difference Result 307 states and 350 transitions. [2018-01-24 20:02:29,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 20:02:29,083 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 20:02:29,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:29,085 INFO L225 Difference]: With dead ends: 307 [2018-01-24 20:02:29,085 INFO L226 Difference]: Without dead ends: 301 [2018-01-24 20:02:29,086 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 20:02:29,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-01-24 20:02:29,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 278. [2018-01-24 20:02:29,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 278 states. [2018-01-24 20:02:29,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 320 transitions. [2018-01-24 20:02:29,094 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 320 transitions. Word has length 107 [2018-01-24 20:02:29,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:29,095 INFO L432 AbstractCegarLoop]: Abstraction has 278 states and 320 transitions. [2018-01-24 20:02:29,095 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 20:02:29,095 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 320 transitions. [2018-01-24 20:02:29,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 20:02:29,096 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:29,096 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:29,096 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:29,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1905968171, now seen corresponding path program 21 times [2018-01-24 20:02:29,096 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:29,097 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:29,097 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:29,097 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:29,097 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:29,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:29,110 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:29,520 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:29,520 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:29,520 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:29,520 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:29,520 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:29,520 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:29,520 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:29,525 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:29,525 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:29,529 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,530 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,530 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,531 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,533 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,534 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,536 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,539 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,541 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,543 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,547 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,549 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,551 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,555 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,558 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,562 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,566 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,570 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:29,570 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:29,572 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:29,592 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:29,592 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:30,099 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:30,119 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:30,119 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:30,122 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:30,122 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:30,126 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,135 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,162 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,173 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,188 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,206 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,248 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,315 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,359 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,403 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,454 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,593 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,785 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:30,799 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:30,803 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:30,823 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:30,824 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:30,854 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:30,856 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:30,856 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 20:02:30,856 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:30,856 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 20:02:30,857 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 20:02:30,857 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 20:02:30,857 INFO L87 Difference]: Start difference. First operand 278 states and 320 transitions. Second operand 24 states. [2018-01-24 20:02:32,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:32,171 INFO L93 Difference]: Finished difference Result 320 states and 365 transitions. [2018-01-24 20:02:32,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 20:02:32,173 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 20:02:32,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:32,174 INFO L225 Difference]: With dead ends: 320 [2018-01-24 20:02:32,174 INFO L226 Difference]: Without dead ends: 314 [2018-01-24 20:02:32,175 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 20:02:32,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-01-24 20:02:32,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 290. [2018-01-24 20:02:32,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-01-24 20:02:32,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 334 transitions. [2018-01-24 20:02:32,183 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 334 transitions. Word has length 112 [2018-01-24 20:02:32,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:32,183 INFO L432 AbstractCegarLoop]: Abstraction has 290 states and 334 transitions. [2018-01-24 20:02:32,183 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 20:02:32,183 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 334 transitions. [2018-01-24 20:02:32,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 20:02:32,184 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:32,184 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:32,184 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:32,184 INFO L82 PathProgramCache]: Analyzing trace with hash -994136898, now seen corresponding path program 22 times [2018-01-24 20:02:32,184 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:32,185 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:32,185 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:32,185 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:32,185 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:32,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:32,191 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:32,487 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:32,487 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:32,487 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:32,487 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:32,487 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:32,487 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:32,487 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:32,492 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:32,492 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:32,517 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:32,519 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:32,540 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:32,541 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:33,102 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:33,122 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:33,122 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:33,126 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:33,126 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:33,244 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:33,249 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:33,281 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:33,281 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:33,307 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:33,309 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:33,309 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 20:02:33,309 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:33,309 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 20:02:33,309 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 20:02:33,310 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 20:02:33,310 INFO L87 Difference]: Start difference. First operand 290 states and 334 transitions. Second operand 25 states. [2018-01-24 20:02:34,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:34,555 INFO L93 Difference]: Finished difference Result 333 states and 380 transitions. [2018-01-24 20:02:34,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 20:02:34,555 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 20:02:34,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:34,556 INFO L225 Difference]: With dead ends: 333 [2018-01-24 20:02:34,556 INFO L226 Difference]: Without dead ends: 327 [2018-01-24 20:02:34,557 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 20:02:34,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-01-24 20:02:34,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 302. [2018-01-24 20:02:34,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-01-24 20:02:34,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 348 transitions. [2018-01-24 20:02:34,564 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 348 transitions. Word has length 117 [2018-01-24 20:02:34,564 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:34,565 INFO L432 AbstractCegarLoop]: Abstraction has 302 states and 348 transitions. [2018-01-24 20:02:34,565 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 20:02:34,565 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 348 transitions. [2018-01-24 20:02:34,565 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 20:02:34,565 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:34,565 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:34,566 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:34,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1248093557, now seen corresponding path program 23 times [2018-01-24 20:02:34,566 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:34,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:34,566 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:34,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:34,566 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:34,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:34,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:34,947 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:34,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:34,947 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:34,947 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:34,947 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:34,947 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:34,947 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:34,952 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:34,952 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:34,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,989 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:34,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,010 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,017 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,026 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:35,028 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:35,050 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:35,050 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:35,636 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:35,656 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:35,656 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:35,659 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:35,659 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:35,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,679 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,686 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,693 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,713 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,729 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,750 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,768 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,903 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:35,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,039 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,221 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,296 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,469 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:36,490 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:36,494 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:36,516 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:36,516 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:36,547 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:36,549 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:36,549 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 20:02:36,549 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:36,550 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 20:02:36,550 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 20:02:36,550 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 20:02:36,550 INFO L87 Difference]: Start difference. First operand 302 states and 348 transitions. Second operand 26 states. [2018-01-24 20:02:37,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:37,932 INFO L93 Difference]: Finished difference Result 346 states and 395 transitions. [2018-01-24 20:02:37,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 20:02:37,932 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 20:02:37,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:37,933 INFO L225 Difference]: With dead ends: 346 [2018-01-24 20:02:37,934 INFO L226 Difference]: Without dead ends: 340 [2018-01-24 20:02:37,934 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 20:02:37,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-01-24 20:02:37,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 314. [2018-01-24 20:02:37,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 314 states. [2018-01-24 20:02:37,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 362 transitions. [2018-01-24 20:02:37,946 INFO L78 Accepts]: Start accepts. Automaton has 314 states and 362 transitions. Word has length 122 [2018-01-24 20:02:37,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:37,947 INFO L432 AbstractCegarLoop]: Abstraction has 314 states and 362 transitions. [2018-01-24 20:02:37,947 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 20:02:37,947 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 362 transitions. [2018-01-24 20:02:37,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 20:02:37,948 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:37,949 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:37,949 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:37,949 INFO L82 PathProgramCache]: Analyzing trace with hash -1210546402, now seen corresponding path program 24 times [2018-01-24 20:02:37,949 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:37,950 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:37,950 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:37,950 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:37,950 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:37,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:37,960 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:38,348 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:38,352 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:38,352 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:38,352 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:38,352 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:38,352 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:38,353 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:38,357 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:38,357 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:38,361 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,362 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,363 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,363 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,364 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,365 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,366 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,367 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,368 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,369 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,370 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,372 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,373 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,376 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,380 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,382 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,385 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,390 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,393 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,404 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:38,405 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:38,408 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:38,469 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:38,469 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:39,303 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:39,323 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:39,323 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:39,326 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 20:02:39,326 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 20:02:39,330 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,332 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,335 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,339 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,344 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,349 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,355 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,365 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,377 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,414 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,438 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,467 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,576 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,686 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,846 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:39,963 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:40,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:40,373 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:40,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:40,844 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 20:02:40,859 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:40,864 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:40,889 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:40,889 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:40,920 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:40,922 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:40,922 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 20:02:40,922 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:40,923 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 20:02:40,923 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 20:02:40,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 20:02:40,924 INFO L87 Difference]: Start difference. First operand 314 states and 362 transitions. Second operand 27 states. [2018-01-24 20:02:42,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:42,416 INFO L93 Difference]: Finished difference Result 359 states and 410 transitions. [2018-01-24 20:02:42,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 20:02:42,416 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 20:02:42,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:42,418 INFO L225 Difference]: With dead ends: 359 [2018-01-24 20:02:42,418 INFO L226 Difference]: Without dead ends: 353 [2018-01-24 20:02:42,419 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 20:02:42,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states. [2018-01-24 20:02:42,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 326. [2018-01-24 20:02:42,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 20:02:42,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 376 transitions. [2018-01-24 20:02:42,427 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 376 transitions. Word has length 127 [2018-01-24 20:02:42,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:42,427 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 376 transitions. [2018-01-24 20:02:42,427 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 20:02:42,427 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 376 transitions. [2018-01-24 20:02:42,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 20:02:42,428 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:42,428 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:42,428 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:42,429 INFO L82 PathProgramCache]: Analyzing trace with hash 53741333, now seen corresponding path program 25 times [2018-01-24 20:02:42,429 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:42,429 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:42,429 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:42,429 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:42,429 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:42,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:42,436 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:42,802 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:42,802 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:42,803 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:42,803 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:42,803 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:42,803 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:42,803 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:42,808 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:42,808 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:42,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:42,834 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:42,875 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:42,875 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:43,689 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,708 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:43,709 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:43,712 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:43,712 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 20:02:43,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:43,744 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:43,773 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,773 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:43,810 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:43,811 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:43,811 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 20:02:43,811 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:43,811 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 20:02:43,812 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 20:02:43,813 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 20:02:43,813 INFO L87 Difference]: Start difference. First operand 326 states and 376 transitions. Second operand 28 states. [2018-01-24 20:02:45,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:45,338 INFO L93 Difference]: Finished difference Result 372 states and 425 transitions. [2018-01-24 20:02:45,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 20:02:45,338 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 20:02:45,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:45,340 INFO L225 Difference]: With dead ends: 372 [2018-01-24 20:02:45,340 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 20:02:45,340 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 20:02:45,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 20:02:45,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 338. [2018-01-24 20:02:45,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 338 states. [2018-01-24 20:02:45,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 338 states to 338 states and 390 transitions. [2018-01-24 20:02:45,348 INFO L78 Accepts]: Start accepts. Automaton has 338 states and 390 transitions. Word has length 132 [2018-01-24 20:02:45,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:45,349 INFO L432 AbstractCegarLoop]: Abstraction has 338 states and 390 transitions. [2018-01-24 20:02:45,349 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 20:02:45,349 INFO L276 IsEmpty]: Start isEmpty. Operand 338 states and 390 transitions. [2018-01-24 20:02:45,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 20:02:45,350 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:45,350 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:45,350 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:45,350 INFO L82 PathProgramCache]: Analyzing trace with hash -173217410, now seen corresponding path program 26 times [2018-01-24 20:02:45,350 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:45,351 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:45,351 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 20:02:45,351 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:45,351 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:45,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:45,357 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:45,757 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:45,757 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:45,757 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:45,757 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:45,758 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:45,758 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:45,758 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:45,764 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:45,764 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:45,768 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:45,779 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:45,780 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:45,783 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:45,815 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:45,815 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:46,550 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:46,569 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:46,569 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:46,572 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 20:02:46,572 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:46,579 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:46,601 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:46,615 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:46,619 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:46,648 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:46,648 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:46,685 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:46,686 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:46,686 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 20:02:46,686 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:46,686 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 20:02:46,687 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 20:02:46,687 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 20:02:46,687 INFO L87 Difference]: Start difference. First operand 338 states and 390 transitions. Second operand 29 states. [2018-01-24 20:02:48,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:48,276 INFO L93 Difference]: Finished difference Result 385 states and 440 transitions. [2018-01-24 20:02:48,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 20:02:48,276 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 137 [2018-01-24 20:02:48,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:48,278 INFO L225 Difference]: With dead ends: 385 [2018-01-24 20:02:48,278 INFO L226 Difference]: Without dead ends: 379 [2018-01-24 20:02:48,279 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 574 GetRequests, 518 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 20:02:48,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2018-01-24 20:02:48,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 350. [2018-01-24 20:02:48,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2018-01-24 20:02:48,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 404 transitions. [2018-01-24 20:02:48,291 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 404 transitions. Word has length 137 [2018-01-24 20:02:48,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:48,292 INFO L432 AbstractCegarLoop]: Abstraction has 350 states and 404 transitions. [2018-01-24 20:02:48,292 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 20:02:48,292 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 404 transitions. [2018-01-24 20:02:48,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 20:02:48,293 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:48,294 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:48,294 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:48,294 INFO L82 PathProgramCache]: Analyzing trace with hash 681451701, now seen corresponding path program 27 times [2018-01-24 20:02:48,294 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:48,295 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:48,295 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:48,295 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:48,295 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:48,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:48,306 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:49,009 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:49,010 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:49,044 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:49,044 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:49,044 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:49,044 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:49,044 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:49,051 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:49,051 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:49,057 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,064 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,070 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,072 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,077 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,079 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,083 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,087 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,090 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,111 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,119 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,124 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,133 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,158 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:49,167 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:49,169 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:49,206 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:49,206 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:50,013 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:50,034 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:50,034 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:50,037 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 20:02:50,038 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 20:02:50,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,047 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,052 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,072 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,109 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,128 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,172 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,199 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,239 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,387 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,450 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,536 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,633 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,728 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:50,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:51,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:51,317 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:51,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:51,705 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 20:02:51,734 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:51,740 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:51,784 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:51,784 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:51,818 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:51,820 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:51,820 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 57 [2018-01-24 20:02:51,820 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:51,821 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 20:02:51,821 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 20:02:51,821 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 20:02:51,822 INFO L87 Difference]: Start difference. First operand 350 states and 404 transitions. Second operand 30 states. [2018-01-24 20:02:53,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:53,627 INFO L93 Difference]: Finished difference Result 398 states and 455 transitions. [2018-01-24 20:02:53,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 20:02:53,627 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 142 [2018-01-24 20:02:53,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:53,629 INFO L225 Difference]: With dead ends: 398 [2018-01-24 20:02:53,629 INFO L226 Difference]: Without dead ends: 392 [2018-01-24 20:02:53,629 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 595 GetRequests, 537 SyntacticMatches, 2 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 20:02:53,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states. [2018-01-24 20:02:53,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 362. [2018-01-24 20:02:53,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 362 states. [2018-01-24 20:02:53,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 362 states to 362 states and 418 transitions. [2018-01-24 20:02:53,639 INFO L78 Accepts]: Start accepts. Automaton has 362 states and 418 transitions. Word has length 142 [2018-01-24 20:02:53,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:53,639 INFO L432 AbstractCegarLoop]: Abstraction has 362 states and 418 transitions. [2018-01-24 20:02:53,639 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 20:02:53,639 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 418 transitions. [2018-01-24 20:02:53,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 20:02:53,640 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:53,641 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:53,641 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:53,641 INFO L82 PathProgramCache]: Analyzing trace with hash 1555157982, now seen corresponding path program 28 times [2018-01-24 20:02:53,641 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:53,642 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:53,642 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:53,642 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:53,642 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:53,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:53,649 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:54,157 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:54,158 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:54,188 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:54,188 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:54,188 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:54,188 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:54,189 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:54,193 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:54,194 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:54,230 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:54,233 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:54,263 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:54,264 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:55,132 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:55,153 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:55,153 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 20:02:55,156 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 20:02:55,156 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 20:02:55,367 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:55,372 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:55,406 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:55,406 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 20:02:55,443 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:55,445 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 20:02:55,445 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 59 [2018-01-24 20:02:55,445 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 20:02:55,446 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-24 20:02:55,446 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-24 20:02:55,446 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 20:02:55,446 INFO L87 Difference]: Start difference. First operand 362 states and 418 transitions. Second operand 31 states. [2018-01-24 20:02:57,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 20:02:57,355 INFO L93 Difference]: Finished difference Result 411 states and 470 transitions. [2018-01-24 20:02:57,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 20:02:57,355 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 147 [2018-01-24 20:02:57,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 20:02:57,357 INFO L225 Difference]: With dead ends: 411 [2018-01-24 20:02:57,357 INFO L226 Difference]: Without dead ends: 405 [2018-01-24 20:02:57,358 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 616 GetRequests, 556 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 20:02:57,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states. [2018-01-24 20:02:57,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 374. [2018-01-24 20:02:57,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-01-24 20:02:57,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 432 transitions. [2018-01-24 20:02:57,367 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 432 transitions. Word has length 147 [2018-01-24 20:02:57,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 20:02:57,368 INFO L432 AbstractCegarLoop]: Abstraction has 374 states and 432 transitions. [2018-01-24 20:02:57,368 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-24 20:02:57,368 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 432 transitions. [2018-01-24 20:02:57,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-24 20:02:57,369 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 20:02:57,369 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1] [2018-01-24 20:02:57,369 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 20:02:57,369 INFO L82 PathProgramCache]: Analyzing trace with hash 1978446421, now seen corresponding path program 29 times [2018-01-24 20:02:57,369 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 20:02:57,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:57,370 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 20:02:57,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 20:02:57,370 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 20:02:57,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 20:02:57,378 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 20:02:58,347 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 0 proven. 2088 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:58,348 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:58,348 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 20:02:58,348 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 20:02:58,348 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 20:02:58,348 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 20:02:58,348 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 20:02:58,353 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 20:02:58,353 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 20:02:58,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,358 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,364 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,370 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,375 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,378 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,381 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,385 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,393 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,397 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,403 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,409 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,416 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,423 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,477 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,491 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,506 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 20:02:58,508 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 20:02:58,511 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 20:02:58,571 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 0 proven. 2088 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 20:02:58,571 INFO L314 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-01-24 20:02:58,881 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-24 20:02:58,882 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 20:02:58,885 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 20:02:58,885 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 08:02:58 BoogieIcfgContainer [2018-01-24 20:02:58,885 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 20:02:58,886 INFO L168 Benchmark]: Toolchain (without parser) took 53799.74 ms. Allocated memory was 300.9 MB in the beginning and 732.4 MB in the end (delta: 431.5 MB). Free memory was 260.2 MB in the beginning and 371.9 MB in the end (delta: -111.7 MB). Peak memory consumption was 319.8 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:58,886 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 300.9 MB. Free memory is still 265.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 20:02:58,887 INFO L168 Benchmark]: CACSL2BoogieTranslator took 183.46 ms. Allocated memory is still 300.9 MB. Free memory was 259.2 MB in the beginning and 252.1 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:58,887 INFO L168 Benchmark]: Boogie Preprocessor took 25.43 ms. Allocated memory is still 300.9 MB. Free memory was 252.1 MB in the beginning and 250.1 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:58,887 INFO L168 Benchmark]: RCFGBuilder took 198.09 ms. Allocated memory is still 300.9 MB. Free memory was 250.1 MB in the beginning and 238.4 MB in the end (delta: 11.7 MB). Peak memory consumption was 11.7 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:58,888 INFO L168 Benchmark]: TraceAbstraction took 53382.76 ms. Allocated memory was 300.9 MB in the beginning and 732.4 MB in the end (delta: 431.5 MB). Free memory was 238.4 MB in the beginning and 371.9 MB in the end (delta: -133.6 MB). Peak memory consumption was 297.9 MB. Max. memory is 5.3 GB. [2018-01-24 20:02:58,890 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 300.9 MB. Free memory is still 265.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 183.46 ms. Allocated memory is still 300.9 MB. Free memory was 259.2 MB in the beginning and 252.1 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 25.43 ms. Allocated memory is still 300.9 MB. Free memory was 252.1 MB in the beginning and 250.1 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 198.09 ms. Allocated memory is still 300.9 MB. Free memory was 250.1 MB in the beginning and 238.4 MB in the end (delta: 11.7 MB). Peak memory consumption was 11.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 53382.76 ms. Allocated memory was 300.9 MB in the beginning and 732.4 MB in the end (delta: 431.5 MB). Free memory was 238.4 MB in the beginning and 371.9 MB in the end (delta: -133.6 MB). Peak memory consumption was 297.9 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 5.055932 RENAME_VARIABLES(MILLISECONDS) : 0.462664 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 4.985312 PROJECTAWAY(MILLISECONDS) : 8.443230 ADD_WEAK_EQUALITY(MILLISECONDS) : 2.530631 DISJOIN(MILLISECONDS) : 0.229887 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.499353 ADD_EQUALITY(MILLISECONDS) : 0.052881 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.735540 #CONJOIN_DISJUNCTIVE : 36 #RENAME_VARIABLES : 82 #UNFREEZE : 0 #CONJOIN : 48 #PROJECTAWAY : 57 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 77 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 45 known predicates. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 45 known predicates. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 45 known predicates. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 45 known predicates. - TimeoutResultAtElement [Line: 12]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 12). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 45 known predicates. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 45 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 34 locations, 6 error locations. TIMEOUT Result, 53.3s OverallTime, 30 OverallIterations, 30 TraceHistogramMax, 21.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4790 SDtfs, 2700 SDslu, 68887 SDs, 0 SdLazy, 62094 SolverSat, 1015 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 17.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 9312 GetRequests, 8387 SyntacticMatches, 56 SemanticMatches, 869 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 434 ImplicationChecksByTransitivity, 16.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=374occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.3s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 29 MinimizatonAttempts, 493 StatesRemovedByMinimization, 29 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 7.7s SatisfiabilityAnalysisTime, 19.9s InterpolantComputationTime, 6685 NumberOfCodeBlocks, 6685 NumberOfCodeBlocksAsserted, 487 NumberOfCheckSat, 10996 ConstructedInterpolants, 0 QuantifiedInterpolants, 8194098 SizeOfPredicates, 0 NumberOfNonLiveVariables, 6468 ConjunctsInSsa, 1792 ConjunctsInUnsatCore, 141 InterpolantComputations, 1 PerfectInterpolantSequences, 0/95410 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_20-02-58-898.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_20-02-58-898.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_20-02-58-898.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_mostprecise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_20-02-58-898.csv Completed graceful shutdown