java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf -i ../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 23:25:05,910 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 23:25:05,911 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 23:25:05,924 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 23:25:05,925 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 23:25:05,925 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 23:25:05,926 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 23:25:05,928 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 23:25:05,930 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 23:25:05,931 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 23:25:05,932 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 23:25:05,932 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 23:25:05,933 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 23:25:05,934 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 23:25:05,935 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 23:25:05,937 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 23:25:05,940 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 23:25:05,942 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 23:25:05,943 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 23:25:05,945 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 23:25:05,948 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 23:25:05,949 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 23:25:05,949 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 23:25:05,950 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 23:25:05,951 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 23:25:05,953 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 23:25:05,953 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 23:25:05,954 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 23:25:05,954 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 23:25:05,954 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 23:25:05,955 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 23:25:05,955 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf [2018-01-24 23:25:05,965 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 23:25:05,966 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 23:25:05,966 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 23:25:05,967 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 23:25:05,967 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 23:25:05,967 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 23:25:05,967 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 23:25:05,967 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 23:25:05,968 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 23:25:05,969 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 23:25:05,969 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 23:25:05,969 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 23:25:05,969 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 23:25:05,969 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 23:25:05,970 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 23:25:05,970 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 23:25:05,970 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 23:25:05,970 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 23:25:05,970 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 23:25:05,971 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 23:25:05,971 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 23:25:05,971 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 23:25:05,971 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 23:25:05,971 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 23:25:05,972 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 23:25:05,972 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 23:25:05,972 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 23:25:05,972 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 23:25:05,972 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 23:25:05,973 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 23:25:05,973 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 23:25:05,973 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 23:25:05,973 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 23:25:05,973 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 23:25:05,974 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 23:25:05,975 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 23:25:06,011 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 23:25:06,024 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 23:25:06,029 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 23:25:06,031 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 23:25:06,031 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 23:25:06,032 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sanfoundry_24_false-valid-deref.i [2018-01-24 23:25:06,170 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 23:25:06,175 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 23:25:06,175 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 23:25:06,175 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 23:25:06,181 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 23:25:06,182 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,185 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@700b35a5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06, skipping insertion in model container [2018-01-24 23:25:06,185 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,199 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 23:25:06,213 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 23:25:06,332 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 23:25:06,346 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 23:25:06,352 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06 WrapperNode [2018-01-24 23:25:06,352 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 23:25:06,353 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 23:25:06,353 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 23:25:06,353 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 23:25:06,365 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,365 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,372 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,373 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,375 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,379 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,380 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... [2018-01-24 23:25:06,382 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 23:25:06,382 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 23:25:06,383 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 23:25:06,383 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 23:25:06,384 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 23:25:06,430 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 23:25:06,431 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 23:25:06,431 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 23:25:06,431 INFO L136 BoogieDeclarations]: Found implementation of procedure printEven [2018-01-24 23:25:06,431 INFO L136 BoogieDeclarations]: Found implementation of procedure printOdd [2018-01-24 23:25:06,431 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 23:25:06,431 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 23:25:06,432 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 23:25:06,432 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-24 23:25:06,432 INFO L128 BoogieDeclarations]: Found specification of procedure printEven [2018-01-24 23:25:06,432 INFO L128 BoogieDeclarations]: Found specification of procedure printOdd [2018-01-24 23:25:06,432 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 23:25:06,432 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 23:25:06,433 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 23:25:06,574 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 23:25:06,575 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 11:25:06 BoogieIcfgContainer [2018-01-24 23:25:06,575 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 23:25:06,576 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 23:25:06,577 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 23:25:06,579 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 23:25:06,579 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 11:25:06" (1/3) ... [2018-01-24 23:25:06,581 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e9d5320 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 11:25:06, skipping insertion in model container [2018-01-24 23:25:06,581 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:25:06" (2/3) ... [2018-01-24 23:25:06,581 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e9d5320 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 11:25:06, skipping insertion in model container [2018-01-24 23:25:06,581 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 11:25:06" (3/3) ... [2018-01-24 23:25:06,584 INFO L105 eAbstractionObserver]: Analyzing ICFG sanfoundry_24_false-valid-deref.i [2018-01-24 23:25:06,595 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 23:25:06,604 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 4 error locations. [2018-01-24 23:25:06,655 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 23:25:06,655 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 23:25:06,656 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 23:25:06,656 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 23:25:06,656 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 23:25:06,656 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 23:25:06,656 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 23:25:06,656 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 23:25:06,657 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 23:25:06,679 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states. [2018-01-24 23:25:06,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-24 23:25:06,687 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:06,689 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:06,689 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:06,693 INFO L82 PathProgramCache]: Analyzing trace with hash 529177341, now seen corresponding path program 1 times [2018-01-24 23:25:06,695 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:06,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:06,740 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:06,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:06,740 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:06,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:06,780 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:06,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:06,846 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 23:25:06,846 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 23:25:06,846 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 23:25:06,848 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 23:25:06,860 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 23:25:06,861 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 23:25:06,863 INFO L87 Difference]: Start difference. First operand 42 states. Second operand 3 states. [2018-01-24 23:25:06,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:06,985 INFO L93 Difference]: Finished difference Result 97 states and 129 transitions. [2018-01-24 23:25:06,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 23:25:06,987 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-01-24 23:25:06,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:06,995 INFO L225 Difference]: With dead ends: 97 [2018-01-24 23:25:06,995 INFO L226 Difference]: Without dead ends: 51 [2018-01-24 23:25:07,000 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 23:25:07,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-01-24 23:25:07,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 46. [2018-01-24 23:25:07,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-24 23:25:07,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 53 transitions. [2018-01-24 23:25:07,103 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 53 transitions. Word has length 8 [2018-01-24 23:25:07,104 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:07,104 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 53 transitions. [2018-01-24 23:25:07,104 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 23:25:07,104 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 53 transitions. [2018-01-24 23:25:07,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-01-24 23:25:07,105 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:07,106 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:07,106 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:07,106 INFO L82 PathProgramCache]: Analyzing trace with hash -2078569521, now seen corresponding path program 1 times [2018-01-24 23:25:07,106 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:07,108 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:07,108 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:07,108 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:07,108 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:07,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:07,126 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:07,221 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:07,222 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:07,223 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 14 with the following transitions: [2018-01-24 23:25:07,225 INFO L201 CegarAbsIntRunner]: [0], [10], [14], [19], [20], [21], [29], [31], [74], [75], [76] [2018-01-24 23:25:07,303 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 23:25:07,303 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 23:25:07,455 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 23:25:07,460 INFO L268 AbstractInterpreter]: Visited 11 different actions 17 times. Merged at 6 different actions 6 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 5 variables. [2018-01-24 23:25:07,480 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 23:25:07,480 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:07,480 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:07,490 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:07,490 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:07,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:07,510 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:07,536 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,537 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:07,615 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,641 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:07,641 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:07,646 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:07,646 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:07,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:07,670 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:07,680 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,681 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:07,697 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,699 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:07,699 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 23:25:07,699 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:07,700 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 23:25:07,701 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 23:25:07,701 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 23:25:07,701 INFO L87 Difference]: Start difference. First operand 46 states and 53 transitions. Second operand 4 states. [2018-01-24 23:25:07,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:07,850 INFO L93 Difference]: Finished difference Result 70 states and 84 transitions. [2018-01-24 23:25:07,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 23:25:07,850 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-01-24 23:25:07,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:07,851 INFO L225 Difference]: With dead ends: 70 [2018-01-24 23:25:07,851 INFO L226 Difference]: Without dead ends: 66 [2018-01-24 23:25:07,852 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 23:25:07,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-24 23:25:07,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 60. [2018-01-24 23:25:07,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 23:25:07,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 72 transitions. [2018-01-24 23:25:07,860 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 72 transitions. Word has length 13 [2018-01-24 23:25:07,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:07,861 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 72 transitions. [2018-01-24 23:25:07,861 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 23:25:07,861 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 72 transitions. [2018-01-24 23:25:07,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-01-24 23:25:07,862 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:07,862 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:07,862 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:07,862 INFO L82 PathProgramCache]: Analyzing trace with hash 1794788925, now seen corresponding path program 2 times [2018-01-24 23:25:07,862 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:07,863 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:07,863 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:07,863 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:07,863 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:07,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:07,873 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:07,936 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,936 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:07,936 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:07,937 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:07,937 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:07,937 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:07,937 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:07,947 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:07,947 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:07,954 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:07,957 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:07,958 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:07,959 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:07,971 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:07,971 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:08,115 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,149 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:08,149 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:08,152 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:08,152 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:08,156 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:08,160 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:08,164 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:08,167 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:08,174 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,174 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:08,191 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,192 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:08,192 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 23:25:08,192 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:08,193 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 23:25:08,193 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 23:25:08,193 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 23:25:08,194 INFO L87 Difference]: Start difference. First operand 60 states and 72 transitions. Second operand 5 states. [2018-01-24 23:25:08,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:08,330 INFO L93 Difference]: Finished difference Result 85 states and 104 transitions. [2018-01-24 23:25:08,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 23:25:08,330 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 18 [2018-01-24 23:25:08,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:08,332 INFO L225 Difference]: With dead ends: 85 [2018-01-24 23:25:08,332 INFO L226 Difference]: Without dead ends: 81 [2018-01-24 23:25:08,333 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 66 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 23:25:08,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-24 23:25:08,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 74. [2018-01-24 23:25:08,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 23:25:08,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 91 transitions. [2018-01-24 23:25:08,344 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 91 transitions. Word has length 18 [2018-01-24 23:25:08,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:08,344 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 91 transitions. [2018-01-24 23:25:08,344 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 23:25:08,345 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 91 transitions. [2018-01-24 23:25:08,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-01-24 23:25:08,346 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:08,346 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:08,346 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:08,346 INFO L82 PathProgramCache]: Analyzing trace with hash -424025969, now seen corresponding path program 3 times [2018-01-24 23:25:08,346 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:08,347 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:08,347 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:08,347 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:08,347 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:08,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:08,361 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:08,473 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,474 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:08,474 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:08,474 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:08,474 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:08,474 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:08,474 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:08,480 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:08,480 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:08,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,487 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,489 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,491 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,491 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:08,493 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:08,502 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,503 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:08,580 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,613 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:08,613 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:08,619 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:08,619 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:08,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,627 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,633 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:08,644 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:08,647 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:08,655 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,655 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:08,666 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:08,668 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:08,668 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 23:25:08,668 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:08,668 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 23:25:08,669 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 23:25:08,669 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 23:25:08,669 INFO L87 Difference]: Start difference. First operand 74 states and 91 transitions. Second operand 6 states. [2018-01-24 23:25:08,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:08,871 INFO L93 Difference]: Finished difference Result 100 states and 124 transitions. [2018-01-24 23:25:08,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 23:25:08,887 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-01-24 23:25:08,887 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:08,888 INFO L225 Difference]: With dead ends: 100 [2018-01-24 23:25:08,888 INFO L226 Difference]: Without dead ends: 96 [2018-01-24 23:25:08,889 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 85 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 23:25:08,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-24 23:25:08,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 88. [2018-01-24 23:25:08,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-24 23:25:08,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 110 transitions. [2018-01-24 23:25:08,900 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 110 transitions. Word has length 23 [2018-01-24 23:25:08,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:08,901 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 110 transitions. [2018-01-24 23:25:08,901 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 23:25:08,901 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 110 transitions. [2018-01-24 23:25:08,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-24 23:25:08,903 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:08,903 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:08,903 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:08,903 INFO L82 PathProgramCache]: Analyzing trace with hash -1714228867, now seen corresponding path program 4 times [2018-01-24 23:25:08,903 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:08,904 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:08,904 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:08,905 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:08,905 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:08,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:08,919 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:09,016 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,016 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:09,016 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:09,017 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:09,017 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:09,017 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:09,017 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:09,026 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:09,026 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:09,034 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:09,036 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:09,044 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,044 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:09,130 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,151 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:09,151 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:09,154 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:09,154 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:09,172 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:09,175 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:09,183 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,183 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:09,196 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,197 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:09,197 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 23:25:09,197 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:09,198 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 23:25:09,198 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 23:25:09,198 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 23:25:09,198 INFO L87 Difference]: Start difference. First operand 88 states and 110 transitions. Second operand 7 states. [2018-01-24 23:25:09,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:09,406 INFO L93 Difference]: Finished difference Result 115 states and 144 transitions. [2018-01-24 23:25:09,407 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 23:25:09,407 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 28 [2018-01-24 23:25:09,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:09,408 INFO L225 Difference]: With dead ends: 115 [2018-01-24 23:25:09,408 INFO L226 Difference]: Without dead ends: 111 [2018-01-24 23:25:09,409 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 116 GetRequests, 104 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 23:25:09,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-01-24 23:25:09,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 102. [2018-01-24 23:25:09,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-01-24 23:25:09,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 129 transitions. [2018-01-24 23:25:09,421 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 129 transitions. Word has length 28 [2018-01-24 23:25:09,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:09,422 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 129 transitions. [2018-01-24 23:25:09,422 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 23:25:09,422 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 129 transitions. [2018-01-24 23:25:09,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-01-24 23:25:09,424 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:09,424 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:09,424 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:09,424 INFO L82 PathProgramCache]: Analyzing trace with hash -771406513, now seen corresponding path program 5 times [2018-01-24 23:25:09,424 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:09,425 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:09,425 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:09,425 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:09,425 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:09,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:09,440 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:09,553 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,553 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:09,553 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:09,553 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:09,553 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:09,553 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:09,553 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:09,561 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:09,561 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:09,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,567 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,569 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,575 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,575 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:09,577 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:09,589 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,589 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:09,676 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,697 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:09,697 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:09,701 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:09,702 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:09,705 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,708 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,713 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,722 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,729 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,739 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:09,745 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:09,749 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:09,766 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,766 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:09,788 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 0 proven. 65 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:09,791 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:09,791 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 23:25:09,791 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:09,792 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 23:25:09,792 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 23:25:09,792 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 23:25:09,793 INFO L87 Difference]: Start difference. First operand 102 states and 129 transitions. Second operand 8 states. [2018-01-24 23:25:10,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:10,097 INFO L93 Difference]: Finished difference Result 130 states and 164 transitions. [2018-01-24 23:25:10,098 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 23:25:10,098 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 33 [2018-01-24 23:25:10,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:10,100 INFO L225 Difference]: With dead ends: 130 [2018-01-24 23:25:10,100 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 23:25:10,100 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 123 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 23:25:10,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 23:25:10,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 116. [2018-01-24 23:25:10,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-01-24 23:25:10,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 148 transitions. [2018-01-24 23:25:10,113 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 148 transitions. Word has length 33 [2018-01-24 23:25:10,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:10,114 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 148 transitions. [2018-01-24 23:25:10,114 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 23:25:10,114 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 148 transitions. [2018-01-24 23:25:10,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-24 23:25:10,116 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:10,116 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:10,116 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:10,116 INFO L82 PathProgramCache]: Analyzing trace with hash -240614211, now seen corresponding path program 6 times [2018-01-24 23:25:10,117 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:10,117 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:10,117 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:10,118 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:10,118 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:10,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:10,132 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:10,271 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:10,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:10,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:10,272 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:10,272 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:10,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:10,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:10,282 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:10,283 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:10,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,289 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,292 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,295 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,297 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,298 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:10,300 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:10,311 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:10,311 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:10,438 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:10,459 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:10,459 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:10,463 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:10,463 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:10,467 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,469 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,476 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,484 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,509 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:10,516 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:10,519 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:10,526 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:10,527 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:10,534 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 93 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:10,535 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:10,535 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 23:25:10,535 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:10,536 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 23:25:10,536 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 23:25:10,536 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:25:10,537 INFO L87 Difference]: Start difference. First operand 116 states and 148 transitions. Second operand 9 states. [2018-01-24 23:25:10,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:10,856 INFO L93 Difference]: Finished difference Result 145 states and 184 transitions. [2018-01-24 23:25:10,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 23:25:10,856 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-01-24 23:25:10,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:10,857 INFO L225 Difference]: With dead ends: 145 [2018-01-24 23:25:10,857 INFO L226 Difference]: Without dead ends: 141 [2018-01-24 23:25:10,858 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 142 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:25:10,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-01-24 23:25:10,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 130. [2018-01-24 23:25:10,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-24 23:25:10,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 167 transitions. [2018-01-24 23:25:10,870 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 167 transitions. Word has length 38 [2018-01-24 23:25:10,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:10,870 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 167 transitions. [2018-01-24 23:25:10,870 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 23:25:10,871 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 167 transitions. [2018-01-24 23:25:10,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-01-24 23:25:10,873 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:10,873 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:10,873 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:10,873 INFO L82 PathProgramCache]: Analyzing trace with hash 1558821391, now seen corresponding path program 7 times [2018-01-24 23:25:10,873 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:10,874 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:10,874 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:10,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:10,875 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:10,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:10,888 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:11,007 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,008 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:11,008 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:11,008 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:11,008 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:11,008 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:11,009 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:11,016 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:11,017 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:11,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:11,029 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:11,041 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,042 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:11,129 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,149 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:11,149 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:11,152 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:11,153 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:11,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:11,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:11,180 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,180 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:11,191 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,193 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:11,194 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 23:25:11,194 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:11,194 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 23:25:11,194 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 23:25:11,195 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 23:25:11,195 INFO L87 Difference]: Start difference. First operand 130 states and 167 transitions. Second operand 10 states. [2018-01-24 23:25:11,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:11,552 INFO L93 Difference]: Finished difference Result 160 states and 204 transitions. [2018-01-24 23:25:11,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 23:25:11,552 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-01-24 23:25:11,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:11,553 INFO L225 Difference]: With dead ends: 160 [2018-01-24 23:25:11,553 INFO L226 Difference]: Without dead ends: 156 [2018-01-24 23:25:11,554 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 161 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 23:25:11,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-01-24 23:25:11,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 144. [2018-01-24 23:25:11,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-24 23:25:11,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 186 transitions. [2018-01-24 23:25:11,563 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 186 transitions. Word has length 43 [2018-01-24 23:25:11,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:11,563 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 186 transitions. [2018-01-24 23:25:11,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 23:25:11,563 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 186 transitions. [2018-01-24 23:25:11,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-01-24 23:25:11,564 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:11,564 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:11,565 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:11,565 INFO L82 PathProgramCache]: Analyzing trace with hash -821098499, now seen corresponding path program 8 times [2018-01-24 23:25:11,565 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:11,565 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:11,566 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:11,566 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:11,566 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:11,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:11,577 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:11,682 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,682 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:11,682 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:11,682 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:11,682 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:11,682 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:11,682 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:11,688 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:11,688 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:11,691 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:11,694 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:11,696 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:11,697 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:11,708 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,709 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:11,835 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,857 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:11,857 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:11,860 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:11,861 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:11,864 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:11,871 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:11,881 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:11,885 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:11,895 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,895 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:11,907 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 164 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:11,908 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:11,909 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 23:25:11,909 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:11,909 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 23:25:11,910 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 23:25:11,910 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 23:25:11,910 INFO L87 Difference]: Start difference. First operand 144 states and 186 transitions. Second operand 11 states. [2018-01-24 23:25:12,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:12,634 INFO L93 Difference]: Finished difference Result 175 states and 224 transitions. [2018-01-24 23:25:12,635 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 23:25:12,635 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 48 [2018-01-24 23:25:12,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:12,636 INFO L225 Difference]: With dead ends: 175 [2018-01-24 23:25:12,636 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 23:25:12,636 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 200 GetRequests, 180 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 23:25:12,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 23:25:12,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 23:25:12,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 23:25:12,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 205 transitions. [2018-01-24 23:25:12,649 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 205 transitions. Word has length 48 [2018-01-24 23:25:12,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:12,649 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 205 transitions. [2018-01-24 23:25:12,649 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 23:25:12,650 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 205 transitions. [2018-01-24 23:25:12,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-24 23:25:12,651 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:12,651 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:12,651 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:12,652 INFO L82 PathProgramCache]: Analyzing trace with hash -413974833, now seen corresponding path program 9 times [2018-01-24 23:25:12,652 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:12,652 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:12,653 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:12,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:12,653 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:12,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:12,666 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:12,851 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:12,851 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:12,851 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:12,852 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:12,852 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:12,852 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:12,852 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:12,859 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:12,859 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:12,868 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,871 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,872 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,873 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,875 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,876 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,878 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,880 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,882 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,885 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:12,886 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:12,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:12,900 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:12,901 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:13,057 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:13,077 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:13,078 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:13,082 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:13,082 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:13,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,092 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,120 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,141 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,153 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:13,162 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:13,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:13,176 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:13,176 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:13,186 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 0 proven. 207 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:13,187 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:13,187 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 23:25:13,187 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:13,187 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 23:25:13,188 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 23:25:13,188 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:25:13,188 INFO L87 Difference]: Start difference. First operand 158 states and 205 transitions. Second operand 12 states. [2018-01-24 23:25:13,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:13,640 INFO L93 Difference]: Finished difference Result 190 states and 244 transitions. [2018-01-24 23:25:13,640 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 23:25:13,640 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 53 [2018-01-24 23:25:13,640 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:13,642 INFO L225 Difference]: With dead ends: 190 [2018-01-24 23:25:13,642 INFO L226 Difference]: Without dead ends: 186 [2018-01-24 23:25:13,642 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 221 GetRequests, 199 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:25:13,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-24 23:25:13,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 172. [2018-01-24 23:25:13,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-01-24 23:25:13,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 224 transitions. [2018-01-24 23:25:13,651 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 224 transitions. Word has length 53 [2018-01-24 23:25:13,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:13,651 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 224 transitions. [2018-01-24 23:25:13,651 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 23:25:13,652 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 224 transitions. [2018-01-24 23:25:13,653 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-24 23:25:13,653 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:13,653 INFO L322 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:13,653 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:13,654 INFO L82 PathProgramCache]: Analyzing trace with hash -442860739, now seen corresponding path program 10 times [2018-01-24 23:25:13,654 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:13,654 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:13,655 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:13,655 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:13,655 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:13,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:13,667 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:13,778 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:13,778 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:13,778 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:13,778 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:13,778 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:13,778 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:13,778 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:13,788 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:13,788 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:13,801 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:13,802 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:13,812 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:13,813 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:13,983 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:14,003 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:14,017 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:14,020 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:14,020 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:14,055 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:14,059 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:14,072 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:14,073 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:14,085 INFO L134 CoverageAnalysis]: Checked inductivity of 255 backedges. 0 proven. 255 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:14,087 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:14,087 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 23:25:14,087 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:14,087 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 23:25:14,087 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 23:25:14,088 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 23:25:14,088 INFO L87 Difference]: Start difference. First operand 172 states and 224 transitions. Second operand 13 states. [2018-01-24 23:25:14,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:14,787 INFO L93 Difference]: Finished difference Result 205 states and 264 transitions. [2018-01-24 23:25:14,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 23:25:14,788 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 58 [2018-01-24 23:25:14,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:14,789 INFO L225 Difference]: With dead ends: 205 [2018-01-24 23:25:14,789 INFO L226 Difference]: Without dead ends: 201 [2018-01-24 23:25:14,790 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 218 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 23:25:14,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-01-24 23:25:14,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 186. [2018-01-24 23:25:14,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-24 23:25:14,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 243 transitions. [2018-01-24 23:25:14,801 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 243 transitions. Word has length 58 [2018-01-24 23:25:14,801 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:14,801 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 243 transitions. [2018-01-24 23:25:14,801 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 23:25:14,801 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 243 transitions. [2018-01-24 23:25:14,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-01-24 23:25:14,803 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:14,803 INFO L322 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:14,803 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:14,803 INFO L82 PathProgramCache]: Analyzing trace with hash -634530929, now seen corresponding path program 11 times [2018-01-24 23:25:14,803 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:14,804 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:14,804 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:14,804 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:14,804 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:14,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:14,818 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:14,965 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:14,965 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:14,965 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:14,965 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:14,966 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:14,966 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:14,966 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:14,971 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:14,971 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:14,974 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,983 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:14,990 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:14,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:15,005 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:15,005 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:15,174 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:15,195 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:15,195 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:15,198 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:15,198 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:15,201 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,209 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,215 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,222 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,240 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,263 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,307 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:15,318 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:15,322 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:15,333 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:15,333 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:15,363 INFO L134 CoverageAnalysis]: Checked inductivity of 308 backedges. 0 proven. 308 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:15,365 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:15,365 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 23:25:15,365 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:15,365 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 23:25:15,366 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 23:25:15,366 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 23:25:15,366 INFO L87 Difference]: Start difference. First operand 186 states and 243 transitions. Second operand 14 states. [2018-01-24 23:25:16,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:16,018 INFO L93 Difference]: Finished difference Result 220 states and 284 transitions. [2018-01-24 23:25:16,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 23:25:16,018 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 63 [2018-01-24 23:25:16,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:16,019 INFO L225 Difference]: With dead ends: 220 [2018-01-24 23:25:16,019 INFO L226 Difference]: Without dead ends: 216 [2018-01-24 23:25:16,020 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 237 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 23:25:16,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-24 23:25:16,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 200. [2018-01-24 23:25:16,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2018-01-24 23:25:16,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 262 transitions. [2018-01-24 23:25:16,030 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 262 transitions. Word has length 63 [2018-01-24 23:25:16,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:16,030 INFO L432 AbstractCegarLoop]: Abstraction has 200 states and 262 transitions. [2018-01-24 23:25:16,030 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 23:25:16,030 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 262 transitions. [2018-01-24 23:25:16,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-24 23:25:16,032 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:16,032 INFO L322 BasicCegarLoop]: trace histogram [13, 13, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:16,032 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:16,033 INFO L82 PathProgramCache]: Analyzing trace with hash 2145312381, now seen corresponding path program 12 times [2018-01-24 23:25:16,033 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:16,034 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:16,034 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:16,034 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:16,034 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:16,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:16,048 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:16,229 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:16,230 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:16,230 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:16,230 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:16,230 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:16,230 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:16,230 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:16,235 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:16,235 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:16,238 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,242 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,244 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,245 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,248 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,250 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,252 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,256 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:16,257 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:16,268 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:16,268 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:16,490 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:16,510 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:16,510 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:16,513 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:16,513 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:16,517 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,543 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,552 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,573 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,599 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:16,641 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:16,645 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:16,656 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:16,656 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:16,676 INFO L134 CoverageAnalysis]: Checked inductivity of 366 backedges. 0 proven. 366 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:16,678 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:16,678 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 23:25:16,678 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:16,678 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 23:25:16,678 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 23:25:16,679 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 23:25:16,679 INFO L87 Difference]: Start difference. First operand 200 states and 262 transitions. Second operand 15 states. [2018-01-24 23:25:17,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:17,417 INFO L93 Difference]: Finished difference Result 235 states and 304 transitions. [2018-01-24 23:25:17,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 23:25:17,418 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-01-24 23:25:17,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:17,419 INFO L225 Difference]: With dead ends: 235 [2018-01-24 23:25:17,419 INFO L226 Difference]: Without dead ends: 231 [2018-01-24 23:25:17,420 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 284 GetRequests, 256 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 23:25:17,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states. [2018-01-24 23:25:17,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 214. [2018-01-24 23:25:17,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-24 23:25:17,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 281 transitions. [2018-01-24 23:25:17,432 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 281 transitions. Word has length 68 [2018-01-24 23:25:17,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:17,433 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 281 transitions. [2018-01-24 23:25:17,433 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 23:25:17,433 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 281 transitions. [2018-01-24 23:25:17,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-01-24 23:25:17,435 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:17,435 INFO L322 BasicCegarLoop]: trace histogram [14, 14, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:17,435 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:17,435 INFO L82 PathProgramCache]: Analyzing trace with hash 1734703183, now seen corresponding path program 13 times [2018-01-24 23:25:17,435 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:17,436 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:17,436 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:17,436 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:17,436 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:17,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:17,451 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:17,688 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:17,688 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:17,688 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:17,688 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:17,689 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:17,689 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:17,689 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:17,698 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:17,698 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:17,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:17,711 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:17,743 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:17,743 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:17,969 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:17,990 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:17,990 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:17,993 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:17,993 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:18,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:18,021 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:18,038 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:18,038 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:18,061 INFO L134 CoverageAnalysis]: Checked inductivity of 429 backedges. 0 proven. 429 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:18,063 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:18,063 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 23:25:18,063 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:18,063 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 23:25:18,063 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 23:25:18,064 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 23:25:18,064 INFO L87 Difference]: Start difference. First operand 214 states and 281 transitions. Second operand 16 states. [2018-01-24 23:25:18,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:18,915 INFO L93 Difference]: Finished difference Result 250 states and 324 transitions. [2018-01-24 23:25:18,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 23:25:18,915 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 73 [2018-01-24 23:25:18,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:18,917 INFO L225 Difference]: With dead ends: 250 [2018-01-24 23:25:18,917 INFO L226 Difference]: Without dead ends: 246 [2018-01-24 23:25:18,917 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 275 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 23:25:18,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-24 23:25:18,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 228. [2018-01-24 23:25:18,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-01-24 23:25:18,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 300 transitions. [2018-01-24 23:25:18,930 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 300 transitions. Word has length 73 [2018-01-24 23:25:18,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:18,931 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 300 transitions. [2018-01-24 23:25:18,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 23:25:18,931 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 300 transitions. [2018-01-24 23:25:18,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-24 23:25:18,933 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:18,933 INFO L322 BasicCegarLoop]: trace histogram [15, 15, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:18,933 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:18,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1083166275, now seen corresponding path program 14 times [2018-01-24 23:25:18,933 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:18,934 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:18,934 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:18,934 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:18,934 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:18,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:18,950 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:19,251 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:19,251 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:19,286 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:19,286 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:19,286 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:19,286 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:19,287 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-24 23:25:19,294 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:19,294 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:19,299 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:19,308 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:19,310 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:19,313 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:19,333 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:19,333 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:19,615 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:19,634 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:19,634 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:19,638 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:19,638 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:19,642 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:19,652 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:19,666 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:19,670 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:19,687 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:19,688 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:19,702 INFO L134 CoverageAnalysis]: Checked inductivity of 497 backedges. 0 proven. 497 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:19,703 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:19,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 23:25:19,704 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:19,704 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 23:25:19,704 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 23:25:19,704 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:25:19,704 INFO L87 Difference]: Start difference. First operand 228 states and 300 transitions. Second operand 17 states. [2018-01-24 23:25:20,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:20,645 INFO L93 Difference]: Finished difference Result 265 states and 344 transitions. [2018-01-24 23:25:20,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 23:25:20,645 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 78 [2018-01-24 23:25:20,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:20,646 INFO L225 Difference]: With dead ends: 265 [2018-01-24 23:25:20,646 INFO L226 Difference]: Without dead ends: 261 [2018-01-24 23:25:20,647 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 326 GetRequests, 294 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:25:20,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-01-24 23:25:20,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 242. [2018-01-24 23:25:20,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 23:25:20,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 319 transitions. [2018-01-24 23:25:20,658 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 319 transitions. Word has length 78 [2018-01-24 23:25:20,658 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:20,658 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 319 transitions. [2018-01-24 23:25:20,658 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 23:25:20,658 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 319 transitions. [2018-01-24 23:25:20,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-24 23:25:20,660 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:20,660 INFO L322 BasicCegarLoop]: trace histogram [16, 16, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:20,660 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:20,660 INFO L82 PathProgramCache]: Analyzing trace with hash 1239821583, now seen corresponding path program 15 times [2018-01-24 23:25:20,660 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:20,660 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:20,661 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:20,661 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:20,661 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:20,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:20,671 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:21,007 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:21,007 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:21,007 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:21,007 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:21,007 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:21,007 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:21,008 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:21,013 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:21,013 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:21,017 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,018 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,021 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,023 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,024 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,026 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,028 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,032 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,037 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,039 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,046 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:21,047 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:21,060 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:21,060 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:21,355 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:21,375 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:21,375 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:21,378 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:21,378 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:21,382 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,389 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,394 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,401 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,408 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,417 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,427 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,438 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,450 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,477 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,493 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,527 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:21,568 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:21,572 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:21,595 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:21,595 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:21,610 INFO L134 CoverageAnalysis]: Checked inductivity of 570 backedges. 0 proven. 570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:21,611 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:21,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 23:25:21,611 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:21,611 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 23:25:21,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 23:25:21,612 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 23:25:21,612 INFO L87 Difference]: Start difference. First operand 242 states and 319 transitions. Second operand 18 states. [2018-01-24 23:25:22,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:22,718 INFO L93 Difference]: Finished difference Result 280 states and 364 transitions. [2018-01-24 23:25:22,718 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 23:25:22,719 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 83 [2018-01-24 23:25:22,719 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:22,720 INFO L225 Difference]: With dead ends: 280 [2018-01-24 23:25:22,720 INFO L226 Difference]: Without dead ends: 276 [2018-01-24 23:25:22,720 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 313 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 23:25:22,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-01-24 23:25:22,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 256. [2018-01-24 23:25:22,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256 states. [2018-01-24 23:25:22,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 338 transitions. [2018-01-24 23:25:22,736 INFO L78 Accepts]: Start accepts. Automaton has 256 states and 338 transitions. Word has length 83 [2018-01-24 23:25:22,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:22,736 INFO L432 AbstractCegarLoop]: Abstraction has 256 states and 338 transitions. [2018-01-24 23:25:22,736 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 23:25:22,736 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 338 transitions. [2018-01-24 23:25:22,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-01-24 23:25:22,738 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:22,739 INFO L322 BasicCegarLoop]: trace histogram [17, 17, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:22,739 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:22,739 INFO L82 PathProgramCache]: Analyzing trace with hash -589138691, now seen corresponding path program 16 times [2018-01-24 23:25:22,739 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:22,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:22,740 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:22,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:22,740 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:22,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:22,758 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:23,105 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:23,105 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:23,105 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:23,105 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:23,106 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:23,106 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:23,106 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:23,112 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:23,113 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:23,135 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:23,138 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:23,153 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:23,153 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:23,551 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:23,572 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:23,572 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:23,575 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:23,575 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:23,629 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:23,633 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:23,652 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:23,652 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:23,669 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:23,671 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:23,671 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 23:25:23,671 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:23,671 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 23:25:23,672 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 23:25:23,672 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 23:25:23,672 INFO L87 Difference]: Start difference. First operand 256 states and 338 transitions. Second operand 19 states. [2018-01-24 23:25:24,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:24,879 INFO L93 Difference]: Finished difference Result 295 states and 384 transitions. [2018-01-24 23:25:24,909 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 23:25:24,909 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 88 [2018-01-24 23:25:24,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:24,910 INFO L225 Difference]: With dead ends: 295 [2018-01-24 23:25:24,910 INFO L226 Difference]: Without dead ends: 291 [2018-01-24 23:25:24,911 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 332 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 23:25:24,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states. [2018-01-24 23:25:24,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 270. [2018-01-24 23:25:24,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 270 states. [2018-01-24 23:25:24,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 357 transitions. [2018-01-24 23:25:24,921 INFO L78 Accepts]: Start accepts. Automaton has 270 states and 357 transitions. Word has length 88 [2018-01-24 23:25:24,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:24,922 INFO L432 AbstractCegarLoop]: Abstraction has 270 states and 357 transitions. [2018-01-24 23:25:24,922 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 23:25:24,922 INFO L276 IsEmpty]: Start isEmpty. Operand 270 states and 357 transitions. [2018-01-24 23:25:24,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-01-24 23:25:24,924 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:24,924 INFO L322 BasicCegarLoop]: trace histogram [18, 18, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:24,924 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:24,925 INFO L82 PathProgramCache]: Analyzing trace with hash -2053377585, now seen corresponding path program 17 times [2018-01-24 23:25:24,925 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:24,925 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:24,925 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:24,925 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:24,926 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:24,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:24,941 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:25,220 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:25,221 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:25,221 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:25,221 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:25,221 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:25,221 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:25,221 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:25,226 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:25,226 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:25,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,232 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,233 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,235 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,236 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,238 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,240 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,245 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,248 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,250 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,254 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,256 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,258 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,262 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,263 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:25,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:25,280 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:25,280 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:25,617 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:25,637 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:25,637 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:25,640 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:25,640 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:25,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,646 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,651 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,657 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,664 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,693 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,704 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,716 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,729 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,744 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,760 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,776 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,864 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:25,884 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:25,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:25,906 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:25,906 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:25,923 INFO L134 CoverageAnalysis]: Checked inductivity of 731 backedges. 0 proven. 731 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:25,925 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:25,925 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 23:25:25,925 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:25,925 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 23:25:25,926 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 23:25:25,926 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 23:25:25,926 INFO L87 Difference]: Start difference. First operand 270 states and 357 transitions. Second operand 20 states. [2018-01-24 23:25:27,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:27,306 INFO L93 Difference]: Finished difference Result 310 states and 404 transitions. [2018-01-24 23:25:27,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 23:25:27,307 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 93 [2018-01-24 23:25:27,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:27,308 INFO L225 Difference]: With dead ends: 310 [2018-01-24 23:25:27,308 INFO L226 Difference]: Without dead ends: 306 [2018-01-24 23:25:27,309 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 389 GetRequests, 351 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 23:25:27,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-24 23:25:27,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 284. [2018-01-24 23:25:27,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 284 states. [2018-01-24 23:25:27,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 284 states to 284 states and 376 transitions. [2018-01-24 23:25:27,318 INFO L78 Accepts]: Start accepts. Automaton has 284 states and 376 transitions. Word has length 93 [2018-01-24 23:25:27,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:27,318 INFO L432 AbstractCegarLoop]: Abstraction has 284 states and 376 transitions. [2018-01-24 23:25:27,318 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 23:25:27,319 INFO L276 IsEmpty]: Start isEmpty. Operand 284 states and 376 transitions. [2018-01-24 23:25:27,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-24 23:25:27,320 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:27,320 INFO L322 BasicCegarLoop]: trace histogram [19, 19, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:27,320 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:27,320 INFO L82 PathProgramCache]: Analyzing trace with hash 1741269053, now seen corresponding path program 18 times [2018-01-24 23:25:27,320 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:27,321 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:27,321 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:27,321 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:27,321 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:27,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:27,332 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:27,567 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:27,567 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:27,567 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:27,567 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:27,567 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:27,568 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:27,568 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:27,573 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:27,573 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:27,576 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,578 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,580 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,587 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,595 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,597 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,600 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,604 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,606 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:27,607 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:27,609 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:27,625 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:27,625 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:28,038 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:28,057 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:28,057 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:28,060 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:28,060 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:28,065 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,067 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,072 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,078 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,084 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,092 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,101 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,111 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,135 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,197 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,215 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,242 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,285 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,307 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:28,332 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:28,337 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:28,356 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:28,356 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:28,377 INFO L134 CoverageAnalysis]: Checked inductivity of 819 backedges. 0 proven. 819 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:28,378 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:28,378 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 23:25:28,379 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:28,379 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 23:25:28,379 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 23:25:28,379 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 23:25:28,379 INFO L87 Difference]: Start difference. First operand 284 states and 376 transitions. Second operand 21 states. [2018-01-24 23:25:30,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:30,327 INFO L93 Difference]: Finished difference Result 325 states and 424 transitions. [2018-01-24 23:25:30,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 23:25:30,353 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-24 23:25:30,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:30,355 INFO L225 Difference]: With dead ends: 325 [2018-01-24 23:25:30,355 INFO L226 Difference]: Without dead ends: 321 [2018-01-24 23:25:30,356 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 410 GetRequests, 370 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 23:25:30,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 321 states. [2018-01-24 23:25:30,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 321 to 298. [2018-01-24 23:25:30,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-24 23:25:30,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 395 transitions. [2018-01-24 23:25:30,369 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 395 transitions. Word has length 98 [2018-01-24 23:25:30,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:30,370 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 395 transitions. [2018-01-24 23:25:30,370 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 23:25:30,370 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 395 transitions. [2018-01-24 23:25:30,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-01-24 23:25:30,372 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:30,372 INFO L322 BasicCegarLoop]: trace histogram [20, 20, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:30,373 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:30,373 INFO L82 PathProgramCache]: Analyzing trace with hash 661833359, now seen corresponding path program 19 times [2018-01-24 23:25:30,373 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:30,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:30,374 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:30,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:30,374 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:30,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:30,391 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:30,827 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:30,827 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:30,827 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:30,827 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:30,828 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:30,828 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:30,828 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:30,833 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:30,833 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:30,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:30,849 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:30,876 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:30,876 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:31,419 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:31,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:31,439 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:31,442 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:31,442 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:31,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:31,482 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:31,503 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:31,504 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:31,524 INFO L134 CoverageAnalysis]: Checked inductivity of 912 backedges. 0 proven. 912 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:31,525 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:31,525 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 23:25:31,525 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:31,525 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 23:25:31,525 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 23:25:31,526 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 23:25:31,526 INFO L87 Difference]: Start difference. First operand 298 states and 395 transitions. Second operand 22 states. [2018-01-24 23:25:33,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:33,158 INFO L93 Difference]: Finished difference Result 340 states and 444 transitions. [2018-01-24 23:25:33,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 23:25:33,158 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 103 [2018-01-24 23:25:33,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:33,160 INFO L225 Difference]: With dead ends: 340 [2018-01-24 23:25:33,161 INFO L226 Difference]: Without dead ends: 336 [2018-01-24 23:25:33,161 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 431 GetRequests, 389 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 23:25:33,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states. [2018-01-24 23:25:33,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 312. [2018-01-24 23:25:33,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-01-24 23:25:33,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 414 transitions. [2018-01-24 23:25:33,175 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 414 transitions. Word has length 103 [2018-01-24 23:25:33,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:33,175 INFO L432 AbstractCegarLoop]: Abstraction has 312 states and 414 transitions. [2018-01-24 23:25:33,176 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 23:25:33,176 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 414 transitions. [2018-01-24 23:25:33,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-24 23:25:33,177 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:33,177 INFO L322 BasicCegarLoop]: trace histogram [21, 21, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:33,177 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:33,177 INFO L82 PathProgramCache]: Analyzing trace with hash -2034644099, now seen corresponding path program 20 times [2018-01-24 23:25:33,177 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:33,178 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:33,178 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:33,178 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:33,178 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:33,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:33,195 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:33,575 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:33,575 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:33,575 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:33,575 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:33,575 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:33,575 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:33,575 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:33,580 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:33,580 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:33,585 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:33,593 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:33,596 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:33,599 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:33,627 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:33,627 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:34,186 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:34,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:34,206 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:34,210 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:34,210 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:34,216 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:34,232 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:34,257 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:34,263 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:34,282 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:34,282 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:34,338 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 0 proven. 1010 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:34,339 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:34,339 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 23:25:34,339 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:34,339 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 23:25:34,340 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 23:25:34,340 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 23:25:34,340 INFO L87 Difference]: Start difference. First operand 312 states and 414 transitions. Second operand 23 states. [2018-01-24 23:25:36,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:36,105 INFO L93 Difference]: Finished difference Result 355 states and 464 transitions. [2018-01-24 23:25:36,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 23:25:36,105 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 108 [2018-01-24 23:25:36,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:36,107 INFO L225 Difference]: With dead ends: 355 [2018-01-24 23:25:36,107 INFO L226 Difference]: Without dead ends: 351 [2018-01-24 23:25:36,107 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 452 GetRequests, 408 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 23:25:36,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 351 states. [2018-01-24 23:25:36,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 351 to 326. [2018-01-24 23:25:36,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 23:25:36,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 433 transitions. [2018-01-24 23:25:36,121 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 433 transitions. Word has length 108 [2018-01-24 23:25:36,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:36,121 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 433 transitions. [2018-01-24 23:25:36,121 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 23:25:36,122 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 433 transitions. [2018-01-24 23:25:36,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-24 23:25:36,124 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:36,124 INFO L322 BasicCegarLoop]: trace histogram [22, 22, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:36,124 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:36,124 INFO L82 PathProgramCache]: Analyzing trace with hash 89566031, now seen corresponding path program 21 times [2018-01-24 23:25:36,124 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:36,125 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:36,125 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:36,125 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:36,125 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:36,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:36,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:36,449 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:36,449 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:36,450 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:36,450 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:36,450 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:36,450 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:36,450 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:36,459 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:36,459 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:36,463 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,464 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,465 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,466 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,467 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,468 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,470 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,471 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,473 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,474 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,476 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,478 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,480 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,482 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,486 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,488 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,490 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,493 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,497 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:36,501 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:36,503 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:36,522 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:36,523 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:37,010 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:37,030 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:37,030 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:37,033 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:25:37,033 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:25:37,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,050 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,057 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,073 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,083 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,094 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,105 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,118 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,132 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,182 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,201 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,228 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,295 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,328 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,353 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:25:37,375 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:37,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:37,418 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:37,418 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:37,462 INFO L134 CoverageAnalysis]: Checked inductivity of 1113 backedges. 0 proven. 1113 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:37,464 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:37,464 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 23:25:37,464 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:37,465 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 23:25:37,465 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 23:25:37,465 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 23:25:37,466 INFO L87 Difference]: Start difference. First operand 326 states and 433 transitions. Second operand 24 states. [2018-01-24 23:25:39,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:39,426 INFO L93 Difference]: Finished difference Result 370 states and 484 transitions. [2018-01-24 23:25:39,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 23:25:39,426 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 113 [2018-01-24 23:25:39,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:39,428 INFO L225 Difference]: With dead ends: 370 [2018-01-24 23:25:39,428 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 23:25:39,429 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 473 GetRequests, 427 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 23:25:39,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 23:25:39,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 340. [2018-01-24 23:25:39,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 340 states. [2018-01-24 23:25:39,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 340 states to 340 states and 452 transitions. [2018-01-24 23:25:39,442 INFO L78 Accepts]: Start accepts. Automaton has 340 states and 452 transitions. Word has length 113 [2018-01-24 23:25:39,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:39,443 INFO L432 AbstractCegarLoop]: Abstraction has 340 states and 452 transitions. [2018-01-24 23:25:39,443 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 23:25:39,443 INFO L276 IsEmpty]: Start isEmpty. Operand 340 states and 452 transitions. [2018-01-24 23:25:39,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-24 23:25:39,445 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:39,445 INFO L322 BasicCegarLoop]: trace histogram [23, 23, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:39,445 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:39,446 INFO L82 PathProgramCache]: Analyzing trace with hash 927391421, now seen corresponding path program 22 times [2018-01-24 23:25:39,446 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:39,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:39,447 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:39,447 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:39,447 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:39,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:39,463 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:39,798 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:39,798 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:39,799 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:39,799 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:39,799 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:39,799 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:39,799 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:39,804 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:39,804 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:39,829 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:39,832 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:39,857 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:39,858 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:40,395 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:40,414 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:40,415 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:40,417 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:25:40,418 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:25:40,485 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:40,490 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:40,522 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:40,523 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:40,557 INFO L134 CoverageAnalysis]: Checked inductivity of 1221 backedges. 0 proven. 1221 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:40,559 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:40,559 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 23:25:40,559 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:40,560 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 23:25:40,560 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 23:25:40,560 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 23:25:40,561 INFO L87 Difference]: Start difference. First operand 340 states and 452 transitions. Second operand 25 states. [2018-01-24 23:25:42,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:42,653 INFO L93 Difference]: Finished difference Result 385 states and 504 transitions. [2018-01-24 23:25:42,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 23:25:42,653 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 118 [2018-01-24 23:25:42,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:42,655 INFO L225 Difference]: With dead ends: 385 [2018-01-24 23:25:42,655 INFO L226 Difference]: Without dead ends: 381 [2018-01-24 23:25:42,656 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 494 GetRequests, 446 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 23:25:42,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2018-01-24 23:25:42,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 354. [2018-01-24 23:25:42,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 354 states. [2018-01-24 23:25:42,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 471 transitions. [2018-01-24 23:25:42,670 INFO L78 Accepts]: Start accepts. Automaton has 354 states and 471 transitions. Word has length 118 [2018-01-24 23:25:42,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:42,670 INFO L432 AbstractCegarLoop]: Abstraction has 354 states and 471 transitions. [2018-01-24 23:25:42,671 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 23:25:42,671 INFO L276 IsEmpty]: Start isEmpty. Operand 354 states and 471 transitions. [2018-01-24 23:25:42,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-01-24 23:25:42,673 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:42,673 INFO L322 BasicCegarLoop]: trace histogram [24, 24, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:42,673 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:42,673 INFO L82 PathProgramCache]: Analyzing trace with hash 2117312527, now seen corresponding path program 23 times [2018-01-24 23:25:42,673 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:42,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:42,674 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:42,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:42,674 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:42,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:42,691 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:43,092 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:43,093 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:43,093 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:43,093 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:43,093 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:43,093 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:43,093 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:43,098 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:43,098 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:43,102 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,103 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,104 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,105 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,106 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,107 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,109 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,110 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,111 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,113 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,115 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,116 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,118 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,120 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,122 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,124 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,126 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,128 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,130 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,133 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,135 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,138 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,140 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,143 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,144 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:43,146 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:43,168 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:43,169 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:43,734 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:43,754 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:43,754 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:43,757 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:25:43,757 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:43,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,764 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,769 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,809 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,877 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,939 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:43,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,004 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,036 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,061 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,089 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,125 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,156 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:44,193 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:44,199 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:44,233 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:44,233 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:44,263 INFO L134 CoverageAnalysis]: Checked inductivity of 1334 backedges. 0 proven. 1334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:44,265 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:44,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 23:25:44,265 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:44,265 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 23:25:44,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 23:25:44,266 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 23:25:44,266 INFO L87 Difference]: Start difference. First operand 354 states and 471 transitions. Second operand 26 states. [2018-01-24 23:25:46,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:46,528 INFO L93 Difference]: Finished difference Result 400 states and 524 transitions. [2018-01-24 23:25:46,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 23:25:46,529 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 123 [2018-01-24 23:25:46,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:46,530 INFO L225 Difference]: With dead ends: 400 [2018-01-24 23:25:46,531 INFO L226 Difference]: Without dead ends: 396 [2018-01-24 23:25:46,532 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 515 GetRequests, 465 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 23:25:46,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states. [2018-01-24 23:25:46,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 368. [2018-01-24 23:25:46,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-01-24 23:25:46,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 490 transitions. [2018-01-24 23:25:46,545 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 490 transitions. Word has length 123 [2018-01-24 23:25:46,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:46,546 INFO L432 AbstractCegarLoop]: Abstraction has 368 states and 490 transitions. [2018-01-24 23:25:46,546 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 23:25:46,546 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 490 transitions. [2018-01-24 23:25:46,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-01-24 23:25:46,548 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:46,548 INFO L322 BasicCegarLoop]: trace histogram [25, 25, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:46,548 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:46,549 INFO L82 PathProgramCache]: Analyzing trace with hash -1912282627, now seen corresponding path program 24 times [2018-01-24 23:25:46,549 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:46,549 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:46,549 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:46,550 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:46,550 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:46,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:46,567 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:46,955 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:46,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:46,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:46,955 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:46,955 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:46,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:46,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:46,960 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:46,960 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:46,965 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,966 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,967 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,970 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,971 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,973 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,978 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,985 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,988 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,990 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:46,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,000 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,003 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,005 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,008 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,011 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,012 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:47,015 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:47,039 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:47,039 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:47,755 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:47,775 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:47,787 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:47,791 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:25:47,791 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:25:47,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,805 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,837 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,848 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,859 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,872 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,913 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,931 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,948 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,967 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:47,998 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,020 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,065 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,097 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,214 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:25:48,276 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:48,281 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:48,305 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:48,305 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:48,346 INFO L134 CoverageAnalysis]: Checked inductivity of 1452 backedges. 0 proven. 1452 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:48,348 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:48,348 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 23:25:48,348 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:48,348 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 23:25:48,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 23:25:48,349 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 23:25:48,349 INFO L87 Difference]: Start difference. First operand 368 states and 490 transitions. Second operand 27 states. [2018-01-24 23:25:50,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:50,775 INFO L93 Difference]: Finished difference Result 415 states and 544 transitions. [2018-01-24 23:25:50,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 23:25:50,775 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 128 [2018-01-24 23:25:50,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:50,777 INFO L225 Difference]: With dead ends: 415 [2018-01-24 23:25:50,777 INFO L226 Difference]: Without dead ends: 411 [2018-01-24 23:25:50,778 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 536 GetRequests, 484 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 23:25:50,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2018-01-24 23:25:50,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 382. [2018-01-24 23:25:50,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-24 23:25:50,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 509 transitions. [2018-01-24 23:25:50,787 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 509 transitions. Word has length 128 [2018-01-24 23:25:50,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:50,788 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 509 transitions. [2018-01-24 23:25:50,788 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 23:25:50,788 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 509 transitions. [2018-01-24 23:25:50,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-01-24 23:25:50,789 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:50,789 INFO L322 BasicCegarLoop]: trace histogram [26, 26, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:50,789 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:50,789 INFO L82 PathProgramCache]: Analyzing trace with hash 972399823, now seen corresponding path program 25 times [2018-01-24 23:25:50,789 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:50,790 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:50,790 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:25:50,790 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:50,790 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:50,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:50,802 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:51,232 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:51,232 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:51,233 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:51,233 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:51,233 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:51,233 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:51,233 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:51,238 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:51,238 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:51,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:51,257 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:51,292 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:51,292 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:52,016 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:52,036 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:52,036 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:52,039 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:52,039 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:25:52,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:52,091 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:52,123 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:52,124 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:52,162 INFO L134 CoverageAnalysis]: Checked inductivity of 1575 backedges. 0 proven. 1575 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:52,163 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:52,163 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 23:25:52,164 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:52,164 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 23:25:52,164 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 23:25:52,165 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 23:25:52,165 INFO L87 Difference]: Start difference. First operand 382 states and 509 transitions. Second operand 28 states. [2018-01-24 23:25:54,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:25:54,809 INFO L93 Difference]: Finished difference Result 430 states and 564 transitions. [2018-01-24 23:25:54,809 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 23:25:54,809 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 133 [2018-01-24 23:25:54,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:25:54,810 INFO L225 Difference]: With dead ends: 430 [2018-01-24 23:25:54,811 INFO L226 Difference]: Without dead ends: 426 [2018-01-24 23:25:54,811 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 557 GetRequests, 503 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 23:25:54,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-24 23:25:54,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 396. [2018-01-24 23:25:54,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 396 states. [2018-01-24 23:25:54,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 396 states to 396 states and 528 transitions. [2018-01-24 23:25:54,826 INFO L78 Accepts]: Start accepts. Automaton has 396 states and 528 transitions. Word has length 133 [2018-01-24 23:25:54,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:25:54,827 INFO L432 AbstractCegarLoop]: Abstraction has 396 states and 528 transitions. [2018-01-24 23:25:54,827 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 23:25:54,827 INFO L276 IsEmpty]: Start isEmpty. Operand 396 states and 528 transitions. [2018-01-24 23:25:54,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-24 23:25:54,828 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:25:54,829 INFO L322 BasicCegarLoop]: trace histogram [27, 27, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 23:25:54,829 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:25:54,829 INFO L82 PathProgramCache]: Analyzing trace with hash -158870211, now seen corresponding path program 26 times [2018-01-24 23:25:54,829 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:25:54,830 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:54,830 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:25:54,830 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:25:54,830 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:25:54,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:25:54,847 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:25:55,377 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:55,377 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:55,377 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:25:55,377 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:25:55,377 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:25:55,378 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:55,378 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:25:55,388 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:55,388 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:55,393 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:55,410 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:55,413 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:55,416 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:55,463 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:55,463 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:56,173 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:56,193 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:25:56,193 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:25:56,196 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:25:56,196 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:25:56,201 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:56,216 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:25:56,241 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:25:56,246 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:25:56,277 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:56,278 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:25:56,315 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:25:56,316 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:25:56,317 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 23:25:56,317 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:25:56,317 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 23:25:56,317 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 23:25:56,318 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 23:25:56,318 INFO L87 Difference]: Start difference. First operand 396 states and 528 transitions. Second operand 29 states. Received shutdown request... [2018-01-24 23:25:58,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 23:25:58,471 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 23:25:58,475 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 23:25:58,476 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 11:25:58 BoogieIcfgContainer [2018-01-24 23:25:58,476 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 23:25:58,476 INFO L168 Benchmark]: Toolchain (without parser) took 52306.06 ms. Allocated memory was 304.1 MB in the beginning and 731.4 MB in the end (delta: 427.3 MB). Free memory was 265.1 MB in the beginning and 528.6 MB in the end (delta: -263.5 MB). Peak memory consumption was 163.8 MB. Max. memory is 5.3 GB. [2018-01-24 23:25:58,477 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 304.1 MB. Free memory is still 270.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 23:25:58,477 INFO L168 Benchmark]: CACSL2BoogieTranslator took 177.12 ms. Allocated memory is still 304.1 MB. Free memory was 264.1 MB in the beginning and 256.1 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 5.3 GB. [2018-01-24 23:25:58,477 INFO L168 Benchmark]: Boogie Preprocessor took 29.40 ms. Allocated memory is still 304.1 MB. Free memory was 256.1 MB in the beginning and 254.1 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-24 23:25:58,478 INFO L168 Benchmark]: RCFGBuilder took 193.02 ms. Allocated memory is still 304.1 MB. Free memory was 254.1 MB in the beginning and 241.5 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. [2018-01-24 23:25:58,478 INFO L168 Benchmark]: TraceAbstraction took 51899.47 ms. Allocated memory was 304.1 MB in the beginning and 731.4 MB in the end (delta: 427.3 MB). Free memory was 240.5 MB in the beginning and 528.6 MB in the end (delta: -288.1 MB). Peak memory consumption was 139.2 MB. Max. memory is 5.3 GB. [2018-01-24 23:25:58,480 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 304.1 MB. Free memory is still 270.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 177.12 ms. Allocated memory is still 304.1 MB. Free memory was 264.1 MB in the beginning and 256.1 MB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 29.40 ms. Allocated memory is still 304.1 MB. Free memory was 256.1 MB in the beginning and 254.1 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 193.02 ms. Allocated memory is still 304.1 MB. Free memory was 254.1 MB in the beginning and 241.5 MB in the end (delta: 12.6 MB). Peak memory consumption was 12.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 51899.47 ms. Allocated memory was 304.1 MB in the beginning and 731.4 MB in the end (delta: 427.3 MB). Free memory was 240.5 MB in the beginning and 528.6 MB in the end (delta: -288.1 MB). Peak memory consumption was 139.2 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 1 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 0 TransStat_MAX_SIZEOF_WEQEDGELABEL : 0 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.223634 RENAME_VARIABLES(MILLISECONDS) : 0.418355 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.142253 PROJECTAWAY(MILLISECONDS) : 0.248446 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.000000 DISJOIN(MILLISECONDS) : 2.427265 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.518602 ADD_EQUALITY(MILLISECONDS) : 0.101880 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.108304 #CONJOIN_DISJUNCTIVE : 18 #RENAME_VARIABLES : 43 #UNFREEZE : 0 #CONJOIN : 29 #PROJECTAWAY : 36 #ADD_WEAK_EQUALITY : 0 #DISJOIN : 1 #RENAME_VARIABLES_DISJUNCTIVE : 41 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 17]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 17). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 27 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (374 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 24]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 24). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 27 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (374 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 26]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 26). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 27 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (374 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 19]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 19). Cancelled while BasicCegarLoop was constructing difference of abstraction (396states) and interpolant automaton (currently 27 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (374 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 42 locations, 4 error locations. TIMEOUT Result, 51.8s OverallTime, 27 OverallIterations, 27 TraceHistogramMax, 29.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4668 SDtfs, 3429 SDslu, 58844 SDs, 0 SdLazy, 81630 SolverSat, 827 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 23.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 8205 GetRequests, 7398 SyntacticMatches, 52 SemanticMatches, 755 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 12.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=396occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.2s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 26 MinimizatonAttempts, 455 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 3.6s SatisfiabilityAnalysisTime, 16.3s InterpolantComputationTime, 5897 NumberOfCodeBlocks, 5897 NumberOfCodeBlocksAsserted, 425 NumberOfCheckSat, 9692 ConstructedInterpolants, 0 QuantifiedInterpolants, 6767390 SizeOfPredicates, 0 NumberOfNonLiveVariables, 5200 ConjunctsInSsa, 1560 ConjunctsInUnsatCore, 131 InterpolantComputations, 1 PerfectInterpolantSequences, 0/78390 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_23-25-58-488.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_23-25-58-488.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_23-25-58-488.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sanfoundry_24_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_23-25-58-488.csv Completed graceful shutdown