java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 23:26:00,969 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 23:26:00,971 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 23:26:00,986 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 23:26:00,987 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 23:26:00,987 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 23:26:00,989 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 23:26:00,990 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 23:26:00,992 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 23:26:00,993 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 23:26:00,994 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 23:26:00,994 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 23:26:00,995 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 23:26:00,996 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 23:26:00,997 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 23:26:01,000 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 23:26:01,002 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 23:26:01,004 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 23:26:01,005 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 23:26:01,006 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 23:26:01,009 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 23:26:01,009 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 23:26:01,009 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 23:26:01,010 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 23:26:01,011 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 23:26:01,012 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 23:26:01,012 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 23:26:01,013 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 23:26:01,013 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 23:26:01,014 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 23:26:01,014 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 23:26:01,014 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf [2018-01-24 23:26:01,024 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 23:26:01,024 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 23:26:01,025 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 23:26:01,025 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 23:26:01,025 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 23:26:01,025 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 23:26:01,025 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 23:26:01,025 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 23:26:01,026 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 23:26:01,026 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 23:26:01,026 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 23:26:01,026 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 23:26:01,026 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 23:26:01,027 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 23:26:01,027 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 23:26:01,028 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 23:26:01,028 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 23:26:01,028 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 23:26:01,028 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 23:26:01,028 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 23:26:01,029 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 23:26:01,030 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 23:26:01,030 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 23:26:01,062 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 23:26:01,072 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 23:26:01,076 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 23:26:01,077 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 23:26:01,077 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 23:26:01,078 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_false-valid-deref_ground.i [2018-01-24 23:26:01,172 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 23:26:01,178 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 23:26:01,178 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 23:26:01,178 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 23:26:01,184 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 23:26:01,185 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,187 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29a4c9af and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01, skipping insertion in model container [2018-01-24 23:26:01,188 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,201 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 23:26:01,215 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 23:26:01,328 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 23:26:01,339 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 23:26:01,344 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01 WrapperNode [2018-01-24 23:26:01,344 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 23:26:01,345 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 23:26:01,345 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 23:26:01,345 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 23:26:01,356 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,356 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,363 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,363 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,365 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,368 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,369 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... [2018-01-24 23:26:01,371 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 23:26:01,371 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 23:26:01,371 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 23:26:01,371 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 23:26:01,372 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 23:26:01,417 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 23:26:01,417 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 23:26:01,417 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 23:26:01,417 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 23:26:01,418 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 23:26:01,418 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 23:26:01,418 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 23:26:01,418 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 23:26:01,418 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 23:26:01,538 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 23:26:01,538 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 11:26:01 BoogieIcfgContainer [2018-01-24 23:26:01,539 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 23:26:01,540 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 23:26:01,540 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 23:26:01,542 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 23:26:01,542 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 11:26:01" (1/3) ... [2018-01-24 23:26:01,544 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5431e13c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 11:26:01, skipping insertion in model container [2018-01-24 23:26:01,544 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:01" (2/3) ... [2018-01-24 23:26:01,544 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5431e13c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 11:26:01, skipping insertion in model container [2018-01-24 23:26:01,544 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 11:26:01" (3/3) ... [2018-01-24 23:26:01,546 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_false-valid-deref_ground.i [2018-01-24 23:26:01,555 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 23:26:01,563 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 5 error locations. [2018-01-24 23:26:01,611 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 23:26:01,611 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 23:26:01,611 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 23:26:01,611 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 23:26:01,611 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 23:26:01,612 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 23:26:01,612 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 23:26:01,612 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 23:26:01,613 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 23:26:01,633 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-01-24 23:26:01,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 23:26:01,639 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:01,640 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:01,641 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:01,646 INFO L82 PathProgramCache]: Analyzing trace with hash -42218404, now seen corresponding path program 1 times [2018-01-24 23:26:01,649 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:01,696 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:01,697 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:01,697 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:01,697 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:01,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:01,731 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:01,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:01,795 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 23:26:01,795 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 23:26:01,795 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 23:26:01,797 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 23:26:01,807 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 23:26:01,808 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 23:26:01,810 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 3 states. [2018-01-24 23:26:01,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:01,881 INFO L93 Difference]: Finished difference Result 71 states and 84 transitions. [2018-01-24 23:26:01,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 23:26:01,882 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 23:26:01,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:01,891 INFO L225 Difference]: With dead ends: 71 [2018-01-24 23:26:01,891 INFO L226 Difference]: Without dead ends: 40 [2018-01-24 23:26:01,896 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 23:26:01,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-01-24 23:26:01,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 31. [2018-01-24 23:26:01,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-24 23:26:01,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 33 transitions. [2018-01-24 23:26:01,990 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 33 transitions. Word has length 7 [2018-01-24 23:26:01,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:01,990 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 33 transitions. [2018-01-24 23:26:01,991 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 23:26:01,991 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 33 transitions. [2018-01-24 23:26:01,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 23:26:01,991 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:01,991 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:01,991 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:01,992 INFO L82 PathProgramCache]: Analyzing trace with hash -207595369, now seen corresponding path program 1 times [2018-01-24 23:26:01,992 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:01,993 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:01,993 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:01,993 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:01,993 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:02,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:02,002 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:02,038 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,038 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:02,038 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:02,039 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-01-24 23:26:02,041 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [10], [11], [16], [18], [20], [56], [57], [58] [2018-01-24 23:26:02,085 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 23:26:02,085 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 23:26:02,376 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 23:26:02,377 INFO L268 AbstractInterpreter]: Visited 11 different actions 23 times. Merged at 6 different actions 12 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-01-24 23:26:02,393 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 23:26:02,393 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:02,393 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:02,408 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:02,408 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:02,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:02,435 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:02,447 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,447 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:02,521 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,542 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:02,542 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:02,546 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:02,547 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:02,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:02,556 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:02,562 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,562 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:02,578 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,579 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:02,579 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 23:26:02,580 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:02,580 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 23:26:02,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 23:26:02,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 23:26:02,581 INFO L87 Difference]: Start difference. First operand 31 states and 33 transitions. Second operand 4 states. [2018-01-24 23:26:02,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:02,644 INFO L93 Difference]: Finished difference Result 57 states and 62 transitions. [2018-01-24 23:26:02,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 23:26:02,644 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 23:26:02,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:02,645 INFO L225 Difference]: With dead ends: 57 [2018-01-24 23:26:02,645 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 23:26:02,646 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 23:26:02,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 23:26:02,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 36. [2018-01-24 23:26:02,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 23:26:02,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 39 transitions. [2018-01-24 23:26:02,655 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 39 transitions. Word has length 12 [2018-01-24 23:26:02,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:02,655 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 39 transitions. [2018-01-24 23:26:02,655 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 23:26:02,655 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 39 transitions. [2018-01-24 23:26:02,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 23:26:02,656 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:02,656 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:02,656 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:02,657 INFO L82 PathProgramCache]: Analyzing trace with hash -209255178, now seen corresponding path program 1 times [2018-01-24 23:26:02,657 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:02,658 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:02,658 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:02,658 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:02,659 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:02,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:02,664 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:02,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,717 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 23:26:02,717 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-24 23:26:02,717 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 23:26:02,718 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 23:26:02,718 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 23:26:02,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 23:26:02,719 INFO L87 Difference]: Start difference. First operand 36 states and 39 transitions. Second operand 4 states. [2018-01-24 23:26:02,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:02,744 INFO L93 Difference]: Finished difference Result 51 states and 54 transitions. [2018-01-24 23:26:02,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 23:26:02,745 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 23:26:02,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:02,745 INFO L225 Difference]: With dead ends: 51 [2018-01-24 23:26:02,745 INFO L226 Difference]: Without dead ends: 36 [2018-01-24 23:26:02,746 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-24 23:26:02,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-01-24 23:26:02,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-01-24 23:26:02,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-01-24 23:26:02,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-01-24 23:26:02,750 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 12 [2018-01-24 23:26:02,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:02,750 INFO L432 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-01-24 23:26:02,750 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 23:26:02,750 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-01-24 23:26:02,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 23:26:02,751 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:02,751 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:02,751 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:02,751 INFO L82 PathProgramCache]: Analyzing trace with hash 2132883772, now seen corresponding path program 2 times [2018-01-24 23:26:02,751 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:02,752 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:02,753 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:02,753 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:02,753 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:02,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:02,762 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:02,810 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,811 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:02,811 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:02,811 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:02,812 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:02,812 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:02,812 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:02,819 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:02,820 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:02,826 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:02,832 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:02,833 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:02,835 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:02,841 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,841 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:02,938 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:02,973 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:02,973 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:02,977 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:02,978 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:02,982 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:02,986 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:02,991 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:02,995 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:03,002 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,002 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:03,010 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,012 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:03,012 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 23:26:03,012 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:03,013 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 23:26:03,013 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 23:26:03,013 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 23:26:03,013 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 5 states. [2018-01-24 23:26:03,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:03,084 INFO L93 Difference]: Finished difference Result 62 states and 67 transitions. [2018-01-24 23:26:03,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 23:26:03,084 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 23:26:03,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:03,085 INFO L225 Difference]: With dead ends: 62 [2018-01-24 23:26:03,086 INFO L226 Difference]: Without dead ends: 59 [2018-01-24 23:26:03,086 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 23:26:03,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-01-24 23:26:03,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 41. [2018-01-24 23:26:03,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-01-24 23:26:03,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 44 transitions. [2018-01-24 23:26:03,093 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 44 transitions. Word has length 17 [2018-01-24 23:26:03,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:03,093 INFO L432 AbstractCegarLoop]: Abstraction has 41 states and 44 transitions. [2018-01-24 23:26:03,093 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 23:26:03,094 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 44 transitions. [2018-01-24 23:26:03,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 23:26:03,094 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:03,095 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:03,095 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:03,095 INFO L82 PathProgramCache]: Analyzing trace with hash 2131223963, now seen corresponding path program 1 times [2018-01-24 23:26:03,095 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:03,096 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:03,096 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:03,097 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:03,097 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:03,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:03,102 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:03,150 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,151 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:03,151 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:03,151 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 18 with the following transitions: [2018-01-24 23:26:03,151 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [14], [16], [18], [20], [24], [28], [33], [34], [56], [57], [58] [2018-01-24 23:26:03,152 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 23:26:03,152 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 23:26:03,362 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 23:26:03,363 INFO L268 AbstractInterpreter]: Visited 15 different actions 35 times. Merged at 10 different actions 20 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 4 variables. [2018-01-24 23:26:03,370 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 23:26:03,370 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:03,370 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:03,384 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:03,384 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:03,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:03,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:03,391 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 23:26:03,392 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:03,414 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-24 23:26:03,434 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-01-24 23:26:03,435 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2, 2] imperfect sequences [5] total 6 [2018-01-24 23:26:03,435 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 23:26:03,435 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 23:26:03,435 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 23:26:03,436 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 23:26:03,436 INFO L87 Difference]: Start difference. First operand 41 states and 44 transitions. Second operand 3 states. [2018-01-24 23:26:03,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:03,446 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-01-24 23:26:03,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 23:26:03,447 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 17 [2018-01-24 23:26:03,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:03,448 INFO L225 Difference]: With dead ends: 49 [2018-01-24 23:26:03,448 INFO L226 Difference]: Without dead ends: 47 [2018-01-24 23:26:03,448 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-01-24 23:26:03,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-01-24 23:26:03,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2018-01-24 23:26:03,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-24 23:26:03,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 48 transitions. [2018-01-24 23:26:03,454 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 48 transitions. Word has length 17 [2018-01-24 23:26:03,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:03,454 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 48 transitions. [2018-01-24 23:26:03,454 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 23:26:03,454 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 48 transitions. [2018-01-24 23:26:03,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 23:26:03,455 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:03,455 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:03,456 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:03,456 INFO L82 PathProgramCache]: Analyzing trace with hash 2059138999, now seen corresponding path program 3 times [2018-01-24 23:26:03,456 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:03,457 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:03,457 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:03,457 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:03,457 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:03,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:03,464 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:03,560 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,560 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:03,561 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:03,561 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:03,561 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:03,561 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:03,561 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:03,573 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:03,573 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:03,580 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,582 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,584 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,586 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,586 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:03,588 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:03,598 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,598 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:03,676 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,708 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:03,708 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:03,712 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:03,712 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:03,717 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,719 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,731 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:03,736 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:03,739 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:03,747 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,747 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:03,776 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,778 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:03,778 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 23:26:03,779 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:03,779 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 23:26:03,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 23:26:03,780 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 23:26:03,780 INFO L87 Difference]: Start difference. First operand 45 states and 48 transitions. Second operand 6 states. [2018-01-24 23:26:03,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:03,865 INFO L93 Difference]: Finished difference Result 92 states and 99 transitions. [2018-01-24 23:26:03,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 23:26:03,866 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 23:26:03,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:03,867 INFO L225 Difference]: With dead ends: 92 [2018-01-24 23:26:03,867 INFO L226 Difference]: Without dead ends: 89 [2018-01-24 23:26:03,868 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 23:26:03,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-24 23:26:03,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 50. [2018-01-24 23:26:03,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 23:26:03,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 23:26:03,875 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 22 [2018-01-24 23:26:03,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:03,876 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 23:26:03,876 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 23:26:03,876 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 23:26:03,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 23:26:03,877 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:03,877 INFO L322 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:03,877 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:03,877 INFO L82 PathProgramCache]: Analyzing trace with hash -6617899, now seen corresponding path program 1 times [2018-01-24 23:26:03,877 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:03,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:03,878 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:03,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:03,878 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:03,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:03,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:03,953 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:03,953 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:03,953 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:03,953 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 28 with the following transitions: [2018-01-24 23:26:03,953 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [14], [16], [18], [20], [24], [28], [33], [34], [35], [37], [40], [46], [53], [55], [56], [57], [58], [60], [61] [2018-01-24 23:26:03,954 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 23:26:03,954 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 23:26:04,289 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 23:26:04,289 INFO L268 AbstractInterpreter]: Visited 23 different actions 81 times. Merged at 14 different actions 39 times. Never widened. Found 5 fixpoints after 3 different actions. Largest state had 5 variables. [2018-01-24 23:26:04,295 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 23:26:04,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:04,296 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:04,308 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:04,308 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:04,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:04,325 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:04,398 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,399 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:04,419 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,447 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:04,447 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:04,451 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:04,451 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:04,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:04,466 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:04,473 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,473 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:04,502 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,507 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:04,508 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 9 [2018-01-24 23:26:04,508 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:04,508 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 23:26:04,508 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 23:26:04,508 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 23:26:04,509 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 8 states. [2018-01-24 23:26:04,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:04,573 INFO L93 Difference]: Finished difference Result 71 states and 76 transitions. [2018-01-24 23:26:04,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 23:26:04,574 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-01-24 23:26:04,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:04,575 INFO L225 Difference]: With dead ends: 71 [2018-01-24 23:26:04,575 INFO L226 Difference]: Without dead ends: 50 [2018-01-24 23:26:04,577 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 101 SyntacticMatches, 4 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=46, Unknown=0, NotChecked=0, Total=72 [2018-01-24 23:26:04,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-24 23:26:04,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-01-24 23:26:04,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 23:26:04,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 53 transitions. [2018-01-24 23:26:04,582 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 53 transitions. Word has length 27 [2018-01-24 23:26:04,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:04,583 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 53 transitions. [2018-01-24 23:26:04,583 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 23:26:04,583 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 53 transitions. [2018-01-24 23:26:04,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 23:26:04,584 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:04,584 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:04,584 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:04,584 INFO L82 PathProgramCache]: Analyzing trace with hash -1173615076, now seen corresponding path program 4 times [2018-01-24 23:26:04,584 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:04,585 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:04,585 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:04,585 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:04,585 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:04,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:04,591 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:04,684 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,684 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:04,684 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:04,684 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:04,685 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:04,685 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:04,685 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:04,693 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:04,693 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:04,700 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:04,701 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:04,709 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,710 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:04,780 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,800 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:04,800 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:04,803 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:04,804 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:04,818 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:04,820 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:04,827 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,827 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:04,857 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:04,859 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:04,859 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 23:26:04,860 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:04,860 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 23:26:04,860 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 23:26:04,860 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 23:26:04,861 INFO L87 Difference]: Start difference. First operand 50 states and 53 transitions. Second operand 7 states. [2018-01-24 23:26:05,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:05,045 INFO L93 Difference]: Finished difference Result 97 states and 104 transitions. [2018-01-24 23:26:05,046 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 23:26:05,046 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 23:26:05,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:05,047 INFO L225 Difference]: With dead ends: 97 [2018-01-24 23:26:05,047 INFO L226 Difference]: Without dead ends: 94 [2018-01-24 23:26:05,048 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 23:26:05,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-01-24 23:26:05,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 55. [2018-01-24 23:26:05,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 23:26:05,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 59 transitions. [2018-01-24 23:26:05,057 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 59 transitions. Word has length 27 [2018-01-24 23:26:05,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:05,057 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 59 transitions. [2018-01-24 23:26:05,058 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 23:26:05,058 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 59 transitions. [2018-01-24 23:26:05,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 23:26:05,059 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:05,059 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:05,059 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:05,062 INFO L82 PathProgramCache]: Analyzing trace with hash 155329936, now seen corresponding path program 2 times [2018-01-24 23:26:05,062 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:05,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:05,063 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:05,063 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:05,063 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:05,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:05,079 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:05,197 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,197 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:05,221 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:05,222 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:05,222 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:05,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:05,222 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:05,230 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:05,230 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:05,234 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,238 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,239 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:05,241 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:05,263 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,263 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:05,345 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,375 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:05,376 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:05,379 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:05,380 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:05,385 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,391 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:05,399 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:05,407 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 2 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,407 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:05,448 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,450 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:05,450 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 14 [2018-01-24 23:26:05,450 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:05,451 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 23:26:05,451 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 23:26:05,451 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=144, Unknown=0, NotChecked=0, Total=210 [2018-01-24 23:26:05,451 INFO L87 Difference]: Start difference. First operand 55 states and 59 transitions. Second operand 9 states. [2018-01-24 23:26:05,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:05,565 INFO L93 Difference]: Finished difference Result 72 states and 78 transitions. [2018-01-24 23:26:05,565 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 23:26:05,565 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 32 [2018-01-24 23:26:05,565 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:05,566 INFO L225 Difference]: With dead ends: 72 [2018-01-24 23:26:05,566 INFO L226 Difference]: Without dead ends: 55 [2018-01-24 23:26:05,566 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:26:05,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-01-24 23:26:05,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-01-24 23:26:05,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-01-24 23:26:05,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 58 transitions. [2018-01-24 23:26:05,572 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 58 transitions. Word has length 32 [2018-01-24 23:26:05,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:05,573 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 58 transitions. [2018-01-24 23:26:05,573 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 23:26:05,573 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 58 transitions. [2018-01-24 23:26:05,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 23:26:05,574 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:05,574 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:05,574 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:05,574 INFO L82 PathProgramCache]: Analyzing trace with hash -1011667241, now seen corresponding path program 5 times [2018-01-24 23:26:05,574 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:05,575 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:05,575 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:05,576 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:05,576 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:05,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:05,583 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:05,665 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,665 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:05,665 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:05,665 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:05,665 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:05,665 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:05,665 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:05,670 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:05,670 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:05,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,675 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,676 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,677 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,680 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,680 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:05,682 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:05,690 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,690 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:05,757 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,784 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:05,785 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:05,788 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:05,788 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:05,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:05,817 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:05,820 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:05,826 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,826 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:05,833 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:05,835 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:05,835 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 23:26:05,835 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:05,836 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 23:26:05,836 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 23:26:05,836 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 23:26:05,836 INFO L87 Difference]: Start difference. First operand 55 states and 58 transitions. Second operand 8 states. [2018-01-24 23:26:05,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:05,936 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-01-24 23:26:05,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 23:26:05,936 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 23:26:05,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:05,937 INFO L225 Difference]: With dead ends: 102 [2018-01-24 23:26:05,937 INFO L226 Difference]: Without dead ends: 99 [2018-01-24 23:26:05,938 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 23:26:05,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-01-24 23:26:05,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 60. [2018-01-24 23:26:05,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-01-24 23:26:05,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2018-01-24 23:26:05,945 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 32 [2018-01-24 23:26:05,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:05,945 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2018-01-24 23:26:05,945 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 23:26:05,945 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2018-01-24 23:26:05,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 23:26:05,947 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:05,947 INFO L322 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:05,947 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:05,947 INFO L82 PathProgramCache]: Analyzing trace with hash -903265867, now seen corresponding path program 3 times [2018-01-24 23:26:05,947 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:05,948 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:05,948 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:05,948 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:05,948 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:05,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:05,956 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:06,026 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,026 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,026 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:06,026 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:06,026 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:06,027 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,027 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:06,036 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:06,036 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:06,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:06,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:06,053 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:06,055 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:06,075 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 23:26:06,076 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:06,125 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 23:26:06,159 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,159 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:06,165 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:06,165 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:06,171 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:06,175 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:06,181 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:06,183 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:06,185 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 23:26:06,185 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:06,194 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 23:26:06,195 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:06,195 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 3, 3, 3, 3] total 12 [2018-01-24 23:26:06,195 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:06,195 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 23:26:06,195 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 23:26:06,196 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2018-01-24 23:26:06,196 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 11 states. [2018-01-24 23:26:06,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:06,260 INFO L93 Difference]: Finished difference Result 97 states and 113 transitions. [2018-01-24 23:26:06,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 23:26:06,263 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 37 [2018-01-24 23:26:06,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:06,264 INFO L225 Difference]: With dead ends: 97 [2018-01-24 23:26:06,264 INFO L226 Difference]: Without dead ends: 74 [2018-01-24 23:26:06,265 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-01-24 23:26:06,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-01-24 23:26:06,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 72. [2018-01-24 23:26:06,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-01-24 23:26:06,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 77 transitions. [2018-01-24 23:26:06,272 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 77 transitions. Word has length 37 [2018-01-24 23:26:06,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:06,272 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 77 transitions. [2018-01-24 23:26:06,272 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 23:26:06,272 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 77 transitions. [2018-01-24 23:26:06,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 23:26:06,274 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:06,274 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:06,274 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:06,274 INFO L82 PathProgramCache]: Analyzing trace with hash -2070263044, now seen corresponding path program 6 times [2018-01-24 23:26:06,275 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:06,275 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:06,275 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:06,275 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:06,276 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:06,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:06,281 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:06,345 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,346 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,346 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:06,346 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:06,346 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:06,346 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,346 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:06,351 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:06,351 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:06,354 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,355 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,356 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,357 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,358 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,359 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,360 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,360 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:06,361 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:06,369 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,369 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:06,439 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,463 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,463 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:06,469 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:06,469 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:06,473 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,478 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,482 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,488 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,495 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,504 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:06,508 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:06,510 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:06,516 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,517 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:06,526 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,528 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:06,528 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 23:26:06,528 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:06,529 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 23:26:06,529 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 23:26:06,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:26:06,529 INFO L87 Difference]: Start difference. First operand 72 states and 77 transitions. Second operand 9 states. [2018-01-24 23:26:06,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:06,618 INFO L93 Difference]: Finished difference Result 155 states and 170 transitions. [2018-01-24 23:26:06,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 23:26:06,619 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 23:26:06,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:06,620 INFO L225 Difference]: With dead ends: 155 [2018-01-24 23:26:06,620 INFO L226 Difference]: Without dead ends: 152 [2018-01-24 23:26:06,621 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:26:06,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-24 23:26:06,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 77. [2018-01-24 23:26:06,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-01-24 23:26:06,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 83 transitions. [2018-01-24 23:26:06,629 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 83 transitions. Word has length 37 [2018-01-24 23:26:06,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:06,629 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 83 transitions. [2018-01-24 23:26:06,629 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 23:26:06,630 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 83 transitions. [2018-01-24 23:26:06,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 23:26:06,630 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:06,631 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:06,631 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:06,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1122500087, now seen corresponding path program 7 times [2018-01-24 23:26:06,631 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:06,632 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:06,632 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:06,632 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:06,632 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:06,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:06,639 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:06,713 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,713 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,713 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:06,713 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:06,713 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:06,713 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,713 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:06,718 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:06,719 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:06,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:06,725 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:06,732 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,732 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:06,839 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,858 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:06,858 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:06,861 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:06,861 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:06,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:06,874 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:06,881 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,881 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:06,892 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:06,894 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:06,894 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 23:26:06,894 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:06,895 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 23:26:06,895 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 23:26:06,895 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 23:26:06,896 INFO L87 Difference]: Start difference. First operand 77 states and 83 transitions. Second operand 10 states. [2018-01-24 23:26:07,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:07,011 INFO L93 Difference]: Finished difference Result 185 states and 204 transitions. [2018-01-24 23:26:07,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 23:26:07,011 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 23:26:07,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:07,012 INFO L225 Difference]: With dead ends: 185 [2018-01-24 23:26:07,012 INFO L226 Difference]: Without dead ends: 182 [2018-01-24 23:26:07,013 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 23:26:07,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-01-24 23:26:07,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 82. [2018-01-24 23:26:07,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-24 23:26:07,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 89 transitions. [2018-01-24 23:26:07,023 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 89 transitions. Word has length 42 [2018-01-24 23:26:07,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:07,023 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 89 transitions. [2018-01-24 23:26:07,023 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 23:26:07,023 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 89 transitions. [2018-01-24 23:26:07,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 23:26:07,024 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:07,025 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:07,025 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:07,025 INFO L82 PathProgramCache]: Analyzing trace with hash -676728868, now seen corresponding path program 8 times [2018-01-24 23:26:07,025 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:07,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:07,026 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:07,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:07,026 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:07,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:07,032 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:07,173 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,173 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:07,173 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:07,173 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:07,173 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:07,174 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:07,174 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:07,182 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:07,182 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:07,186 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:07,190 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:07,191 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:07,192 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:07,201 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,201 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:07,358 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:07,379 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:07,382 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:07,382 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:07,386 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:07,394 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:07,400 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:07,403 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:07,412 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,412 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:07,425 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,426 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:07,427 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 23:26:07,427 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:07,427 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 23:26:07,427 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 23:26:07,428 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 23:26:07,428 INFO L87 Difference]: Start difference. First operand 82 states and 89 transitions. Second operand 11 states. [2018-01-24 23:26:07,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:07,579 INFO L93 Difference]: Finished difference Result 215 states and 238 transitions. [2018-01-24 23:26:07,579 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 23:26:07,579 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 23:26:07,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:07,581 INFO L225 Difference]: With dead ends: 215 [2018-01-24 23:26:07,581 INFO L226 Difference]: Without dead ends: 212 [2018-01-24 23:26:07,582 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 23:26:07,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 212 states. [2018-01-24 23:26:07,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 212 to 87. [2018-01-24 23:26:07,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-01-24 23:26:07,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 95 transitions. [2018-01-24 23:26:07,593 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 95 transitions. Word has length 47 [2018-01-24 23:26:07,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:07,593 INFO L432 AbstractCegarLoop]: Abstraction has 87 states and 95 transitions. [2018-01-24 23:26:07,593 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 23:26:07,593 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 95 transitions. [2018-01-24 23:26:07,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 23:26:07,594 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:07,594 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:07,595 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:07,595 INFO L82 PathProgramCache]: Analyzing trace with hash -633576169, now seen corresponding path program 9 times [2018-01-24 23:26:07,595 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:07,596 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:07,596 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:07,596 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:07,596 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:07,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:07,604 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:07,730 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,730 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:07,730 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:07,731 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:07,731 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:07,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:07,731 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:07,739 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:07,739 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:07,743 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,744 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,745 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,746 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,747 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,749 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,750 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,752 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,754 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:07,756 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:07,758 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:07,770 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:07,770 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:07,978 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,010 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:08,011 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:08,014 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:08,014 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:08,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,022 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,027 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,052 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,060 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,070 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:08,105 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:08,114 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:08,125 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,126 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:08,142 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,144 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:08,144 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 23:26:08,144 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:08,145 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 23:26:08,145 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 23:26:08,145 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:26:08,145 INFO L87 Difference]: Start difference. First operand 87 states and 95 transitions. Second operand 12 states. [2018-01-24 23:26:08,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:08,399 INFO L93 Difference]: Finished difference Result 245 states and 272 transitions. [2018-01-24 23:26:08,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 23:26:08,400 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 23:26:08,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:08,402 INFO L225 Difference]: With dead ends: 245 [2018-01-24 23:26:08,402 INFO L226 Difference]: Without dead ends: 242 [2018-01-24 23:26:08,403 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:26:08,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-24 23:26:08,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 92. [2018-01-24 23:26:08,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-01-24 23:26:08,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 101 transitions. [2018-01-24 23:26:08,413 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 101 transitions. Word has length 52 [2018-01-24 23:26:08,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:08,413 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 101 transitions. [2018-01-24 23:26:08,413 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 23:26:08,414 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 101 transitions. [2018-01-24 23:26:08,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 23:26:08,414 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:08,414 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:08,414 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:08,414 INFO L82 PathProgramCache]: Analyzing trace with hash -1365705540, now seen corresponding path program 10 times [2018-01-24 23:26:08,415 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:08,415 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:08,415 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:08,415 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:08,415 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:08,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:08,423 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:08,526 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,526 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:08,526 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:08,526 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:08,527 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:08,527 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:08,527 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:08,532 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:08,532 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:08,542 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:08,544 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:08,553 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,553 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:08,698 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,719 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:08,719 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:08,722 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:08,722 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:08,754 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:08,757 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:08,768 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,768 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:08,788 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:08,789 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:08,789 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 23:26:08,790 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:08,790 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 23:26:08,790 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 23:26:08,790 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 23:26:08,790 INFO L87 Difference]: Start difference. First operand 92 states and 101 transitions. Second operand 13 states. [2018-01-24 23:26:09,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:09,028 INFO L93 Difference]: Finished difference Result 275 states and 306 transitions. [2018-01-24 23:26:09,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 23:26:09,029 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 23:26:09,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:09,030 INFO L225 Difference]: With dead ends: 275 [2018-01-24 23:26:09,030 INFO L226 Difference]: Without dead ends: 272 [2018-01-24 23:26:09,031 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 23:26:09,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-01-24 23:26:09,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 97. [2018-01-24 23:26:09,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-24 23:26:09,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 107 transitions. [2018-01-24 23:26:09,043 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 107 transitions. Word has length 57 [2018-01-24 23:26:09,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:09,044 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 107 transitions. [2018-01-24 23:26:09,044 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 23:26:09,044 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 107 transitions. [2018-01-24 23:26:09,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 23:26:09,044 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:09,045 INFO L322 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:09,045 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:09,045 INFO L82 PathProgramCache]: Analyzing trace with hash -1933470172, now seen corresponding path program 4 times [2018-01-24 23:26:09,045 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:09,046 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,046 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:09,046 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,046 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:09,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:09,056 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:09,167 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 10 proven. 59 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-24 23:26:09,167 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:09,167 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:09,167 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:09,167 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:09,167 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:09,167 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:09,173 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:09,173 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:09,182 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:09,184 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:09,229 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 23:26:09,229 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:09,282 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 23:26:09,314 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:09,315 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:09,318 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:09,318 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:09,352 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:09,355 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:09,383 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 23:26:09,383 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:09,405 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 54 trivial. 0 not checked. [2018-01-24 23:26:09,407 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:09,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 5, 5, 5, 5] total 18 [2018-01-24 23:26:09,407 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:09,408 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 23:26:09,408 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 23:26:09,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2018-01-24 23:26:09,408 INFO L87 Difference]: Start difference. First operand 97 states and 107 transitions. Second operand 15 states. [2018-01-24 23:26:09,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:09,574 INFO L93 Difference]: Finished difference Result 134 states and 152 transitions. [2018-01-24 23:26:09,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 23:26:09,575 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 62 [2018-01-24 23:26:09,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:09,576 INFO L225 Difference]: With dead ends: 134 [2018-01-24 23:26:09,576 INFO L226 Difference]: Without dead ends: 105 [2018-01-24 23:26:09,577 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 260 GetRequests, 238 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=359, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:26:09,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-01-24 23:26:09,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 103. [2018-01-24 23:26:09,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-01-24 23:26:09,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 113 transitions. [2018-01-24 23:26:09,585 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 113 transitions. Word has length 62 [2018-01-24 23:26:09,585 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:09,585 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 113 transitions. [2018-01-24 23:26:09,585 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 23:26:09,585 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 113 transitions. [2018-01-24 23:26:09,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 23:26:09,586 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:09,586 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:09,586 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:09,586 INFO L82 PathProgramCache]: Analyzing trace with hash -116235209, now seen corresponding path program 11 times [2018-01-24 23:26:09,586 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:09,587 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,587 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:09,587 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,587 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:09,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:09,594 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:09,845 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:09,845 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:09,846 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:09,846 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:09,846 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:09,846 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:09,846 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:09,853 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:09,853 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:09,856 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,859 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,863 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,872 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:09,878 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:09,880 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:09,891 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:09,892 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:10,259 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,280 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,280 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:10,283 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:10,283 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:10,286 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,293 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,303 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,310 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,318 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,330 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,377 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,404 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:10,408 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:10,424 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,424 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:10,446 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,447 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:10,448 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 23:26:10,448 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:10,448 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 23:26:10,448 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 23:26:10,448 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 23:26:10,449 INFO L87 Difference]: Start difference. First operand 103 states and 113 transitions. Second operand 14 states. [2018-01-24 23:26:10,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:10,694 INFO L93 Difference]: Finished difference Result 328 states and 367 transitions. [2018-01-24 23:26:10,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 23:26:10,694 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 23:26:10,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:10,697 INFO L225 Difference]: With dead ends: 328 [2018-01-24 23:26:10,697 INFO L226 Difference]: Without dead ends: 325 [2018-01-24 23:26:10,697 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 23:26:10,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2018-01-24 23:26:10,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 108. [2018-01-24 23:26:10,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-01-24 23:26:10,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 119 transitions. [2018-01-24 23:26:10,713 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 119 transitions. Word has length 62 [2018-01-24 23:26:10,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:10,713 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 119 transitions. [2018-01-24 23:26:10,713 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 23:26:10,713 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 119 transitions. [2018-01-24 23:26:10,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 23:26:10,714 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:10,714 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:10,715 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:10,715 INFO L82 PathProgramCache]: Analyzing trace with hash -414879332, now seen corresponding path program 12 times [2018-01-24 23:26:10,715 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:10,716 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:10,716 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:10,716 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:10,716 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:10,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:10,725 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:10,886 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,886 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,886 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:10,886 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:10,886 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:10,887 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,887 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:10,891 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:10,891 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:10,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,896 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,896 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,899 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,901 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,903 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,905 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:10,908 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:10,910 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:10,921 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,921 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:11,116 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,137 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,137 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:11,140 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:11,140 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:11,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,145 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,172 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,197 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,223 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:11,301 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:11,304 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,319 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,319 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:11,336 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,337 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:11,337 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 23:26:11,337 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:11,338 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 23:26:11,338 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 23:26:11,338 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 23:26:11,339 INFO L87 Difference]: Start difference. First operand 108 states and 119 transitions. Second operand 15 states. [2018-01-24 23:26:11,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:11,634 INFO L93 Difference]: Finished difference Result 364 states and 408 transitions. [2018-01-24 23:26:11,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 23:26:11,634 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 23:26:11,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:11,636 INFO L225 Difference]: With dead ends: 364 [2018-01-24 23:26:11,636 INFO L226 Difference]: Without dead ends: 361 [2018-01-24 23:26:11,636 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 23:26:11,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 361 states. [2018-01-24 23:26:11,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 361 to 113. [2018-01-24 23:26:11,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-01-24 23:26:11,650 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 125 transitions. [2018-01-24 23:26:11,650 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 125 transitions. Word has length 67 [2018-01-24 23:26:11,650 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:11,650 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 125 transitions. [2018-01-24 23:26:11,650 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 23:26:11,650 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 125 transitions. [2018-01-24 23:26:11,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 23:26:11,651 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:11,651 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:11,652 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:11,652 INFO L82 PathProgramCache]: Analyzing trace with hash -1135871145, now seen corresponding path program 13 times [2018-01-24 23:26:11,652 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:11,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:11,653 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:11,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:11,653 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:11,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:11,660 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:11,841 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,841 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,841 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:11,841 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:11,842 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:11,842 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,842 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:11,846 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:11,847 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:11,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:11,858 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,869 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,869 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,091 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,111 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,111 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:12,114 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:12,114 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:12,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:12,136 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:12,152 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,153 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,168 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,169 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:12,169 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 23:26:12,169 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:12,169 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 23:26:12,169 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 23:26:12,170 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 23:26:12,170 INFO L87 Difference]: Start difference. First operand 113 states and 125 transitions. Second operand 16 states. [2018-01-24 23:26:12,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:12,510 INFO L93 Difference]: Finished difference Result 400 states and 449 transitions. [2018-01-24 23:26:12,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 23:26:12,510 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 23:26:12,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:12,512 INFO L225 Difference]: With dead ends: 400 [2018-01-24 23:26:12,513 INFO L226 Difference]: Without dead ends: 397 [2018-01-24 23:26:12,513 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 23:26:12,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2018-01-24 23:26:12,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 118. [2018-01-24 23:26:12,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-24 23:26:12,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 131 transitions. [2018-01-24 23:26:12,527 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 131 transitions. Word has length 72 [2018-01-24 23:26:12,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:12,527 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 131 transitions. [2018-01-24 23:26:12,527 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 23:26:12,527 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 131 transitions. [2018-01-24 23:26:12,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 23:26:12,528 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:12,528 INFO L322 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:12,528 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:12,528 INFO L82 PathProgramCache]: Analyzing trace with hash 1226682691, now seen corresponding path program 5 times [2018-01-24 23:26:12,528 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:12,529 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:12,529 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:12,529 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:12,529 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:12,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:12,538 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:12,655 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 24 proven. 89 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-01-24 23:26:12,655 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,655 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:12,655 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:12,655 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:12,655 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,655 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:12,661 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:12,661 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:12,664 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,666 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,670 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,674 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,675 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:12,676 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:12,711 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 23:26:12,711 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,772 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 23:26:12,792 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,792 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:12,795 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:12,795 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:12,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,846 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,853 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:12,857 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:12,867 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 23:26:12,867 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,879 INFO L134 CoverageAnalysis]: Checked inductivity of 137 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 89 trivial. 0 not checked. [2018-01-24 23:26:12,880 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:12,880 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 22 [2018-01-24 23:26:12,880 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:12,880 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 23:26:12,881 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 23:26:12,881 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-01-24 23:26:12,881 INFO L87 Difference]: Start difference. First operand 118 states and 131 transitions. Second operand 18 states. [2018-01-24 23:26:13,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:13,079 INFO L93 Difference]: Finished difference Result 161 states and 183 transitions. [2018-01-24 23:26:13,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 23:26:13,079 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 77 [2018-01-24 23:26:13,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:13,080 INFO L225 Difference]: With dead ends: 161 [2018-01-24 23:26:13,080 INFO L226 Difference]: Without dead ends: 126 [2018-01-24 23:26:13,080 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 296 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=146, Invalid=556, Unknown=0, NotChecked=0, Total=702 [2018-01-24 23:26:13,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-24 23:26:13,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-01-24 23:26:13,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-01-24 23:26:13,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 137 transitions. [2018-01-24 23:26:13,091 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 137 transitions. Word has length 77 [2018-01-24 23:26:13,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:13,091 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 137 transitions. [2018-01-24 23:26:13,091 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 23:26:13,092 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 137 transitions. [2018-01-24 23:26:13,092 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 23:26:13,092 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:13,093 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:13,093 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:13,093 INFO L82 PathProgramCache]: Analyzing trace with hash 571297404, now seen corresponding path program 14 times [2018-01-24 23:26:13,093 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:13,093 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:13,094 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:13,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:13,094 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:13,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:13,101 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:13,415 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,415 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,416 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:13,416 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:13,416 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:13,416 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,416 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:13,423 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:13,423 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:13,427 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,433 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,435 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:13,437 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:13,455 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,455 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:13,909 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,931 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,931 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:13,934 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:13,934 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:13,939 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,950 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,957 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:13,961 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:13,979 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,979 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:14,014 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (40)] Exception during sending of exit command (exit): Broken pipe [2018-01-24 23:26:14,015 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:14,015 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 23:26:14,015 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:14,016 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 23:26:14,016 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 23:26:14,016 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:26:14,017 INFO L87 Difference]: Start difference. First operand 124 states and 137 transitions. Second operand 17 states. [2018-01-24 23:26:14,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:14,403 INFO L93 Difference]: Finished difference Result 465 states and 524 transitions. [2018-01-24 23:26:14,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 23:26:14,403 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 23:26:14,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:14,405 INFO L225 Difference]: With dead ends: 465 [2018-01-24 23:26:14,405 INFO L226 Difference]: Without dead ends: 462 [2018-01-24 23:26:14,406 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:26:14,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-24 23:26:14,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 129. [2018-01-24 23:26:14,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-01-24 23:26:14,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 143 transitions. [2018-01-24 23:26:14,424 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 143 transitions. Word has length 77 [2018-01-24 23:26:14,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:14,424 INFO L432 AbstractCegarLoop]: Abstraction has 129 states and 143 transitions. [2018-01-24 23:26:14,425 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 23:26:14,425 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 143 transitions. [2018-01-24 23:26:14,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 23:26:14,425 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:14,425 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:14,425 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:14,425 INFO L82 PathProgramCache]: Analyzing trace with hash 239807095, now seen corresponding path program 15 times [2018-01-24 23:26:14,426 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:14,426 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:14,426 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:14,426 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:14,426 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:14,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:14,435 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:14,650 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,650 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:14,650 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:14,651 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:14,651 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:14,651 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:14,651 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:14,657 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:14,658 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:14,661 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,662 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,663 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,665 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,666 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,667 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,668 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,670 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,671 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,673 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,675 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,676 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,679 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,681 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,684 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,684 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:14,686 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:14,704 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,704 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:14,986 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,006 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:15,007 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:15,009 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:15,010 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:15,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,015 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,023 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,028 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,035 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,078 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,140 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,169 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,210 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,255 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:15,263 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:15,267 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:15,280 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,281 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:15,300 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,301 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:15,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 23:26:15,301 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:15,302 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 23:26:15,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 23:26:15,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 23:26:15,302 INFO L87 Difference]: Start difference. First operand 129 states and 143 transitions. Second operand 18 states. [2018-01-24 23:26:15,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:15,767 INFO L93 Difference]: Finished difference Result 507 states and 572 transitions. [2018-01-24 23:26:15,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 23:26:15,768 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 23:26:15,769 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:15,771 INFO L225 Difference]: With dead ends: 507 [2018-01-24 23:26:15,771 INFO L226 Difference]: Without dead ends: 504 [2018-01-24 23:26:15,772 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 23:26:15,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2018-01-24 23:26:15,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 134. [2018-01-24 23:26:15,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 23:26:15,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 149 transitions. [2018-01-24 23:26:15,795 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 149 transitions. Word has length 82 [2018-01-24 23:26:15,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:15,795 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 149 transitions. [2018-01-24 23:26:15,795 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 23:26:15,795 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 149 transitions. [2018-01-24 23:26:15,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 23:26:15,796 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:15,797 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:15,797 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:15,797 INFO L82 PathProgramCache]: Analyzing trace with hash -1580297380, now seen corresponding path program 16 times [2018-01-24 23:26:15,797 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:15,798 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:15,798 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:15,798 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:15,798 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:15,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:15,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:16,299 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:16,299 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:16,299 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:16,300 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:16,300 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:16,300 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:16,308 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:16,308 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:16,332 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:16,335 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:16,355 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,356 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:16,772 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,792 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:16,792 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:16,795 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:16,795 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:16,859 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:16,862 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:16,876 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,876 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:16,894 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,896 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:16,896 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 23:26:16,896 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:16,896 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 23:26:16,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 23:26:16,897 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 23:26:16,897 INFO L87 Difference]: Start difference. First operand 134 states and 149 transitions. Second operand 19 states. [2018-01-24 23:26:17,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:17,390 INFO L93 Difference]: Finished difference Result 549 states and 620 transitions. [2018-01-24 23:26:17,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 23:26:17,391 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 23:26:17,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:17,393 INFO L225 Difference]: With dead ends: 549 [2018-01-24 23:26:17,393 INFO L226 Difference]: Without dead ends: 546 [2018-01-24 23:26:17,393 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 23:26:17,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-24 23:26:17,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 139. [2018-01-24 23:26:17,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-24 23:26:17,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 155 transitions. [2018-01-24 23:26:17,410 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 155 transitions. Word has length 87 [2018-01-24 23:26:17,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:17,410 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 155 transitions. [2018-01-24 23:26:17,410 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 23:26:17,410 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 155 transitions. [2018-01-24 23:26:17,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 23:26:17,411 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:17,411 INFO L322 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:17,411 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:17,411 INFO L82 PathProgramCache]: Analyzing trace with hash 677887160, now seen corresponding path program 6 times [2018-01-24 23:26:17,411 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:17,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:17,412 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:17,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:17,412 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:17,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:17,421 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:17,572 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 44 proven. 124 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-01-24 23:26:17,572 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:17,572 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:17,572 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:17,572 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:17,573 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:17,573 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:17,577 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:17,577 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:17,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,593 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:17,595 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:17,644 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 23:26:17,645 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:17,738 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 23:26:17,758 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:17,758 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:17,761 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:17,761 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:17,766 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,837 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:17,840 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:17,855 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 23:26:17,855 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:17,870 INFO L134 CoverageAnalysis]: Checked inductivity of 208 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-01-24 23:26:17,871 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:17,871 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 7, 7, 7, 7] total 26 [2018-01-24 23:26:17,871 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:17,872 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 23:26:17,872 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 23:26:17,872 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=571, Unknown=0, NotChecked=0, Total=702 [2018-01-24 23:26:17,872 INFO L87 Difference]: Start difference. First operand 139 states and 155 transitions. Second operand 21 states. [2018-01-24 23:26:18,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:18,045 INFO L93 Difference]: Finished difference Result 188 states and 214 transitions. [2018-01-24 23:26:18,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 23:26:18,045 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 92 [2018-01-24 23:26:18,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:18,046 INFO L225 Difference]: With dead ends: 188 [2018-01-24 23:26:18,046 INFO L226 Difference]: Without dead ends: 147 [2018-01-24 23:26:18,047 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 354 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 238 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=196, Invalid=796, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:26:18,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-24 23:26:18,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-01-24 23:26:18,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-01-24 23:26:18,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 161 transitions. [2018-01-24 23:26:18,059 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 161 transitions. Word has length 92 [2018-01-24 23:26:18,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:18,060 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 161 transitions. [2018-01-24 23:26:18,060 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 23:26:18,060 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 161 transitions. [2018-01-24 23:26:18,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 23:26:18,060 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:18,060 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:18,061 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:18,061 INFO L82 PathProgramCache]: Analyzing trace with hash -957222505, now seen corresponding path program 17 times [2018-01-24 23:26:18,061 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:18,061 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:18,061 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:18,061 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:18,061 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:18,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:18,068 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:18,347 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:18,347 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:18,347 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:18,348 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:18,348 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:18,348 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:18,354 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:18,354 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:18,358 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,361 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,362 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,364 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,369 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,371 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,375 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,377 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,383 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,388 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,391 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,396 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,396 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:18,399 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:18,413 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,413 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:18,803 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,823 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:18,823 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:18,826 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:18,826 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:18,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,840 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,861 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,871 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,886 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:18,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,044 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,080 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,121 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,169 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,179 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:19,183 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:19,200 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:19,200 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:19,218 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:19,219 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:19,220 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 23:26:19,220 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:19,220 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 23:26:19,220 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 23:26:19,221 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 23:26:19,221 INFO L87 Difference]: Start difference. First operand 145 states and 161 transitions. Second operand 20 states. [2018-01-24 23:26:19,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:19,777 INFO L93 Difference]: Finished difference Result 626 states and 709 transitions. [2018-01-24 23:26:19,778 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 23:26:19,778 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 23:26:19,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:19,780 INFO L225 Difference]: With dead ends: 626 [2018-01-24 23:26:19,780 INFO L226 Difference]: Without dead ends: 623 [2018-01-24 23:26:19,780 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 23:26:19,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states. [2018-01-24 23:26:19,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 150. [2018-01-24 23:26:19,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-01-24 23:26:19,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 167 transitions. [2018-01-24 23:26:19,811 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 167 transitions. Word has length 92 [2018-01-24 23:26:19,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:19,811 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 167 transitions. [2018-01-24 23:26:19,811 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 23:26:19,811 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 167 transitions. [2018-01-24 23:26:19,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 23:26:19,812 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:19,812 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:19,812 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:19,813 INFO L82 PathProgramCache]: Analyzing trace with hash 736575548, now seen corresponding path program 18 times [2018-01-24 23:26:19,813 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:19,813 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:19,813 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:19,813 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:19,813 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:19,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:19,821 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:20,160 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,160 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:20,160 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:20,160 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:20,160 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:20,160 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:20,160 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:20,165 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:20,165 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:20,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,170 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,170 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,171 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,172 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,173 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,174 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,175 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,177 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,178 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,181 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,184 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,188 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,192 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,193 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:20,195 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:20,212 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,212 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:20,706 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,739 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:20,739 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:20,742 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:20,742 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:20,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,751 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,754 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,764 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,854 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,875 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,927 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,959 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:20,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:21,044 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:21,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:21,168 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:21,172 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:21,188 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:21,189 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:21,207 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:21,208 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:21,208 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 23:26:21,208 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:21,209 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 23:26:21,209 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 23:26:21,209 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 23:26:21,209 INFO L87 Difference]: Start difference. First operand 150 states and 167 transitions. Second operand 21 states. [2018-01-24 23:26:21,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:21,814 INFO L93 Difference]: Finished difference Result 674 states and 764 transitions. [2018-01-24 23:26:21,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 23:26:21,815 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 23:26:21,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:21,817 INFO L225 Difference]: With dead ends: 674 [2018-01-24 23:26:21,818 INFO L226 Difference]: Without dead ends: 671 [2018-01-24 23:26:21,818 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 23:26:21,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 671 states. [2018-01-24 23:26:21,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 671 to 155. [2018-01-24 23:26:21,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-01-24 23:26:21,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 173 transitions. [2018-01-24 23:26:21,852 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 173 transitions. Word has length 97 [2018-01-24 23:26:21,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:21,852 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 173 transitions. [2018-01-24 23:26:21,852 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 23:26:21,853 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 173 transitions. [2018-01-24 23:26:21,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 23:26:21,854 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:21,854 INFO L322 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:21,854 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:21,854 INFO L82 PathProgramCache]: Analyzing trace with hash -891985897, now seen corresponding path program 7 times [2018-01-24 23:26:21,854 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:21,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:21,855 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:21,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:21,855 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:21,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:21,865 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:22,148 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 70 proven. 164 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-24 23:26:22,148 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:22,148 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:22,148 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:22,148 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:22,148 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:22,148 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:22,155 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:22,155 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:22,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:22,176 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:22,300 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 23:26:22,300 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:22,473 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 23:26:22,493 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:22,493 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:22,496 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:22,496 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:22,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:22,528 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:22,569 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 23:26:22,569 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:22,586 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 0 proven. 108 refuted. 0 times theorem prover too weak. 186 trivial. 0 not checked. [2018-01-24 23:26:22,587 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:22,588 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 8, 8, 8, 8] total 30 [2018-01-24 23:26:22,588 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:22,588 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 23:26:22,588 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 23:26:22,588 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=764, Unknown=0, NotChecked=0, Total=930 [2018-01-24 23:26:22,589 INFO L87 Difference]: Start difference. First operand 155 states and 173 transitions. Second operand 24 states. [2018-01-24 23:26:22,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:22,840 INFO L93 Difference]: Finished difference Result 210 states and 239 transitions. [2018-01-24 23:26:22,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 23:26:22,841 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-01-24 23:26:22,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:22,841 INFO L225 Difference]: With dead ends: 210 [2018-01-24 23:26:22,841 INFO L226 Difference]: Without dead ends: 163 [2018-01-24 23:26:22,842 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 449 GetRequests, 412 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=253, Invalid=1079, Unknown=0, NotChecked=0, Total=1332 [2018-01-24 23:26:22,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-01-24 23:26:22,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 161. [2018-01-24 23:26:22,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-01-24 23:26:22,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 179 transitions. [2018-01-24 23:26:22,859 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 179 transitions. Word has length 107 [2018-01-24 23:26:22,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:22,860 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 179 transitions. [2018-01-24 23:26:22,860 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 23:26:22,860 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 179 transitions. [2018-01-24 23:26:22,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 23:26:22,860 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:22,860 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:22,860 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:22,861 INFO L82 PathProgramCache]: Analyzing trace with hash -878554953, now seen corresponding path program 19 times [2018-01-24 23:26:22,861 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:22,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:22,861 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:22,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:22,861 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:22,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:22,867 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:23,347 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:23,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:23,347 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:23,347 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:23,347 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:23,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:23,347 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:23,352 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:23,352 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:23,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:23,369 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:23,404 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:23,404 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:23,878 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:23,897 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:23,898 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:23,900 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:23,901 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:23,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:23,926 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:23,953 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:23,953 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:23,973 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:23,974 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:23,974 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 23:26:23,974 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:23,974 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 23:26:23,975 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 23:26:23,975 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 23:26:23,975 INFO L87 Difference]: Start difference. First operand 161 states and 179 transitions. Second operand 22 states. [2018-01-24 23:26:24,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:24,658 INFO L93 Difference]: Finished difference Result 757 states and 860 transitions. [2018-01-24 23:26:24,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 23:26:24,659 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 23:26:24,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:24,661 INFO L225 Difference]: With dead ends: 757 [2018-01-24 23:26:24,661 INFO L226 Difference]: Without dead ends: 754 [2018-01-24 23:26:24,662 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 23:26:24,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 754 states. [2018-01-24 23:26:24,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 754 to 166. [2018-01-24 23:26:24,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-24 23:26:24,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 185 transitions. [2018-01-24 23:26:24,701 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 185 transitions. Word has length 102 [2018-01-24 23:26:24,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:24,701 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 185 transitions. [2018-01-24 23:26:24,701 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 23:26:24,701 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 185 transitions. [2018-01-24 23:26:24,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 23:26:24,702 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:24,702 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:24,703 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:24,703 INFO L82 PathProgramCache]: Analyzing trace with hash -399157988, now seen corresponding path program 20 times [2018-01-24 23:26:24,703 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:24,704 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:24,704 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:24,704 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:24,704 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:24,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:24,712 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:25,261 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:25,261 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:25,261 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:25,261 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:25,261 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:25,261 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:25,262 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:25,266 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:25,266 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:25,270 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:25,278 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:25,279 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:25,281 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:25,298 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:25,299 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:25,756 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:25,776 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:25,776 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:25,779 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:25,779 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:25,785 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:25,805 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:25,820 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:25,825 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:25,843 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:25,843 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:25,873 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:25,874 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:25,874 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 23:26:25,875 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:25,875 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 23:26:25,875 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 23:26:25,875 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 23:26:25,876 INFO L87 Difference]: Start difference. First operand 166 states and 185 transitions. Second operand 23 states. [2018-01-24 23:26:26,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:26,803 INFO L93 Difference]: Finished difference Result 811 states and 922 transitions. [2018-01-24 23:26:26,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 23:26:26,804 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 23:26:26,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:26,808 INFO L225 Difference]: With dead ends: 811 [2018-01-24 23:26:26,808 INFO L226 Difference]: Without dead ends: 808 [2018-01-24 23:26:26,809 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 23:26:26,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2018-01-24 23:26:26,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 171. [2018-01-24 23:26:26,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-01-24 23:26:26,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 191 transitions. [2018-01-24 23:26:26,852 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 191 transitions. Word has length 107 [2018-01-24 23:26:26,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:26,853 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 191 transitions. [2018-01-24 23:26:26,853 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 23:26:26,853 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 191 transitions. [2018-01-24 23:26:26,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 23:26:26,854 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:26,854 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:26,854 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:26,854 INFO L82 PathProgramCache]: Analyzing trace with hash 792610775, now seen corresponding path program 21 times [2018-01-24 23:26:26,854 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:26,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:26,855 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:26,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:26,855 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:26,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:26,862 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:27,250 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:27,250 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:27,250 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:27,251 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:27,251 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:27,251 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:27,251 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:27,261 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:27,261 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:27,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,267 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,271 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,274 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,278 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,280 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,289 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,292 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,297 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,301 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,305 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,310 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,315 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,321 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,328 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,334 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:27,335 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:27,339 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:27,382 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:27,382 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:28,175 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,196 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:28,196 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:28,199 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:28,199 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:28,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,208 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,213 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,218 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,226 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,233 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,242 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,253 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,288 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,308 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,332 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,362 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,403 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,448 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,547 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,697 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,793 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,885 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:28,898 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:28,902 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:28,928 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,928 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:28,951 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,952 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:28,952 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 23:26:28,952 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:28,952 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 23:26:28,953 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 23:26:28,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 23:26:28,953 INFO L87 Difference]: Start difference. First operand 171 states and 191 transitions. Second operand 24 states. [2018-01-24 23:26:29,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:29,832 INFO L93 Difference]: Finished difference Result 865 states and 984 transitions. [2018-01-24 23:26:29,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 23:26:29,832 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 23:26:29,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:29,835 INFO L225 Difference]: With dead ends: 865 [2018-01-24 23:26:29,835 INFO L226 Difference]: Without dead ends: 862 [2018-01-24 23:26:29,836 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 23:26:29,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2018-01-24 23:26:29,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 176. [2018-01-24 23:26:29,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-24 23:26:29,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 197 transitions. [2018-01-24 23:26:29,880 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 197 transitions. Word has length 112 [2018-01-24 23:26:29,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:29,880 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 197 transitions. [2018-01-24 23:26:29,880 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 23:26:29,881 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 197 transitions. [2018-01-24 23:26:29,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 23:26:29,882 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:29,882 INFO L322 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:29,882 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:29,882 INFO L82 PathProgramCache]: Analyzing trace with hash -600860340, now seen corresponding path program 8 times [2018-01-24 23:26:29,882 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:29,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:29,883 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:29,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:29,883 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:29,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:29,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:30,135 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 102 proven. 209 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 23:26:30,135 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:30,135 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:30,135 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:30,135 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:30,135 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:30,135 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:30,144 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:30,144 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:30,149 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:30,161 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:30,163 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:30,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:30,291 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 23:26:30,291 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:30,433 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 248 trivial. 0 not checked. [2018-01-24 23:26:30,453 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:30,453 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:30,455 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:30,456 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:30,461 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:30,479 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:30,493 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:30,497 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:30,530 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 140 proven. 171 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 23:26:30,530 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:31,184 INFO L134 CoverageAnalysis]: Checked inductivity of 395 backedges. 126 proven. 185 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-01-24 23:26:31,185 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:31,186 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 9, 9, 19, 19] total 52 [2018-01-24 23:26:31,186 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:31,186 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 23:26:31,186 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 23:26:31,187 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=550, Invalid=2206, Unknown=0, NotChecked=0, Total=2756 [2018-01-24 23:26:31,187 INFO L87 Difference]: Start difference. First operand 176 states and 197 transitions. Second operand 27 states. [2018-01-24 23:26:31,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:31,508 INFO L93 Difference]: Finished difference Result 237 states and 270 transitions. [2018-01-24 23:26:31,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 23:26:31,509 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-24 23:26:31,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:31,510 INFO L225 Difference]: With dead ends: 237 [2018-01-24 23:26:31,510 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 23:26:31,511 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 453 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 951 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=788, Invalid=2752, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 23:26:31,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 23:26:31,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 182. [2018-01-24 23:26:31,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 23:26:31,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 203 transitions. [2018-01-24 23:26:31,536 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 203 transitions. Word has length 122 [2018-01-24 23:26:31,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:31,536 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 203 transitions. [2018-01-24 23:26:31,536 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 23:26:31,536 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 203 transitions. [2018-01-24 23:26:31,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 23:26:31,537 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:31,537 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:31,537 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:31,537 INFO L82 PathProgramCache]: Analyzing trace with hash 1092014588, now seen corresponding path program 22 times [2018-01-24 23:26:31,537 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:31,538 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:31,538 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:31,538 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:31,538 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:31,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:31,546 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:32,349 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:32,349 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:32,349 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:32,349 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:32,349 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:32,349 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:32,349 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:32,355 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:32,355 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:32,387 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:32,390 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:32,411 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:32,411 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:32,979 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:32,999 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:32,999 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:33,002 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:33,002 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:33,121 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:33,125 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:33,146 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:33,146 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:33,181 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:33,183 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:33,183 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 23:26:33,183 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:33,183 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 23:26:33,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 23:26:33,184 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 23:26:33,184 INFO L87 Difference]: Start difference. First operand 182 states and 203 transitions. Second operand 25 states. [2018-01-24 23:26:34,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:34,136 INFO L93 Difference]: Finished difference Result 960 states and 1094 transitions. [2018-01-24 23:26:34,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 23:26:34,136 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 23:26:34,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:34,139 INFO L225 Difference]: With dead ends: 960 [2018-01-24 23:26:34,139 INFO L226 Difference]: Without dead ends: 957 [2018-01-24 23:26:34,140 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 23:26:34,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 957 states. [2018-01-24 23:26:34,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 957 to 187. [2018-01-24 23:26:34,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-01-24 23:26:34,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 209 transitions. [2018-01-24 23:26:34,183 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 209 transitions. Word has length 117 [2018-01-24 23:26:34,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:34,183 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 209 transitions. [2018-01-24 23:26:34,183 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 23:26:34,183 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 209 transitions. [2018-01-24 23:26:34,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 23:26:34,184 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:34,184 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:34,184 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:34,184 INFO L82 PathProgramCache]: Analyzing trace with hash 1378342647, now seen corresponding path program 23 times [2018-01-24 23:26:34,184 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:34,185 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:34,185 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:34,185 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:34,185 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:34,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:34,191 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:34,523 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:34,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:34,524 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:34,524 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:34,524 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:34,524 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:34,524 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:34,529 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:34,530 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:34,533 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,534 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,535 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,536 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,538 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,539 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,541 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,542 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,545 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,547 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,550 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,553 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,576 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,582 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,589 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,597 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,606 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,620 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,628 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:34,629 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:34,631 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:34,653 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:34,653 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:35,248 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:35,268 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:35,268 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:35,270 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:35,270 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:35,274 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,280 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,284 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,290 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,306 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,315 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,366 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,386 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,409 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,436 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,477 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,863 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:35,940 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:36,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:36,121 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:36,147 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:36,151 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:36,173 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:36,174 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:36,209 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:36,211 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:36,211 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 23:26:36,211 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:36,211 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 23:26:36,211 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 23:26:36,212 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 23:26:36,212 INFO L87 Difference]: Start difference. First operand 187 states and 209 transitions. Second operand 26 states. [2018-01-24 23:26:37,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:37,311 INFO L93 Difference]: Finished difference Result 1020 states and 1163 transitions. [2018-01-24 23:26:37,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 23:26:37,312 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 23:26:37,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:37,315 INFO L225 Difference]: With dead ends: 1020 [2018-01-24 23:26:37,316 INFO L226 Difference]: Without dead ends: 1017 [2018-01-24 23:26:37,316 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 23:26:37,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017 states. [2018-01-24 23:26:37,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017 to 192. [2018-01-24 23:26:37,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-01-24 23:26:37,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 215 transitions. [2018-01-24 23:26:37,367 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 215 transitions. Word has length 122 [2018-01-24 23:26:37,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:37,367 INFO L432 AbstractCegarLoop]: Abstraction has 192 states and 215 transitions. [2018-01-24 23:26:37,367 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 23:26:37,368 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 215 transitions. [2018-01-24 23:26:37,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 23:26:37,368 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:37,368 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:37,368 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:37,368 INFO L82 PathProgramCache]: Analyzing trace with hash -1016482084, now seen corresponding path program 24 times [2018-01-24 23:26:37,369 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:37,369 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:37,369 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:37,369 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:37,369 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:37,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:37,376 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:37,770 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:37,770 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:37,770 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:37,770 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:37,770 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:37,770 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:37,770 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:37,775 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:37,775 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:37,778 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,782 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,786 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,787 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,790 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,793 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,795 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,797 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,799 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,801 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,804 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,806 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,817 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:37,822 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:37,823 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:37,849 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:37,849 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:38,498 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:38,518 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:38,518 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:38,521 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:38,521 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:38,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,533 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,545 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,551 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,557 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,566 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,577 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,610 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,684 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,712 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,827 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:38,942 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:39,035 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:39,228 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:39,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:39,691 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:39,914 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:39,929 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:39,933 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:39,960 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:39,960 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:39,991 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:39,993 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:39,993 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 23:26:39,993 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:39,993 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 23:26:39,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 23:26:39,994 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 23:26:39,994 INFO L87 Difference]: Start difference. First operand 192 states and 215 transitions. Second operand 27 states. [2018-01-24 23:26:41,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:41,836 INFO L93 Difference]: Finished difference Result 1080 states and 1232 transitions. [2018-01-24 23:26:41,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 23:26:41,837 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 23:26:41,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:41,840 INFO L225 Difference]: With dead ends: 1080 [2018-01-24 23:26:41,840 INFO L226 Difference]: Without dead ends: 1077 [2018-01-24 23:26:41,841 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 23:26:41,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1077 states. [2018-01-24 23:26:41,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1077 to 197. [2018-01-24 23:26:41,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-01-24 23:26:41,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 221 transitions. [2018-01-24 23:26:41,885 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 221 transitions. Word has length 127 [2018-01-24 23:26:41,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:41,885 INFO L432 AbstractCegarLoop]: Abstraction has 197 states and 221 transitions. [2018-01-24 23:26:41,885 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 23:26:41,885 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 221 transitions. [2018-01-24 23:26:41,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 23:26:41,886 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:41,886 INFO L322 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:41,886 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:41,887 INFO L82 PathProgramCache]: Analyzing trace with hash 795448555, now seen corresponding path program 9 times [2018-01-24 23:26:41,887 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:41,887 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:41,888 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:41,888 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:41,888 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:41,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:41,895 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:42,134 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 140 proven. 259 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-01-24 23:26:42,134 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:42,134 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:42,134 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:42,134 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:42,135 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:42,135 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:42,139 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:42,139 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:42,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,158 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,161 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,164 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,165 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:42,167 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:42,269 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 23:26:42,269 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:42,437 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 23:26:42,457 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:42,457 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:42,460 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:42,460 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:42,465 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,468 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,475 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,484 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,515 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,536 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,575 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,620 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:42,633 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:42,638 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:42,664 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 23:26:42,664 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:42,698 INFO L134 CoverageAnalysis]: Checked inductivity of 511 backedges. 0 proven. 192 refuted. 0 times theorem prover too weak. 319 trivial. 0 not checked. [2018-01-24 23:26:42,699 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:42,700 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 10, 10, 10, 10] total 38 [2018-01-24 23:26:42,700 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:42,700 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 23:26:42,701 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 23:26:42,701 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=248, Invalid=1234, Unknown=0, NotChecked=0, Total=1482 [2018-01-24 23:26:42,701 INFO L87 Difference]: Start difference. First operand 197 states and 221 transitions. Second operand 30 states. [2018-01-24 23:26:43,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:43,112 INFO L93 Difference]: Finished difference Result 264 states and 301 transitions. [2018-01-24 23:26:43,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 23:26:43,112 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 137 [2018-01-24 23:26:43,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:43,113 INFO L225 Difference]: With dead ends: 264 [2018-01-24 23:26:43,113 INFO L226 Difference]: Without dead ends: 205 [2018-01-24 23:26:43,113 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 528 SyntacticMatches, 2 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 517 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=388, Invalid=1774, Unknown=0, NotChecked=0, Total=2162 [2018-01-24 23:26:43,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-01-24 23:26:43,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 203. [2018-01-24 23:26:43,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-01-24 23:26:43,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 227 transitions. [2018-01-24 23:26:43,147 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 227 transitions. Word has length 137 [2018-01-24 23:26:43,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:43,147 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 227 transitions. [2018-01-24 23:26:43,147 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 23:26:43,147 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 227 transitions. [2018-01-24 23:26:43,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 23:26:43,148 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:43,148 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:43,148 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:43,148 INFO L82 PathProgramCache]: Analyzing trace with hash 37813783, now seen corresponding path program 25 times [2018-01-24 23:26:43,148 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:43,149 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:43,149 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:43,149 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:43,149 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:43,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:43,158 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:43,691 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:43,691 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:43,691 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:43,691 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:43,691 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:43,691 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:43,691 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:43,696 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:43,696 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:43,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:43,711 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:43,757 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:43,757 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:44,426 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:44,445 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:44,446 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:44,448 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:44,449 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:44,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:44,484 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:44,524 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:44,524 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:44,572 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (70)] Exception during sending of exit command (exit): Stream closed [2018-01-24 23:26:44,573 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:44,573 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 23:26:44,573 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:44,574 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 23:26:44,574 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 23:26:44,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 23:26:44,575 INFO L87 Difference]: Start difference. First operand 203 states and 227 transitions. Second operand 28 states. [2018-01-24 23:26:46,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:46,204 INFO L93 Difference]: Finished difference Result 1187 states and 1356 transitions. [2018-01-24 23:26:46,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 23:26:46,205 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 23:26:46,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:46,209 INFO L225 Difference]: With dead ends: 1187 [2018-01-24 23:26:46,209 INFO L226 Difference]: Without dead ends: 1184 [2018-01-24 23:26:46,210 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 23:26:46,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states. [2018-01-24 23:26:46,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 208. [2018-01-24 23:26:46,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208 states. [2018-01-24 23:26:46,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 233 transitions. [2018-01-24 23:26:46,285 INFO L78 Accepts]: Start accepts. Automaton has 208 states and 233 transitions. Word has length 132 [2018-01-24 23:26:46,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:46,285 INFO L432 AbstractCegarLoop]: Abstraction has 208 states and 233 transitions. [2018-01-24 23:26:46,285 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 23:26:46,285 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 233 transitions. [2018-01-24 23:26:46,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 23:26:46,287 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:46,287 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:46,287 INFO L371 AbstractCegarLoop]: === Iteration 38 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:46,287 INFO L82 PathProgramCache]: Analyzing trace with hash -24378436, now seen corresponding path program 26 times [2018-01-24 23:26:46,287 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:46,288 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:46,288 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:46,288 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:46,288 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:46,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:46,296 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:46,765 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:46,765 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:46,801 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:46,801 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:46,801 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:46,801 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:46,801 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:46,806 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:46,806 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:46,810 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:46,820 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:46,821 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:46,824 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:46,879 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:46,879 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:47,646 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:47,666 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:47,666 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 72 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:47,669 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:47,669 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:47,674 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:47,690 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:47,703 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:47,707 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:47,738 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:47,738 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:47,771 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:47,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:47,773 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 23:26:47,773 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:47,773 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 23:26:47,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 23:26:47,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 23:26:47,774 INFO L87 Difference]: Start difference. First operand 208 states and 233 transitions. Second operand 29 states. Received shutdown request... [2018-01-24 23:26:47,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 23:26:47,943 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 23:26:47,947 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 23:26:47,947 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 11:26:47 BoogieIcfgContainer [2018-01-24 23:26:47,947 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 23:26:47,948 INFO L168 Benchmark]: Toolchain (without parser) took 46774.99 ms. Allocated memory was 299.9 MB in the beginning and 743.4 MB in the end (delta: 443.5 MB). Free memory was 260.9 MB in the beginning and 588.4 MB in the end (delta: -327.4 MB). Peak memory consumption was 116.1 MB. Max. memory is 5.3 GB. [2018-01-24 23:26:47,949 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 299.9 MB. Free memory is still 265.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 23:26:47,949 INFO L168 Benchmark]: CACSL2BoogieTranslator took 166.30 ms. Allocated memory is still 299.9 MB. Free memory was 259.9 MB in the beginning and 252.0 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. [2018-01-24 23:26:47,949 INFO L168 Benchmark]: Boogie Preprocessor took 26.02 ms. Allocated memory is still 299.9 MB. Free memory was 252.0 MB in the beginning and 251.0 MB in the end (delta: 996.1 kB). Peak memory consumption was 996.1 kB. Max. memory is 5.3 GB. [2018-01-24 23:26:47,949 INFO L168 Benchmark]: RCFGBuilder took 167.63 ms. Allocated memory is still 299.9 MB. Free memory was 251.0 MB in the beginning and 239.2 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 5.3 GB. [2018-01-24 23:26:47,949 INFO L168 Benchmark]: TraceAbstraction took 46407.73 ms. Allocated memory was 299.9 MB in the beginning and 743.4 MB in the end (delta: 443.5 MB). Free memory was 239.2 MB in the beginning and 588.4 MB in the end (delta: -349.2 MB). Peak memory consumption was 94.4 MB. Max. memory is 5.3 GB. [2018-01-24 23:26:47,951 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 299.9 MB. Free memory is still 265.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 166.30 ms. Allocated memory is still 299.9 MB. Free memory was 259.9 MB in the beginning and 252.0 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 26.02 ms. Allocated memory is still 299.9 MB. Free memory was 252.0 MB in the beginning and 251.0 MB in the end (delta: 996.1 kB). Peak memory consumption was 996.1 kB. Max. memory is 5.3 GB. * RCFGBuilder took 167.63 ms. Allocated memory is still 299.9 MB. Free memory was 251.0 MB in the beginning and 239.2 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 46407.73 ms. Allocated memory was 299.9 MB in the beginning and 743.4 MB in the end (delta: 443.5 MB). Free memory was 239.2 MB in the beginning and 588.4 MB in the end (delta: -349.2 MB). Peak memory consumption was 94.4 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 3.323413 RENAME_VARIABLES(MILLISECONDS) : 0.369559 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 3.244115 PROJECTAWAY(MILLISECONDS) : 6.283317 ADD_WEAK_EQUALITY(MILLISECONDS) : 2.170966 DISJOIN(MILLISECONDS) : 0.220531 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.395076 ADD_EQUALITY(MILLISECONDS) : 3.862090 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.728765 #CONJOIN_DISJUNCTIVE : 36 #RENAME_VARIABLES : 82 #UNFREEZE : 0 #CONJOIN : 48 #PROJECTAWAY : 57 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 77 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 14 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 9 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -28 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 19 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 7 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 20 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.591148 RENAME_VARIABLES(MILLISECONDS) : 0.405574 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.227734 PROJECTAWAY(MILLISECONDS) : 0.044848 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.508934 DISJOIN(MILLISECONDS) : 0.177648 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.434361 ADD_EQUALITY(MILLISECONDS) : 0.033774 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.334776 #CONJOIN_DISJUNCTIVE : 56 #RENAME_VARIABLES : 122 #UNFREEZE : 0 #CONJOIN : 68 #PROJECTAWAY : 81 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 14 #RENAME_VARIABLES_DISJUNCTIVE : 117 #ADD_EQUALITY : 7 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 21 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 11 LocStat_NO_SUPPORTING_DISEQUALITIES : 7 LocStat_NO_DISJUNCTIONS : -42 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 29 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 10 TransStat_NO_SUPPORTING_DISEQUALITIES : 2 TransStat_NO_DISJUNCTIONS : 30 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.110962 RENAME_VARIABLES(MILLISECONDS) : 0.094011 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.082049 PROJECTAWAY(MILLISECONDS) : 0.104498 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.237400 DISJOIN(MILLISECONDS) : 0.154191 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.110151 ADD_EQUALITY(MILLISECONDS) : 0.034098 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.009497 #CONJOIN_DISJUNCTIVE : 121 #RENAME_VARIABLES : 295 #UNFREEZE : 0 #CONJOIN : 184 #PROJECTAWAY : 191 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 26 #RENAME_VARIABLES_DISJUNCTIVE : 287 #ADD_EQUALITY : 10 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 2 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while BasicCegarLoop was constructing difference of abstraction (208states) and interpolant automaton (currently 11 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (45 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was constructing difference of abstraction (208states) and interpolant automaton (currently 11 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (45 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was constructing difference of abstraction (208states) and interpolant automaton (currently 11 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (45 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was constructing difference of abstraction (208states) and interpolant automaton (currently 11 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (45 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was constructing difference of abstraction (208states) and interpolant automaton (currently 11 states, 29 states before enhancement), while ReachableStatesComputation was computing reachable states (45 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 32 locations, 5 error locations. TIMEOUT Result, 46.3s OverallTime, 38 OverallIterations, 27 TraceHistogramMax, 14.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3819 SDtfs, 2413 SDslu, 54444 SDs, 0 SdLazy, 28369 SolverSat, 228 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 11050 GetRequests, 9973 SyntacticMatches, 68 SemanticMatches, 1009 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2796 ImplicationChecksByTransitivity, 17.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=208occurred in iteration=37, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.9s AbstIntTime, 3 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.8s AutomataMinimizationTime, 37 MinimizatonAttempts, 9008 StatesRemovedByMinimization, 34 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 6.2s SatisfiabilityAnalysisTime, 21.4s InterpolantComputationTime, 7943 NumberOfCodeBlocks, 7913 NumberOfCodeBlocksAsserted, 501 NumberOfCheckSat, 13040 ConstructedInterpolants, 0 QuantifiedInterpolants, 7741836 SizeOfPredicates, 7 NumberOfNonLiveVariables, 7716 ConjunctsInSsa, 1767 ConjunctsInUnsatCore, 180 InterpolantComputations, 4 PerfectInterpolantSequences, 4895/85009 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-1-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-1-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-2-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-2-2018-01-24_23-26-47-961.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_false-valid-deref_ground.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_23-26-47-961.csv Completed graceful shutdown