java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf -i ../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-24 23:26:08,667 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-24 23:26:08,669 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-24 23:26:08,681 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-24 23:26:08,682 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-24 23:26:08,683 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-24 23:26:08,684 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-24 23:26:08,685 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-24 23:26:08,688 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-24 23:26:08,688 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-24 23:26:08,689 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-24 23:26:08,689 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-24 23:26:08,690 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-24 23:26:08,691 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-24 23:26:08,692 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-24 23:26:08,694 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-24 23:26:08,696 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-24 23:26:08,698 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-24 23:26:08,700 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-24 23:26:08,701 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-24 23:26:08,703 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-24 23:26:08,703 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-24 23:26:08,704 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-24 23:26:08,704 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-24 23:26:08,705 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-24 23:26:08,706 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-24 23:26:08,707 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-24 23:26:08,707 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-24 23:26:08,707 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-24 23:26:08,707 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-24 23:26:08,708 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-24 23:26:08,708 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf [2018-01-24 23:26:08,718 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-24 23:26:08,718 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-24 23:26:08,719 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-24 23:26:08,719 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-24 23:26:08,719 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-24 23:26:08,720 INFO L133 SettingsManager]: * Weq Fattening=true [2018-01-24 23:26:08,720 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-24 23:26:08,720 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-24 23:26:08,721 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-24 23:26:08,721 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-24 23:26:08,721 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-24 23:26:08,721 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-24 23:26:08,722 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-24 23:26:08,722 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-24 23:26:08,722 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-24 23:26:08,722 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-24 23:26:08,722 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-24 23:26:08,723 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-24 23:26:08,723 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-24 23:26:08,723 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-24 23:26:08,723 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-24 23:26:08,723 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-24 23:26:08,724 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-24 23:26:08,724 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-24 23:26:08,724 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 23:26:08,724 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-24 23:26:08,724 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-24 23:26:08,725 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-24 23:26:08,725 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-24 23:26:08,725 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-24 23:26:08,725 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-24 23:26:08,725 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-24 23:26:08,725 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-24 23:26:08,726 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-24 23:26:08,726 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-24 23:26:08,727 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-24 23:26:08,762 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-24 23:26:08,774 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-24 23:26:08,778 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-24 23:26:08,780 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-24 23:26:08,781 INFO L276 PluginConnector]: CDTParser initialized [2018-01-24 23:26:08,781 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/standard_strcpy_original_false-valid-deref.i [2018-01-24 23:26:08,914 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-24 23:26:08,921 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-24 23:26:08,922 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-24 23:26:08,922 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-24 23:26:08,930 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-24 23:26:08,932 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 11:26:08" (1/1) ... [2018-01-24 23:26:08,934 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2ae50da6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:08, skipping insertion in model container [2018-01-24 23:26:08,935 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.01 11:26:08" (1/1) ... [2018-01-24 23:26:08,952 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 23:26:08,970 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-24 23:26:09,085 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 23:26:09,096 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-24 23:26:09,100 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09 WrapperNode [2018-01-24 23:26:09,100 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-24 23:26:09,101 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-24 23:26:09,101 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-24 23:26:09,101 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-24 23:26:09,114 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,114 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,121 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,121 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,122 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,127 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,128 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... [2018-01-24 23:26:09,130 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-24 23:26:09,131 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-24 23:26:09,131 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-24 23:26:09,131 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-24 23:26:09,132 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-24 23:26:09,182 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-24 23:26:09,182 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-24 23:26:09,182 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-24 23:26:09,182 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-24 23:26:09,182 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-24 23:26:09,183 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-24 23:26:09,183 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-24 23:26:09,183 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-24 23:26:09,183 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-24 23:26:09,321 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-24 23:26:09,322 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 11:26:09 BoogieIcfgContainer [2018-01-24 23:26:09,322 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-24 23:26:09,322 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-24 23:26:09,322 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-24 23:26:09,324 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-24 23:26:09,325 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.01 11:26:08" (1/3) ... [2018-01-24 23:26:09,325 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4409d8dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 11:26:09, skipping insertion in model container [2018-01-24 23:26:09,326 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.01 11:26:09" (2/3) ... [2018-01-24 23:26:09,326 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4409d8dc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.01 11:26:09, skipping insertion in model container [2018-01-24 23:26:09,326 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.01 11:26:09" (3/3) ... [2018-01-24 23:26:09,327 INFO L105 eAbstractionObserver]: Analyzing ICFG standard_strcpy_original_false-valid-deref.i [2018-01-24 23:26:09,335 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-24 23:26:09,341 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-01-24 23:26:09,382 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-24 23:26:09,382 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-24 23:26:09,382 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-24 23:26:09,383 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-24 23:26:09,383 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-24 23:26:09,383 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-24 23:26:09,383 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-24 23:26:09,383 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-24 23:26:09,384 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-24 23:26:09,402 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states. [2018-01-24 23:26:09,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2018-01-24 23:26:09,407 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:09,408 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:09,408 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:09,412 INFO L82 PathProgramCache]: Analyzing trace with hash 1734695582, now seen corresponding path program 1 times [2018-01-24 23:26:09,414 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:09,455 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,456 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:09,456 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,456 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:09,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:09,500 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:09,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:09,563 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-24 23:26:09,563 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-24 23:26:09,563 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-24 23:26:09,565 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-24 23:26:09,576 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-24 23:26:09,576 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 23:26:09,578 INFO L87 Difference]: Start difference. First operand 34 states. Second operand 3 states. [2018-01-24 23:26:09,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:09,681 INFO L93 Difference]: Finished difference Result 74 states and 90 transitions. [2018-01-24 23:26:09,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-24 23:26:09,682 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 7 [2018-01-24 23:26:09,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:09,690 INFO L225 Difference]: With dead ends: 74 [2018-01-24 23:26:09,690 INFO L226 Difference]: Without dead ends: 41 [2018-01-24 23:26:09,694 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-24 23:26:09,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-01-24 23:26:09,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 38. [2018-01-24 23:26:09,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-24 23:26:09,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 40 transitions. [2018-01-24 23:26:09,796 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 40 transitions. Word has length 7 [2018-01-24 23:26:09,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:09,797 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 40 transitions. [2018-01-24 23:26:09,797 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-24 23:26:09,797 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 40 transitions. [2018-01-24 23:26:09,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-01-24 23:26:09,798 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:09,798 INFO L322 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:09,798 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:09,798 INFO L82 PathProgramCache]: Analyzing trace with hash 337601429, now seen corresponding path program 1 times [2018-01-24 23:26:09,799 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:09,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,800 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:09,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:09,800 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:09,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:09,811 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:09,851 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:09,851 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:09,851 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:09,853 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 13 with the following transitions: [2018-01-24 23:26:09,855 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [10], [11], [16], [18], [20], [58], [59], [60] [2018-01-24 23:26:09,903 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-24 23:26:09,904 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-24 23:26:10,190 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-24 23:26:10,191 INFO L268 AbstractInterpreter]: Visited 11 different actions 23 times. Merged at 6 different actions 12 times. Never widened. Found 1 fixpoints after 1 different actions. Largest state had 3 variables. [2018-01-24 23:26:10,205 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-24 23:26:10,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,241 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:10,249 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:10,250 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:10,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:10,269 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:10,284 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,284 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:10,334 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,357 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,357 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:10,361 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:10,361 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:10,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:10,371 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:10,383 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,384 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:10,405 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,406 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:10,406 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3, 3, 3] total 5 [2018-01-24 23:26:10,407 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:10,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-24 23:26:10,408 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-24 23:26:10,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 23:26:10,408 INFO L87 Difference]: Start difference. First operand 38 states and 40 transitions. Second operand 4 states. [2018-01-24 23:26:10,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:10,523 INFO L93 Difference]: Finished difference Result 60 states and 65 transitions. [2018-01-24 23:26:10,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-24 23:26:10,523 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 12 [2018-01-24 23:26:10,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:10,525 INFO L225 Difference]: With dead ends: 60 [2018-01-24 23:26:10,525 INFO L226 Difference]: Without dead ends: 54 [2018-01-24 23:26:10,526 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 43 SyntacticMatches, 2 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-01-24 23:26:10,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-24 23:26:10,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 50. [2018-01-24 23:26:10,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-24 23:26:10,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-01-24 23:26:10,535 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 12 [2018-01-24 23:26:10,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:10,535 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-01-24 23:26:10,535 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-24 23:26:10,535 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-01-24 23:26:10,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-24 23:26:10,536 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:10,536 INFO L322 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:10,537 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:10,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1746445058, now seen corresponding path program 2 times [2018-01-24 23:26:10,537 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:10,538 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:10,538 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:10,538 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:10,538 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:10,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:10,546 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:10,633 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,634 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,634 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:10,634 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:10,634 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:10,634 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,634 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:10,645 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:10,646 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:10,652 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,655 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,656 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:10,658 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:10,667 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,667 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:10,725 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,760 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:10,760 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:10,765 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:10,765 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:10,771 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,775 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:10,780 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:10,783 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:10,797 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,797 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:10,806 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:10,807 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:10,808 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-01-24 23:26:10,808 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:10,808 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-24 23:26:10,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-24 23:26:10,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 23:26:10,809 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 5 states. [2018-01-24 23:26:10,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:10,920 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2018-01-24 23:26:10,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-24 23:26:10,920 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-01-24 23:26:10,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:10,922 INFO L225 Difference]: With dead ends: 73 [2018-01-24 23:26:10,922 INFO L226 Difference]: Without dead ends: 67 [2018-01-24 23:26:10,923 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-01-24 23:26:10,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-24 23:26:10,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 62. [2018-01-24 23:26:10,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-01-24 23:26:10,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 68 transitions. [2018-01-24 23:26:10,931 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 68 transitions. Word has length 17 [2018-01-24 23:26:10,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:10,931 INFO L432 AbstractCegarLoop]: Abstraction has 62 states and 68 transitions. [2018-01-24 23:26:10,931 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-24 23:26:10,931 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 68 transitions. [2018-01-24 23:26:10,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-01-24 23:26:10,932 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:10,932 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:10,932 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:10,932 INFO L82 PathProgramCache]: Analyzing trace with hash -228598475, now seen corresponding path program 3 times [2018-01-24 23:26:10,932 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:10,933 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:10,933 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:10,933 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:10,933 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:10,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:10,939 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:11,028 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,028 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,028 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:11,029 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:11,029 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:11,029 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,029 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:11,037 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:11,038 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:11,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,046 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:11,047 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,059 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,060 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:11,159 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,192 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,192 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:11,197 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:11,198 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:11,201 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,208 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,214 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:11,218 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:11,221 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,228 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,228 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:11,236 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,237 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:11,237 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 9 [2018-01-24 23:26:11,237 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:11,238 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-24 23:26:11,238 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-24 23:26:11,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 23:26:11,238 INFO L87 Difference]: Start difference. First operand 62 states and 68 transitions. Second operand 6 states. [2018-01-24 23:26:11,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:11,377 INFO L93 Difference]: Finished difference Result 86 states and 95 transitions. [2018-01-24 23:26:11,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-24 23:26:11,377 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-01-24 23:26:11,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:11,378 INFO L225 Difference]: With dead ends: 86 [2018-01-24 23:26:11,378 INFO L226 Difference]: Without dead ends: 80 [2018-01-24 23:26:11,379 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 81 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-01-24 23:26:11,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-24 23:26:11,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 74. [2018-01-24 23:26:11,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-01-24 23:26:11,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 82 transitions. [2018-01-24 23:26:11,385 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 82 transitions. Word has length 22 [2018-01-24 23:26:11,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:11,386 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 82 transitions. [2018-01-24 23:26:11,386 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-24 23:26:11,386 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 82 transitions. [2018-01-24 23:26:11,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-01-24 23:26:11,387 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:11,387 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:11,387 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:11,387 INFO L82 PathProgramCache]: Analyzing trace with hash 756148062, now seen corresponding path program 4 times [2018-01-24 23:26:11,387 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:11,388 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:11,388 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:11,388 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:11,388 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:11,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:11,397 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:11,479 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,479 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,480 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:11,480 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:11,480 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:11,480 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,480 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:11,490 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:11,491 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:11,502 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:11,504 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,515 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,515 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:11,579 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,600 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,601 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:11,605 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:11,605 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:11,619 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:11,622 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,630 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,630 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:11,636 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,637 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:11,638 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 11 [2018-01-24 23:26:11,638 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:11,638 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-24 23:26:11,638 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-24 23:26:11,638 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 23:26:11,638 INFO L87 Difference]: Start difference. First operand 74 states and 82 transitions. Second operand 7 states. [2018-01-24 23:26:11,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:11,775 INFO L93 Difference]: Finished difference Result 99 states and 110 transitions. [2018-01-24 23:26:11,776 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-24 23:26:11,776 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-01-24 23:26:11,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:11,778 INFO L225 Difference]: With dead ends: 99 [2018-01-24 23:26:11,778 INFO L226 Difference]: Without dead ends: 93 [2018-01-24 23:26:11,778 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 100 SyntacticMatches, 2 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-01-24 23:26:11,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-01-24 23:26:11,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 86. [2018-01-24 23:26:11,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-01-24 23:26:11,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 96 transitions. [2018-01-24 23:26:11,788 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 96 transitions. Word has length 27 [2018-01-24 23:26:11,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:11,789 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 96 transitions. [2018-01-24 23:26:11,789 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-24 23:26:11,789 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 96 transitions. [2018-01-24 23:26:11,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-24 23:26:11,790 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:11,790 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:11,790 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:11,790 INFO L82 PathProgramCache]: Analyzing trace with hash 671928021, now seen corresponding path program 5 times [2018-01-24 23:26:11,791 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:11,791 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:11,792 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:11,792 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:11,792 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:11,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:11,799 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:11,908 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,908 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,908 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:11,909 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:11,909 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:11,909 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:11,909 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:11,914 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:11,914 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:11,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:11,919 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:11,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:11,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:11,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:11,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:11,925 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:11,926 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:11,935 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:11,936 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,055 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,075 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,075 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:12,079 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:12,080 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:12,083 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,085 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,089 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,094 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,100 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,107 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:12,111 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:12,114 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:12,133 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,133 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,145 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,147 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:12,147 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 13 [2018-01-24 23:26:12,147 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:12,147 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-24 23:26:12,148 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-24 23:26:12,148 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 23:26:12,148 INFO L87 Difference]: Start difference. First operand 86 states and 96 transitions. Second operand 8 states. [2018-01-24 23:26:12,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:12,307 INFO L93 Difference]: Finished difference Result 112 states and 125 transitions. [2018-01-24 23:26:12,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-24 23:26:12,308 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-01-24 23:26:12,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:12,309 INFO L225 Difference]: With dead ends: 112 [2018-01-24 23:26:12,309 INFO L226 Difference]: Without dead ends: 106 [2018-01-24 23:26:12,309 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-01-24 23:26:12,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-01-24 23:26:12,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 98. [2018-01-24 23:26:12,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-01-24 23:26:12,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 110 transitions. [2018-01-24 23:26:12,317 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 110 transitions. Word has length 32 [2018-01-24 23:26:12,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:12,317 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 110 transitions. [2018-01-24 23:26:12,317 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-24 23:26:12,318 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 110 transitions. [2018-01-24 23:26:12,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-01-24 23:26:12,318 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:12,319 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:12,319 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:12,319 INFO L82 PathProgramCache]: Analyzing trace with hash -203753026, now seen corresponding path program 6 times [2018-01-24 23:26:12,319 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:12,320 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:12,320 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:12,320 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:12,320 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:12,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:12,327 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:12,414 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,414 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,414 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:12,414 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:12,415 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:12,415 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,415 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:12,420 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:12,420 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:12,424 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,427 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,429 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,429 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:12,431 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:12,439 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,440 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,556 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,582 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:12,582 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:12,591 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:12,592 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:12,596 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,598 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,606 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,613 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,630 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:12,635 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:12,639 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:12,656 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,656 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:12,668 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:12,670 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:12,670 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 15 [2018-01-24 23:26:12,670 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:12,670 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-24 23:26:12,670 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-24 23:26:12,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:26:12,671 INFO L87 Difference]: Start difference. First operand 98 states and 110 transitions. Second operand 9 states. [2018-01-24 23:26:12,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:12,865 INFO L93 Difference]: Finished difference Result 125 states and 140 transitions. [2018-01-24 23:26:12,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-24 23:26:12,865 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 37 [2018-01-24 23:26:12,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:12,866 INFO L225 Difference]: With dead ends: 125 [2018-01-24 23:26:12,866 INFO L226 Difference]: Without dead ends: 119 [2018-01-24 23:26:12,866 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 138 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-01-24 23:26:12,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-01-24 23:26:12,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 110. [2018-01-24 23:26:12,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-01-24 23:26:12,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 124 transitions. [2018-01-24 23:26:12,874 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 124 transitions. Word has length 37 [2018-01-24 23:26:12,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:12,875 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 124 transitions. [2018-01-24 23:26:12,875 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-24 23:26:12,875 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 124 transitions. [2018-01-24 23:26:12,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-24 23:26:12,876 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:12,876 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:12,876 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:12,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1846527883, now seen corresponding path program 7 times [2018-01-24 23:26:12,876 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:12,877 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:12,877 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:12,877 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:12,877 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:12,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:12,886 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:13,030 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,031 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:13,031 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:13,031 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:13,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,031 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:13,043 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:13,043 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:13,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:13,054 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:13,071 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,071 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:13,236 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,258 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,258 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:13,262 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:13,262 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:13,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:13,280 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:13,288 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,288 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:13,301 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,303 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:13,303 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 17 [2018-01-24 23:26:13,304 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:13,306 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-24 23:26:13,306 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-24 23:26:13,307 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 23:26:13,307 INFO L87 Difference]: Start difference. First operand 110 states and 124 transitions. Second operand 10 states. [2018-01-24 23:26:13,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:13,535 INFO L93 Difference]: Finished difference Result 138 states and 155 transitions. [2018-01-24 23:26:13,535 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-24 23:26:13,535 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-01-24 23:26:13,535 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:13,536 INFO L225 Difference]: With dead ends: 138 [2018-01-24 23:26:13,536 INFO L226 Difference]: Without dead ends: 132 [2018-01-24 23:26:13,536 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 157 SyntacticMatches, 2 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-01-24 23:26:13,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-01-24 23:26:13,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 122. [2018-01-24 23:26:13,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-24 23:26:13,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 138 transitions. [2018-01-24 23:26:13,546 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 138 transitions. Word has length 42 [2018-01-24 23:26:13,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:13,547 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 138 transitions. [2018-01-24 23:26:13,547 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-24 23:26:13,547 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 138 transitions. [2018-01-24 23:26:13,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-01-24 23:26:13,548 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:13,548 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:13,548 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:13,548 INFO L82 PathProgramCache]: Analyzing trace with hash 2109248542, now seen corresponding path program 8 times [2018-01-24 23:26:13,548 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:13,549 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:13,549 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:13,549 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:13,549 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:13,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:13,557 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:13,679 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,679 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,679 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:13,680 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:13,680 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:13,680 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,680 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:13,686 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:13,686 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:13,689 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,694 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,695 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:13,697 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:13,710 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,710 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:13,841 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,861 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:13,861 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:13,864 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:13,865 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:13,868 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,876 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:13,884 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:13,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:13,902 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,902 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:13,912 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:13,917 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:13,917 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 19 [2018-01-24 23:26:13,918 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:13,918 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-24 23:26:13,918 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-24 23:26:13,918 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 23:26:13,918 INFO L87 Difference]: Start difference. First operand 122 states and 138 transitions. Second operand 11 states. [2018-01-24 23:26:14,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:14,317 INFO L93 Difference]: Finished difference Result 151 states and 170 transitions. [2018-01-24 23:26:14,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-24 23:26:14,317 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 47 [2018-01-24 23:26:14,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:14,318 INFO L225 Difference]: With dead ends: 151 [2018-01-24 23:26:14,318 INFO L226 Difference]: Without dead ends: 145 [2018-01-24 23:26:14,319 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 176 SyntacticMatches, 2 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-01-24 23:26:14,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-01-24 23:26:14,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 134. [2018-01-24 23:26:14,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-01-24 23:26:14,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 152 transitions. [2018-01-24 23:26:14,329 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 152 transitions. Word has length 47 [2018-01-24 23:26:14,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:14,329 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 152 transitions. [2018-01-24 23:26:14,329 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-24 23:26:14,329 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 152 transitions. [2018-01-24 23:26:14,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-24 23:26:14,331 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:14,331 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:14,331 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:14,331 INFO L82 PathProgramCache]: Analyzing trace with hash 408164885, now seen corresponding path program 9 times [2018-01-24 23:26:14,331 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:14,332 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:14,332 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:14,333 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:14,333 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:14,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:14,342 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:14,483 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,483 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:14,483 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:14,483 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:14,484 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:14,484 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:14,484 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:14,490 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:14,490 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:14,493 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,494 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,496 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,497 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,505 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:14,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:14,522 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,522 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:14,759 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,779 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:14,779 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:14,782 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:14,782 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:14,787 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,789 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,794 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,798 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,803 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,810 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,817 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,837 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,852 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:14,857 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:14,860 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:14,871 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,871 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:14,882 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:14,883 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:14,883 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 21 [2018-01-24 23:26:14,883 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:14,884 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-24 23:26:14,884 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-24 23:26:14,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:26:14,884 INFO L87 Difference]: Start difference. First operand 134 states and 152 transitions. Second operand 12 states. [2018-01-24 23:26:15,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:15,255 INFO L93 Difference]: Finished difference Result 164 states and 185 transitions. [2018-01-24 23:26:15,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-24 23:26:15,255 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 52 [2018-01-24 23:26:15,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:15,257 INFO L225 Difference]: With dead ends: 164 [2018-01-24 23:26:15,257 INFO L226 Difference]: Without dead ends: 158 [2018-01-24 23:26:15,257 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 217 GetRequests, 195 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-01-24 23:26:15,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-01-24 23:26:15,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 146. [2018-01-24 23:26:15,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-01-24 23:26:15,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 166 transitions. [2018-01-24 23:26:15,268 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 166 transitions. Word has length 52 [2018-01-24 23:26:15,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:15,268 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 166 transitions. [2018-01-24 23:26:15,268 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-24 23:26:15,269 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 166 transitions. [2018-01-24 23:26:15,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-01-24 23:26:15,270 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:15,270 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:15,270 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:15,270 INFO L82 PathProgramCache]: Analyzing trace with hash -2136951170, now seen corresponding path program 10 times [2018-01-24 23:26:15,270 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:15,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:15,271 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:15,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:15,271 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:15,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:15,287 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:15,439 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:15,440 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:15,440 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:15,440 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:15,440 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:15,440 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:15,447 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:15,448 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:15,459 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:15,461 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:15,477 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,477 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:15,635 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,655 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:15,655 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:15,658 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:15,658 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:15,690 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:15,693 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:15,705 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,705 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:15,715 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:15,717 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:15,717 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 23 [2018-01-24 23:26:15,717 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:15,717 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-24 23:26:15,717 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-24 23:26:15,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 23:26:15,718 INFO L87 Difference]: Start difference. First operand 146 states and 166 transitions. Second operand 13 states. [2018-01-24 23:26:16,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:16,060 INFO L93 Difference]: Finished difference Result 177 states and 200 transitions. [2018-01-24 23:26:16,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-24 23:26:16,060 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 57 [2018-01-24 23:26:16,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:16,062 INFO L225 Difference]: With dead ends: 177 [2018-01-24 23:26:16,062 INFO L226 Difference]: Without dead ends: 171 [2018-01-24 23:26:16,062 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 214 SyntacticMatches, 2 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-01-24 23:26:16,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-01-24 23:26:16,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 158. [2018-01-24 23:26:16,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-01-24 23:26:16,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 180 transitions. [2018-01-24 23:26:16,070 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 180 transitions. Word has length 57 [2018-01-24 23:26:16,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:16,070 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 180 transitions. [2018-01-24 23:26:16,070 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-24 23:26:16,071 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 180 transitions. [2018-01-24 23:26:16,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-24 23:26:16,071 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:16,071 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:16,071 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:16,072 INFO L82 PathProgramCache]: Analyzing trace with hash 1325560757, now seen corresponding path program 11 times [2018-01-24 23:26:16,072 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:16,072 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:16,072 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:16,072 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:16,072 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:16,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:16,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:16,222 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,223 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:16,223 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:16,223 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:16,223 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:16,223 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:16,223 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:16,228 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:16,228 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:16,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,232 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,232 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,233 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,234 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,235 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,237 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,238 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,240 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,244 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,246 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,247 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:16,248 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:16,262 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,263 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:16,452 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,472 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:16,472 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:16,475 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:16,475 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:16,478 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,480 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,484 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,489 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,494 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,501 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,509 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,521 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,536 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,551 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,589 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:16,596 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:16,600 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:16,614 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,614 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:16,630 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:16,631 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:16,631 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 25 [2018-01-24 23:26:16,631 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:16,632 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-24 23:26:16,632 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-24 23:26:16,632 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 23:26:16,632 INFO L87 Difference]: Start difference. First operand 158 states and 180 transitions. Second operand 14 states. [2018-01-24 23:26:17,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:17,021 INFO L93 Difference]: Finished difference Result 190 states and 215 transitions. [2018-01-24 23:26:17,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-24 23:26:17,022 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 62 [2018-01-24 23:26:17,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:17,023 INFO L225 Difference]: With dead ends: 190 [2018-01-24 23:26:17,023 INFO L226 Difference]: Without dead ends: 184 [2018-01-24 23:26:17,024 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 259 GetRequests, 233 SyntacticMatches, 2 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-01-24 23:26:17,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-01-24 23:26:17,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 170. [2018-01-24 23:26:17,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-01-24 23:26:17,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 194 transitions. [2018-01-24 23:26:17,031 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 194 transitions. Word has length 62 [2018-01-24 23:26:17,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:17,031 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 194 transitions. [2018-01-24 23:26:17,031 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-24 23:26:17,031 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 194 transitions. [2018-01-24 23:26:17,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-01-24 23:26:17,032 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:17,032 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:17,032 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:17,032 INFO L82 PathProgramCache]: Analyzing trace with hash 923361502, now seen corresponding path program 12 times [2018-01-24 23:26:17,033 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:17,033 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:17,033 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:17,033 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:17,034 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:17,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:17,042 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:17,271 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:17,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:17,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:17,272 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:17,272 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:17,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:17,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:17,278 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:17,278 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:17,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,289 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,290 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,292 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,293 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,295 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,296 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,298 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,299 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,300 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:17,302 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:17,318 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:17,319 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:17,559 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:17,579 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:17,579 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:17,582 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:17,582 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:17,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,587 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,598 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,603 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,640 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,662 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,680 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,702 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,729 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:17,736 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:17,740 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:17,757 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:17,757 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:17,781 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 0 proven. 354 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:17,783 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:17,783 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 27 [2018-01-24 23:26:17,783 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:17,783 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-24 23:26:17,783 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-24 23:26:17,783 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 23:26:17,784 INFO L87 Difference]: Start difference. First operand 170 states and 194 transitions. Second operand 15 states. [2018-01-24 23:26:18,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:18,222 INFO L93 Difference]: Finished difference Result 203 states and 230 transitions. [2018-01-24 23:26:18,223 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-24 23:26:18,223 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 67 [2018-01-24 23:26:18,223 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:18,224 INFO L225 Difference]: With dead ends: 203 [2018-01-24 23:26:18,224 INFO L226 Difference]: Without dead ends: 197 [2018-01-24 23:26:18,225 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 280 GetRequests, 252 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-01-24 23:26:18,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-24 23:26:18,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 182. [2018-01-24 23:26:18,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-24 23:26:18,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 208 transitions. [2018-01-24 23:26:18,235 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 208 transitions. Word has length 67 [2018-01-24 23:26:18,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:18,235 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 208 transitions. [2018-01-24 23:26:18,235 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-24 23:26:18,235 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 208 transitions. [2018-01-24 23:26:18,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-01-24 23:26:18,236 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:18,236 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:18,236 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:18,236 INFO L82 PathProgramCache]: Analyzing trace with hash 356861269, now seen corresponding path program 13 times [2018-01-24 23:26:18,236 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:18,237 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:18,237 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:18,237 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:18,237 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:18,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:18,246 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:18,438 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:18,439 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:18,439 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:18,439 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:18,439 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:18,439 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:18,444 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:18,444 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:18,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:18,454 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:18,466 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,466 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:18,706 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,726 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:18,726 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:18,729 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:18,729 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:18,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:18,748 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:18,760 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,760 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:18,783 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 0 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:18,784 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:18,784 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 29 [2018-01-24 23:26:18,784 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:18,785 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-24 23:26:18,785 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-24 23:26:18,785 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 23:26:18,785 INFO L87 Difference]: Start difference. First operand 182 states and 208 transitions. Second operand 16 states. [2018-01-24 23:26:19,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:19,309 INFO L93 Difference]: Finished difference Result 216 states and 245 transitions. [2018-01-24 23:26:19,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-24 23:26:19,310 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 72 [2018-01-24 23:26:19,310 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:19,311 INFO L225 Difference]: With dead ends: 216 [2018-01-24 23:26:19,311 INFO L226 Difference]: Without dead ends: 210 [2018-01-24 23:26:19,311 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 271 SyntacticMatches, 2 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-01-24 23:26:19,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-24 23:26:19,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 194. [2018-01-24 23:26:19,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-01-24 23:26:19,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 222 transitions. [2018-01-24 23:26:19,321 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 222 transitions. Word has length 72 [2018-01-24 23:26:19,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:19,321 INFO L432 AbstractCegarLoop]: Abstraction has 194 states and 222 transitions. [2018-01-24 23:26:19,321 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-24 23:26:19,321 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 222 transitions. [2018-01-24 23:26:19,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-01-24 23:26:19,322 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:19,322 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:19,322 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:19,323 INFO L82 PathProgramCache]: Analyzing trace with hash -1075276994, now seen corresponding path program 14 times [2018-01-24 23:26:19,323 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:19,323 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:19,324 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:19,324 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:19,324 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:19,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:19,333 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:19,581 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:19,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:19,581 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:19,581 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:19,581 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:19,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:19,581 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:19,587 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:19,587 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:19,590 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,598 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:19,599 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:19,601 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:19,631 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:19,631 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:19,998 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,018 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:20,018 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:20,022 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:20,022 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:20,026 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:20,036 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:20,044 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:20,048 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:20,060 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,060 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:20,074 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 0 proven. 483 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,075 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:20,075 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 31 [2018-01-24 23:26:20,075 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:20,075 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-24 23:26:20,076 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-24 23:26:20,076 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:26:20,076 INFO L87 Difference]: Start difference. First operand 194 states and 222 transitions. Second operand 17 states. [2018-01-24 23:26:20,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:20,645 INFO L93 Difference]: Finished difference Result 229 states and 260 transitions. [2018-01-24 23:26:20,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-24 23:26:20,678 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 77 [2018-01-24 23:26:20,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:20,679 INFO L225 Difference]: With dead ends: 229 [2018-01-24 23:26:20,679 INFO L226 Difference]: Without dead ends: 223 [2018-01-24 23:26:20,680 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 290 SyntacticMatches, 2 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-01-24 23:26:20,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-01-24 23:26:20,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 206. [2018-01-24 23:26:20,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-01-24 23:26:20,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 236 transitions. [2018-01-24 23:26:20,688 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 236 transitions. Word has length 77 [2018-01-24 23:26:20,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:20,688 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 236 transitions. [2018-01-24 23:26:20,688 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-24 23:26:20,688 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 236 transitions. [2018-01-24 23:26:20,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-24 23:26:20,689 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:20,689 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:20,689 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:20,690 INFO L82 PathProgramCache]: Analyzing trace with hash 904302325, now seen corresponding path program 15 times [2018-01-24 23:26:20,690 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:20,690 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:20,690 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:20,691 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:20,691 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:20,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:20,699 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:20,918 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,918 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:20,918 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:20,918 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:20,918 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:20,918 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:20,918 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:20,923 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:20,924 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:20,928 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,929 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,930 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,931 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,932 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,934 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,935 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,937 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,939 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,940 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,943 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,945 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,947 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,955 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,966 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,970 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:20,970 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:20,972 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:20,985 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:20,985 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:21,280 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:21,300 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:21,300 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:21,302 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:21,303 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:21,307 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,309 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,312 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,316 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,321 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,328 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,335 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,344 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,354 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,369 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,387 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,407 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,429 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,456 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,495 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,540 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:21,549 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:21,552 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:21,565 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:21,565 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:21,580 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 0 proven. 555 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:21,582 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:21,582 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 33 [2018-01-24 23:26:21,582 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:21,582 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-24 23:26:21,583 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-24 23:26:21,583 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 23:26:21,583 INFO L87 Difference]: Start difference. First operand 206 states and 236 transitions. Second operand 18 states. [2018-01-24 23:26:22,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:22,218 INFO L93 Difference]: Finished difference Result 242 states and 275 transitions. [2018-01-24 23:26:22,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-24 23:26:22,219 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 82 [2018-01-24 23:26:22,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:22,220 INFO L225 Difference]: With dead ends: 242 [2018-01-24 23:26:22,220 INFO L226 Difference]: Without dead ends: 236 [2018-01-24 23:26:22,221 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 309 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-01-24 23:26:22,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-01-24 23:26:22,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 218. [2018-01-24 23:26:22,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-01-24 23:26:22,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-01-24 23:26:22,228 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 82 [2018-01-24 23:26:22,228 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:22,228 INFO L432 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-01-24 23:26:22,228 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-24 23:26:22,229 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-01-24 23:26:22,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-24 23:26:22,229 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:22,229 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:22,230 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:22,230 INFO L82 PathProgramCache]: Analyzing trace with hash 2125745566, now seen corresponding path program 16 times [2018-01-24 23:26:22,230 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:22,230 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:22,231 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:22,231 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:22,231 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:22,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:22,239 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:22,430 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:22,430 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:22,430 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:22,430 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:22,430 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:22,430 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:22,430 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:22,435 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:22,435 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:22,453 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:22,455 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:22,481 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:22,481 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:22,800 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:22,819 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:22,820 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:22,822 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:22,823 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:22,890 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:22,894 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:22,910 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:22,910 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:22,933 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 0 proven. 632 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:22,934 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:22,934 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 35 [2018-01-24 23:26:22,934 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:22,935 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-24 23:26:22,935 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-24 23:26:22,935 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 23:26:22,935 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 19 states. [2018-01-24 23:26:23,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:23,758 INFO L93 Difference]: Finished difference Result 255 states and 290 transitions. [2018-01-24 23:26:23,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-24 23:26:23,758 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 87 [2018-01-24 23:26:23,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:23,759 INFO L225 Difference]: With dead ends: 255 [2018-01-24 23:26:23,760 INFO L226 Difference]: Without dead ends: 249 [2018-01-24 23:26:23,760 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 364 GetRequests, 328 SyntacticMatches, 2 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-01-24 23:26:23,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-01-24 23:26:23,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 230. [2018-01-24 23:26:23,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-01-24 23:26:23,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 264 transitions. [2018-01-24 23:26:23,772 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 264 transitions. Word has length 87 [2018-01-24 23:26:23,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:23,773 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 264 transitions. [2018-01-24 23:26:23,773 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-24 23:26:23,773 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 264 transitions. [2018-01-24 23:26:23,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-24 23:26:23,774 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:23,774 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:23,774 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:23,775 INFO L82 PathProgramCache]: Analyzing trace with hash 120606869, now seen corresponding path program 17 times [2018-01-24 23:26:23,775 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:23,775 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:23,776 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:23,776 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:23,776 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:23,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:23,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:24,018 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:24,018 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:24,018 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:24,018 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:24,018 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:24,018 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:24,019 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:24,025 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:24,025 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:24,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,030 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,031 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,032 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,033 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,034 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,036 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,037 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,039 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,040 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,043 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,045 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,047 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,050 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,054 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,057 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,061 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,062 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:24,064 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:24,083 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:24,084 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:24,430 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:24,450 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:24,450 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:24,452 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:24,453 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:24,456 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,458 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,462 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,467 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,473 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,479 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,487 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,497 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,512 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,529 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,545 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,565 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,587 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,744 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:24,805 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:24,809 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:24,824 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:24,824 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:24,848 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 0 proven. 714 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:24,849 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:24,849 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 37 [2018-01-24 23:26:24,849 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:24,850 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-24 23:26:24,850 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-24 23:26:24,850 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 23:26:24,851 INFO L87 Difference]: Start difference. First operand 230 states and 264 transitions. Second operand 20 states. [2018-01-24 23:26:25,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:25,637 INFO L93 Difference]: Finished difference Result 268 states and 305 transitions. [2018-01-24 23:26:25,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-24 23:26:25,638 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-01-24 23:26:25,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:25,639 INFO L225 Difference]: With dead ends: 268 [2018-01-24 23:26:25,639 INFO L226 Difference]: Without dead ends: 262 [2018-01-24 23:26:25,640 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 385 GetRequests, 347 SyntacticMatches, 2 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-01-24 23:26:25,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states. [2018-01-24 23:26:25,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 242. [2018-01-24 23:26:25,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-01-24 23:26:25,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 278 transitions. [2018-01-24 23:26:25,649 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 278 transitions. Word has length 92 [2018-01-24 23:26:25,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:25,649 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 278 transitions. [2018-01-24 23:26:25,649 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-24 23:26:25,649 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 278 transitions. [2018-01-24 23:26:25,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-01-24 23:26:25,651 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:25,651 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:25,651 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:25,651 INFO L82 PathProgramCache]: Analyzing trace with hash 2070056958, now seen corresponding path program 18 times [2018-01-24 23:26:25,651 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:25,652 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:25,652 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:25,652 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:25,652 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:25,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:25,662 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:25,955 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:25,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:25,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:25,955 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:25,955 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:25,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:25,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:25,961 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:25,961 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:25,965 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,966 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,967 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,971 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,973 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,975 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,979 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,982 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,985 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,989 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,991 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,994 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:25,997 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:26,000 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:26,024 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:26,024 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:26,567 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:26,587 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:26,587 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:26,590 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:26,590 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:26,595 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,597 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,607 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,618 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,653 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,676 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,698 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,723 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,746 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,774 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,806 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,847 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:26,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:27,090 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:27,101 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:27,106 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:27,124 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:27,124 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:27,143 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 0 proven. 801 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:27,145 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:27,145 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 39 [2018-01-24 23:26:27,145 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:27,145 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-24 23:26:27,145 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-24 23:26:27,146 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 23:26:27,146 INFO L87 Difference]: Start difference. First operand 242 states and 278 transitions. Second operand 21 states. [2018-01-24 23:26:28,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:28,027 INFO L93 Difference]: Finished difference Result 281 states and 320 transitions. [2018-01-24 23:26:28,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-24 23:26:28,027 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 97 [2018-01-24 23:26:28,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:28,028 INFO L225 Difference]: With dead ends: 281 [2018-01-24 23:26:28,028 INFO L226 Difference]: Without dead ends: 275 [2018-01-24 23:26:28,029 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 406 GetRequests, 366 SyntacticMatches, 2 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=438, Invalid=1122, Unknown=0, NotChecked=0, Total=1560 [2018-01-24 23:26:28,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states. [2018-01-24 23:26:28,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 254. [2018-01-24 23:26:28,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 254 states. [2018-01-24 23:26:28,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 292 transitions. [2018-01-24 23:26:28,041 INFO L78 Accepts]: Start accepts. Automaton has 254 states and 292 transitions. Word has length 97 [2018-01-24 23:26:28,041 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:28,041 INFO L432 AbstractCegarLoop]: Abstraction has 254 states and 292 transitions. [2018-01-24 23:26:28,041 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-24 23:26:28,042 INFO L276 IsEmpty]: Start isEmpty. Operand 254 states and 292 transitions. [2018-01-24 23:26:28,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-24 23:26:28,043 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:28,043 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:28,043 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:28,043 INFO L82 PathProgramCache]: Analyzing trace with hash 183274037, now seen corresponding path program 19 times [2018-01-24 23:26:28,043 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:28,044 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:28,044 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:28,044 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:28,044 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:28,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:28,054 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:28,399 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,399 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:28,399 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:28,399 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:28,400 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:28,400 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:28,400 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:28,405 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:28,405 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:28,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:28,417 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:28,435 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,435 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:28,893 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,913 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:28,913 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:28,916 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:28,916 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:28,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:28,943 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:28,964 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,964 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:28,988 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 0 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:28,989 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:28,990 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 41 [2018-01-24 23:26:28,990 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:28,990 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-24 23:26:28,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-24 23:26:28,991 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 23:26:28,991 INFO L87 Difference]: Start difference. First operand 254 states and 292 transitions. Second operand 22 states. [2018-01-24 23:26:29,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:29,916 INFO L93 Difference]: Finished difference Result 294 states and 335 transitions. [2018-01-24 23:26:29,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-24 23:26:29,917 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-24 23:26:29,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:29,918 INFO L225 Difference]: With dead ends: 294 [2018-01-24 23:26:29,918 INFO L226 Difference]: Without dead ends: 288 [2018-01-24 23:26:29,919 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 427 GetRequests, 385 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=481, Invalid=1241, Unknown=0, NotChecked=0, Total=1722 [2018-01-24 23:26:29,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2018-01-24 23:26:29,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 266. [2018-01-24 23:26:29,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 266 states. [2018-01-24 23:26:29,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 266 states to 266 states and 306 transitions. [2018-01-24 23:26:29,927 INFO L78 Accepts]: Start accepts. Automaton has 266 states and 306 transitions. Word has length 102 [2018-01-24 23:26:29,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:29,928 INFO L432 AbstractCegarLoop]: Abstraction has 266 states and 306 transitions. [2018-01-24 23:26:29,928 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-24 23:26:29,928 INFO L276 IsEmpty]: Start isEmpty. Operand 266 states and 306 transitions. [2018-01-24 23:26:29,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-24 23:26:29,929 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:29,930 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:29,930 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:29,930 INFO L82 PathProgramCache]: Analyzing trace with hash -1033282978, now seen corresponding path program 20 times [2018-01-24 23:26:29,930 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:29,931 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:29,931 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:29,931 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:29,931 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:29,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:29,942 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:30,722 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:30,722 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:30,756 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:30,756 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:30,756 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:30,756 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:30,756 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:30,761 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:30,761 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:30,766 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:30,776 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:30,777 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:30,780 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:30,810 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:30,810 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:31,375 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:31,395 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:31,395 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:31,399 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:31,399 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:31,404 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:31,418 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:31,429 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:31,433 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:31,451 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:31,452 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:31,475 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:31,477 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:31,477 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 43 [2018-01-24 23:26:31,477 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:31,478 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-24 23:26:31,478 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-24 23:26:31,478 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 23:26:31,478 INFO L87 Difference]: Start difference. First operand 266 states and 306 transitions. Second operand 23 states. [2018-01-24 23:26:32,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:32,559 INFO L93 Difference]: Finished difference Result 307 states and 350 transitions. [2018-01-24 23:26:32,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-24 23:26:32,559 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 107 [2018-01-24 23:26:32,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:32,561 INFO L225 Difference]: With dead ends: 307 [2018-01-24 23:26:32,561 INFO L226 Difference]: Without dead ends: 301 [2018-01-24 23:26:32,561 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 404 SyntacticMatches, 2 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=526, Invalid=1366, Unknown=0, NotChecked=0, Total=1892 [2018-01-24 23:26:32,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-01-24 23:26:32,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 278. [2018-01-24 23:26:32,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 278 states. [2018-01-24 23:26:32,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 320 transitions. [2018-01-24 23:26:32,572 INFO L78 Accepts]: Start accepts. Automaton has 278 states and 320 transitions. Word has length 107 [2018-01-24 23:26:32,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:32,572 INFO L432 AbstractCegarLoop]: Abstraction has 278 states and 320 transitions. [2018-01-24 23:26:32,572 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-24 23:26:32,572 INFO L276 IsEmpty]: Start isEmpty. Operand 278 states and 320 transitions. [2018-01-24 23:26:32,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-01-24 23:26:32,573 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:32,573 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:32,573 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:32,573 INFO L82 PathProgramCache]: Analyzing trace with hash -1905968171, now seen corresponding path program 21 times [2018-01-24 23:26:32,573 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:32,574 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:32,574 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:32,574 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:32,574 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:32,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:32,581 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:33,031 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:33,031 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:33,031 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:33,031 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:33,032 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:33,032 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:33,032 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:33,036 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:33,037 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:33,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,047 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,048 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,054 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,059 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,061 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,066 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,070 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,078 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,082 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:33,084 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:33,104 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:33,104 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:33,602 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:33,621 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:33,621 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:33,624 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:33,625 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:33,629 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,634 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,638 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,643 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,650 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,657 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,666 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,677 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,692 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,710 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,729 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,752 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,779 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,818 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,863 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,907 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:33,958 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:34,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:34,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:34,191 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:34,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:34,301 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:34,305 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:34,331 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:34,331 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:34,362 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 0 proven. 1092 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:34,363 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:34,363 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 45 [2018-01-24 23:26:34,363 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:34,364 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-24 23:26:34,364 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-24 23:26:34,364 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 23:26:34,364 INFO L87 Difference]: Start difference. First operand 278 states and 320 transitions. Second operand 24 states. [2018-01-24 23:26:35,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:35,589 INFO L93 Difference]: Finished difference Result 320 states and 365 transitions. [2018-01-24 23:26:35,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-24 23:26:35,590 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 112 [2018-01-24 23:26:35,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:35,591 INFO L225 Difference]: With dead ends: 320 [2018-01-24 23:26:35,591 INFO L226 Difference]: Without dead ends: 314 [2018-01-24 23:26:35,592 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 469 GetRequests, 423 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-01-24 23:26:35,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-01-24 23:26:35,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 290. [2018-01-24 23:26:35,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 290 states. [2018-01-24 23:26:35,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 290 states to 290 states and 334 transitions. [2018-01-24 23:26:35,601 INFO L78 Accepts]: Start accepts. Automaton has 290 states and 334 transitions. Word has length 112 [2018-01-24 23:26:35,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:35,601 INFO L432 AbstractCegarLoop]: Abstraction has 290 states and 334 transitions. [2018-01-24 23:26:35,601 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-24 23:26:35,601 INFO L276 IsEmpty]: Start isEmpty. Operand 290 states and 334 transitions. [2018-01-24 23:26:35,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-24 23:26:35,603 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:35,603 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:35,603 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:35,603 INFO L82 PathProgramCache]: Analyzing trace with hash -994136898, now seen corresponding path program 22 times [2018-01-24 23:26:35,603 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:35,604 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:35,604 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:35,604 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:35,604 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:35,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:35,614 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:35,961 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:35,961 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:35,961 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:35,961 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:35,962 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:35,962 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:35,962 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:35,966 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:35,967 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:35,989 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:35,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:36,013 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:36,013 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:36,574 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:36,594 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:36,595 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:36,597 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:36,598 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:36,716 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:36,720 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:36,745 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:36,746 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:36,775 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 0 proven. 1199 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:36,776 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:36,777 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 47 [2018-01-24 23:26:36,777 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:36,777 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-24 23:26:36,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-24 23:26:36,778 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 23:26:36,778 INFO L87 Difference]: Start difference. First operand 290 states and 334 transitions. Second operand 25 states. [2018-01-24 23:26:37,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:37,994 INFO L93 Difference]: Finished difference Result 333 states and 380 transitions. [2018-01-24 23:26:37,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-24 23:26:37,994 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 117 [2018-01-24 23:26:37,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:37,995 INFO L225 Difference]: With dead ends: 333 [2018-01-24 23:26:37,996 INFO L226 Difference]: Without dead ends: 327 [2018-01-24 23:26:37,996 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 442 SyntacticMatches, 2 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=622, Invalid=1634, Unknown=0, NotChecked=0, Total=2256 [2018-01-24 23:26:37,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-01-24 23:26:38,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 302. [2018-01-24 23:26:38,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-01-24 23:26:38,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 348 transitions. [2018-01-24 23:26:38,005 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 348 transitions. Word has length 117 [2018-01-24 23:26:38,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:38,006 INFO L432 AbstractCegarLoop]: Abstraction has 302 states and 348 transitions. [2018-01-24 23:26:38,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-24 23:26:38,006 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 348 transitions. [2018-01-24 23:26:38,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-24 23:26:38,006 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:38,007 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:38,007 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:38,007 INFO L82 PathProgramCache]: Analyzing trace with hash 1248093557, now seen corresponding path program 23 times [2018-01-24 23:26:38,007 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:38,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:38,007 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:38,008 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:38,008 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:38,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:38,014 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:38,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:38,320 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:38,320 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:38,320 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:38,321 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:38,321 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:38,321 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:38,325 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:38,326 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:38,329 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,332 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,334 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,335 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,337 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,339 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,341 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,343 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,345 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,347 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,350 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,353 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,356 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,359 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,363 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,368 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,378 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,384 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,390 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:38,399 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:38,401 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:38,424 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:38,424 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:39,001 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:39,021 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:39,021 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:39,026 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-24 23:26:39,027 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:39,031 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,033 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,037 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,041 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,047 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,054 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,070 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,081 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,098 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,118 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,137 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,159 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,184 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,224 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,272 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,311 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,355 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,488 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,586 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,742 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:39,851 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:39,855 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:39,877 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:39,877 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:39,903 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 0 proven. 1311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:39,905 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:39,905 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 49 [2018-01-24 23:26:39,905 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:39,905 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-24 23:26:39,905 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-24 23:26:39,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 23:26:39,906 INFO L87 Difference]: Start difference. First operand 302 states and 348 transitions. Second operand 26 states. [2018-01-24 23:26:41,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:41,324 INFO L93 Difference]: Finished difference Result 346 states and 395 transitions. [2018-01-24 23:26:41,356 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-24 23:26:41,356 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 122 [2018-01-24 23:26:41,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:41,358 INFO L225 Difference]: With dead ends: 346 [2018-01-24 23:26:41,358 INFO L226 Difference]: Without dead ends: 340 [2018-01-24 23:26:41,359 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 461 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=673, Invalid=1777, Unknown=0, NotChecked=0, Total=2450 [2018-01-24 23:26:41,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-01-24 23:26:41,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 314. [2018-01-24 23:26:41,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 314 states. [2018-01-24 23:26:41,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 314 states to 314 states and 362 transitions. [2018-01-24 23:26:41,369 INFO L78 Accepts]: Start accepts. Automaton has 314 states and 362 transitions. Word has length 122 [2018-01-24 23:26:41,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:41,370 INFO L432 AbstractCegarLoop]: Abstraction has 314 states and 362 transitions. [2018-01-24 23:26:41,370 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-24 23:26:41,370 INFO L276 IsEmpty]: Start isEmpty. Operand 314 states and 362 transitions. [2018-01-24 23:26:41,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-01-24 23:26:41,370 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:41,371 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:41,371 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:41,371 INFO L82 PathProgramCache]: Analyzing trace with hash -1210546402, now seen corresponding path program 24 times [2018-01-24 23:26:41,371 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:41,372 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:41,372 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:41,372 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:41,372 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:41,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:41,382 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:41,964 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:41,964 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:41,964 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:41,965 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:41,965 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:41,965 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:41,965 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:41,971 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:41,971 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:41,976 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,978 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,979 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,981 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,983 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,984 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,986 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,994 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:41,998 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,000 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,005 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,007 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,012 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,015 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,019 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,022 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,026 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,027 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:42,030 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:42,077 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:42,078 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:42,870 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:42,891 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:42,891 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:42,894 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-24 23:26:42,894 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-24 23:26:42,900 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,914 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,920 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,926 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,933 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,944 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,957 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,972 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:42,994 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,017 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,080 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,114 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,201 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,337 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,430 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,553 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:43,971 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:44,217 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:44,437 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-24 23:26:44,452 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:44,457 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:44,481 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:44,481 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:44,517 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 0 proven. 1428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:44,519 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:44,519 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 51 [2018-01-24 23:26:44,519 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:44,520 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-24 23:26:44,520 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-24 23:26:44,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 23:26:44,521 INFO L87 Difference]: Start difference. First operand 314 states and 362 transitions. Second operand 27 states. [2018-01-24 23:26:45,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:45,994 INFO L93 Difference]: Finished difference Result 359 states and 410 transitions. [2018-01-24 23:26:45,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-24 23:26:45,994 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 127 [2018-01-24 23:26:45,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:45,995 INFO L225 Difference]: With dead ends: 359 [2018-01-24 23:26:45,995 INFO L226 Difference]: Without dead ends: 353 [2018-01-24 23:26:45,996 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 532 GetRequests, 480 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=726, Invalid=1926, Unknown=0, NotChecked=0, Total=2652 [2018-01-24 23:26:45,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states. [2018-01-24 23:26:46,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 326. [2018-01-24 23:26:46,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 326 states. [2018-01-24 23:26:46,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 326 states to 326 states and 376 transitions. [2018-01-24 23:26:46,009 INFO L78 Accepts]: Start accepts. Automaton has 326 states and 376 transitions. Word has length 127 [2018-01-24 23:26:46,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:46,009 INFO L432 AbstractCegarLoop]: Abstraction has 326 states and 376 transitions. [2018-01-24 23:26:46,009 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-24 23:26:46,009 INFO L276 IsEmpty]: Start isEmpty. Operand 326 states and 376 transitions. [2018-01-24 23:26:46,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2018-01-24 23:26:46,010 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:46,011 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:46,011 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:46,011 INFO L82 PathProgramCache]: Analyzing trace with hash 53741333, now seen corresponding path program 25 times [2018-01-24 23:26:46,011 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:46,012 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:46,012 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:46,012 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:46,012 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:46,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:46,021 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:46,989 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:46,989 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:46,989 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:46,989 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:46,989 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:46,989 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:46,990 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:46,995 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:46,995 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:47,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:47,019 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:47,057 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:47,058 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:47,935 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:47,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:47,955 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:47,958 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:47,958 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-24 23:26:47,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:47,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:48,016 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:48,017 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:48,046 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 0 proven. 1550 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:48,047 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:48,047 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 53 [2018-01-24 23:26:48,047 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:48,047 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-24 23:26:48,050 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-24 23:26:48,051 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 23:26:48,051 INFO L87 Difference]: Start difference. First operand 326 states and 376 transitions. Second operand 28 states. [2018-01-24 23:26:49,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:49,495 INFO L93 Difference]: Finished difference Result 372 states and 425 transitions. [2018-01-24 23:26:49,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-24 23:26:49,496 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 132 [2018-01-24 23:26:49,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:49,497 INFO L225 Difference]: With dead ends: 372 [2018-01-24 23:26:49,497 INFO L226 Difference]: Without dead ends: 366 [2018-01-24 23:26:49,498 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 553 GetRequests, 499 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=781, Invalid=2081, Unknown=0, NotChecked=0, Total=2862 [2018-01-24 23:26:49,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-24 23:26:49,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 338. [2018-01-24 23:26:49,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 338 states. [2018-01-24 23:26:49,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 338 states to 338 states and 390 transitions. [2018-01-24 23:26:49,511 INFO L78 Accepts]: Start accepts. Automaton has 338 states and 390 transitions. Word has length 132 [2018-01-24 23:26:49,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:49,511 INFO L432 AbstractCegarLoop]: Abstraction has 338 states and 390 transitions. [2018-01-24 23:26:49,511 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-24 23:26:49,511 INFO L276 IsEmpty]: Start isEmpty. Operand 338 states and 390 transitions. [2018-01-24 23:26:49,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-01-24 23:26:49,512 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:49,513 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:49,513 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:49,513 INFO L82 PathProgramCache]: Analyzing trace with hash -173217410, now seen corresponding path program 26 times [2018-01-24 23:26:49,513 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:49,514 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:49,514 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-24 23:26:49,514 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:49,514 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:49,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:49,523 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:49,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:49,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:49,917 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:49,917 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:49,917 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:49,917 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:49,918 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:49,922 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:49,923 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:49,927 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:49,937 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:49,939 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:49,941 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:49,968 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:49,968 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:50,731 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:50,751 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:50,751 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:50,754 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-24 23:26:50,755 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-24 23:26:50,759 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:50,777 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-24 23:26:50,790 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:50,794 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:50,821 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:50,821 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:50,853 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 0 proven. 1677 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:50,854 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:50,854 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 55 [2018-01-24 23:26:50,854 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:50,854 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-24 23:26:50,855 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-24 23:26:50,855 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 23:26:50,855 INFO L87 Difference]: Start difference. First operand 338 states and 390 transitions. Second operand 29 states. [2018-01-24 23:26:52,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:52,514 INFO L93 Difference]: Finished difference Result 385 states and 440 transitions. [2018-01-24 23:26:52,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-24 23:26:52,514 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 137 [2018-01-24 23:26:52,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:52,516 INFO L225 Difference]: With dead ends: 385 [2018-01-24 23:26:52,516 INFO L226 Difference]: Without dead ends: 379 [2018-01-24 23:26:52,517 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 574 GetRequests, 518 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=838, Invalid=2242, Unknown=0, NotChecked=0, Total=3080 [2018-01-24 23:26:52,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states. [2018-01-24 23:26:52,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 350. [2018-01-24 23:26:52,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2018-01-24 23:26:52,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 404 transitions. [2018-01-24 23:26:52,530 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 404 transitions. Word has length 137 [2018-01-24 23:26:52,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:52,530 INFO L432 AbstractCegarLoop]: Abstraction has 350 states and 404 transitions. [2018-01-24 23:26:52,530 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-24 23:26:52,530 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 404 transitions. [2018-01-24 23:26:52,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-24 23:26:52,532 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:52,532 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:52,532 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:52,532 INFO L82 PathProgramCache]: Analyzing trace with hash 681451701, now seen corresponding path program 27 times [2018-01-24 23:26:52,532 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:52,533 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:52,533 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:52,533 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:52,534 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:52,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:52,543 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:53,054 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:53,054 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:53,054 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:53,055 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:53,055 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:53,055 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:53,055 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:53,060 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:53,060 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:53,065 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,067 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,068 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,070 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,072 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,075 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,077 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,079 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,091 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,094 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,103 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,122 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,126 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,131 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,157 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:53,166 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:53,168 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:53,197 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:53,197 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:54,007 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:54,028 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:54,028 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:54,031 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-24 23:26:54,031 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-24 23:26:54,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,059 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,067 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,076 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,124 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,144 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,169 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,197 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,238 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,333 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,389 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,452 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,540 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,637 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,733 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,841 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:54,963 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:55,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:55,330 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:55,509 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:55,714 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-24 23:26:55,745 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:55,751 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:55,811 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:55,812 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:55,858 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 0 proven. 1809 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:55,860 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:55,860 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 57 [2018-01-24 23:26:55,860 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:55,861 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-24 23:26:55,861 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-24 23:26:55,862 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 23:26:55,862 INFO L87 Difference]: Start difference. First operand 350 states and 404 transitions. Second operand 30 states. [2018-01-24 23:26:57,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:26:57,656 INFO L93 Difference]: Finished difference Result 398 states and 455 transitions. [2018-01-24 23:26:57,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-24 23:26:57,656 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 142 [2018-01-24 23:26:57,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:26:57,657 INFO L225 Difference]: With dead ends: 398 [2018-01-24 23:26:57,657 INFO L226 Difference]: Without dead ends: 392 [2018-01-24 23:26:57,658 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 595 GetRequests, 537 SyntacticMatches, 2 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=897, Invalid=2409, Unknown=0, NotChecked=0, Total=3306 [2018-01-24 23:26:57,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states. [2018-01-24 23:26:57,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 362. [2018-01-24 23:26:57,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 362 states. [2018-01-24 23:26:57,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 362 states to 362 states and 418 transitions. [2018-01-24 23:26:57,670 INFO L78 Accepts]: Start accepts. Automaton has 362 states and 418 transitions. Word has length 142 [2018-01-24 23:26:57,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:26:57,671 INFO L432 AbstractCegarLoop]: Abstraction has 362 states and 418 transitions. [2018-01-24 23:26:57,671 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-24 23:26:57,671 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 418 transitions. [2018-01-24 23:26:57,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-24 23:26:57,673 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:26:57,673 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1] [2018-01-24 23:26:57,673 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:26:57,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1555157982, now seen corresponding path program 28 times [2018-01-24 23:26:57,673 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:26:57,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:57,674 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:26:57,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:26:57,674 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:26:57,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:26:57,681 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-24 23:26:58,181 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:58,181 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:58,181 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-24 23:26:58,181 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-24 23:26:58,181 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-24 23:26:58,181 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:58,181 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-24 23:26:58,186 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:58,186 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:58,222 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:58,225 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:58,259 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:58,259 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:59,113 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:59,134 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-24 23:26:59,134 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-24 23:26:59,137 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-24 23:26:59,137 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-24 23:26:59,348 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-24 23:26:59,353 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-24 23:26:59,384 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:59,384 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-24 23:26:59,420 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 0 proven. 1946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-24 23:26:59,423 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-24 23:26:59,423 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 59 [2018-01-24 23:26:59,423 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-24 23:26:59,423 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-24 23:26:59,423 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-24 23:26:59,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 23:26:59,424 INFO L87 Difference]: Start difference. First operand 362 states and 418 transitions. Second operand 31 states. [2018-01-24 23:27:01,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-24 23:27:01,275 INFO L93 Difference]: Finished difference Result 411 states and 470 transitions. [2018-01-24 23:27:01,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-24 23:27:01,275 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 147 [2018-01-24 23:27:01,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-24 23:27:01,277 INFO L225 Difference]: With dead ends: 411 [2018-01-24 23:27:01,277 INFO L226 Difference]: Without dead ends: 405 [2018-01-24 23:27:01,278 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 616 GetRequests, 556 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=958, Invalid=2582, Unknown=0, NotChecked=0, Total=3540 [2018-01-24 23:27:01,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 405 states. [2018-01-24 23:27:01,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 405 to 374. [2018-01-24 23:27:01,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 374 states. [2018-01-24 23:27:01,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 374 states to 374 states and 432 transitions. [2018-01-24 23:27:01,292 INFO L78 Accepts]: Start accepts. Automaton has 374 states and 432 transitions. Word has length 147 [2018-01-24 23:27:01,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-24 23:27:01,292 INFO L432 AbstractCegarLoop]: Abstraction has 374 states and 432 transitions. [2018-01-24 23:27:01,292 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-24 23:27:01,292 INFO L276 IsEmpty]: Start isEmpty. Operand 374 states and 432 transitions. [2018-01-24 23:27:01,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-24 23:27:01,294 INFO L314 BasicCegarLoop]: Found error trace [2018-01-24 23:27:01,294 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1] [2018-01-24 23:27:01,294 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr2AssertViolation, mainErr5AssertViolation, mainErr4AssertViolation, mainErr3AssertViolation, mainErr1AssertViolation]=== [2018-01-24 23:27:01,294 INFO L82 PathProgramCache]: Analyzing trace with hash 1978446421, now seen corresponding path program 29 times [2018-01-24 23:27:01,294 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-24 23:27:01,295 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:27:01,295 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-24 23:27:01,295 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-24 23:27:01,296 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-24 23:27:01,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-24 23:27:01,305 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-24 23:27:01,514 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-24 23:27:01,517 WARN L187 ceAbstractionStarter]: Timeout [2018-01-24 23:27:01,517 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.01 11:27:01 BoogieIcfgContainer [2018-01-24 23:27:01,517 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-24 23:27:01,518 INFO L168 Benchmark]: Toolchain (without parser) took 52603.07 ms. Allocated memory was 298.3 MB in the beginning and 738.2 MB in the end (delta: 439.9 MB). Free memory was 259.2 MB in the beginning and 519.5 MB in the end (delta: -260.3 MB). Peak memory consumption was 179.6 MB. Max. memory is 5.3 GB. [2018-01-24 23:27:01,518 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 298.3 MB. Free memory is still 263.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 23:27:01,519 INFO L168 Benchmark]: CACSL2BoogieTranslator took 178.59 ms. Allocated memory is still 298.3 MB. Free memory was 257.2 MB in the beginning and 249.3 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. [2018-01-24 23:27:01,519 INFO L168 Benchmark]: Boogie Preprocessor took 29.21 ms. Allocated memory is still 298.3 MB. Free memory is still 249.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-24 23:27:01,519 INFO L168 Benchmark]: RCFGBuilder took 191.23 ms. Allocated memory is still 298.3 MB. Free memory was 249.3 MB in the beginning and 236.3 MB in the end (delta: 13.0 MB). Peak memory consumption was 13.0 MB. Max. memory is 5.3 GB. [2018-01-24 23:27:01,520 INFO L168 Benchmark]: TraceAbstraction took 52194.70 ms. Allocated memory was 298.3 MB in the beginning and 738.2 MB in the end (delta: 439.9 MB). Free memory was 236.3 MB in the beginning and 519.5 MB in the end (delta: -283.2 MB). Peak memory consumption was 156.7 MB. Max. memory is 5.3 GB. [2018-01-24 23:27:01,522 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 298.3 MB. Free memory is still 263.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 178.59 ms. Allocated memory is still 298.3 MB. Free memory was 257.2 MB in the beginning and 249.3 MB in the end (delta: 8.0 MB). Peak memory consumption was 8.0 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 29.21 ms. Allocated memory is still 298.3 MB. Free memory is still 249.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * RCFGBuilder took 191.23 ms. Allocated memory is still 298.3 MB. Free memory was 249.3 MB in the beginning and 236.3 MB in the end (delta: 13.0 MB). Peak memory consumption was 13.0 MB. Max. memory is 5.3 GB. * TraceAbstraction took 52194.70 ms. Allocated memory was 298.3 MB in the beginning and 738.2 MB in the end (delta: 439.9 MB). Free memory was 236.3 MB in the beginning and 519.5 MB in the end (delta: -283.2 MB). Peak memory consumption was 156.7 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 10 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 0 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -20 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 15 TransStat_MAX_WEQGRAPH_SIZE : 3 TransStat_MAX_SIZEOF_WEQEDGELABEL : 2 TransStat_NO_SUPPORTING_EQUALITIES : 5 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 16 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 5.381136 RENAME_VARIABLES(MILLISECONDS) : 0.519620 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 5.291026 PROJECTAWAY(MILLISECONDS) : 8.567163 ADD_WEAK_EQUALITY(MILLISECONDS) : 2.229473 DISJOIN(MILLISECONDS) : 0.235739 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.560727 ADD_EQUALITY(MILLISECONDS) : 0.054013 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.769182 #CONJOIN_DISJUNCTIVE : 36 #RENAME_VARIABLES : 82 #UNFREEZE : 0 #CONJOIN : 48 #PROJECTAWAY : 57 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 10 #RENAME_VARIABLES_DISJUNCTIVE : 77 #ADD_EQUALITY : 5 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 7]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 7). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 5. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 5. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 5. - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 5. - TimeoutResultAtElement [Line: 12]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 12). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 5. - TimeoutResultAtElement [Line: 8]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 8). Cancelled while BasicCegarLoop was analyzing trace of length 153 with TraceHistMax 30, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 5. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 34 locations, 6 error locations. TIMEOUT Result, 52.1s OverallTime, 30 OverallIterations, 30 TraceHistogramMax, 21.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4790 SDtfs, 2700 SDslu, 68887 SDs, 0 SdLazy, 62094 SolverSat, 1015 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 16.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 9312 GetRequests, 8387 SyntacticMatches, 56 SemanticMatches, 869 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 434 ImplicationChecksByTransitivity, 16.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=374occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.3s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 29 MinimizatonAttempts, 493 StatesRemovedByMinimization, 29 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 7.7s SatisfiabilityAnalysisTime, 20.1s InterpolantComputationTime, 6685 NumberOfCodeBlocks, 6685 NumberOfCodeBlocksAsserted, 487 NumberOfCheckSat, 10996 ConstructedInterpolants, 0 QuantifiedInterpolants, 8194098 SizeOfPredicates, 0 NumberOfNonLiveVariables, 6468 ConjunctsInSsa, 1792 ConjunctsInUnsatCore, 141 InterpolantComputations, 1 PerfectInterpolantSequences, 0/95410 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-24_23-27-01-533.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-24_23-27-01-533.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-24_23-27-01-533.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/standard_strcpy_original_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_precise.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-24_23-27-01-533.csv Completed graceful shutdown