java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_smtcomp.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-6b94a2f [2018-01-25 06:28:04,042 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-25 06:28:04,044 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-25 06:28:04,058 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-25 06:28:04,059 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-25 06:28:04,060 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-25 06:28:04,061 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-25 06:28:04,062 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-25 06:28:04,064 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-25 06:28:04,065 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-25 06:28:04,066 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-25 06:28:04,066 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-25 06:28:04,067 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-25 06:28:04,069 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-25 06:28:04,069 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-25 06:28:04,072 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-25 06:28:04,074 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-25 06:28:04,076 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-25 06:28:04,077 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-25 06:28:04,079 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-25 06:28:04,081 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-25 06:28:04,081 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-25 06:28:04,081 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-25 06:28:04,083 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-25 06:28:04,083 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-25 06:28:04,085 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-25 06:28:04,085 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-25 06:28:04,086 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-25 06:28:04,086 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-25 06:28:04,086 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-25 06:28:04,087 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-25 06:28:04,087 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_smtcomp.epf [2018-01-25 06:28:04,095 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-25 06:28:04,095 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-25 06:28:04,096 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-25 06:28:04,096 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-25 06:28:04,096 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-25 06:28:04,096 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-25 06:28:04,096 INFO L133 SettingsManager]: * Precise comparison operator=true [2018-01-25 06:28:04,096 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-25 06:28:04,097 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-25 06:28:04,097 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-25 06:28:04,097 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-01-25 06:28:04,097 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-25 06:28:04,097 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-25 06:28:04,097 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-25 06:28:04,098 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-01-25 06:28:04,098 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-25 06:28:04,099 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-25 06:28:04,099 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-25 06:28:04,099 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-25 06:28:04,099 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-25 06:28:04,099 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * Trace refinement strategy=TAIPAN [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-25 06:28:04,100 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-01-25 06:28:04,101 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-25 06:28:04,101 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-25 06:28:04,132 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-25 06:28:04,142 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-25 06:28:04,145 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-25 06:28:04,147 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-25 06:28:04,147 INFO L276 PluginConnector]: CDTParser initialized [2018-01-25 06:28:04,147 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array3_false-valid-deref.i [2018-01-25 06:28:04,240 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-25 06:28:04,246 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-25 06:28:04,246 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-25 06:28:04,246 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-25 06:28:04,252 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-25 06:28:04,253 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,255 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d2930b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04, skipping insertion in model container [2018-01-25 06:28:04,255 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,268 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-25 06:28:04,281 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-25 06:28:04,389 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-25 06:28:04,400 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-25 06:28:04,405 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04 WrapperNode [2018-01-25 06:28:04,405 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-25 06:28:04,406 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-25 06:28:04,406 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-25 06:28:04,406 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-25 06:28:04,416 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,416 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,422 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,423 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,424 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,427 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,428 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... [2018-01-25 06:28:04,429 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-25 06:28:04,430 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-25 06:28:04,430 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-25 06:28:04,430 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-25 06:28:04,431 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-25 06:28:04,475 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-25 06:28:04,475 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-25 06:28:04,475 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-25 06:28:04,475 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-25 06:28:04,475 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-25 06:28:04,476 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-25 06:28:04,476 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-25 06:28:04,476 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-25 06:28:04,476 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-25 06:28:04,476 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-25 06:28:04,586 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-25 06:28:04,586 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.01 06:28:04 BoogieIcfgContainer [2018-01-25 06:28:04,586 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-25 06:28:04,587 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-25 06:28:04,587 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-25 06:28:04,589 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-25 06:28:04,589 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 25.01 06:28:04" (1/3) ... [2018-01-25 06:28:04,590 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a1872c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 25.01 06:28:04, skipping insertion in model container [2018-01-25 06:28:04,590 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 25.01 06:28:04" (2/3) ... [2018-01-25 06:28:04,591 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a1872c8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 25.01 06:28:04, skipping insertion in model container [2018-01-25 06:28:04,591 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 25.01 06:28:04" (3/3) ... [2018-01-25 06:28:04,592 INFO L105 eAbstractionObserver]: Analyzing ICFG array3_false-valid-deref.i [2018-01-25 06:28:04,598 INFO L130 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-25 06:28:04,604 INFO L142 ceAbstractionStarter]: Appying trace abstraction to program that has 2 error locations. [2018-01-25 06:28:04,639 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-25 06:28:04,639 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-25 06:28:04,639 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-25 06:28:04,640 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-25 06:28:04,640 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-25 06:28:04,640 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-25 06:28:04,640 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-25 06:28:04,640 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-25 06:28:04,641 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-25 06:28:04,660 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states. [2018-01-25 06:28:04,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-01-25 06:28:04,667 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:04,668 INFO L322 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:04,668 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:04,673 INFO L82 PathProgramCache]: Analyzing trace with hash 1213833872, now seen corresponding path program 1 times [2018-01-25 06:28:04,675 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:04,714 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:04,715 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:04,715 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:04,715 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:04,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:04,749 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:04,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-25 06:28:04,844 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-25 06:28:04,844 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-25 06:28:04,844 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-25 06:28:04,846 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-25 06:28:04,856 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-25 06:28:04,857 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-25 06:28:04,859 INFO L87 Difference]: Start difference. First operand 27 states. Second operand 4 states. [2018-01-25 06:28:05,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:05,035 INFO L93 Difference]: Finished difference Result 69 states and 95 transitions. [2018-01-25 06:28:05,036 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-25 06:28:05,037 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 8 [2018-01-25 06:28:05,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:05,044 INFO L225 Difference]: With dead ends: 69 [2018-01-25 06:28:05,044 INFO L226 Difference]: Without dead ends: 35 [2018-01-25 06:28:05,046 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-25 06:28:05,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2018-01-25 06:28:05,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 31. [2018-01-25 06:28:05,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 31 states. [2018-01-25 06:28:05,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 32 transitions. [2018-01-25 06:28:05,135 INFO L78 Accepts]: Start accepts. Automaton has 31 states and 32 transitions. Word has length 8 [2018-01-25 06:28:05,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:05,135 INFO L432 AbstractCegarLoop]: Abstraction has 31 states and 32 transitions. [2018-01-25 06:28:05,135 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-25 06:28:05,135 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 32 transitions. [2018-01-25 06:28:05,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-01-25 06:28:05,136 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:05,136 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:05,136 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:05,136 INFO L82 PathProgramCache]: Analyzing trace with hash -863334142, now seen corresponding path program 1 times [2018-01-25 06:28:05,137 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:05,137 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:05,138 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:05,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:05,138 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:05,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:05,149 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:05,245 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-25 06:28:05,246 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-25 06:28:05,246 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-01-25 06:28:05,246 INFO L252 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-01-25 06:28:05,248 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-25 06:28:05,248 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-25 06:28:05,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-25 06:28:05,249 INFO L87 Difference]: Start difference. First operand 31 states and 32 transitions. Second operand 6 states. [2018-01-25 06:28:05,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:05,337 INFO L93 Difference]: Finished difference Result 35 states and 36 transitions. [2018-01-25 06:28:05,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-25 06:28:05,337 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-01-25 06:28:05,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:05,338 INFO L225 Difference]: With dead ends: 35 [2018-01-25 06:28:05,338 INFO L226 Difference]: Without dead ends: 34 [2018-01-25 06:28:05,339 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-25 06:28:05,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-01-25 06:28:05,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 29. [2018-01-25 06:28:05,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-01-25 06:28:05,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2018-01-25 06:28:05,346 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 30 transitions. Word has length 16 [2018-01-25 06:28:05,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:05,346 INFO L432 AbstractCegarLoop]: Abstraction has 29 states and 30 transitions. [2018-01-25 06:28:05,346 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-25 06:28:05,346 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 30 transitions. [2018-01-25 06:28:05,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-01-25 06:28:05,347 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:05,347 INFO L322 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:05,347 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:05,348 INFO L82 PathProgramCache]: Analyzing trace with hash -1135364244, now seen corresponding path program 1 times [2018-01-25 06:28:05,348 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:05,349 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:05,349 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:05,349 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:05,349 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:05,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:05,364 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:05,427 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,427 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:05,428 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:05,428 INFO L199 CegarAbsIntRunner]: Running AI on error trace of length 29 with the following transitions: [2018-01-25 06:28:05,430 INFO L201 CegarAbsIntRunner]: [0], [4], [8], [11], [13], [15], [17], [21], [25], [26], [27], [32], [37], [39], [55], [56], [57] [2018-01-25 06:28:05,475 INFO L147 AbstractInterpreter]: Using domain VPDomain [2018-01-25 06:28:05,475 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-25 06:28:05,597 INFO L259 AbstractInterpreter]: Some error location(s) were reachable [2018-01-25 06:28:05,598 INFO L268 AbstractInterpreter]: Visited 17 different actions 29 times. Merged at 11 different actions 11 times. Never widened. Found 3 fixpoints after 3 different actions. Largest state had 5 variables. [2018-01-25 06:28:05,610 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown [2018-01-25 06:28:05,610 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:05,610 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:05,621 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:05,621 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:05,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:05,642 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:05,660 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,660 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:05,689 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,709 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:05,709 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:05,713 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:05,713 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:05,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:05,730 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:05,735 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,735 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:05,750 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,752 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:05,752 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-01-25 06:28:05,752 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:05,753 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-25 06:28:05,753 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-25 06:28:05,753 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-25 06:28:05,753 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. Second operand 5 states. [2018-01-25 06:28:05,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:05,829 INFO L93 Difference]: Finished difference Result 58 states and 60 transitions. [2018-01-25 06:28:05,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-25 06:28:05,830 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-01-25 06:28:05,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:05,830 INFO L225 Difference]: With dead ends: 58 [2018-01-25 06:28:05,831 INFO L226 Difference]: Without dead ends: 44 [2018-01-25 06:28:05,831 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-25 06:28:05,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-01-25 06:28:05,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 33. [2018-01-25 06:28:05,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-01-25 06:28:05,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 34 transitions. [2018-01-25 06:28:05,838 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 34 transitions. Word has length 28 [2018-01-25 06:28:05,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:05,838 INFO L432 AbstractCegarLoop]: Abstraction has 33 states and 34 transitions. [2018-01-25 06:28:05,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-25 06:28:05,838 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 34 transitions. [2018-01-25 06:28:05,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-25 06:28:05,839 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:05,840 INFO L322 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:05,840 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:05,840 INFO L82 PathProgramCache]: Analyzing trace with hash 1230203493, now seen corresponding path program 2 times [2018-01-25 06:28:05,840 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:05,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:05,841 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:05,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:05,841 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:05,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:05,852 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:05,940 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,940 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:05,940 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:05,940 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:05,940 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:05,941 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:05,941 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:05,952 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:05,952 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:05,958 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:05,973 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:05,974 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:05,976 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:05,982 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:05,983 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:06,140 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:06,161 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,161 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:06,172 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:06,172 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:06,178 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:06,184 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:06,189 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:06,192 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:06,200 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:06,201 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:06,217 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:06,218 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:06,219 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-01-25 06:28:06,219 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:06,219 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-25 06:28:06,220 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-25 06:28:06,220 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-25 06:28:06,221 INFO L87 Difference]: Start difference. First operand 33 states and 34 transitions. Second operand 6 states. [2018-01-25 06:28:06,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:06,291 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2018-01-25 06:28:06,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-25 06:28:06,291 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 32 [2018-01-25 06:28:06,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:06,293 INFO L225 Difference]: With dead ends: 67 [2018-01-25 06:28:06,293 INFO L226 Difference]: Without dead ends: 53 [2018-01-25 06:28:06,293 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-25 06:28:06,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-01-25 06:28:06,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 37. [2018-01-25 06:28:06,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-01-25 06:28:06,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-01-25 06:28:06,300 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 32 [2018-01-25 06:28:06,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:06,300 INFO L432 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-01-25 06:28:06,300 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-25 06:28:06,300 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-01-25 06:28:06,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-25 06:28:06,302 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:06,302 INFO L322 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:06,302 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:06,302 INFO L82 PathProgramCache]: Analyzing trace with hash 417265886, now seen corresponding path program 3 times [2018-01-25 06:28:06,302 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:06,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:06,303 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:06,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:06,304 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:06,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:06,315 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:06,369 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-01-25 06:28:06,369 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,369 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:06,370 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:06,370 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:06,370 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,370 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:06,379 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:06,379 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:06,384 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:06,386 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:06,388 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:06,389 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:06,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:06,409 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-25 06:28:06,410 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:06,534 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-25 06:28:06,555 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,555 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:06,563 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:06,563 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:06,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:06,575 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:06,581 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:06,585 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:06,588 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:06,592 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-25 06:28:06,592 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:06,601 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-01-25 06:28:06,602 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:06,603 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 4, 4, 4, 4] total 13 [2018-01-25 06:28:06,603 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:06,603 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-25 06:28:06,603 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-25 06:28:06,604 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-25 06:28:06,604 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 10 states. [2018-01-25 06:28:06,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:06,691 INFO L93 Difference]: Finished difference Result 76 states and 80 transitions. [2018-01-25 06:28:06,691 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-25 06:28:06,691 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 36 [2018-01-25 06:28:06,691 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:06,692 INFO L225 Difference]: With dead ends: 76 [2018-01-25 06:28:06,692 INFO L226 Difference]: Without dead ends: 62 [2018-01-25 06:28:06,692 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 138 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=102, Unknown=0, NotChecked=0, Total=156 [2018-01-25 06:28:06,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-01-25 06:28:06,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 46. [2018-01-25 06:28:06,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-25 06:28:06,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2018-01-25 06:28:06,697 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 47 transitions. Word has length 36 [2018-01-25 06:28:06,697 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:06,697 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 47 transitions. [2018-01-25 06:28:06,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-25 06:28:06,698 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 47 transitions. [2018-01-25 06:28:06,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-01-25 06:28:06,698 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:06,699 INFO L322 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:06,699 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:06,699 INFO L82 PathProgramCache]: Analyzing trace with hash 576961419, now seen corresponding path program 4 times [2018-01-25 06:28:06,699 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:06,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:06,700 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:06,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:06,700 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:06,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:06,709 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:06,770 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:06,771 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,771 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:06,771 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:06,771 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:06,771 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,771 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:06,776 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:06,776 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:06,790 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:06,792 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:06,801 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:06,801 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:06,865 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:06,885 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:06,885 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:06,888 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:06,888 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:06,909 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:06,913 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:06,920 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:06,921 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:06,934 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:06,936 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:06,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-01-25 06:28:06,936 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:06,936 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-25 06:28:06,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-25 06:28:06,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-25 06:28:06,937 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. Second operand 8 states. [2018-01-25 06:28:07,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:07,012 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-01-25 06:28:07,014 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-25 06:28:07,014 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 45 [2018-01-25 06:28:07,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:07,016 INFO L225 Difference]: With dead ends: 90 [2018-01-25 06:28:07,016 INFO L226 Difference]: Without dead ends: 71 [2018-01-25 06:28:07,016 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 186 GetRequests, 174 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-25 06:28:07,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-01-25 06:28:07,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2018-01-25 06:28:07,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-01-25 06:28:07,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2018-01-25 06:28:07,023 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 51 transitions. Word has length 45 [2018-01-25 06:28:07,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:07,023 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 51 transitions. [2018-01-25 06:28:07,023 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-25 06:28:07,023 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 51 transitions. [2018-01-25 06:28:07,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-01-25 06:28:07,024 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:07,024 INFO L322 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:07,024 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:07,025 INFO L82 PathProgramCache]: Analyzing trace with hash -194823758, now seen corresponding path program 5 times [2018-01-25 06:28:07,025 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:07,025 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:07,025 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:07,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:07,026 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:07,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:07,038 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:07,147 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:07,147 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:07,147 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:07,147 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:07,147 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:07,148 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:07,148 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:07,157 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:07,157 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:07,163 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,167 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,170 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,172 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,175 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,178 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,182 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,183 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:07,186 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:07,195 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:07,195 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:07,293 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:07,313 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:07,313 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:07,316 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:07,317 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:07,321 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,322 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,326 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,332 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,347 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,365 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:07,374 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:07,379 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:07,389 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:07,389 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:07,399 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:07,401 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:07,401 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-01-25 06:28:07,404 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:07,405 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-25 06:28:07,405 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-25 06:28:07,405 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-25 06:28:07,405 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. Second operand 9 states. [2018-01-25 06:28:07,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:07,483 INFO L93 Difference]: Finished difference Result 99 states and 104 transitions. [2018-01-25 06:28:07,483 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-25 06:28:07,483 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 49 [2018-01-25 06:28:07,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:07,485 INFO L225 Difference]: With dead ends: 99 [2018-01-25 06:28:07,486 INFO L226 Difference]: Without dead ends: 80 [2018-01-25 06:28:07,486 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-25 06:28:07,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-25 06:28:07,491 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 54. [2018-01-25 06:28:07,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-25 06:28:07,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2018-01-25 06:28:07,492 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 55 transitions. Word has length 49 [2018-01-25 06:28:07,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:07,492 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 55 transitions. [2018-01-25 06:28:07,492 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-25 06:28:07,493 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 55 transitions. [2018-01-25 06:28:07,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-01-25 06:28:07,494 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:07,494 INFO L322 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:07,494 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:07,494 INFO L82 PathProgramCache]: Analyzing trace with hash -1600566183, now seen corresponding path program 6 times [2018-01-25 06:28:07,494 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:07,495 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:07,495 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:07,495 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:07,495 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:07,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:07,505 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:07,597 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-25 06:28:07,597 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:07,597 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:07,597 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:07,597 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:07,597 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:07,597 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:07,605 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:07,606 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:07,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,626 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,636 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,637 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:07,640 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:07,669 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-25 06:28:07,669 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:07,734 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-25 06:28:07,756 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:07,756 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:07,759 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:07,759 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:07,765 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,767 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,771 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,776 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:07,809 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:07,812 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:07,815 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-25 06:28:07,815 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:07,823 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2018-01-25 06:28:07,825 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:07,825 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5, 5, 5, 5] total 18 [2018-01-25 06:28:07,825 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:07,826 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-25 06:28:07,826 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-25 06:28:07,826 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-25 06:28:07,826 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. Second operand 14 states. [2018-01-25 06:28:07,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:07,978 INFO L93 Difference]: Finished difference Result 108 states and 114 transitions. [2018-01-25 06:28:07,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-25 06:28:07,978 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-01-25 06:28:07,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:07,979 INFO L225 Difference]: With dead ends: 108 [2018-01-25 06:28:07,979 INFO L226 Difference]: Without dead ends: 89 [2018-01-25 06:28:07,979 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 220 GetRequests, 204 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=103, Invalid=203, Unknown=0, NotChecked=0, Total=306 [2018-01-25 06:28:07,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-01-25 06:28:07,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 63. [2018-01-25 06:28:07,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-01-25 06:28:07,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2018-01-25 06:28:07,988 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 64 transitions. Word has length 53 [2018-01-25 06:28:07,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:07,988 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 64 transitions. [2018-01-25 06:28:07,988 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-25 06:28:07,989 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 64 transitions. [2018-01-25 06:28:07,989 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-25 06:28:07,990 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:07,990 INFO L322 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:07,990 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:07,990 INFO L82 PathProgramCache]: Analyzing trace with hash 1495641218, now seen corresponding path program 7 times [2018-01-25 06:28:07,990 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:07,991 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:07,991 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:07,991 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:07,992 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:08,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:08,005 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:08,084 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,084 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:08,084 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:08,084 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:08,084 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:08,084 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:08,084 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:08,090 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:08,090 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:08,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:08,106 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:08,116 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,116 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:08,288 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,309 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:08,309 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:08,321 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:08,321 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:08,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:08,350 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:08,362 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,362 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:08,399 INFO L134 CoverageAnalysis]: Checked inductivity of 166 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,401 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:08,401 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-01-25 06:28:08,401 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:08,402 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-25 06:28:08,402 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-25 06:28:08,402 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-25 06:28:08,402 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. Second operand 11 states. [2018-01-25 06:28:08,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:08,503 INFO L93 Difference]: Finished difference Result 122 states and 128 transitions. [2018-01-25 06:28:08,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-25 06:28:08,504 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 62 [2018-01-25 06:28:08,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:08,505 INFO L225 Difference]: With dead ends: 122 [2018-01-25 06:28:08,505 INFO L226 Difference]: Without dead ends: 98 [2018-01-25 06:28:08,505 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 257 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-25 06:28:08,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-01-25 06:28:08,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 67. [2018-01-25 06:28:08,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-01-25 06:28:08,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2018-01-25 06:28:08,513 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 68 transitions. Word has length 62 [2018-01-25 06:28:08,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:08,514 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 68 transitions. [2018-01-25 06:28:08,514 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-25 06:28:08,514 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 68 transitions. [2018-01-25 06:28:08,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-25 06:28:08,515 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:08,515 INFO L322 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:08,515 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:08,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1534369477, now seen corresponding path program 8 times [2018-01-25 06:28:08,516 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:08,516 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:08,517 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:08,517 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:08,517 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:08,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:08,529 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:08,610 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,610 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:08,610 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:08,610 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:08,610 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:08,610 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:08,611 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:08,615 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:08,616 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:08,620 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:08,626 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:08,627 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:08,629 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:08,639 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,639 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:08,759 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,779 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:08,779 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:08,782 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:08,782 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:08,787 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:08,796 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:08,803 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:08,806 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:08,815 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,815 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:08,858 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:08,860 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:08,860 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-01-25 06:28:08,860 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:08,861 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-25 06:28:08,861 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-25 06:28:08,861 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-25 06:28:08,861 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. Second operand 12 states. [2018-01-25 06:28:08,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:08,931 INFO L93 Difference]: Finished difference Result 131 states and 138 transitions. [2018-01-25 06:28:08,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-25 06:28:08,931 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 66 [2018-01-25 06:28:08,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:08,933 INFO L225 Difference]: With dead ends: 131 [2018-01-25 06:28:08,933 INFO L226 Difference]: Without dead ends: 107 [2018-01-25 06:28:08,934 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 274 GetRequests, 254 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-25 06:28:08,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-01-25 06:28:08,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 71. [2018-01-25 06:28:08,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 71 states. [2018-01-25 06:28:08,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2018-01-25 06:28:08,942 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 72 transitions. Word has length 66 [2018-01-25 06:28:08,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:08,942 INFO L432 AbstractCegarLoop]: Abstraction has 71 states and 72 transitions. [2018-01-25 06:28:08,943 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-25 06:28:08,943 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 72 transitions. [2018-01-25 06:28:08,944 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-25 06:28:08,944 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:08,944 INFO L322 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:08,944 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:08,944 INFO L82 PathProgramCache]: Analyzing trace with hash -1473900172, now seen corresponding path program 9 times [2018-01-25 06:28:08,944 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:08,945 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:08,945 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:08,946 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:08,946 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:08,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:08,957 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:09,042 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-01-25 06:28:09,042 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:09,070 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:09,071 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:09,071 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:09,071 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:09,071 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:09,076 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:09,076 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:09,080 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,086 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:09,087 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:09,109 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-25 06:28:09,109 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:09,160 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-25 06:28:09,180 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:09,180 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:09,183 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:09,183 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:09,188 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,191 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,196 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,203 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,213 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:09,218 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:09,222 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:09,228 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-25 06:28:09,228 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:09,242 INFO L134 CoverageAnalysis]: Checked inductivity of 238 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-01-25 06:28:09,244 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:09,244 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 6, 6, 6, 6] total 23 [2018-01-25 06:28:09,244 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:09,244 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-25 06:28:09,245 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-25 06:28:09,245 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-25 06:28:09,245 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. Second operand 18 states. [2018-01-25 06:28:09,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:09,421 INFO L93 Difference]: Finished difference Result 140 states and 148 transitions. [2018-01-25 06:28:09,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-25 06:28:09,421 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 70 [2018-01-25 06:28:09,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:09,422 INFO L225 Difference]: With dead ends: 140 [2018-01-25 06:28:09,422 INFO L226 Difference]: Without dead ends: 116 [2018-01-25 06:28:09,423 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 291 GetRequests, 270 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 175 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=168, Invalid=338, Unknown=0, NotChecked=0, Total=506 [2018-01-25 06:28:09,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-01-25 06:28:09,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 80. [2018-01-25 06:28:09,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-01-25 06:28:09,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2018-01-25 06:28:09,432 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 81 transitions. Word has length 70 [2018-01-25 06:28:09,432 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:09,432 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 81 transitions. [2018-01-25 06:28:09,433 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-25 06:28:09,433 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 81 transitions. [2018-01-25 06:28:09,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-01-25 06:28:09,434 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:09,434 INFO L322 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:09,434 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:09,434 INFO L82 PathProgramCache]: Analyzing trace with hash -1757583627, now seen corresponding path program 10 times [2018-01-25 06:28:09,435 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:09,435 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:09,436 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:09,436 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:09,436 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:09,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:09,447 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:09,550 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:09,550 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:09,550 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:09,550 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:09,550 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:09,551 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:09,551 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:09,560 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:09,561 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:09,574 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:09,575 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:09,583 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:09,583 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:09,717 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:09,736 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:09,737 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:09,739 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:09,740 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:09,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:09,769 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:09,779 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:09,779 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:09,799 INFO L134 CoverageAnalysis]: Checked inductivity of 302 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:09,800 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:09,800 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-01-25 06:28:09,800 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:09,800 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-25 06:28:09,801 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-25 06:28:09,801 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-25 06:28:09,801 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. Second operand 14 states. [2018-01-25 06:28:09,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:09,896 INFO L93 Difference]: Finished difference Result 154 states and 162 transitions. [2018-01-25 06:28:09,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-25 06:28:09,896 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 79 [2018-01-25 06:28:09,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:09,897 INFO L225 Difference]: With dead ends: 154 [2018-01-25 06:28:09,897 INFO L226 Difference]: Without dead ends: 125 [2018-01-25 06:28:09,897 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 304 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-25 06:28:09,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-01-25 06:28:09,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 84. [2018-01-25 06:28:09,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-01-25 06:28:09,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 85 transitions. [2018-01-25 06:28:09,906 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 85 transitions. Word has length 79 [2018-01-25 06:28:09,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:09,906 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 85 transitions. [2018-01-25 06:28:09,906 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-25 06:28:09,906 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 85 transitions. [2018-01-25 06:28:09,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-01-25 06:28:09,908 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:09,908 INFO L322 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:09,908 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:09,908 INFO L82 PathProgramCache]: Analyzing trace with hash -2099078308, now seen corresponding path program 11 times [2018-01-25 06:28:09,908 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:09,909 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:09,909 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:09,909 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:09,910 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:09,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:09,920 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:10,041 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:10,041 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:10,041 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:10,041 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:10,042 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:10,042 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:10,042 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:10,047 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:10,047 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:10,051 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,053 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,054 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,055 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,056 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,057 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,058 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,060 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,064 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,067 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,069 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,074 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:10,076 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:10,087 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:10,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:10,288 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:10,319 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:10,319 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:10,322 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:10,322 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:10,327 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,330 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,338 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,343 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,357 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,367 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,394 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,412 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,435 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,520 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:10,530 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:10,534 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:10,542 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:10,542 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:10,555 INFO L134 CoverageAnalysis]: Checked inductivity of 348 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:10,557 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:10,557 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-01-25 06:28:10,557 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:10,558 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-25 06:28:10,558 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-25 06:28:10,558 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-25 06:28:10,558 INFO L87 Difference]: Start difference. First operand 84 states and 85 transitions. Second operand 15 states. [2018-01-25 06:28:10,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:10,667 INFO L93 Difference]: Finished difference Result 163 states and 172 transitions. [2018-01-25 06:28:10,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-25 06:28:10,667 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 83 [2018-01-25 06:28:10,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:10,668 INFO L225 Difference]: With dead ends: 163 [2018-01-25 06:28:10,668 INFO L226 Difference]: Without dead ends: 134 [2018-01-25 06:28:10,669 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 345 GetRequests, 319 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-25 06:28:10,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-01-25 06:28:10,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 88. [2018-01-25 06:28:10,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-25 06:28:10,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 89 transitions. [2018-01-25 06:28:10,674 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 89 transitions. Word has length 83 [2018-01-25 06:28:10,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:10,675 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 89 transitions. [2018-01-25 06:28:10,675 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-25 06:28:10,675 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 89 transitions. [2018-01-25 06:28:10,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-01-25 06:28:10,675 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:10,675 INFO L322 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:10,675 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:10,676 INFO L82 PathProgramCache]: Analyzing trace with hash -159824829, now seen corresponding path program 12 times [2018-01-25 06:28:10,676 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:10,681 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:10,681 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:10,681 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:10,681 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:10,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:10,694 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:10,835 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-01-25 06:28:10,835 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:10,835 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:10,835 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:10,835 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:10,835 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:10,835 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:10,841 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:10,841 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:10,847 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,849 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,850 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,852 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,854 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,855 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,857 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,859 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,860 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,862 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,865 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:10,866 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:10,867 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:10,902 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-25 06:28:10,902 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:10,983 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-25 06:28:11,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:11,004 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:11,009 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:11,009 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:11,017 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,019 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,025 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,033 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,043 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,057 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,075 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,105 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,137 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,161 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:11,168 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:11,171 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:11,176 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-25 06:28:11,176 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:11,186 INFO L134 CoverageAnalysis]: Checked inductivity of 398 backedges. 0 proven. 60 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-01-25 06:28:11,188 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:11,188 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 7, 7, 7, 7] total 28 [2018-01-25 06:28:11,188 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:11,188 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-25 06:28:11,188 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-25 06:28:11,188 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-25 06:28:11,189 INFO L87 Difference]: Start difference. First operand 88 states and 89 transitions. Second operand 22 states. [2018-01-25 06:28:11,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:11,332 INFO L93 Difference]: Finished difference Result 172 states and 182 transitions. [2018-01-25 06:28:11,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-25 06:28:11,332 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 87 [2018-01-25 06:28:11,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:11,333 INFO L225 Difference]: With dead ends: 172 [2018-01-25 06:28:11,333 INFO L226 Difference]: Without dead ends: 143 [2018-01-25 06:28:11,333 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 362 GetRequests, 336 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 270 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=249, Invalid=507, Unknown=0, NotChecked=0, Total=756 [2018-01-25 06:28:11,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-01-25 06:28:11,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 97. [2018-01-25 06:28:11,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-01-25 06:28:11,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-01-25 06:28:11,339 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 87 [2018-01-25 06:28:11,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:11,339 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-01-25 06:28:11,339 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-25 06:28:11,339 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-01-25 06:28:11,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-01-25 06:28:11,340 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:11,340 INFO L322 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:11,340 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:11,340 INFO L82 PathProgramCache]: Analyzing trace with hash -2110093160, now seen corresponding path program 13 times [2018-01-25 06:28:11,340 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:11,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:11,341 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:11,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:11,341 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:11,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:11,351 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:11,536 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:11,537 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:11,537 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:11,537 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:11,537 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:11,537 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:11,537 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:11,542 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:11,542 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:11,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:11,557 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:11,571 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:11,572 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:11,768 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:11,788 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:11,788 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:11,790 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:11,791 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:11,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:11,819 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:11,832 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:11,832 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:11,857 INFO L134 CoverageAnalysis]: Checked inductivity of 479 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:11,858 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:11,859 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-01-25 06:28:11,859 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:11,859 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-25 06:28:11,859 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-25 06:28:11,860 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-25 06:28:11,860 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 17 states. [2018-01-25 06:28:11,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:11,979 INFO L93 Difference]: Finished difference Result 186 states and 196 transitions. [2018-01-25 06:28:11,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-25 06:28:11,980 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 96 [2018-01-25 06:28:11,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:11,981 INFO L225 Difference]: With dead ends: 186 [2018-01-25 06:28:11,981 INFO L226 Difference]: Without dead ends: 152 [2018-01-25 06:28:11,981 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 369 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-25 06:28:11,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-01-25 06:28:11,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 101. [2018-01-25 06:28:11,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-01-25 06:28:11,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2018-01-25 06:28:11,990 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 102 transitions. Word has length 96 [2018-01-25 06:28:11,990 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:11,990 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 102 transitions. [2018-01-25 06:28:11,990 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-25 06:28:11,991 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 102 transitions. [2018-01-25 06:28:11,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-25 06:28:11,991 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:11,991 INFO L322 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:11,992 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:11,992 INFO L82 PathProgramCache]: Analyzing trace with hash 1842728721, now seen corresponding path program 14 times [2018-01-25 06:28:11,992 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:11,993 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:11,993 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:11,993 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:11,993 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:12,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:12,006 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:12,230 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:12,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:12,231 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:12,231 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:12,231 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:12,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:12,231 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:12,236 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:12,236 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:12,241 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:12,249 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:12,250 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:12,252 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:12,262 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:12,262 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:12,486 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:12,506 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:12,506 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:12,509 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:12,510 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:12,517 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:12,531 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:12,541 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:12,545 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:12,555 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:12,555 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:12,579 INFO L134 CoverageAnalysis]: Checked inductivity of 537 backedges. 0 proven. 450 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:12,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:12,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-01-25 06:28:12,581 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:12,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-25 06:28:12,582 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-25 06:28:12,582 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-25 06:28:12,582 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. Second operand 18 states. [2018-01-25 06:28:12,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:12,770 INFO L93 Difference]: Finished difference Result 195 states and 206 transitions. [2018-01-25 06:28:12,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-25 06:28:12,771 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 100 [2018-01-25 06:28:12,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:12,772 INFO L225 Difference]: With dead ends: 195 [2018-01-25 06:28:12,772 INFO L226 Difference]: Without dead ends: 161 [2018-01-25 06:28:12,773 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-25 06:28:12,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-01-25 06:28:12,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 105. [2018-01-25 06:28:12,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-01-25 06:28:12,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 106 transitions. [2018-01-25 06:28:12,784 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 106 transitions. Word has length 100 [2018-01-25 06:28:12,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:12,784 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 106 transitions. [2018-01-25 06:28:12,784 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-25 06:28:12,784 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 106 transitions. [2018-01-25 06:28:12,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-01-25 06:28:12,785 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:12,785 INFO L322 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:12,785 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:12,785 INFO L82 PathProgramCache]: Analyzing trace with hash -184078070, now seen corresponding path program 15 times [2018-01-25 06:28:12,785 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:12,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:12,786 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:12,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:12,786 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:12,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:12,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:12,971 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 512 refuted. 0 times theorem prover too weak. 87 trivial. 0 not checked. [2018-01-25 06:28:12,972 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:12,972 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:12,972 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:12,972 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:12,972 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:12,972 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:12,979 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:12,979 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:12,986 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,987 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,989 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,990 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,992 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,995 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,997 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:12,998 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:13,001 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:13,087 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-25 06:28:13,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:13,251 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-25 06:28:13,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:13,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:13,276 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:13,276 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:13,285 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,292 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,301 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,326 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,347 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:13,355 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:13,358 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:13,365 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-25 06:28:13,366 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:13,381 INFO L134 CoverageAnalysis]: Checked inductivity of 599 backedges. 0 proven. 87 refuted. 0 times theorem prover too weak. 512 trivial. 0 not checked. [2018-01-25 06:28:13,382 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:13,382 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 8, 8, 8, 8] total 33 [2018-01-25 06:28:13,382 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:13,383 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-25 06:28:13,383 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-25 06:28:13,383 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-25 06:28:13,383 INFO L87 Difference]: Start difference. First operand 105 states and 106 transitions. Second operand 26 states. [2018-01-25 06:28:13,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:13,652 INFO L93 Difference]: Finished difference Result 204 states and 216 transitions. [2018-01-25 06:28:13,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-25 06:28:13,652 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 104 [2018-01-25 06:28:13,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:13,653 INFO L225 Difference]: With dead ends: 204 [2018-01-25 06:28:13,653 INFO L226 Difference]: Without dead ends: 170 [2018-01-25 06:28:13,654 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 433 GetRequests, 402 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=346, Invalid=710, Unknown=0, NotChecked=0, Total=1056 [2018-01-25 06:28:13,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-01-25 06:28:13,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 114. [2018-01-25 06:28:13,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-01-25 06:28:13,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 115 transitions. [2018-01-25 06:28:13,665 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 115 transitions. Word has length 104 [2018-01-25 06:28:13,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:13,665 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 115 transitions. [2018-01-25 06:28:13,665 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-25 06:28:13,665 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 115 transitions. [2018-01-25 06:28:13,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-01-25 06:28:13,666 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:13,666 INFO L322 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:13,666 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:13,667 INFO L82 PathProgramCache]: Analyzing trace with hash 950262623, now seen corresponding path program 16 times [2018-01-25 06:28:13,667 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:13,667 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:13,668 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:13,668 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:13,668 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:13,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:13,681 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:13,862 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:13,862 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:13,862 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:13,862 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:13,862 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:13,862 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:13,862 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:13,867 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:13,867 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:13,885 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:13,887 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:13,904 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:13,904 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:14,243 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:14,272 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:14,272 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:14,275 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:14,275 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:14,316 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:14,320 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:14,337 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:14,337 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:14,369 INFO L134 CoverageAnalysis]: Checked inductivity of 697 backedges. 0 proven. 578 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:14,371 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:14,371 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-01-25 06:28:14,372 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:14,372 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-25 06:28:14,372 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-25 06:28:14,373 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-25 06:28:14,373 INFO L87 Difference]: Start difference. First operand 114 states and 115 transitions. Second operand 20 states. [2018-01-25 06:28:14,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:14,572 INFO L93 Difference]: Finished difference Result 218 states and 230 transitions. [2018-01-25 06:28:14,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-25 06:28:14,572 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 113 [2018-01-25 06:28:14,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:14,574 INFO L225 Difference]: With dead ends: 218 [2018-01-25 06:28:14,574 INFO L226 Difference]: Without dead ends: 179 [2018-01-25 06:28:14,575 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 470 GetRequests, 434 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-25 06:28:14,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-01-25 06:28:14,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 118. [2018-01-25 06:28:14,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-25 06:28:14,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 119 transitions. [2018-01-25 06:28:14,589 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 119 transitions. Word has length 113 [2018-01-25 06:28:14,589 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:14,589 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 119 transitions. [2018-01-25 06:28:14,589 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-25 06:28:14,589 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 119 transitions. [2018-01-25 06:28:14,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-01-25 06:28:14,590 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:14,590 INFO L322 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:14,590 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:14,590 INFO L82 PathProgramCache]: Analyzing trace with hash 1664169478, now seen corresponding path program 17 times [2018-01-25 06:28:14,591 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:14,591 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:14,591 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:14,591 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:14,592 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:14,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:14,605 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:14,835 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:14,835 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:14,835 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:14,835 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:14,835 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:14,835 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:14,835 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:14,840 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:14,840 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:14,846 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,849 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,850 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,856 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,869 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,873 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,877 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,882 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,887 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:14,899 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:14,901 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:14,914 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:14,914 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:15,214 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:15,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:15,235 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:15,238 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:15,238 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:15,244 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,246 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,255 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,261 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,268 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,276 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,286 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,298 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,312 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,329 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,349 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,372 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,400 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,434 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,523 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,582 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:15,937 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:15,942 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:15,954 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:15,955 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:15,977 INFO L134 CoverageAnalysis]: Checked inductivity of 767 backedges. 0 proven. 648 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:15,980 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:15,980 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-01-25 06:28:15,980 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:15,980 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-25 06:28:15,980 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-25 06:28:15,981 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-25 06:28:15,981 INFO L87 Difference]: Start difference. First operand 118 states and 119 transitions. Second operand 21 states. [2018-01-25 06:28:16,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:16,134 INFO L93 Difference]: Finished difference Result 227 states and 240 transitions. [2018-01-25 06:28:16,134 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-25 06:28:16,134 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 117 [2018-01-25 06:28:16,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:16,135 INFO L225 Difference]: With dead ends: 227 [2018-01-25 06:28:16,135 INFO L226 Difference]: Without dead ends: 188 [2018-01-25 06:28:16,136 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 449 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-25 06:28:16,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-01-25 06:28:16,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 122. [2018-01-25 06:28:16,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-01-25 06:28:16,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 123 transitions. [2018-01-25 06:28:16,150 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 123 transitions. Word has length 117 [2018-01-25 06:28:16,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:16,151 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 123 transitions. [2018-01-25 06:28:16,151 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-25 06:28:16,151 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 123 transitions. [2018-01-25 06:28:16,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-25 06:28:16,152 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:16,152 INFO L322 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:16,152 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:16,152 INFO L82 PathProgramCache]: Analyzing trace with hash 2092098861, now seen corresponding path program 18 times [2018-01-25 06:28:16,152 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:16,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:16,153 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:16,153 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:16,153 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:16,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:16,164 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:16,379 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 722 refuted. 0 times theorem prover too weak. 119 trivial. 0 not checked. [2018-01-25 06:28:16,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:16,379 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:16,379 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:16,379 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:16,379 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:16,380 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:16,384 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:16,385 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:16,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,393 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,394 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,395 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,396 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,400 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,404 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,406 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,407 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,409 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,414 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,415 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:16,417 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:16,458 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-25 06:28:16,458 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:16,569 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-25 06:28:16,588 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:16,588 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:16,592 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:16,592 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:16,600 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,606 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,628 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,640 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,667 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,693 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,717 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,819 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,892 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,952 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:16,966 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:16,971 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:16,984 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-25 06:28:16,984 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:17,008 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 119 refuted. 0 times theorem prover too weak. 722 trivial. 0 not checked. [2018-01-25 06:28:17,010 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:17,011 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 9, 9, 9, 9] total 38 [2018-01-25 06:28:17,011 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:17,011 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-25 06:28:17,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-25 06:28:17,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-25 06:28:17,012 INFO L87 Difference]: Start difference. First operand 122 states and 123 transitions. Second operand 30 states. [2018-01-25 06:28:17,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:17,381 INFO L93 Difference]: Finished difference Result 236 states and 250 transitions. [2018-01-25 06:28:17,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-25 06:28:17,381 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 121 [2018-01-25 06:28:17,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:17,382 INFO L225 Difference]: With dead ends: 236 [2018-01-25 06:28:17,382 INFO L226 Difference]: Without dead ends: 197 [2018-01-25 06:28:17,383 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 504 GetRequests, 468 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=459, Invalid=947, Unknown=0, NotChecked=0, Total=1406 [2018-01-25 06:28:17,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-25 06:28:17,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 131. [2018-01-25 06:28:17,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-25 06:28:17,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 132 transitions. [2018-01-25 06:28:17,399 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 132 transitions. Word has length 121 [2018-01-25 06:28:17,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:17,399 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 132 transitions. [2018-01-25 06:28:17,399 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-25 06:28:17,399 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 132 transitions. [2018-01-25 06:28:17,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-25 06:28:17,400 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:17,400 INFO L322 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:17,400 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:17,400 INFO L82 PathProgramCache]: Analyzing trace with hash 734718894, now seen corresponding path program 19 times [2018-01-25 06:28:17,400 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:17,401 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:17,401 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:17,401 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:17,401 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:17,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:17,414 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:17,676 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:17,676 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:17,676 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:17,676 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:17,676 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:17,676 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:17,676 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:17,681 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:17,681 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:17,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:17,702 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:17,716 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:17,716 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:18,089 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:18,109 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:18,109 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:18,113 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:18,113 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:18,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:18,152 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:18,166 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:18,166 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:18,180 INFO L134 CoverageAnalysis]: Checked inductivity of 956 backedges. 0 proven. 800 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:18,182 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:18,182 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-01-25 06:28:18,182 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:18,182 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-25 06:28:18,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-25 06:28:18,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-25 06:28:18,183 INFO L87 Difference]: Start difference. First operand 131 states and 132 transitions. Second operand 23 states. [2018-01-25 06:28:18,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:18,533 INFO L93 Difference]: Finished difference Result 250 states and 264 transitions. [2018-01-25 06:28:18,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-25 06:28:18,534 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 130 [2018-01-25 06:28:18,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:18,535 INFO L225 Difference]: With dead ends: 250 [2018-01-25 06:28:18,535 INFO L226 Difference]: Without dead ends: 206 [2018-01-25 06:28:18,535 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 541 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-25 06:28:18,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-01-25 06:28:18,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 135. [2018-01-25 06:28:18,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-01-25 06:28:18,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 136 transitions. [2018-01-25 06:28:18,547 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 136 transitions. Word has length 130 [2018-01-25 06:28:18,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:18,547 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 136 transitions. [2018-01-25 06:28:18,547 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-25 06:28:18,547 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 136 transitions. [2018-01-25 06:28:18,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-25 06:28:18,548 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:18,548 INFO L322 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:18,548 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:18,548 INFO L82 PathProgramCache]: Analyzing trace with hash 1367823335, now seen corresponding path program 20 times [2018-01-25 06:28:18,548 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:18,549 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:18,549 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:18,549 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:18,549 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:18,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:18,560 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:18,787 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:18,787 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:18,787 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:18,788 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:18,788 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:18,788 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:18,788 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:18,793 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:18,793 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:18,799 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:18,811 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:18,813 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:18,816 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:18,839 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:18,839 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:19,440 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:19,460 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:19,460 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:19,463 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:19,464 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:19,473 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:19,494 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:19,508 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:19,513 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:19,535 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:19,535 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:19,559 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 0 proven. 882 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:19,561 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:19,561 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-01-25 06:28:19,561 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:19,561 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-25 06:28:19,561 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-25 06:28:19,562 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-25 06:28:19,562 INFO L87 Difference]: Start difference. First operand 135 states and 136 transitions. Second operand 24 states. [2018-01-25 06:28:19,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:19,848 INFO L93 Difference]: Finished difference Result 259 states and 274 transitions. [2018-01-25 06:28:19,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-25 06:28:19,850 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 134 [2018-01-25 06:28:19,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:19,852 INFO L225 Difference]: With dead ends: 259 [2018-01-25 06:28:19,852 INFO L226 Difference]: Without dead ends: 215 [2018-01-25 06:28:19,852 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 558 GetRequests, 514 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-25 06:28:19,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-01-25 06:28:19,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 139. [2018-01-25 06:28:19,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-25 06:28:19,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 140 transitions. [2018-01-25 06:28:19,867 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 140 transitions. Word has length 134 [2018-01-25 06:28:19,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:19,867 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 140 transitions. [2018-01-25 06:28:19,867 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-25 06:28:19,867 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 140 transitions. [2018-01-25 06:28:19,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-25 06:28:19,868 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:19,868 INFO L322 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:19,868 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:19,868 INFO L82 PathProgramCache]: Analyzing trace with hash -168626272, now seen corresponding path program 21 times [2018-01-25 06:28:19,868 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:19,869 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:19,869 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:19,869 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:19,869 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:19,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:19,883 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:20,211 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 968 refuted. 0 times theorem prover too weak. 156 trivial. 0 not checked. [2018-01-25 06:28:20,211 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:20,211 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:20,211 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:20,212 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:20,212 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:20,212 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:20,217 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:20,217 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:20,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,224 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,227 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,228 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,232 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,235 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,238 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,238 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:20,241 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:20,307 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-25 06:28:20,307 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:20,466 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-25 06:28:20,486 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:20,486 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:20,489 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:20,489 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:20,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,519 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,529 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,543 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,564 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,592 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:20,640 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:20,645 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:20,658 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-25 06:28:20,659 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:20,682 INFO L134 CoverageAnalysis]: Checked inductivity of 1124 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 968 trivial. 0 not checked. [2018-01-25 06:28:20,683 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:20,683 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 10, 10, 10, 10] total 43 [2018-01-25 06:28:20,683 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:20,684 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-25 06:28:20,684 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-25 06:28:20,684 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-25 06:28:20,684 INFO L87 Difference]: Start difference. First operand 139 states and 140 transitions. Second operand 34 states. [2018-01-25 06:28:21,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:21,195 INFO L93 Difference]: Finished difference Result 268 states and 284 transitions. [2018-01-25 06:28:21,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-25 06:28:21,195 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 138 [2018-01-25 06:28:21,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:21,197 INFO L225 Difference]: With dead ends: 268 [2018-01-25 06:28:21,197 INFO L226 Difference]: Without dead ends: 224 [2018-01-25 06:28:21,198 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 534 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 675 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=588, Invalid=1218, Unknown=0, NotChecked=0, Total=1806 [2018-01-25 06:28:21,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-01-25 06:28:21,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 148. [2018-01-25 06:28:21,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-01-25 06:28:21,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 149 transitions. [2018-01-25 06:28:21,214 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 149 transitions. Word has length 138 [2018-01-25 06:28:21,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:21,214 INFO L432 AbstractCegarLoop]: Abstraction has 148 states and 149 transitions. [2018-01-25 06:28:21,214 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-25 06:28:21,214 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 149 transitions. [2018-01-25 06:28:21,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 148 [2018-01-25 06:28:21,214 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:21,215 INFO L322 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:21,215 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:21,215 INFO L82 PathProgramCache]: Analyzing trace with hash -219252535, now seen corresponding path program 22 times [2018-01-25 06:28:21,215 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:21,215 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:21,216 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:21,216 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:21,216 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:21,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:21,226 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:21,480 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:21,480 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:21,481 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:21,481 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:21,481 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:21,481 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:21,481 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:21,486 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:21,486 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:21,506 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:21,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:21,524 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:21,524 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:21,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:22,012 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:22,013 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:22,015 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:22,016 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:22,065 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:22,069 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:22,084 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:22,084 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:22,104 INFO L134 CoverageAnalysis]: Checked inductivity of 1256 backedges. 0 proven. 1058 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:22,105 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:22,105 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-01-25 06:28:22,105 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:22,105 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-25 06:28:22,106 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-25 06:28:22,106 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-25 06:28:22,106 INFO L87 Difference]: Start difference. First operand 148 states and 149 transitions. Second operand 26 states. [2018-01-25 06:28:23,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:23,006 INFO L93 Difference]: Finished difference Result 282 states and 298 transitions. [2018-01-25 06:28:23,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-25 06:28:23,006 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 147 [2018-01-25 06:28:23,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:23,007 INFO L225 Difference]: With dead ends: 282 [2018-01-25 06:28:23,007 INFO L226 Difference]: Without dead ends: 233 [2018-01-25 06:28:23,008 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 612 GetRequests, 564 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-25 06:28:23,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-01-25 06:28:23,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 152. [2018-01-25 06:28:23,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-01-25 06:28:23,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 153 transitions. [2018-01-25 06:28:23,024 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 153 transitions. Word has length 147 [2018-01-25 06:28:23,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:23,024 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 153 transitions. [2018-01-25 06:28:23,024 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-25 06:28:23,024 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 153 transitions. [2018-01-25 06:28:23,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2018-01-25 06:28:23,025 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:23,025 INFO L322 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:23,025 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:23,025 INFO L82 PathProgramCache]: Analyzing trace with hash -2062915152, now seen corresponding path program 23 times [2018-01-25 06:28:23,025 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:23,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:23,026 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:23,026 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:23,026 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:23,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:23,036 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:23,593 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:23,594 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:23,594 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:23,594 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:23,594 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:23,594 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:23,594 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:23,599 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:23,599 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:23,606 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,607 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,608 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,610 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,618 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,620 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,625 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,627 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,631 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,635 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,639 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,650 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,656 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,670 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,687 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,708 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:23,709 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:23,712 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:23,729 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:23,730 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:24,247 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:24,268 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:24,283 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:24,285 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:24,286 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:24,293 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,295 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,299 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,304 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,309 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,316 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,324 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,333 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,344 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,358 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,374 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,392 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,414 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,438 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,467 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,499 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,538 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,583 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,638 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,701 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,777 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,861 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:24,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:25,079 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:26,050 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:26,089 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:26,094 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:26,110 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:26,110 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:26,142 INFO L134 CoverageAnalysis]: Checked inductivity of 1350 backedges. 0 proven. 1152 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:26,144 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:26,144 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-01-25 06:28:26,144 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:26,145 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-25 06:28:26,145 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-25 06:28:26,145 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-25 06:28:26,145 INFO L87 Difference]: Start difference. First operand 152 states and 153 transitions. Second operand 27 states. [2018-01-25 06:28:26,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:26,400 INFO L93 Difference]: Finished difference Result 291 states and 308 transitions. [2018-01-25 06:28:26,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-25 06:28:26,400 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 151 [2018-01-25 06:28:26,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:26,402 INFO L225 Difference]: With dead ends: 291 [2018-01-25 06:28:26,402 INFO L226 Difference]: Without dead ends: 242 [2018-01-25 06:28:26,403 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 629 GetRequests, 579 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-25 06:28:26,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states. [2018-01-25 06:28:26,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 156. [2018-01-25 06:28:26,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-01-25 06:28:26,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 157 transitions. [2018-01-25 06:28:26,429 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 157 transitions. Word has length 151 [2018-01-25 06:28:26,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:26,429 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 157 transitions. [2018-01-25 06:28:26,429 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-25 06:28:26,429 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 157 transitions. [2018-01-25 06:28:26,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-01-25 06:28:26,430 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:26,430 INFO L322 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:26,430 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:26,430 INFO L82 PathProgramCache]: Analyzing trace with hash -731541737, now seen corresponding path program 24 times [2018-01-25 06:28:26,430 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:26,431 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:26,431 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:26,431 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:26,431 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:26,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:26,445 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:26,920 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 1250 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-01-25 06:28:26,921 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:26,921 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:26,921 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:26,921 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:26,921 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:26,921 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:26,932 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:26,933 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:26,941 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,955 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,958 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,960 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,962 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,963 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,965 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,967 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,969 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,972 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,974 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,980 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,984 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,988 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:26,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,007 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,009 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:27,011 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:27,072 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-25 06:28:27,072 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:27,280 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-25 06:28:27,302 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:27,302 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:27,305 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:27,305 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:27,313 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,315 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,320 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,324 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,331 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,341 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,353 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,367 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,383 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,418 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,668 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:27,937 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:28,294 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:28,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:29,454 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:29,481 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:29,486 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:29,497 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-25 06:28:29,497 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:29,518 INFO L134 CoverageAnalysis]: Checked inductivity of 1448 backedges. 0 proven. 198 refuted. 0 times theorem prover too weak. 1250 trivial. 0 not checked. [2018-01-25 06:28:29,520 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:29,520 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 11, 11, 11, 11] total 48 [2018-01-25 06:28:29,520 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:29,521 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-25 06:28:29,521 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-25 06:28:29,522 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-25 06:28:29,522 INFO L87 Difference]: Start difference. First operand 156 states and 157 transitions. Second operand 38 states. [2018-01-25 06:28:30,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:30,219 INFO L93 Difference]: Finished difference Result 300 states and 318 transitions. [2018-01-25 06:28:30,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-25 06:28:30,219 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 155 [2018-01-25 06:28:30,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:30,220 INFO L225 Difference]: With dead ends: 300 [2018-01-25 06:28:30,220 INFO L226 Difference]: Without dead ends: 251 [2018-01-25 06:28:30,221 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 646 GetRequests, 600 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 850 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=733, Invalid=1523, Unknown=0, NotChecked=0, Total=2256 [2018-01-25 06:28:30,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-01-25 06:28:30,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 165. [2018-01-25 06:28:30,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-01-25 06:28:30,251 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 166 transitions. [2018-01-25 06:28:30,251 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 166 transitions. Word has length 155 [2018-01-25 06:28:30,251 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:30,251 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 166 transitions. [2018-01-25 06:28:30,251 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-25 06:28:30,251 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 166 transitions. [2018-01-25 06:28:30,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-01-25 06:28:30,252 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:30,253 INFO L322 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:30,253 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:30,253 INFO L82 PathProgramCache]: Analyzing trace with hash 7304644, now seen corresponding path program 25 times [2018-01-25 06:28:30,253 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:30,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:30,254 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:30,254 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:30,254 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:30,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:30,270 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:30,698 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:30,698 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:30,698 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:30,698 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:30,698 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:30,698 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:30,698 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:30,706 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:30,707 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:30,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:30,735 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:30,763 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:30,764 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:31,650 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:31,670 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:31,670 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:31,674 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:31,674 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-01-25 06:28:31,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:31,728 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:31,762 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:31,763 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:31,785 INFO L134 CoverageAnalysis]: Checked inductivity of 1597 backedges. 0 proven. 1352 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:31,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:31,787 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-01-25 06:28:31,787 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:31,787 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-25 06:28:31,787 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-25 06:28:31,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-25 06:28:31,788 INFO L87 Difference]: Start difference. First operand 165 states and 166 transitions. Second operand 29 states. [2018-01-25 06:28:32,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:32,105 INFO L93 Difference]: Finished difference Result 314 states and 332 transitions. [2018-01-25 06:28:32,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-25 06:28:32,106 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 164 [2018-01-25 06:28:32,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:32,107 INFO L225 Difference]: With dead ends: 314 [2018-01-25 06:28:32,107 INFO L226 Difference]: Without dead ends: 260 [2018-01-25 06:28:32,108 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 683 GetRequests, 629 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-25 06:28:32,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 260 states. [2018-01-25 06:28:32,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 260 to 169. [2018-01-25 06:28:32,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-01-25 06:28:32,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 170 transitions. [2018-01-25 06:28:32,136 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 170 transitions. Word has length 164 [2018-01-25 06:28:32,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:32,136 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 170 transitions. [2018-01-25 06:28:32,136 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-25 06:28:32,136 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 170 transitions. [2018-01-25 06:28:32,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2018-01-25 06:28:32,137 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:32,137 INFO L322 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:32,137 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:32,137 INFO L82 PathProgramCache]: Analyzing trace with hash -1420521539, now seen corresponding path program 26 times [2018-01-25 06:28:32,137 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:32,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:32,138 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-25 06:28:32,138 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:32,138 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:32,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:32,152 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:33,004 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:33,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:33,005 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:33,005 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:33,005 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:33,005 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:33,005 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:33,013 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:33,014 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:33,021 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:33,037 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:33,040 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:33,042 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:33,075 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:33,075 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:33,712 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:33,732 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:33,733 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:33,736 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-25 06:28:33,736 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:33,744 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:33,768 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:33,785 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:33,789 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:33,807 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:33,808 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:33,841 INFO L134 CoverageAnalysis]: Checked inductivity of 1703 backedges. 0 proven. 1458 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:33,843 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:33,843 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-01-25 06:28:33,843 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:33,843 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-25 06:28:33,844 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-25 06:28:33,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-25 06:28:33,845 INFO L87 Difference]: Start difference. First operand 169 states and 170 transitions. Second operand 30 states. [2018-01-25 06:28:34,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:34,158 INFO L93 Difference]: Finished difference Result 323 states and 342 transitions. [2018-01-25 06:28:34,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-25 06:28:34,158 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 168 [2018-01-25 06:28:34,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:34,159 INFO L225 Difference]: With dead ends: 323 [2018-01-25 06:28:34,160 INFO L226 Difference]: Without dead ends: 269 [2018-01-25 06:28:34,161 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 700 GetRequests, 644 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-25 06:28:34,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-01-25 06:28:34,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 173. [2018-01-25 06:28:34,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-01-25 06:28:34,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 174 transitions. [2018-01-25 06:28:34,184 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 174 transitions. Word has length 168 [2018-01-25 06:28:34,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:34,184 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 174 transitions. [2018-01-25 06:28:34,184 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-25 06:28:34,184 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 174 transitions. [2018-01-25 06:28:34,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-01-25 06:28:34,185 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:34,185 INFO L322 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:34,185 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:34,185 INFO L82 PathProgramCache]: Analyzing trace with hash -910555850, now seen corresponding path program 27 times [2018-01-25 06:28:34,185 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:34,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:34,186 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:34,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:34,186 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:34,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:34,200 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:34,761 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 1568 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2018-01-25 06:28:34,761 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:34,761 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:34,761 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:34,761 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:34,761 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:34,761 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:34,766 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:34,766 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:34,773 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,775 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,776 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,778 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,779 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,781 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,784 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,787 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,789 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,793 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,799 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:34,800 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:34,802 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:34,867 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-25 06:28:34,867 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:35,082 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-25 06:28:35,103 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:35,103 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:35,107 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-25 06:28:35,107 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-01-25 06:28:35,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,120 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,127 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,184 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,212 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,251 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,299 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,363 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-25 06:28:35,376 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:35,380 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:35,402 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-25 06:28:35,402 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:35,438 INFO L134 CoverageAnalysis]: Checked inductivity of 1813 backedges. 0 proven. 245 refuted. 0 times theorem prover too weak. 1568 trivial. 0 not checked. [2018-01-25 06:28:35,439 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:35,439 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 12, 12, 12, 12] total 53 [2018-01-25 06:28:35,439 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:35,440 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-25 06:28:35,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-25 06:28:35,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-25 06:28:35,440 INFO L87 Difference]: Start difference. First operand 173 states and 174 transitions. Second operand 42 states. [2018-01-25 06:28:35,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:35,912 INFO L93 Difference]: Finished difference Result 332 states and 352 transitions. [2018-01-25 06:28:35,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-25 06:28:35,912 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 172 [2018-01-25 06:28:35,913 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:35,914 INFO L225 Difference]: With dead ends: 332 [2018-01-25 06:28:35,914 INFO L226 Difference]: Without dead ends: 278 [2018-01-25 06:28:35,914 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 717 GetRequests, 666 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1045 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=894, Invalid=1862, Unknown=0, NotChecked=0, Total=2756 [2018-01-25 06:28:35,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2018-01-25 06:28:35,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 182. [2018-01-25 06:28:35,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-01-25 06:28:35,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 183 transitions. [2018-01-25 06:28:35,942 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 183 transitions. Word has length 172 [2018-01-25 06:28:35,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:35,942 INFO L432 AbstractCegarLoop]: Abstraction has 182 states and 183 transitions. [2018-01-25 06:28:35,942 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-25 06:28:35,942 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 183 transitions. [2018-01-25 06:28:35,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-01-25 06:28:35,943 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:35,943 INFO L322 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:35,943 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:35,943 INFO L82 PathProgramCache]: Analyzing trace with hash 1830068019, now seen corresponding path program 28 times [2018-01-25 06:28:35,943 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:35,944 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:35,944 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:35,944 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:35,944 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:35,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:35,954 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:36,546 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:36,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:36,546 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:36,546 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:36,546 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:36,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:36,546 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:36,552 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:36,552 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:36,583 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:36,585 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:36,607 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:36,607 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:37,715 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:37,735 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:37,735 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:37,738 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-25 06:28:37,738 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-01-25 06:28:37,802 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:37,808 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:37,840 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:37,841 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:37,881 INFO L134 CoverageAnalysis]: Checked inductivity of 1979 backedges. 0 proven. 1682 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:37,882 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:37,882 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-01-25 06:28:37,882 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:37,883 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-25 06:28:37,883 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-25 06:28:37,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-25 06:28:37,884 INFO L87 Difference]: Start difference. First operand 182 states and 183 transitions. Second operand 32 states. [2018-01-25 06:28:38,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:38,403 INFO L93 Difference]: Finished difference Result 346 states and 366 transitions. [2018-01-25 06:28:38,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-25 06:28:38,404 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 181 [2018-01-25 06:28:38,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:38,405 INFO L225 Difference]: With dead ends: 346 [2018-01-25 06:28:38,406 INFO L226 Difference]: Without dead ends: 287 [2018-01-25 06:28:38,406 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 754 GetRequests, 694 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-25 06:28:38,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-01-25 06:28:38,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 186. [2018-01-25 06:28:38,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-01-25 06:28:38,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 187 transitions. [2018-01-25 06:28:38,452 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 187 transitions. Word has length 181 [2018-01-25 06:28:38,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:38,452 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 187 transitions. [2018-01-25 06:28:38,452 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-25 06:28:38,452 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 187 transitions. [2018-01-25 06:28:38,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-01-25 06:28:38,453 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:38,453 INFO L322 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:38,454 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:38,454 INFO L82 PathProgramCache]: Analyzing trace with hash -1177971110, now seen corresponding path program 29 times [2018-01-25 06:28:38,454 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:38,455 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:38,455 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:38,455 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:38,455 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:38,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:38,470 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:39,580 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:39,580 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:39,580 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:39,580 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:39,581 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:39,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:39,581 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:39,586 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:39,586 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:39,595 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,609 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,617 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,624 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,648 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,657 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,677 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,691 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,695 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,704 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,707 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,714 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,724 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,732 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,740 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,745 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,752 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,759 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,873 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:39,930 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:39,934 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:39,969 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:39,969 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:40,939 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:40,960 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:40,961 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:40,964 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-25 06:28:40,964 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-01-25 06:28:40,974 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:40,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:40,980 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:40,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:40,991 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:40,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,016 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,042 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,059 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,079 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,103 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,131 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,161 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,195 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,233 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,274 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,322 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,373 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,498 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,657 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,766 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:41,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:42,037 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:42,201 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:42,387 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:42,595 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:45,100 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-25 06:28:45,169 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:45,176 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:45,197 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:45,197 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:45,235 INFO L134 CoverageAnalysis]: Checked inductivity of 2097 backedges. 0 proven. 1800 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:45,238 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-01-25 06:28:45,238 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-01-25 06:28:45,238 INFO L247 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-01-25 06:28:45,239 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-25 06:28:45,239 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-25 06:28:45,240 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-25 06:28:45,240 INFO L87 Difference]: Start difference. First operand 186 states and 187 transitions. Second operand 33 states. [2018-01-25 06:28:45,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-25 06:28:45,630 INFO L93 Difference]: Finished difference Result 355 states and 376 transitions. [2018-01-25 06:28:45,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-25 06:28:45,630 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 185 [2018-01-25 06:28:45,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-25 06:28:45,631 INFO L225 Difference]: With dead ends: 355 [2018-01-25 06:28:45,631 INFO L226 Difference]: Without dead ends: 296 [2018-01-25 06:28:45,632 INFO L525 BasicCegarLoop]: 0 DeclaredPredicates, 771 GetRequests, 709 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-25 06:28:45,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 296 states. [2018-01-25 06:28:45,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 296 to 190. [2018-01-25 06:28:45,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-25 06:28:45,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 191 transitions. [2018-01-25 06:28:45,658 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 191 transitions. Word has length 185 [2018-01-25 06:28:45,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-25 06:28:45,659 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 191 transitions. [2018-01-25 06:28:45,659 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-25 06:28:45,659 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 191 transitions. [2018-01-25 06:28:45,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 190 [2018-01-25 06:28:45,659 INFO L314 BasicCegarLoop]: Found error trace [2018-01-25 06:28:45,659 INFO L322 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-25 06:28:45,659 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolation, mainErr1AssertViolation]=== [2018-01-25 06:28:45,660 INFO L82 PathProgramCache]: Analyzing trace with hash 659595777, now seen corresponding path program 30 times [2018-01-25 06:28:45,660 INFO L67 tionRefinementEngine]: Using refinement strategy TaipanRefinementStrategy [2018-01-25 06:28:45,660 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:45,660 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-25 06:28:45,660 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-25 06:28:45,660 INFO L280 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-01-25 06:28:45,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-25 06:28:45,672 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-25 06:28:46,363 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 1922 refuted. 0 times theorem prover too weak. 297 trivial. 0 not checked. [2018-01-25 06:28:46,363 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:46,363 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode ABSTRACT_INTERPRETATION [2018-01-25 06:28:46,363 INFO L183 CegarAbsIntRunner]: Skipping current iteration for AI because we have already analyzed this path program [2018-01-25 06:28:46,364 INFO L434 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: AbsInt can only provide a hoare triple checker if it generated fixpoints [2018-01-25 06:28:46,364 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:46,364 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-25 06:28:46,369 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:46,369 INFO L280 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:46,376 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,377 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,379 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,380 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,382 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,383 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,384 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,386 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,389 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,391 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,394 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,405 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,409 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,416 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,421 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,427 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,432 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,434 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:46,436 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:46,507 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-25 06:28:46,508 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-01-25 06:28:46,749 INFO L134 CoverageAnalysis]: Checked inductivity of 2219 backedges. 0 proven. 297 refuted. 0 times theorem prover too weak. 1922 trivial. 0 not checked. [2018-01-25 06:28:46,770 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-25 06:28:46,771 INFO L187 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/cvc4 Starting monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4 --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-01-25 06:28:46,774 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-25 06:28:46,774 INFO L280 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-01-25 06:28:46,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,790 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,825 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,843 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,859 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,881 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,946 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:46,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:47,062 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:47,125 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:47,398 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:47,707 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:48,307 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:48,936 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:49,978 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command Received shutdown request... [2018-01-25 06:28:51,235 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:52,666 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:53,129 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-25 06:28:53,157 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-25 06:28:53,163 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-25 06:28:53,165 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-01-25 06:28:53,166 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-25 06:28:53,168 WARN L187 ceAbstractionStarter]: Timeout [2018-01-25 06:28:53,169 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 25.01 06:28:53 BoogieIcfgContainer [2018-01-25 06:28:53,169 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-25 06:28:53,170 INFO L168 Benchmark]: Toolchain (without parser) took 48928.88 ms. Allocated memory was 297.8 MB in the beginning and 757.1 MB in the end (delta: 459.3 MB). Free memory was 258.8 MB in the beginning and 339.1 MB in the end (delta: -80.3 MB). Peak memory consumption was 379.0 MB. Max. memory is 5.3 GB. [2018-01-25 06:28:53,170 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 297.8 MB. Free memory is still 263.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-25 06:28:53,171 INFO L168 Benchmark]: CACSL2BoogieTranslator took 158.97 ms. Allocated memory is still 297.8 MB. Free memory was 257.8 MB in the beginning and 250.7 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. [2018-01-25 06:28:53,171 INFO L168 Benchmark]: Boogie Preprocessor took 24.03 ms. Allocated memory is still 297.8 MB. Free memory was 250.7 MB in the beginning and 248.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. [2018-01-25 06:28:53,171 INFO L168 Benchmark]: RCFGBuilder took 156.69 ms. Allocated memory is still 297.8 MB. Free memory was 248.7 MB in the beginning and 237.1 MB in the end (delta: 11.6 MB). Peak memory consumption was 11.6 MB. Max. memory is 5.3 GB. [2018-01-25 06:28:53,171 INFO L168 Benchmark]: TraceAbstraction took 48581.60 ms. Allocated memory was 297.8 MB in the beginning and 757.1 MB in the end (delta: 459.3 MB). Free memory was 237.1 MB in the beginning and 339.1 MB in the end (delta: -102.0 MB). Peak memory consumption was 357.3 MB. Max. memory is 5.3 GB. [2018-01-25 06:28:53,172 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 297.8 MB. Free memory is still 263.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 158.97 ms. Allocated memory is still 297.8 MB. Free memory was 257.8 MB in the beginning and 250.7 MB in the end (delta: 7.1 MB). Peak memory consumption was 7.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 24.03 ms. Allocated memory is still 297.8 MB. Free memory was 250.7 MB in the beginning and 248.7 MB in the end (delta: 2.0 MB). Peak memory consumption was 2.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 156.69 ms. Allocated memory is still 297.8 MB. Free memory was 248.7 MB in the beginning and 237.1 MB in the end (delta: 11.6 MB). Peak memory consumption was 11.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 48581.60 ms. Allocated memory was 297.8 MB in the beginning and 757.1 MB in the end (delta: 459.3 MB). Free memory was 237.1 MB in the beginning and 339.1 MB in the end (delta: -102.0 MB). Peak memory consumption was 357.3 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 15 LocStat_MAX_WEQGRAPH_SIZE : 0 LocStat_MAX_SIZEOF_WEQEDGELABEL : 0 LocStat_NO_SUPPORTING_EQUALITIES : 2 LocStat_NO_SUPPORTING_DISEQUALITIES : 4 LocStat_NO_DISJUNCTIONS : -30 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 21 TransStat_MAX_WEQGRAPH_SIZE : 1 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 9 TransStat_NO_SUPPORTING_DISEQUALITIES : 1 TransStat_NO_DISJUNCTIONS : 22 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.269212 RENAME_VARIABLES(MILLISECONDS) : 0.387483 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.204902 PROJECTAWAY(MILLISECONDS) : 0.277454 ADD_WEAK_EQUALITY(MILLISECONDS) : 3.256352 DISJOIN(MILLISECONDS) : 0.164506 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.429242 ADD_EQUALITY(MILLISECONDS) : 0.071091 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.112767 #CONJOIN_DISJUNCTIVE : 34 #RENAME_VARIABLES : 76 #UNFREEZE : 0 #CONJOIN : 45 #PROJECTAWAY : 59 #ADD_WEAK_EQUALITY : 1 #DISJOIN : 6 #RENAME_VARIABLES_DISJUNCTIVE : 73 #ADD_EQUALITY : 9 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 1 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 13]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 13). Cancelled while BasicCegarLoop was analyzing trace of length 190 with TraceHistMax 32, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - TimeoutResultAtElement [Line: 15]: Timeout (TraceAbstraction) Unable to prove that array index is always in bounds (line 15). Cancelled while BasicCegarLoop was analyzing trace of length 190 with TraceHistMax 32, while TraceCheckSpWp was constructing forward predicates, while XnfDer was eliminating 1 quantified variables from 2 xjuncts. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 27 locations, 2 error locations. TIMEOUT Result, 48.5s OverallTime, 32 OverallIterations, 32 TraceHistogramMax, 7.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 491 SDtfs, 3720 SDslu, 4386 SDs, 0 SdLazy, 7185 SolverSat, 1162 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 12765 GetRequests, 11800 SyntacticMatches, 0 SemanticMatches, 965 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4065 ImplicationChecksByTransitivity, 14.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=190occurred in iteration=31, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.1s AbstIntTime, 1 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 31 MinimizatonAttempts, 1683 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 11.9s SatisfiabilityAnalysisTime, 18.7s InterpolantComputationTime, 9222 NumberOfCodeBlocks, 8694 NumberOfCodeBlocksAsserted, 445 NumberOfCheckSat, 15207 ConstructedInterpolants, 0 QuantifiedInterpolants, 4481453 SizeOfPredicates, 40 NumberOfNonLiveVariables, 8824 ConjunctsInSsa, 990 ConjunctsInUnsatCore, 147 InterpolantComputations, 2 PerfectInterpolantSequences, 35995/111515 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, REUSE_STATISTICS: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_smtcomp.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-25_06-28-53-180.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_smtcomp.epf_AutomizerC.xml/Csv-VPDomainBenchmark-0-2018-01-25_06-28-53-180.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_smtcomp.epf_AutomizerC.xml/Csv-BenchmarkWithCounters-0-2018-01-25_06-28-53-180.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array3_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Taipan+AI_EQ_smtcomp.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-25_06-28-53-180.csv Completed graceful shutdown