java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-industry-pattern/array_monotonic_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-30 00:25:03,847 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-30 00:25:03,848 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-30 00:25:03,857 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-30 00:25:03,858 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-30 00:25:03,859 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-30 00:25:03,860 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-30 00:25:03,863 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-30 00:25:03,864 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-30 00:25:03,865 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-30 00:25:03,865 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-30 00:25:03,865 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-30 00:25:03,866 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-30 00:25:03,867 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-30 00:25:03,867 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-30 00:25:03,870 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-30 00:25:03,871 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-30 00:25:03,872 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-30 00:25:03,873 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-30 00:25:03,874 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-30 00:25:03,876 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-30 00:25:03,879 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-30 00:25:03,884 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-30 00:25:03,884 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-30 00:25:03,885 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-30 00:25:03,885 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-30 00:25:03,885 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-30 00:25:03,885 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-30 00:25:03,885 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-30 00:25:03,886 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-30 00:25:03,886 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-30 00:25:03,887 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-30 00:25:03,887 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 00:25:03,887 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-30 00:25:03,888 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-30 00:25:03,889 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-30 00:25:03,889 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-30 00:25:03,907 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-30 00:25:03,913 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-30 00:25:03,915 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-30 00:25:03,916 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-30 00:25:03,916 INFO L276 PluginConnector]: CDTParser initialized [2018-01-30 00:25:03,916 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-industry-pattern/array_monotonic_true-unreach-call_true-termination.i [2018-01-30 00:25:03,980 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-30 00:25:03,981 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-01-30 00:25:03,982 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-30 00:25:03,982 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-30 00:25:03,985 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-30 00:25:03,986 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 12:25:03" (1/1) ... [2018-01-30 00:25:03,988 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@395107c2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:03, skipping insertion in model container [2018-01-30 00:25:03,988 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 12:25:03" (1/1) ... [2018-01-30 00:25:03,997 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 00:25:04,005 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 00:25:04,071 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 00:25:04,079 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 00:25:04,081 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04 WrapperNode [2018-01-30 00:25:04,081 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-30 00:25:04,082 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-30 00:25:04,082 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-30 00:25:04,082 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-30 00:25:04,090 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,090 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,095 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,095 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,096 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,098 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,098 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... [2018-01-30 00:25:04,099 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-30 00:25:04,099 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-30 00:25:04,099 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-30 00:25:04,099 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-30 00:25:04,100 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 00:25:04,141 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-30 00:25:04,141 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-30 00:25:04,141 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-30 00:25:04,141 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-30 00:25:04,141 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-30 00:25:04,141 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-30 00:25:04,142 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-30 00:25:04,142 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-30 00:25:04,142 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-30 00:25:04,142 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-30 00:25:04,329 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-30 00:25:04,330 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 12:25:04 BoogieIcfgContainer [2018-01-30 00:25:04,330 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-30 00:25:04,330 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-30 00:25:04,330 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-30 00:25:04,332 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-30 00:25:04,332 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 30.01 12:25:03" (1/3) ... [2018-01-30 00:25:04,333 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@702cfa20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 12:25:04, skipping insertion in model container [2018-01-30 00:25:04,333 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 12:25:04" (2/3) ... [2018-01-30 00:25:04,333 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@702cfa20 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 12:25:04, skipping insertion in model container [2018-01-30 00:25:04,333 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 12:25:04" (3/3) ... [2018-01-30 00:25:04,334 INFO L107 eAbstractionObserver]: Analyzing ICFG array_monotonic_true-unreach-call_true-termination.i [2018-01-30 00:25:04,339 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-30 00:25:04,343 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-30 00:25:04,366 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-30 00:25:04,366 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-30 00:25:04,366 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-30 00:25:04,366 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-30 00:25:04,367 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-30 00:25:04,367 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-30 00:25:04,367 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-30 00:25:04,367 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-30 00:25:04,367 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-30 00:25:04,376 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-01-30 00:25:04,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-30 00:25:04,379 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:04,380 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:04,380 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:04,382 INFO L82 PathProgramCache]: Analyzing trace with hash -384920621, now seen corresponding path program 1 times [2018-01-30 00:25:04,384 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:04,384 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:04,414 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:04,414 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:04,414 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:04,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:04,433 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:04,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:04,452 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 00:25:04,452 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-30 00:25:04,453 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-30 00:25:04,460 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-30 00:25:04,461 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 00:25:04,462 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 2 states. [2018-01-30 00:25:04,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:04,474 INFO L93 Difference]: Finished difference Result 48 states and 57 transitions. [2018-01-30 00:25:04,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-30 00:25:04,475 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-01-30 00:25:04,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:04,480 INFO L225 Difference]: With dead ends: 48 [2018-01-30 00:25:04,481 INFO L226 Difference]: Without dead ends: 28 [2018-01-30 00:25:04,484 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 00:25:04,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-01-30 00:25:04,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-01-30 00:25:04,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-01-30 00:25:04,507 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2018-01-30 00:25:04,508 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 17 [2018-01-30 00:25:04,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:04,509 INFO L432 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2018-01-30 00:25:04,509 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-30 00:25:04,509 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2018-01-30 00:25:04,510 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-01-30 00:25:04,510 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:04,510 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:04,510 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:04,511 INFO L82 PathProgramCache]: Analyzing trace with hash -2070763423, now seen corresponding path program 1 times [2018-01-30 00:25:04,511 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:04,511 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:04,511 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:04,512 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:04,512 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:04,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:04,518 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:04,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:04,584 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 00:25:04,584 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-30 00:25:04,585 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-30 00:25:04,585 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-30 00:25:04,585 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 00:25:04,586 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand 3 states. [2018-01-30 00:25:04,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:04,780 INFO L93 Difference]: Finished difference Result 53 states and 63 transitions. [2018-01-30 00:25:04,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-30 00:25:04,780 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2018-01-30 00:25:04,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:04,782 INFO L225 Difference]: With dead ends: 53 [2018-01-30 00:25:04,782 INFO L226 Difference]: Without dead ends: 41 [2018-01-30 00:25:04,782 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 00:25:04,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-01-30 00:25:04,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 30. [2018-01-30 00:25:04,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-01-30 00:25:04,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2018-01-30 00:25:04,788 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 18 [2018-01-30 00:25:04,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:04,788 INFO L432 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2018-01-30 00:25:04,788 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-30 00:25:04,788 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2018-01-30 00:25:04,789 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-30 00:25:04,789 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:04,789 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:04,789 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:04,789 INFO L82 PathProgramCache]: Analyzing trace with hash -1062128952, now seen corresponding path program 1 times [2018-01-30 00:25:04,789 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:04,789 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:04,790 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:04,790 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:04,790 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:04,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:04,857 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:04,883 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:04,884 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:04,884 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:04,890 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:04,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:04,907 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:04,919 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:04,935 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:04,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-30 00:25:04,936 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-30 00:25:04,936 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-30 00:25:04,936 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 00:25:04,936 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand 4 states. [2018-01-30 00:25:05,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:05,105 INFO L93 Difference]: Finished difference Result 66 states and 79 transitions. [2018-01-30 00:25:05,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-30 00:25:05,105 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-01-30 00:25:05,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:05,106 INFO L225 Difference]: With dead ends: 66 [2018-01-30 00:25:05,106 INFO L226 Difference]: Without dead ends: 54 [2018-01-30 00:25:05,106 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 00:25:05,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-30 00:25:05,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 38. [2018-01-30 00:25:05,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-30 00:25:05,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 43 transitions. [2018-01-30 00:25:05,110 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 43 transitions. Word has length 25 [2018-01-30 00:25:05,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:05,110 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 43 transitions. [2018-01-30 00:25:05,110 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-30 00:25:05,110 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 43 transitions. [2018-01-30 00:25:05,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-30 00:25:05,111 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:05,111 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:05,111 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:05,111 INFO L82 PathProgramCache]: Analyzing trace with hash 1956411009, now seen corresponding path program 2 times [2018-01-30 00:25:05,111 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:05,111 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:05,112 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:05,112 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:05,112 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:05,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:05,120 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:05,163 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:05,164 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:05,164 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:05,174 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:05,180 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:05,187 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:05,188 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:05,189 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:05,193 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:05,210 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:05,210 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-30 00:25:05,210 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-30 00:25:05,210 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-30 00:25:05,210 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 00:25:05,210 INFO L87 Difference]: Start difference. First operand 38 states and 43 transitions. Second operand 5 states. [2018-01-30 00:25:05,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:05,393 INFO L93 Difference]: Finished difference Result 79 states and 95 transitions. [2018-01-30 00:25:05,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-30 00:25:05,393 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 32 [2018-01-30 00:25:05,393 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:05,394 INFO L225 Difference]: With dead ends: 79 [2018-01-30 00:25:05,394 INFO L226 Difference]: Without dead ends: 67 [2018-01-30 00:25:05,394 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 00:25:05,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-30 00:25:05,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 46. [2018-01-30 00:25:05,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-30 00:25:05,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2018-01-30 00:25:05,398 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 32 [2018-01-30 00:25:05,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:05,398 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2018-01-30 00:25:05,398 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-30 00:25:05,398 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2018-01-30 00:25:05,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-01-30 00:25:05,399 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:05,399 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:05,399 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:05,399 INFO L82 PathProgramCache]: Analyzing trace with hash -1832304472, now seen corresponding path program 3 times [2018-01-30 00:25:05,399 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:05,399 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:05,400 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:05,400 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:05,400 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:05,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:05,407 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:05,494 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:05,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:05,494 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:05,512 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:05,520 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:05,523 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:05,525 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:05,526 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:05,527 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:05,528 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:05,532 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:05,549 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:05,549 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-30 00:25:05,549 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-30 00:25:05,550 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-30 00:25:05,550 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 00:25:05,550 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand 6 states. [2018-01-30 00:25:05,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:05,627 INFO L93 Difference]: Finished difference Result 92 states and 111 transitions. [2018-01-30 00:25:05,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-30 00:25:05,627 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-01-30 00:25:05,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:05,628 INFO L225 Difference]: With dead ends: 92 [2018-01-30 00:25:05,628 INFO L226 Difference]: Without dead ends: 80 [2018-01-30 00:25:05,628 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 00:25:05,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-30 00:25:05,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 54. [2018-01-30 00:25:05,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-30 00:25:05,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 61 transitions. [2018-01-30 00:25:05,633 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 61 transitions. Word has length 39 [2018-01-30 00:25:05,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:05,633 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 61 transitions. [2018-01-30 00:25:05,633 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-30 00:25:05,633 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 61 transitions. [2018-01-30 00:25:05,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-30 00:25:05,634 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:05,634 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:05,634 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:05,634 INFO L82 PathProgramCache]: Analyzing trace with hash -338490207, now seen corresponding path program 4 times [2018-01-30 00:25:05,634 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:05,634 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:05,635 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:05,635 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:05,635 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:05,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:05,642 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:05,738 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:05,739 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:05,739 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 00:25:05,747 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:05,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:05,767 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:05,860 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:05,861 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:05,896 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:05,896 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 00:25:05,921 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:05,923 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:05,924 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:05,931 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:05,931 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:05,999 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:06,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:06,001 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:06,051 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:06,052 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:06,091 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:06,092 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:06,092 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:06,105 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:06,105 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 00:25:06,120 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 15 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:06,136 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:06,136 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-01-30 00:25:06,137 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-30 00:25:06,137 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-30 00:25:06,137 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-01-30 00:25:06,137 INFO L87 Difference]: Start difference. First operand 54 states and 61 transitions. Second operand 13 states. [2018-01-30 00:25:06,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:06,527 INFO L93 Difference]: Finished difference Result 176 states and 216 transitions. [2018-01-30 00:25:06,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-30 00:25:06,527 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 46 [2018-01-30 00:25:06,527 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:06,528 INFO L225 Difference]: With dead ends: 176 [2018-01-30 00:25:06,528 INFO L226 Difference]: Without dead ends: 164 [2018-01-30 00:25:06,528 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=83, Invalid=189, Unknown=0, NotChecked=0, Total=272 [2018-01-30 00:25:06,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-01-30 00:25:06,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 101. [2018-01-30 00:25:06,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-01-30 00:25:06,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 114 transitions. [2018-01-30 00:25:06,534 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 114 transitions. Word has length 46 [2018-01-30 00:25:06,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:06,535 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 114 transitions. [2018-01-30 00:25:06,535 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-30 00:25:06,535 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 114 transitions. [2018-01-30 00:25:06,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-30 00:25:06,535 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:06,535 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:06,536 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:06,536 INFO L82 PathProgramCache]: Analyzing trace with hash -2010395986, now seen corresponding path program 1 times [2018-01-30 00:25:06,536 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:06,536 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:06,536 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:06,536 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:06,536 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:06,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:06,545 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:06,632 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:06,632 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:06,632 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:06,636 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:06,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:06,644 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:06,649 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:06,665 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:06,665 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-30 00:25:06,666 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-30 00:25:06,666 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-30 00:25:06,666 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 00:25:06,666 INFO L87 Difference]: Start difference. First operand 101 states and 114 transitions. Second operand 8 states. [2018-01-30 00:25:06,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:06,762 INFO L93 Difference]: Finished difference Result 175 states and 208 transitions. [2018-01-30 00:25:06,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-30 00:25:06,763 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 54 [2018-01-30 00:25:06,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:06,764 INFO L225 Difference]: With dead ends: 175 [2018-01-30 00:25:06,764 INFO L226 Difference]: Without dead ends: 159 [2018-01-30 00:25:06,764 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 00:25:06,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-01-30 00:25:06,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 117. [2018-01-30 00:25:06,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-01-30 00:25:06,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 132 transitions. [2018-01-30 00:25:06,770 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 132 transitions. Word has length 54 [2018-01-30 00:25:06,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:06,770 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 132 transitions. [2018-01-30 00:25:06,770 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-30 00:25:06,770 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 132 transitions. [2018-01-30 00:25:06,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-01-30 00:25:06,771 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:06,771 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:06,771 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:06,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1437093851, now seen corresponding path program 2 times [2018-01-30 00:25:06,771 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:06,771 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:06,772 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:06,772 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:06,772 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:06,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:06,780 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:06,845 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:06,845 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:06,845 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:06,849 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:06,853 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:06,872 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:06,876 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:06,877 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:06,882 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:06,898 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:06,899 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-30 00:25:06,899 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-30 00:25:06,899 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-30 00:25:06,899 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 00:25:06,899 INFO L87 Difference]: Start difference. First operand 117 states and 132 transitions. Second operand 9 states. [2018-01-30 00:25:07,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:07,085 INFO L93 Difference]: Finished difference Result 196 states and 233 transitions. [2018-01-30 00:25:07,085 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-30 00:25:07,085 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 61 [2018-01-30 00:25:07,085 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:07,086 INFO L225 Difference]: With dead ends: 196 [2018-01-30 00:25:07,086 INFO L226 Difference]: Without dead ends: 180 [2018-01-30 00:25:07,086 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 00:25:07,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-01-30 00:25:07,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 133. [2018-01-30 00:25:07,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-01-30 00:25:07,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 150 transitions. [2018-01-30 00:25:07,092 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 150 transitions. Word has length 61 [2018-01-30 00:25:07,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:07,093 INFO L432 AbstractCegarLoop]: Abstraction has 133 states and 150 transitions. [2018-01-30 00:25:07,093 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-30 00:25:07,093 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 150 transitions. [2018-01-30 00:25:07,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-30 00:25:07,094 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:07,094 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:07,094 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:07,094 INFO L82 PathProgramCache]: Analyzing trace with hash -477032946, now seen corresponding path program 3 times [2018-01-30 00:25:07,094 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:07,094 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:07,095 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:07,095 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:07,095 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:07,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:07,102 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:07,183 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 161 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:07,183 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:07,183 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:07,188 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:07,198 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,199 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,200 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,201 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,202 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,204 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,205 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:07,206 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:07,207 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:07,214 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:07,214 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:07,216 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:07,216 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 00:25:07,239 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 123 trivial. 0 not checked. [2018-01-30 00:25:07,256 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:07,256 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 15 [2018-01-30 00:25:07,256 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-30 00:25:07,256 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-30 00:25:07,256 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=137, Unknown=0, NotChecked=0, Total=210 [2018-01-30 00:25:07,256 INFO L87 Difference]: Start difference. First operand 133 states and 150 transitions. Second operand 15 states. [2018-01-30 00:25:07,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:07,522 INFO L93 Difference]: Finished difference Result 262 states and 320 transitions. [2018-01-30 00:25:07,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-30 00:25:07,523 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-01-30 00:25:07,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:07,523 INFO L225 Difference]: With dead ends: 262 [2018-01-30 00:25:07,523 INFO L226 Difference]: Without dead ends: 246 [2018-01-30 00:25:07,524 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=154, Invalid=352, Unknown=0, NotChecked=0, Total=506 [2018-01-30 00:25:07,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-30 00:25:07,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 157. [2018-01-30 00:25:07,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-01-30 00:25:07,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 177 transitions. [2018-01-30 00:25:07,530 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 177 transitions. Word has length 68 [2018-01-30 00:25:07,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:07,531 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 177 transitions. [2018-01-30 00:25:07,531 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-30 00:25:07,531 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 177 transitions. [2018-01-30 00:25:07,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-30 00:25:07,532 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:07,532 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:07,532 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:07,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1777182234, now seen corresponding path program 1 times [2018-01-30 00:25:07,532 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:07,532 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:07,532 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:07,533 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:07,533 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:07,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:07,541 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:07,689 INFO L134 CoverageAnalysis]: Checked inductivity of 215 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:07,690 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:07,690 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:07,697 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:07,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:07,711 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:07,719 INFO L134 CoverageAnalysis]: Checked inductivity of 215 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:07,735 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:07,736 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-30 00:25:07,736 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-30 00:25:07,736 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-30 00:25:07,736 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 00:25:07,736 INFO L87 Difference]: Start difference. First operand 157 states and 177 transitions. Second operand 11 states. [2018-01-30 00:25:07,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:07,878 INFO L93 Difference]: Finished difference Result 250 states and 295 transitions. [2018-01-30 00:25:07,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-30 00:25:07,879 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 78 [2018-01-30 00:25:07,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:07,880 INFO L225 Difference]: With dead ends: 250 [2018-01-30 00:25:07,880 INFO L226 Difference]: Without dead ends: 226 [2018-01-30 00:25:07,880 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 00:25:07,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-01-30 00:25:07,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 173. [2018-01-30 00:25:07,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-01-30 00:25:07,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 195 transitions. [2018-01-30 00:25:07,885 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 195 transitions. Word has length 78 [2018-01-30 00:25:07,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:07,885 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 195 transitions. [2018-01-30 00:25:07,885 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-30 00:25:07,885 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 195 transitions. [2018-01-30 00:25:07,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-30 00:25:07,886 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:07,886 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:07,886 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:07,886 INFO L82 PathProgramCache]: Analyzing trace with hash -488324095, now seen corresponding path program 2 times [2018-01-30 00:25:07,886 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:07,886 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:07,887 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:07,887 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:07,887 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:07,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:07,897 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:08,136 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 0 proven. 270 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:08,137 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:08,137 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:08,145 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:08,148 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:08,166 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:08,176 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:08,177 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:08,185 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 0 proven. 270 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:08,201 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:08,202 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-30 00:25:08,202 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-30 00:25:08,202 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-30 00:25:08,202 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 00:25:08,202 INFO L87 Difference]: Start difference. First operand 173 states and 195 transitions. Second operand 12 states. [2018-01-30 00:25:08,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:08,537 INFO L93 Difference]: Finished difference Result 271 states and 320 transitions. [2018-01-30 00:25:08,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-30 00:25:08,538 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-01-30 00:25:08,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:08,539 INFO L225 Difference]: With dead ends: 271 [2018-01-30 00:25:08,539 INFO L226 Difference]: Without dead ends: 247 [2018-01-30 00:25:08,539 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 00:25:08,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-01-30 00:25:08,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 189. [2018-01-30 00:25:08,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-01-30 00:25:08,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 213 transitions. [2018-01-30 00:25:08,545 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 213 transitions. Word has length 85 [2018-01-30 00:25:08,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:08,546 INFO L432 AbstractCegarLoop]: Abstraction has 189 states and 213 transitions. [2018-01-30 00:25:08,546 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-30 00:25:08,546 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 213 transitions. [2018-01-30 00:25:08,546 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-30 00:25:08,547 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:08,547 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:08,547 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:08,547 INFO L82 PathProgramCache]: Analyzing trace with hash -195918790, now seen corresponding path program 3 times [2018-01-30 00:25:08,547 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:08,547 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:08,547 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:08,548 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:08,548 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:08,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:08,554 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:08,638 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 335 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:08,638 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:08,638 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:08,646 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:08,651 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,652 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,653 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,654 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,655 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,656 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,658 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,659 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,661 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,663 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,665 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:08,665 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:08,666 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:08,679 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 335 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:08,696 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:08,696 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-30 00:25:08,696 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-30 00:25:08,697 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-30 00:25:08,697 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 00:25:08,697 INFO L87 Difference]: Start difference. First operand 189 states and 213 transitions. Second operand 13 states. [2018-01-30 00:25:08,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:08,906 INFO L93 Difference]: Finished difference Result 292 states and 345 transitions. [2018-01-30 00:25:08,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-30 00:25:08,907 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 92 [2018-01-30 00:25:08,907 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:08,907 INFO L225 Difference]: With dead ends: 292 [2018-01-30 00:25:08,908 INFO L226 Difference]: Without dead ends: 268 [2018-01-30 00:25:08,908 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 00:25:08,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states. [2018-01-30 00:25:08,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 205. [2018-01-30 00:25:08,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-01-30 00:25:08,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 231 transitions. [2018-01-30 00:25:08,913 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 231 transitions. Word has length 92 [2018-01-30 00:25:08,913 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:08,913 INFO L432 AbstractCegarLoop]: Abstraction has 205 states and 231 transitions. [2018-01-30 00:25:08,913 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-30 00:25:08,913 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 231 transitions. [2018-01-30 00:25:08,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-01-30 00:25:08,916 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:08,917 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 11, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:08,917 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:08,917 INFO L82 PathProgramCache]: Analyzing trace with hash -519061023, now seen corresponding path program 4 times [2018-01-30 00:25:08,917 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:08,917 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:08,917 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:08,917 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:08,917 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:08,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:08,925 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:09,025 INFO L134 CoverageAnalysis]: Checked inductivity of 410 backedges. 0 proven. 407 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:09,026 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:09,026 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:09,032 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 00:25:09,047 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:09,049 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:09,099 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:09,099 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,152 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,152 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 00:25:09,275 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,276 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,276 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,280 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,281 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,294 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,295 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,296 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,299 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,300 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,324 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,325 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,325 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,338 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,338 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,354 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,355 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,355 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,359 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,359 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,374 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,375 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,375 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,380 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,380 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,417 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,418 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,432 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,432 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,468 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,469 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,469 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,472 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,473 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,488 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,489 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,489 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,500 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,501 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:09,533 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:09,534 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:09,534 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,537 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:09,537 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 00:25:09,562 INFO L134 CoverageAnalysis]: Checked inductivity of 410 backedges. 228 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:09,579 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:09,579 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 16] total 28 [2018-01-30 00:25:09,580 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-30 00:25:09,580 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-30 00:25:09,580 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=542, Unknown=0, NotChecked=0, Total=756 [2018-01-30 00:25:09,580 INFO L87 Difference]: Start difference. First operand 205 states and 231 transitions. Second operand 28 states. [2018-01-30 00:25:10,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:10,278 INFO L93 Difference]: Finished difference Result 560 states and 668 transitions. [2018-01-30 00:25:10,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-30 00:25:10,278 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 99 [2018-01-30 00:25:10,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:10,279 INFO L225 Difference]: With dead ends: 560 [2018-01-30 00:25:10,279 INFO L226 Difference]: Without dead ends: 536 [2018-01-30 00:25:10,280 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 85 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 391 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=354, Invalid=1052, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 00:25:10,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 536 states. [2018-01-30 00:25:10,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 536 to 397. [2018-01-30 00:25:10,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 397 states. [2018-01-30 00:25:10,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 397 states and 449 transitions. [2018-01-30 00:25:10,289 INFO L78 Accepts]: Start accepts. Automaton has 397 states and 449 transitions. Word has length 99 [2018-01-30 00:25:10,289 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:10,289 INFO L432 AbstractCegarLoop]: Abstraction has 397 states and 449 transitions. [2018-01-30 00:25:10,289 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-30 00:25:10,289 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 449 transitions. [2018-01-30 00:25:10,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-30 00:25:10,291 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:10,291 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 11, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:10,291 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:10,291 INFO L82 PathProgramCache]: Analyzing trace with hash 1024940590, now seen corresponding path program 1 times [2018-01-30 00:25:10,291 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:10,291 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:10,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:10,292 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:10,292 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:10,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:10,298 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:10,430 INFO L134 CoverageAnalysis]: Checked inductivity of 489 backedges. 0 proven. 486 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:10,430 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:10,430 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:10,435 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:10,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:10,449 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:10,458 INFO L134 CoverageAnalysis]: Checked inductivity of 489 backedges. 0 proven. 486 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:10,475 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:10,475 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-30 00:25:10,475 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-30 00:25:10,475 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-30 00:25:10,475 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 00:25:10,475 INFO L87 Difference]: Start difference. First operand 397 states and 449 transitions. Second operand 15 states. [2018-01-30 00:25:10,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:10,681 INFO L93 Difference]: Finished difference Result 551 states and 644 transitions. [2018-01-30 00:25:10,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-30 00:25:10,682 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 107 [2018-01-30 00:25:10,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:10,683 INFO L225 Difference]: With dead ends: 551 [2018-01-30 00:25:10,683 INFO L226 Difference]: Without dead ends: 517 [2018-01-30 00:25:10,683 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 00:25:10,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-01-30 00:25:10,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 429. [2018-01-30 00:25:10,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 429 states. [2018-01-30 00:25:10,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 485 transitions. [2018-01-30 00:25:10,691 INFO L78 Accepts]: Start accepts. Automaton has 429 states and 485 transitions. Word has length 107 [2018-01-30 00:25:10,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:10,691 INFO L432 AbstractCegarLoop]: Abstraction has 429 states and 485 transitions. [2018-01-30 00:25:10,691 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-30 00:25:10,691 INFO L276 IsEmpty]: Start isEmpty. Operand 429 states and 485 transitions. [2018-01-30 00:25:10,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-01-30 00:25:10,692 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:10,692 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 13, 12, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:10,692 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:10,692 INFO L82 PathProgramCache]: Analyzing trace with hash 1354764653, now seen corresponding path program 2 times [2018-01-30 00:25:10,692 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:10,692 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:10,693 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:10,693 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:10,693 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:10,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:10,698 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:10,814 INFO L134 CoverageAnalysis]: Checked inductivity of 575 backedges. 0 proven. 572 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:10,814 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:10,814 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:10,827 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:10,831 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:10,837 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:10,838 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:10,839 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:10,850 INFO L134 CoverageAnalysis]: Checked inductivity of 575 backedges. 0 proven. 572 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:10,867 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:10,867 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-30 00:25:10,867 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-30 00:25:10,867 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-30 00:25:10,867 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 00:25:10,867 INFO L87 Difference]: Start difference. First operand 429 states and 485 transitions. Second operand 16 states. [2018-01-30 00:25:11,635 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:11,635 INFO L93 Difference]: Finished difference Result 588 states and 687 transitions. [2018-01-30 00:25:11,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-30 00:25:11,636 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 114 [2018-01-30 00:25:11,636 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:11,637 INFO L225 Difference]: With dead ends: 588 [2018-01-30 00:25:11,637 INFO L226 Difference]: Without dead ends: 554 [2018-01-30 00:25:11,638 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 00:25:11,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states. [2018-01-30 00:25:11,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 461. [2018-01-30 00:25:11,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-01-30 00:25:11,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 521 transitions. [2018-01-30 00:25:11,661 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 521 transitions. Word has length 114 [2018-01-30 00:25:11,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:11,661 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 521 transitions. [2018-01-30 00:25:11,661 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-30 00:25:11,661 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 521 transitions. [2018-01-30 00:25:11,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-30 00:25:11,662 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:11,662 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 14, 13, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:11,662 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:11,663 INFO L82 PathProgramCache]: Analyzing trace with hash -678066866, now seen corresponding path program 3 times [2018-01-30 00:25:11,663 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:11,663 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:11,663 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:11,663 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:11,663 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:11,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:11,670 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:12,072 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 0 proven. 665 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 00:25:12,072 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:12,072 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:12,076 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:12,084 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,087 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,089 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,090 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,092 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,103 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:12,104 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:12,106 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:12,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:12,122 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:12,139 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:12,139 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 00:25:12,232 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 498 trivial. 0 not checked. [2018-01-30 00:25:12,248 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:12,248 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 9] total 24 [2018-01-30 00:25:12,249 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-30 00:25:12,249 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-30 00:25:12,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=340, Unknown=0, NotChecked=0, Total=552 [2018-01-30 00:25:12,249 INFO L87 Difference]: Start difference. First operand 461 states and 521 transitions. Second operand 24 states. [2018-01-30 00:25:13,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:13,403 INFO L93 Difference]: Finished difference Result 700 states and 834 transitions. [2018-01-30 00:25:13,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-30 00:25:13,403 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 121 [2018-01-30 00:25:13,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:13,405 INFO L225 Difference]: With dead ends: 700 [2018-01-30 00:25:13,405 INFO L226 Difference]: Without dead ends: 666 [2018-01-30 00:25:13,405 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 312 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=450, Invalid=956, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 00:25:13,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666 states. [2018-01-30 00:25:13,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666 to 505. [2018-01-30 00:25:13,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 505 states. [2018-01-30 00:25:13,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 505 states to 505 states and 570 transitions. [2018-01-30 00:25:13,425 INFO L78 Accepts]: Start accepts. Automaton has 505 states and 570 transitions. Word has length 121 [2018-01-30 00:25:13,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:13,426 INFO L432 AbstractCegarLoop]: Abstraction has 505 states and 570 transitions. [2018-01-30 00:25:13,426 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-30 00:25:13,426 INFO L276 IsEmpty]: Start isEmpty. Operand 505 states and 570 transitions. [2018-01-30 00:25:13,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-01-30 00:25:13,427 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:13,427 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 15, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:13,427 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:13,427 INFO L82 PathProgramCache]: Analyzing trace with hash 1069882074, now seen corresponding path program 5 times [2018-01-30 00:25:13,427 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:13,427 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:13,428 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:13,428 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:13,428 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:13,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:13,445 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:13,613 INFO L134 CoverageAnalysis]: Checked inductivity of 775 backedges. 0 proven. 765 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:13,613 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:13,613 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:13,618 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 00:25:13,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,629 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,630 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,631 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,632 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,633 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,634 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,636 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,637 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,639 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,646 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,648 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,651 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,656 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:13,657 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:13,658 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:13,669 INFO L134 CoverageAnalysis]: Checked inductivity of 775 backedges. 0 proven. 765 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:13,686 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:13,686 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-30 00:25:13,687 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-30 00:25:13,687 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-30 00:25:13,687 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 00:25:13,687 INFO L87 Difference]: Start difference. First operand 505 states and 570 transitions. Second operand 18 states. [2018-01-30 00:25:13,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:13,989 INFO L93 Difference]: Finished difference Result 678 states and 789 transitions. [2018-01-30 00:25:13,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-30 00:25:13,989 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 131 [2018-01-30 00:25:13,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:13,990 INFO L225 Difference]: With dead ends: 678 [2018-01-30 00:25:13,991 INFO L226 Difference]: Without dead ends: 632 [2018-01-30 00:25:13,991 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 00:25:13,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 632 states. [2018-01-30 00:25:13,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 632 to 537. [2018-01-30 00:25:13,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-01-30 00:25:13,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 606 transitions. [2018-01-30 00:25:13,999 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 606 transitions. Word has length 131 [2018-01-30 00:25:14,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:14,000 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 606 transitions. [2018-01-30 00:25:14,000 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-30 00:25:14,000 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 606 transitions. [2018-01-30 00:25:14,001 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-30 00:25:14,001 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:14,001 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 16, 16, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:14,001 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:14,001 INFO L82 PathProgramCache]: Analyzing trace with hash -1621794989, now seen corresponding path program 6 times [2018-01-30 00:25:14,001 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:14,001 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:14,002 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:14,002 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:14,002 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:14,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:14,008 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:14,365 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 872 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:14,365 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:14,366 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:14,370 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 00:25:14,374 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,377 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,379 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,380 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,381 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,383 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,384 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,386 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,389 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,391 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,393 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,395 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:14,400 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:14,401 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:14,414 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 872 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:14,431 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:14,431 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-30 00:25:14,431 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-30 00:25:14,431 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-30 00:25:14,431 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 00:25:14,431 INFO L87 Difference]: Start difference. First operand 537 states and 606 transitions. Second operand 19 states. [2018-01-30 00:25:14,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:14,582 INFO L93 Difference]: Finished difference Result 715 states and 832 transitions. [2018-01-30 00:25:14,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-30 00:25:14,583 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 138 [2018-01-30 00:25:14,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:14,584 INFO L225 Difference]: With dead ends: 715 [2018-01-30 00:25:14,584 INFO L226 Difference]: Without dead ends: 669 [2018-01-30 00:25:14,585 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 00:25:14,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 669 states. [2018-01-30 00:25:14,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 669 to 569. [2018-01-30 00:25:14,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. [2018-01-30 00:25:14,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 642 transitions. [2018-01-30 00:25:14,592 INFO L78 Accepts]: Start accepts. Automaton has 569 states and 642 transitions. Word has length 138 [2018-01-30 00:25:14,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:14,592 INFO L432 AbstractCegarLoop]: Abstraction has 569 states and 642 transitions. [2018-01-30 00:25:14,592 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-30 00:25:14,592 INFO L276 IsEmpty]: Start isEmpty. Operand 569 states and 642 transitions. [2018-01-30 00:25:14,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-01-30 00:25:14,593 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:14,593 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 17, 17, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:14,593 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:14,593 INFO L82 PathProgramCache]: Analyzing trace with hash -2028023622, now seen corresponding path program 7 times [2018-01-30 00:25:14,593 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:14,593 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:14,594 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:14,594 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:14,594 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:14,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:14,600 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:14,805 INFO L134 CoverageAnalysis]: Checked inductivity of 996 backedges. 0 proven. 986 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:14,806 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:14,806 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:14,810 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:14,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:14,824 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:14,837 INFO L134 CoverageAnalysis]: Checked inductivity of 996 backedges. 0 proven. 986 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:14,853 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:14,853 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-30 00:25:14,854 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-30 00:25:14,854 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-30 00:25:14,854 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 00:25:14,854 INFO L87 Difference]: Start difference. First operand 569 states and 642 transitions. Second operand 20 states. [2018-01-30 00:25:15,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:15,569 INFO L93 Difference]: Finished difference Result 752 states and 875 transitions. [2018-01-30 00:25:15,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-30 00:25:15,569 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 145 [2018-01-30 00:25:15,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:15,570 INFO L225 Difference]: With dead ends: 752 [2018-01-30 00:25:15,571 INFO L226 Difference]: Without dead ends: 706 [2018-01-30 00:25:15,571 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 146 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 00:25:15,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states. [2018-01-30 00:25:15,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 601. [2018-01-30 00:25:15,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 601 states. [2018-01-30 00:25:15,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 601 states to 601 states and 678 transitions. [2018-01-30 00:25:15,578 INFO L78 Accepts]: Start accepts. Automaton has 601 states and 678 transitions. Word has length 145 [2018-01-30 00:25:15,579 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:15,579 INFO L432 AbstractCegarLoop]: Abstraction has 601 states and 678 transitions. [2018-01-30 00:25:15,579 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-30 00:25:15,579 INFO L276 IsEmpty]: Start isEmpty. Operand 601 states and 678 transitions. [2018-01-30 00:25:15,580 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-30 00:25:15,580 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:15,580 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 18, 18, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:15,580 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:15,580 INFO L82 PathProgramCache]: Analyzing trace with hash 731729267, now seen corresponding path program 8 times [2018-01-30 00:25:15,580 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:15,580 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:15,581 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:15,581 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:15,581 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:15,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:15,587 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:15,825 INFO L134 CoverageAnalysis]: Checked inductivity of 1117 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:15,825 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:15,825 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:15,830 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:15,834 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:15,842 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:15,843 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:15,845 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:15,858 INFO L134 CoverageAnalysis]: Checked inductivity of 1117 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:15,875 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:15,875 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-30 00:25:15,876 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-30 00:25:15,876 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-30 00:25:15,876 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 00:25:15,876 INFO L87 Difference]: Start difference. First operand 601 states and 678 transitions. Second operand 21 states. [2018-01-30 00:25:16,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:16,081 INFO L93 Difference]: Finished difference Result 789 states and 918 transitions. [2018-01-30 00:25:16,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-30 00:25:16,082 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 152 [2018-01-30 00:25:16,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:16,083 INFO L225 Difference]: With dead ends: 789 [2018-01-30 00:25:16,083 INFO L226 Difference]: Without dead ends: 743 [2018-01-30 00:25:16,084 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 00:25:16,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 743 states. [2018-01-30 00:25:16,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 743 to 633. [2018-01-30 00:25:16,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 633 states. [2018-01-30 00:25:16,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 714 transitions. [2018-01-30 00:25:16,091 INFO L78 Accepts]: Start accepts. Automaton has 633 states and 714 transitions. Word has length 152 [2018-01-30 00:25:16,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:16,091 INFO L432 AbstractCegarLoop]: Abstraction has 633 states and 714 transitions. [2018-01-30 00:25:16,091 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-30 00:25:16,092 INFO L276 IsEmpty]: Start isEmpty. Operand 633 states and 714 transitions. [2018-01-30 00:25:16,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-01-30 00:25:16,093 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:16,093 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 19, 19, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:16,093 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:16,093 INFO L82 PathProgramCache]: Analyzing trace with hash 1087684250, now seen corresponding path program 9 times [2018-01-30 00:25:16,093 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:16,093 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:16,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:16,094 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:16,094 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:16,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:16,100 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:16,295 INFO L134 CoverageAnalysis]: Checked inductivity of 1245 backedges. 0 proven. 1235 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:16,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:16,295 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:16,301 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:16,305 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,306 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,307 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,308 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,310 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,311 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,312 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,313 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,315 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,317 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,319 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,321 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,323 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,326 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,328 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,331 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,334 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,338 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,342 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,346 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:16,346 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:16,348 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:16,363 INFO L134 CoverageAnalysis]: Checked inductivity of 1245 backedges. 0 proven. 1235 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:16,380 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:16,380 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-30 00:25:16,380 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-30 00:25:16,380 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-30 00:25:16,380 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 00:25:16,380 INFO L87 Difference]: Start difference. First operand 633 states and 714 transitions. Second operand 22 states. [2018-01-30 00:25:16,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:16,559 INFO L93 Difference]: Finished difference Result 826 states and 961 transitions. [2018-01-30 00:25:16,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-30 00:25:16,559 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 159 [2018-01-30 00:25:16,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:16,561 INFO L225 Difference]: With dead ends: 826 [2018-01-30 00:25:16,561 INFO L226 Difference]: Without dead ends: 780 [2018-01-30 00:25:16,562 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 180 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 00:25:16,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 780 states. [2018-01-30 00:25:16,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 780 to 665. [2018-01-30 00:25:16,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-01-30 00:25:16,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 750 transitions. [2018-01-30 00:25:16,569 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 750 transitions. Word has length 159 [2018-01-30 00:25:16,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:16,569 INFO L432 AbstractCegarLoop]: Abstraction has 665 states and 750 transitions. [2018-01-30 00:25:16,569 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-30 00:25:16,569 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 750 transitions. [2018-01-30 00:25:16,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-30 00:25:16,570 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:16,570 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:16,570 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:16,570 INFO L82 PathProgramCache]: Analyzing trace with hash 1742341011, now seen corresponding path program 10 times [2018-01-30 00:25:16,570 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:16,571 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:16,571 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:16,571 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:16,571 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:16,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:16,577 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:16,825 INFO L134 CoverageAnalysis]: Checked inductivity of 1380 backedges. 0 proven. 1370 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:16,825 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:16,825 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:16,834 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 00:25:16,846 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:16,848 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:16,857 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:16,858 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,860 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,860 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 00:25:16,879 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:16,879 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:16,880 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,915 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,915 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:16,927 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:16,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:16,929 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,935 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,936 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:16,969 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:16,970 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:16,970 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,974 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,974 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:16,986 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:16,987 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:16,987 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,991 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:16,991 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,007 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,008 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,011 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,011 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,026 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,027 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,027 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,031 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,031 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,052 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,053 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,060 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,060 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,075 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,075 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,076 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,079 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,079 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,094 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,095 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,095 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,099 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,099 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,118 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,119 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,119 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,123 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,123 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,140 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,141 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,141 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,145 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,145 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,163 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,163 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,164 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,167 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,167 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,185 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,186 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,186 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,189 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,190 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,209 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,210 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,210 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,213 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,214 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,233 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,234 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,235 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,238 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,238 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,274 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,275 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,275 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,278 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,279 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:17,645 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:17,646 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:17,646 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,650 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:17,650 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 00:25:17,718 INFO L134 CoverageAnalysis]: Checked inductivity of 1380 backedges. 904 proven. 476 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:17,734 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:17,734 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 26] total 47 [2018-01-30 00:25:17,735 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-30 00:25:17,735 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-30 00:25:17,735 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=580, Invalid=1582, Unknown=0, NotChecked=0, Total=2162 [2018-01-30 00:25:17,735 INFO L87 Difference]: Start difference. First operand 665 states and 750 transitions. Second operand 47 states. [2018-01-30 00:25:19,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:19,095 INFO L93 Difference]: Finished difference Result 1602 states and 1872 transitions. [2018-01-30 00:25:19,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-30 00:25:19,097 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 166 [2018-01-30 00:25:19,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:19,100 INFO L225 Difference]: With dead ends: 1602 [2018-01-30 00:25:19,100 INFO L226 Difference]: Without dead ends: 1556 [2018-01-30 00:25:19,101 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 142 SyntacticMatches, 1 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1165 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=976, Invalid=3184, Unknown=0, NotChecked=0, Total=4160 [2018-01-30 00:25:19,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1556 states. [2018-01-30 00:25:19,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1556 to 1309. [2018-01-30 00:25:19,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1309 states. [2018-01-30 00:25:19,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1309 states to 1309 states and 1480 transitions. [2018-01-30 00:25:19,136 INFO L78 Accepts]: Start accepts. Automaton has 1309 states and 1480 transitions. Word has length 166 [2018-01-30 00:25:19,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:19,146 INFO L432 AbstractCegarLoop]: Abstraction has 1309 states and 1480 transitions. [2018-01-30 00:25:19,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-30 00:25:19,146 INFO L276 IsEmpty]: Start isEmpty. Operand 1309 states and 1480 transitions. [2018-01-30 00:25:19,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-30 00:25:19,147 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:19,147 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 21, 20, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:19,148 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:19,148 INFO L82 PathProgramCache]: Analyzing trace with hash -1558521504, now seen corresponding path program 4 times [2018-01-30 00:25:19,148 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:19,148 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:19,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:19,148 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:19,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:19,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:19,156 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:20,026 INFO L134 CoverageAnalysis]: Checked inductivity of 1522 backedges. 0 proven. 1512 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:20,026 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:20,026 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:20,030 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 00:25:20,052 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:20,054 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:20,070 INFO L134 CoverageAnalysis]: Checked inductivity of 1522 backedges. 0 proven. 1512 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:20,087 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:20,087 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-30 00:25:20,088 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-30 00:25:20,088 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-30 00:25:20,088 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 00:25:20,088 INFO L87 Difference]: Start difference. First operand 1309 states and 1480 transitions. Second operand 24 states. [2018-01-30 00:25:20,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:20,346 INFO L93 Difference]: Finished difference Result 1599 states and 1846 transitions. [2018-01-30 00:25:20,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-30 00:25:20,346 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 174 [2018-01-30 00:25:20,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:20,349 INFO L225 Difference]: With dead ends: 1599 [2018-01-30 00:25:20,349 INFO L226 Difference]: Without dead ends: 1529 [2018-01-30 00:25:20,350 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 197 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 00:25:20,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1529 states. [2018-01-30 00:25:20,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1529 to 1373. [2018-01-30 00:25:20,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1373 states. [2018-01-30 00:25:20,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1373 states to 1373 states and 1552 transitions. [2018-01-30 00:25:20,367 INFO L78 Accepts]: Start accepts. Automaton has 1373 states and 1552 transitions. Word has length 174 [2018-01-30 00:25:20,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:20,368 INFO L432 AbstractCegarLoop]: Abstraction has 1373 states and 1552 transitions. [2018-01-30 00:25:20,368 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-30 00:25:20,368 INFO L276 IsEmpty]: Start isEmpty. Operand 1373 states and 1552 transitions. [2018-01-30 00:25:20,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-01-30 00:25:20,369 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:20,369 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 22, 21, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:20,369 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:20,369 INFO L82 PathProgramCache]: Analyzing trace with hash 1099652621, now seen corresponding path program 5 times [2018-01-30 00:25:20,369 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:20,369 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:20,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:20,370 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:20,370 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:20,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:20,378 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:20,653 INFO L134 CoverageAnalysis]: Checked inductivity of 1671 backedges. 0 proven. 1661 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:20,653 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:20,653 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:20,657 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 00:25:20,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,662 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,664 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,666 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,668 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,670 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,672 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,674 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,676 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,681 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,683 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,686 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,694 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,698 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,707 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,713 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,720 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:20,721 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:20,722 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:20,740 INFO L134 CoverageAnalysis]: Checked inductivity of 1671 backedges. 0 proven. 1661 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:20,757 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:20,757 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-30 00:25:20,757 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-30 00:25:20,758 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-30 00:25:20,758 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 00:25:20,758 INFO L87 Difference]: Start difference. First operand 1373 states and 1552 transitions. Second operand 25 states. [2018-01-30 00:25:20,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:20,989 INFO L93 Difference]: Finished difference Result 1668 states and 1925 transitions. [2018-01-30 00:25:20,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-30 00:25:20,989 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 181 [2018-01-30 00:25:20,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:20,992 INFO L225 Difference]: With dead ends: 1668 [2018-01-30 00:25:20,992 INFO L226 Difference]: Without dead ends: 1598 [2018-01-30 00:25:20,992 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 205 GetRequests, 182 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 00:25:20,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1598 states. [2018-01-30 00:25:21,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1598 to 1437. [2018-01-30 00:25:21,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1437 states. [2018-01-30 00:25:21,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1437 states to 1437 states and 1624 transitions. [2018-01-30 00:25:21,008 INFO L78 Accepts]: Start accepts. Automaton has 1437 states and 1624 transitions. Word has length 181 [2018-01-30 00:25:21,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:21,008 INFO L432 AbstractCegarLoop]: Abstraction has 1437 states and 1624 transitions. [2018-01-30 00:25:21,008 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-30 00:25:21,009 INFO L276 IsEmpty]: Start isEmpty. Operand 1437 states and 1624 transitions. [2018-01-30 00:25:21,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-01-30 00:25:21,010 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:21,010 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 23, 22, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:21,010 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:21,010 INFO L82 PathProgramCache]: Analyzing trace with hash -748049216, now seen corresponding path program 6 times [2018-01-30 00:25:21,010 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:21,010 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:21,011 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:21,011 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:21,011 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:21,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:21,017 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:21,646 INFO L134 CoverageAnalysis]: Checked inductivity of 1827 backedges. 0 proven. 1817 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 00:25:21,646 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:21,646 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:21,650 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 00:25:21,655 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,658 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,659 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,660 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,661 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,662 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,663 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,664 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,666 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,667 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,669 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,670 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,672 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,674 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,676 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,678 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,680 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,682 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,685 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,688 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:21,688 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:21,690 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:21,716 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:21,716 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:21,739 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:21,739 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 00:25:21,838 INFO L134 CoverageAnalysis]: Checked inductivity of 1827 backedges. 0 proven. 437 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-01-30 00:25:21,855 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:21,856 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 11] total 35 [2018-01-30 00:25:21,856 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-30 00:25:21,856 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-30 00:25:21,856 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=487, Invalid=703, Unknown=0, NotChecked=0, Total=1190 [2018-01-30 00:25:21,856 INFO L87 Difference]: Start difference. First operand 1437 states and 1624 transitions. Second operand 35 states. [2018-01-30 00:25:22,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:22,734 INFO L93 Difference]: Finished difference Result 1852 states and 2164 transitions. [2018-01-30 00:25:22,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-30 00:25:22,734 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 188 [2018-01-30 00:25:22,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:22,737 INFO L225 Difference]: With dead ends: 1852 [2018-01-30 00:25:22,737 INFO L226 Difference]: Without dead ends: 1782 [2018-01-30 00:25:22,738 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 180 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 726 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1058, Invalid=2134, Unknown=0, NotChecked=0, Total=3192 [2018-01-30 00:25:22,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1782 states. [2018-01-30 00:25:22,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1782 to 1517. [2018-01-30 00:25:22,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1517 states. [2018-01-30 00:25:22,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1517 states to 1517 states and 1713 transitions. [2018-01-30 00:25:22,754 INFO L78 Accepts]: Start accepts. Automaton has 1517 states and 1713 transitions. Word has length 188 [2018-01-30 00:25:22,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:22,755 INFO L432 AbstractCegarLoop]: Abstraction has 1517 states and 1713 transitions. [2018-01-30 00:25:22,755 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-30 00:25:22,755 INFO L276 IsEmpty]: Start isEmpty. Operand 1517 states and 1713 transitions. [2018-01-30 00:25:22,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-30 00:25:22,756 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:22,756 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 24, 24, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:22,756 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:22,757 INFO L82 PathProgramCache]: Analyzing trace with hash 1260393484, now seen corresponding path program 11 times [2018-01-30 00:25:22,757 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:22,757 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:22,757 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:22,757 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:22,757 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:22,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:22,764 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:23,019 INFO L134 CoverageAnalysis]: Checked inductivity of 2001 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:23,019 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:23,019 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:23,024 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 00:25:23,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,040 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,041 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,042 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,044 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,045 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,046 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,048 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,049 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,051 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,053 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,055 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,058 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,061 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,063 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,067 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,070 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,079 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,085 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,090 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,096 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,102 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,111 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:23,111 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:23,113 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:23,134 INFO L134 CoverageAnalysis]: Checked inductivity of 2001 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:23,151 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:23,151 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-30 00:25:23,151 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-30 00:25:23,152 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-30 00:25:23,152 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 00:25:23,152 INFO L87 Difference]: Start difference. First operand 1517 states and 1713 transitions. Second operand 27 states. [2018-01-30 00:25:23,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:23,427 INFO L93 Difference]: Finished difference Result 1826 states and 2103 transitions. [2018-01-30 00:25:23,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-30 00:25:23,428 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 198 [2018-01-30 00:25:23,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:23,431 INFO L225 Difference]: With dead ends: 1826 [2018-01-30 00:25:23,431 INFO L226 Difference]: Without dead ends: 1740 [2018-01-30 00:25:23,431 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 00:25:23,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1740 states. [2018-01-30 00:25:23,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1740 to 1581. [2018-01-30 00:25:23,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1581 states. [2018-01-30 00:25:23,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1581 states to 1581 states and 1785 transitions. [2018-01-30 00:25:23,448 INFO L78 Accepts]: Start accepts. Automaton has 1581 states and 1785 transitions. Word has length 198 [2018-01-30 00:25:23,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:23,448 INFO L432 AbstractCegarLoop]: Abstraction has 1581 states and 1785 transitions. [2018-01-30 00:25:23,448 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-30 00:25:23,448 INFO L276 IsEmpty]: Start isEmpty. Operand 1581 states and 1785 transitions. [2018-01-30 00:25:23,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2018-01-30 00:25:23,450 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:23,450 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 25, 25, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:23,450 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:23,450 INFO L82 PathProgramCache]: Analyzing trace with hash -1466590989, now seen corresponding path program 12 times [2018-01-30 00:25:23,450 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:23,450 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:23,451 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:23,451 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:23,451 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:23,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:23,458 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:23,878 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 0 proven. 2150 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:23,878 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:23,878 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:23,883 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 00:25:23,888 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,891 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,892 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,893 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,894 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,895 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,898 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,899 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,901 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,902 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,906 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,908 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,910 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,912 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,914 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,916 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,919 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,921 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,924 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,927 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,931 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,935 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,939 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,943 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:23,944 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:23,946 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:23,967 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 0 proven. 2150 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:23,984 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:23,984 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-30 00:25:23,984 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-30 00:25:23,985 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-30 00:25:23,985 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 00:25:23,985 INFO L87 Difference]: Start difference. First operand 1581 states and 1785 transitions. Second operand 28 states. [2018-01-30 00:25:24,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:24,312 INFO L93 Difference]: Finished difference Result 1895 states and 2182 transitions. [2018-01-30 00:25:24,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-30 00:25:24,312 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 205 [2018-01-30 00:25:24,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:24,315 INFO L225 Difference]: With dead ends: 1895 [2018-01-30 00:25:24,315 INFO L226 Difference]: Without dead ends: 1809 [2018-01-30 00:25:24,315 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 206 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 00:25:24,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1809 states. [2018-01-30 00:25:24,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1809 to 1645. [2018-01-30 00:25:24,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2018-01-30 00:25:24,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 1857 transitions. [2018-01-30 00:25:24,337 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 1857 transitions. Word has length 205 [2018-01-30 00:25:24,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:24,337 INFO L432 AbstractCegarLoop]: Abstraction has 1645 states and 1857 transitions. [2018-01-30 00:25:24,337 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-30 00:25:24,337 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 1857 transitions. [2018-01-30 00:25:24,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-01-30 00:25:24,339 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:24,339 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 26, 26, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:24,340 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:24,340 INFO L82 PathProgramCache]: Analyzing trace with hash 80941612, now seen corresponding path program 13 times [2018-01-30 00:25:24,340 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:24,340 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:24,340 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:24,340 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:24,340 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:24,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:24,348 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:24,707 INFO L134 CoverageAnalysis]: Checked inductivity of 2348 backedges. 0 proven. 2327 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:24,707 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:24,707 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:24,719 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:24,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:24,747 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:24,769 INFO L134 CoverageAnalysis]: Checked inductivity of 2348 backedges. 0 proven. 2327 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:24,794 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:24,794 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-30 00:25:24,794 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-30 00:25:24,794 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-30 00:25:24,794 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 00:25:24,795 INFO L87 Difference]: Start difference. First operand 1645 states and 1857 transitions. Second operand 29 states. [2018-01-30 00:25:25,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:25,225 INFO L93 Difference]: Finished difference Result 1964 states and 2261 transitions. [2018-01-30 00:25:25,225 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-30 00:25:25,226 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 212 [2018-01-30 00:25:25,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:25,229 INFO L225 Difference]: With dead ends: 1964 [2018-01-30 00:25:25,229 INFO L226 Difference]: Without dead ends: 1878 [2018-01-30 00:25:25,240 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 00:25:25,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1878 states. [2018-01-30 00:25:25,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1878 to 1709. [2018-01-30 00:25:25,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1709 states. [2018-01-30 00:25:25,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1709 states to 1709 states and 1929 transitions. [2018-01-30 00:25:25,256 INFO L78 Accepts]: Start accepts. Automaton has 1709 states and 1929 transitions. Word has length 212 [2018-01-30 00:25:25,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:25,257 INFO L432 AbstractCegarLoop]: Abstraction has 1709 states and 1929 transitions. [2018-01-30 00:25:25,257 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-30 00:25:25,257 INFO L276 IsEmpty]: Start isEmpty. Operand 1709 states and 1929 transitions. [2018-01-30 00:25:25,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 220 [2018-01-30 00:25:25,258 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:25,259 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 27, 27, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:25,259 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:25,259 INFO L82 PathProgramCache]: Analyzing trace with hash 1766749907, now seen corresponding path program 14 times [2018-01-30 00:25:25,259 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:25,259 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:25,259 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:25,259 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:25,260 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:25,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:25,270 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:25,790 INFO L134 CoverageAnalysis]: Checked inductivity of 2532 backedges. 0 proven. 2511 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:25,791 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:25,791 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:25,796 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:25,803 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:25,813 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:25,815 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:25,817 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:25,842 INFO L134 CoverageAnalysis]: Checked inductivity of 2532 backedges. 0 proven. 2511 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:25,862 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:25,863 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-30 00:25:25,863 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-30 00:25:25,863 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-30 00:25:25,863 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 00:25:25,863 INFO L87 Difference]: Start difference. First operand 1709 states and 1929 transitions. Second operand 30 states. [2018-01-30 00:25:26,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:26,280 INFO L93 Difference]: Finished difference Result 2033 states and 2340 transitions. [2018-01-30 00:25:26,280 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-30 00:25:26,280 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 219 [2018-01-30 00:25:26,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:26,284 INFO L225 Difference]: With dead ends: 2033 [2018-01-30 00:25:26,284 INFO L226 Difference]: Without dead ends: 1947 [2018-01-30 00:25:26,284 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 220 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 00:25:26,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1947 states. [2018-01-30 00:25:26,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1947 to 1773. [2018-01-30 00:25:26,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1773 states. [2018-01-30 00:25:26,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1773 states to 1773 states and 2001 transitions. [2018-01-30 00:25:26,311 INFO L78 Accepts]: Start accepts. Automaton has 1773 states and 2001 transitions. Word has length 219 [2018-01-30 00:25:26,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:26,311 INFO L432 AbstractCegarLoop]: Abstraction has 1773 states and 2001 transitions. [2018-01-30 00:25:26,311 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-30 00:25:26,311 INFO L276 IsEmpty]: Start isEmpty. Operand 1773 states and 2001 transitions. [2018-01-30 00:25:26,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-01-30 00:25:26,314 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:26,314 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 28, 28, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:26,314 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:26,314 INFO L82 PathProgramCache]: Analyzing trace with hash -841033652, now seen corresponding path program 15 times [2018-01-30 00:25:26,314 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:26,314 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:26,315 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:26,315 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:26,315 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:26,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:26,322 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:26,783 INFO L134 CoverageAnalysis]: Checked inductivity of 2723 backedges. 0 proven. 2702 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:26,783 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:26,783 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:26,795 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:26,801 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,802 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,803 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,804 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,806 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,807 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,808 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,810 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,811 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,813 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,815 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,818 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,823 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,825 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,840 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,844 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,849 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,854 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,859 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,865 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,873 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,880 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,889 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,897 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,906 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:26,907 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:26,909 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:26,934 INFO L134 CoverageAnalysis]: Checked inductivity of 2723 backedges. 0 proven. 2702 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:26,952 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:26,952 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-30 00:25:26,952 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-30 00:25:26,952 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-30 00:25:26,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 00:25:26,953 INFO L87 Difference]: Start difference. First operand 1773 states and 2001 transitions. Second operand 31 states. [2018-01-30 00:25:28,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:28,115 INFO L93 Difference]: Finished difference Result 2102 states and 2419 transitions. [2018-01-30 00:25:28,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-30 00:25:28,116 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 226 [2018-01-30 00:25:28,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:28,119 INFO L225 Difference]: With dead ends: 2102 [2018-01-30 00:25:28,119 INFO L226 Difference]: Without dead ends: 2016 [2018-01-30 00:25:28,120 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 00:25:28,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2016 states. [2018-01-30 00:25:28,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2016 to 1837. [2018-01-30 00:25:28,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1837 states. [2018-01-30 00:25:28,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1837 states to 1837 states and 2073 transitions. [2018-01-30 00:25:28,137 INFO L78 Accepts]: Start accepts. Automaton has 1837 states and 2073 transitions. Word has length 226 [2018-01-30 00:25:28,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:28,137 INFO L432 AbstractCegarLoop]: Abstraction has 1837 states and 2073 transitions. [2018-01-30 00:25:28,137 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-30 00:25:28,137 INFO L276 IsEmpty]: Start isEmpty. Operand 1837 states and 2073 transitions. [2018-01-30 00:25:28,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-01-30 00:25:28,139 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:28,139 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 29, 29, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:28,139 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:28,139 INFO L82 PathProgramCache]: Analyzing trace with hash -1833071437, now seen corresponding path program 16 times [2018-01-30 00:25:28,139 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:28,139 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:28,140 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:28,140 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:28,140 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:28,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:28,147 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:28,760 INFO L134 CoverageAnalysis]: Checked inductivity of 2921 backedges. 0 proven. 2900 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:28,760 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:28,760 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:28,764 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 00:25:28,786 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:28,788 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:29,132 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:29,132 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,188 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,188 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 00:25:29,249 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,250 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,250 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,253 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,253 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,267 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,268 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,268 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,272 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,272 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,286 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,287 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,287 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,290 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,290 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,305 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,306 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,306 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,310 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,310 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,326 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,327 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,327 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,330 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,330 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,347 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,348 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,348 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,352 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,352 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,409 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,418 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,418 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,422 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,422 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,440 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,441 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,441 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,445 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,445 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,464 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,465 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,465 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,469 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,469 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,493 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,494 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,494 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,497 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,497 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,561 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,562 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,562 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,570 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,570 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,591 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,592 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,596 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,596 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,618 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,619 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,619 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,623 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,623 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,645 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,646 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,646 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,650 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,650 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,674 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,675 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,676 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,680 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,680 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,704 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,705 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,708 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,708 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,732 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,733 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,733 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,736 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,737 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,760 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,761 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,761 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,765 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,765 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,793 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,794 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,794 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,797 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,798 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,833 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,834 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,834 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,837 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,837 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,863 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,864 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,865 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,869 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,869 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,893 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,894 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,894 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,897 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,897 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,940 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,941 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,942 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,945 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,946 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:29,973 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:29,974 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:29,974 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,977 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:29,977 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:30,003 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:30,004 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:30,004 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:30,008 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:30,008 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 00:25:30,115 INFO L134 CoverageAnalysis]: Checked inductivity of 2921 backedges. 2028 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:30,132 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:30,132 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 36] total 66 [2018-01-30 00:25:30,133 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-30 00:25:30,133 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-30 00:25:30,133 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1125, Invalid=3165, Unknown=0, NotChecked=0, Total=4290 [2018-01-30 00:25:30,134 INFO L87 Difference]: Start difference. First operand 1837 states and 2073 transitions. Second operand 66 states. [2018-01-30 00:25:32,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:32,622 INFO L93 Difference]: Finished difference Result 4110 states and 4738 transitions. [2018-01-30 00:25:32,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-30 00:25:32,623 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 233 [2018-01-30 00:25:32,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:32,629 INFO L225 Difference]: With dead ends: 4110 [2018-01-30 00:25:32,630 INFO L226 Difference]: Without dead ends: 4024 [2018-01-30 00:25:32,631 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 290 GetRequests, 199 SyntacticMatches, 1 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2348 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1905, Invalid=6467, Unknown=0, NotChecked=0, Total=8372 [2018-01-30 00:25:32,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4024 states. [2018-01-30 00:25:32,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4024 to 3645. [2018-01-30 00:25:32,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3645 states. [2018-01-30 00:25:32,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3645 states to 3645 states and 4119 transitions. [2018-01-30 00:25:32,674 INFO L78 Accepts]: Start accepts. Automaton has 3645 states and 4119 transitions. Word has length 233 [2018-01-30 00:25:32,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:32,674 INFO L432 AbstractCegarLoop]: Abstraction has 3645 states and 4119 transitions. [2018-01-30 00:25:32,674 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-30 00:25:32,674 INFO L276 IsEmpty]: Start isEmpty. Operand 3645 states and 4119 transitions. [2018-01-30 00:25:32,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2018-01-30 00:25:32,677 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:32,677 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 30, 30, 29, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:32,677 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:32,677 INFO L82 PathProgramCache]: Analyzing trace with hash -1538321920, now seen corresponding path program 7 times [2018-01-30 00:25:32,677 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:32,677 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:32,678 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:32,678 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:32,678 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:32,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:32,685 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:33,219 INFO L134 CoverageAnalysis]: Checked inductivity of 3126 backedges. 0 proven. 3105 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:33,220 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:33,220 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:33,224 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:33,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:33,244 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:33,272 INFO L134 CoverageAnalysis]: Checked inductivity of 3126 backedges. 0 proven. 3105 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:33,288 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:33,289 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-30 00:25:33,289 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-30 00:25:33,289 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-30 00:25:33,289 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 00:25:33,289 INFO L87 Difference]: Start difference. First operand 3645 states and 4119 transitions. Second operand 33 states. [2018-01-30 00:25:33,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:33,604 INFO L93 Difference]: Finished difference Result 4163 states and 4768 transitions. [2018-01-30 00:25:33,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-30 00:25:33,605 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 241 [2018-01-30 00:25:33,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:33,611 INFO L225 Difference]: With dead ends: 4163 [2018-01-30 00:25:33,611 INFO L226 Difference]: Without dead ends: 4021 [2018-01-30 00:25:33,612 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 242 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 00:25:33,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4021 states. [2018-01-30 00:25:33,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4021 to 3773. [2018-01-30 00:25:33,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3773 states. [2018-01-30 00:25:33,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3773 states to 3773 states and 4263 transitions. [2018-01-30 00:25:33,649 INFO L78 Accepts]: Start accepts. Automaton has 3773 states and 4263 transitions. Word has length 241 [2018-01-30 00:25:33,649 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:33,650 INFO L432 AbstractCegarLoop]: Abstraction has 3773 states and 4263 transitions. [2018-01-30 00:25:33,650 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-30 00:25:33,650 INFO L276 IsEmpty]: Start isEmpty. Operand 3773 states and 4263 transitions. [2018-01-30 00:25:33,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2018-01-30 00:25:33,652 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:33,653 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 31, 31, 30, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:33,653 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:33,653 INFO L82 PathProgramCache]: Analyzing trace with hash -878788481, now seen corresponding path program 8 times [2018-01-30 00:25:33,653 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:33,653 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:33,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:33,653 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:33,653 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:33,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:33,661 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:34,214 INFO L134 CoverageAnalysis]: Checked inductivity of 3338 backedges. 0 proven. 3317 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:34,214 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:34,214 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:34,219 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:34,224 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:34,237 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:34,241 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:34,243 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:34,283 INFO L134 CoverageAnalysis]: Checked inductivity of 3338 backedges. 0 proven. 3317 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:34,300 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:34,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-30 00:25:34,301 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-30 00:25:34,301 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-30 00:25:34,301 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 00:25:34,301 INFO L87 Difference]: Start difference. First operand 3773 states and 4263 transitions. Second operand 34 states. [2018-01-30 00:25:34,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:34,625 INFO L93 Difference]: Finished difference Result 4296 states and 4919 transitions. [2018-01-30 00:25:34,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-30 00:25:34,625 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 248 [2018-01-30 00:25:34,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:34,629 INFO L225 Difference]: With dead ends: 4296 [2018-01-30 00:25:34,629 INFO L226 Difference]: Without dead ends: 4154 [2018-01-30 00:25:34,631 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 281 GetRequests, 249 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 00:25:34,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2018-01-30 00:25:34,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 3901. [2018-01-30 00:25:34,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3901 states. [2018-01-30 00:25:34,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3901 states to 3901 states and 4407 transitions. [2018-01-30 00:25:34,670 INFO L78 Accepts]: Start accepts. Automaton has 3901 states and 4407 transitions. Word has length 248 [2018-01-30 00:25:34,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:34,670 INFO L432 AbstractCegarLoop]: Abstraction has 3901 states and 4407 transitions. [2018-01-30 00:25:34,670 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-30 00:25:34,670 INFO L276 IsEmpty]: Start isEmpty. Operand 3901 states and 4407 transitions. [2018-01-30 00:25:34,673 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 256 [2018-01-30 00:25:34,673 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:34,673 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 32, 31, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:34,674 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:34,674 INFO L82 PathProgramCache]: Analyzing trace with hash 849646880, now seen corresponding path program 9 times [2018-01-30 00:25:34,674 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:34,674 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:34,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:34,674 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:34,674 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:34,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:34,682 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:35,556 INFO L134 CoverageAnalysis]: Checked inductivity of 3557 backedges. 0 proven. 3536 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 00:25:35,557 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:35,557 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:35,561 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:35,566 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,567 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,568 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,570 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,571 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,572 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,574 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,575 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,577 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,578 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,580 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,583 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,585 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,588 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,590 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,593 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,597 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,600 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,604 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,614 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,619 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,624 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,637 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,645 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,653 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,663 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:35,664 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:35,666 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:35,676 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:35,676 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:35,677 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:35,677 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 00:25:35,775 INFO L134 CoverageAnalysis]: Checked inductivity of 3557 backedges. 0 proven. 827 refuted. 0 times theorem prover too weak. 2730 trivial. 0 not checked. [2018-01-30 00:25:35,792 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:35,792 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 13] total 46 [2018-01-30 00:25:35,792 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-30 00:25:35,792 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-30 00:25:35,793 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=877, Invalid=1193, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 00:25:35,793 INFO L87 Difference]: Start difference. First operand 3901 states and 4407 transitions. Second operand 46 states. [2018-01-30 00:25:36,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:36,888 INFO L93 Difference]: Finished difference Result 4584 states and 5286 transitions. [2018-01-30 00:25:36,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-01-30 00:25:36,888 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 255 [2018-01-30 00:25:36,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:36,892 INFO L225 Difference]: With dead ends: 4584 [2018-01-30 00:25:36,892 INFO L226 Difference]: Without dead ends: 4442 [2018-01-30 00:25:36,893 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 319 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1309 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1925, Invalid=3775, Unknown=0, NotChecked=0, Total=5700 [2018-01-30 00:25:36,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4442 states. [2018-01-30 00:25:36,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4442 to 4049. [2018-01-30 00:25:36,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4049 states. [2018-01-30 00:25:36,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4049 states to 4049 states and 4572 transitions. [2018-01-30 00:25:36,932 INFO L78 Accepts]: Start accepts. Automaton has 4049 states and 4572 transitions. Word has length 255 [2018-01-30 00:25:36,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:36,932 INFO L432 AbstractCegarLoop]: Abstraction has 4049 states and 4572 transitions. [2018-01-30 00:25:36,932 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-30 00:25:36,932 INFO L276 IsEmpty]: Start isEmpty. Operand 4049 states and 4572 transitions. [2018-01-30 00:25:36,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 266 [2018-01-30 00:25:36,935 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:36,936 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 33, 33, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:36,936 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:36,936 INFO L82 PathProgramCache]: Analyzing trace with hash 761224364, now seen corresponding path program 17 times [2018-01-30 00:25:36,936 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:36,936 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:36,936 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:36,936 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:36,936 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:36,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:36,944 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:37,880 INFO L134 CoverageAnalysis]: Checked inductivity of 3798 backedges. 0 proven. 3762 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:37,880 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:37,880 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:37,884 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 00:25:37,889 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,890 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,892 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,893 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,894 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,895 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,896 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,899 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,901 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,903 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,905 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,911 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,914 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,925 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,929 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,933 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,939 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,967 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:37,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:38,009 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:38,021 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:38,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:38,050 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:38,074 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:38,075 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:38,078 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:38,111 INFO L134 CoverageAnalysis]: Checked inductivity of 3798 backedges. 0 proven. 3762 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:38,129 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:38,129 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-30 00:25:38,129 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-30 00:25:38,129 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-30 00:25:38,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 00:25:38,130 INFO L87 Difference]: Start difference. First operand 4049 states and 4572 transitions. Second operand 36 states. [2018-01-30 00:25:38,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:38,482 INFO L93 Difference]: Finished difference Result 4586 states and 5245 transitions. [2018-01-30 00:25:38,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-30 00:25:38,482 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 265 [2018-01-30 00:25:38,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:38,486 INFO L225 Difference]: With dead ends: 4586 [2018-01-30 00:25:38,486 INFO L226 Difference]: Without dead ends: 4424 [2018-01-30 00:25:38,487 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 300 GetRequests, 266 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 00:25:38,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4424 states. [2018-01-30 00:25:38,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4424 to 4177. [2018-01-30 00:25:38,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4177 states. [2018-01-30 00:25:38,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4177 states to 4177 states and 4716 transitions. [2018-01-30 00:25:38,525 INFO L78 Accepts]: Start accepts. Automaton has 4177 states and 4716 transitions. Word has length 265 [2018-01-30 00:25:38,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:38,525 INFO L432 AbstractCegarLoop]: Abstraction has 4177 states and 4716 transitions. [2018-01-30 00:25:38,525 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-30 00:25:38,525 INFO L276 IsEmpty]: Start isEmpty. Operand 4177 states and 4716 transitions. [2018-01-30 00:25:38,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 273 [2018-01-30 00:25:38,528 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:38,528 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 34, 34, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:38,528 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:38,528 INFO L82 PathProgramCache]: Analyzing trace with hash -450227611, now seen corresponding path program 18 times [2018-01-30 00:25:38,528 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:38,529 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:38,529 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:38,529 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:38,529 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:38,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:38,536 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:39,396 INFO L134 CoverageAnalysis]: Checked inductivity of 4031 backedges. 0 proven. 3995 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:39,397 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:39,397 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:39,416 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 00:25:39,421 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,428 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,438 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,447 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,457 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,467 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,468 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,469 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,471 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,473 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,476 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,477 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,479 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,481 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,488 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,491 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,497 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,500 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,503 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,506 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,510 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,527 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,545 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,552 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,558 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,566 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:39,567 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:39,569 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:39,610 INFO L134 CoverageAnalysis]: Checked inductivity of 4031 backedges. 0 proven. 3995 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:39,627 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:39,627 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-30 00:25:39,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-30 00:25:39,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-30 00:25:39,628 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 00:25:39,628 INFO L87 Difference]: Start difference. First operand 4177 states and 4716 transitions. Second operand 37 states. [2018-01-30 00:25:40,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:40,026 INFO L93 Difference]: Finished difference Result 4719 states and 5396 transitions. [2018-01-30 00:25:40,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-30 00:25:40,027 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 272 [2018-01-30 00:25:40,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:40,031 INFO L225 Difference]: With dead ends: 4719 [2018-01-30 00:25:40,031 INFO L226 Difference]: Without dead ends: 4557 [2018-01-30 00:25:40,032 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 273 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 00:25:40,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4557 states. [2018-01-30 00:25:40,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4557 to 4305. [2018-01-30 00:25:40,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4305 states. [2018-01-30 00:25:40,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4305 states to 4305 states and 4860 transitions. [2018-01-30 00:25:40,072 INFO L78 Accepts]: Start accepts. Automaton has 4305 states and 4860 transitions. Word has length 272 [2018-01-30 00:25:40,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:40,072 INFO L432 AbstractCegarLoop]: Abstraction has 4305 states and 4860 transitions. [2018-01-30 00:25:40,072 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-30 00:25:40,072 INFO L276 IsEmpty]: Start isEmpty. Operand 4305 states and 4860 transitions. [2018-01-30 00:25:40,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 280 [2018-01-30 00:25:40,075 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:40,076 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 35, 35, 35, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:40,076 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:40,076 INFO L82 PathProgramCache]: Analyzing trace with hash -57464180, now seen corresponding path program 19 times [2018-01-30 00:25:40,076 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:40,076 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:40,076 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:40,076 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:40,076 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:40,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:40,083 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:40,853 INFO L134 CoverageAnalysis]: Checked inductivity of 4271 backedges. 0 proven. 4235 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:40,853 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:40,853 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:40,870 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:40,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:40,911 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:40,947 INFO L134 CoverageAnalysis]: Checked inductivity of 4271 backedges. 0 proven. 4235 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:40,964 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:40,964 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-30 00:25:40,964 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-30 00:25:40,964 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-30 00:25:40,965 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 00:25:40,965 INFO L87 Difference]: Start difference. First operand 4305 states and 4860 transitions. Second operand 38 states. [2018-01-30 00:25:41,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:41,327 INFO L93 Difference]: Finished difference Result 4852 states and 5547 transitions. [2018-01-30 00:25:41,327 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-30 00:25:41,327 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 279 [2018-01-30 00:25:41,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:41,331 INFO L225 Difference]: With dead ends: 4852 [2018-01-30 00:25:41,331 INFO L226 Difference]: Without dead ends: 4690 [2018-01-30 00:25:41,331 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 316 GetRequests, 280 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 00:25:41,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4690 states. [2018-01-30 00:25:41,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4690 to 4433. [2018-01-30 00:25:41,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4433 states. [2018-01-30 00:25:41,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4433 states to 4433 states and 5004 transitions. [2018-01-30 00:25:41,380 INFO L78 Accepts]: Start accepts. Automaton has 4433 states and 5004 transitions. Word has length 279 [2018-01-30 00:25:41,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:41,380 INFO L432 AbstractCegarLoop]: Abstraction has 4433 states and 5004 transitions. [2018-01-30 00:25:41,380 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-30 00:25:41,380 INFO L276 IsEmpty]: Start isEmpty. Operand 4433 states and 5004 transitions. [2018-01-30 00:25:41,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-01-30 00:25:41,385 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:41,385 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 36, 36, 36, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:41,385 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:41,385 INFO L82 PathProgramCache]: Analyzing trace with hash 1552738437, now seen corresponding path program 20 times [2018-01-30 00:25:41,385 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:41,385 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:41,387 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:41,387 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:41,387 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:41,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:41,398 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:42,021 INFO L134 CoverageAnalysis]: Checked inductivity of 4518 backedges. 0 proven. 4482 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:42,021 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:42,022 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:42,026 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:42,032 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:42,046 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:42,056 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:42,058 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:42,096 INFO L134 CoverageAnalysis]: Checked inductivity of 4518 backedges. 0 proven. 4482 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:42,113 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:42,113 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-30 00:25:42,113 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-30 00:25:42,113 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-30 00:25:42,113 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 00:25:42,114 INFO L87 Difference]: Start difference. First operand 4433 states and 5004 transitions. Second operand 39 states. [2018-01-30 00:25:42,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:42,697 INFO L93 Difference]: Finished difference Result 4985 states and 5698 transitions. [2018-01-30 00:25:42,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-30 00:25:42,698 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 286 [2018-01-30 00:25:42,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:42,699 INFO L225 Difference]: With dead ends: 4985 [2018-01-30 00:25:42,700 INFO L226 Difference]: Without dead ends: 4823 [2018-01-30 00:25:42,700 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 324 GetRequests, 287 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 00:25:42,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4823 states. [2018-01-30 00:25:42,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4823 to 4561. [2018-01-30 00:25:42,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4561 states. [2018-01-30 00:25:42,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4561 states to 4561 states and 5148 transitions. [2018-01-30 00:25:42,737 INFO L78 Accepts]: Start accepts. Automaton has 4561 states and 5148 transitions. Word has length 286 [2018-01-30 00:25:42,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:42,737 INFO L432 AbstractCegarLoop]: Abstraction has 4561 states and 5148 transitions. [2018-01-30 00:25:42,737 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-30 00:25:42,737 INFO L276 IsEmpty]: Start isEmpty. Operand 4561 states and 5148 transitions. [2018-01-30 00:25:42,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-01-30 00:25:42,741 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:42,741 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 37, 37, 37, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:42,741 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:42,741 INFO L82 PathProgramCache]: Analyzing trace with hash 177811564, now seen corresponding path program 21 times [2018-01-30 00:25:42,741 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:42,741 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:42,742 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:42,742 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:42,742 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:42,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:42,749 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:43,492 INFO L134 CoverageAnalysis]: Checked inductivity of 4772 backedges. 0 proven. 4736 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:43,492 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:43,492 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:43,497 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:43,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,506 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,508 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,510 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,513 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,516 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,518 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,521 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,523 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,528 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,531 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,543 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,547 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,552 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,557 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,562 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,568 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,575 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,582 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,590 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,598 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,608 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,617 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,628 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,640 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,653 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,667 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,682 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,699 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,715 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,734 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,755 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:43,756 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:43,758 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:43,798 INFO L134 CoverageAnalysis]: Checked inductivity of 4772 backedges. 0 proven. 4736 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:43,815 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:43,816 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-30 00:25:43,816 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-30 00:25:43,816 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-30 00:25:43,816 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 00:25:43,816 INFO L87 Difference]: Start difference. First operand 4561 states and 5148 transitions. Second operand 40 states. [2018-01-30 00:25:44,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:44,247 INFO L93 Difference]: Finished difference Result 5118 states and 5849 transitions. [2018-01-30 00:25:44,248 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-30 00:25:44,248 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 293 [2018-01-30 00:25:44,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:44,251 INFO L225 Difference]: With dead ends: 5118 [2018-01-30 00:25:44,251 INFO L226 Difference]: Without dead ends: 4956 [2018-01-30 00:25:44,252 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 294 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 00:25:44,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4956 states. [2018-01-30 00:25:44,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4956 to 4689. [2018-01-30 00:25:44,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4689 states. [2018-01-30 00:25:44,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4689 states to 4689 states and 5292 transitions. [2018-01-30 00:25:44,294 INFO L78 Accepts]: Start accepts. Automaton has 4689 states and 5292 transitions. Word has length 293 [2018-01-30 00:25:44,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:44,294 INFO L432 AbstractCegarLoop]: Abstraction has 4689 states and 5292 transitions. [2018-01-30 00:25:44,294 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-30 00:25:44,295 INFO L276 IsEmpty]: Start isEmpty. Operand 4689 states and 5292 transitions. [2018-01-30 00:25:44,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 301 [2018-01-30 00:25:44,298 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:44,298 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 38, 38, 38, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:44,298 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:44,299 INFO L82 PathProgramCache]: Analyzing trace with hash -424769883, now seen corresponding path program 22 times [2018-01-30 00:25:44,299 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:44,299 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:44,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:44,299 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:44,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:44,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:44,307 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:44,952 INFO L134 CoverageAnalysis]: Checked inductivity of 5033 backedges. 0 proven. 4997 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:44,952 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:44,952 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:44,957 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 00:25:44,979 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:44,981 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:45,016 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:45,016 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,020 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,020 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 00:25:45,042 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,043 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,043 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,047 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,047 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,063 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,064 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,064 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,067 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,067 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,085 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,085 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,086 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,089 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,089 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,106 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,107 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,107 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,111 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,111 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,129 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,129 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,130 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,133 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,133 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,159 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,160 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,160 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,164 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,164 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,185 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,186 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,186 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,190 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,190 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,210 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,211 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,211 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,214 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,214 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,234 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,235 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,235 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,238 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,238 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:45,258 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:45,259 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:45,259 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,263 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:45,263 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,045 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,064 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,064 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,156 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,156 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,214 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,215 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,215 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,219 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,219 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,241 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,242 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,242 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,245 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,245 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,269 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,270 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,270 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,273 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,273 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,297 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,297 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,298 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,301 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,301 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,324 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,325 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,325 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,328 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,328 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,352 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,353 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,353 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,356 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,356 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,383 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,384 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,384 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,387 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,387 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,412 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,413 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,413 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,416 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,416 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,442 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,442 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,443 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,446 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,446 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,472 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,472 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,473 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,476 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,476 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,512 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,513 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,513 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,516 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,516 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,544 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,544 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,545 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,549 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,549 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,577 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,578 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,578 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,581 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,581 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,609 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,610 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,613 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,613 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,642 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,642 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,643 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,646 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,646 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,680 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,681 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,682 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,685 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,685 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,714 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,715 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,715 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,719 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,719 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,749 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,750 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,750 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,753 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,753 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,783 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,784 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,784 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,788 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,788 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,818 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,819 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,819 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,823 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,823 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,854 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,855 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,855 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,858 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,859 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 00:25:46,913 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 00:25:46,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 00:25:46,914 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,917 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:46,918 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 00:25:47,087 INFO L134 CoverageAnalysis]: Checked inductivity of 5033 backedges. 3600 proven. 1433 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 00:25:47,104 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:47,104 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 46] total 85 [2018-01-30 00:25:47,105 INFO L409 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-01-30 00:25:47,105 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-01-30 00:25:47,105 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1849, Invalid=5291, Unknown=0, NotChecked=0, Total=7140 [2018-01-30 00:25:47,106 INFO L87 Difference]: Start difference. First operand 4689 states and 5292 transitions. Second operand 85 states. [2018-01-30 00:25:50,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:50,000 INFO L93 Difference]: Finished difference Result 10062 states and 11504 transitions. [2018-01-30 00:25:50,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-01-30 00:25:50,000 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 300 [2018-01-30 00:25:50,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:50,007 INFO L225 Difference]: With dead ends: 10062 [2018-01-30 00:25:50,007 INFO L226 Difference]: Without dead ends: 9900 [2018-01-30 00:25:50,009 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 374 GetRequests, 256 SyntacticMatches, 1 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3940 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3141, Invalid=10901, Unknown=0, NotChecked=0, Total=14042 [2018-01-30 00:25:50,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9900 states. [2018-01-30 00:25:50,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9900 to 9341. [2018-01-30 00:25:50,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9341 states. [2018-01-30 00:25:50,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9341 states to 9341 states and 10550 transitions. [2018-01-30 00:25:50,127 INFO L78 Accepts]: Start accepts. Automaton has 9341 states and 10550 transitions. Word has length 300 [2018-01-30 00:25:50,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:50,127 INFO L432 AbstractCegarLoop]: Abstraction has 9341 states and 10550 transitions. [2018-01-30 00:25:50,127 INFO L433 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-01-30 00:25:50,127 INFO L276 IsEmpty]: Start isEmpty. Operand 9341 states and 10550 transitions. [2018-01-30 00:25:50,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2018-01-30 00:25:50,134 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:50,134 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 39, 39, 38, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:50,134 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:50,134 INFO L82 PathProgramCache]: Analyzing trace with hash -1375041166, now seen corresponding path program 10 times [2018-01-30 00:25:50,134 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:50,134 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:50,134 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:50,134 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:50,134 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:50,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:50,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:50,870 INFO L134 CoverageAnalysis]: Checked inductivity of 5301 backedges. 0 proven. 5265 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:50,871 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:50,871 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:50,876 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 00:25:50,934 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:50,936 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:50,979 INFO L134 CoverageAnalysis]: Checked inductivity of 5301 backedges. 0 proven. 5265 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:50,999 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:50,999 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-30 00:25:51,000 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-30 00:25:51,000 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-30 00:25:51,000 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 00:25:51,000 INFO L87 Difference]: Start difference. First operand 9341 states and 10550 transitions. Second operand 42 states. [2018-01-30 00:25:51,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:51,437 INFO L93 Difference]: Finished difference Result 10271 states and 11706 transitions. [2018-01-30 00:25:51,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-30 00:25:51,438 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 308 [2018-01-30 00:25:51,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:51,444 INFO L225 Difference]: With dead ends: 10271 [2018-01-30 00:25:51,444 INFO L226 Difference]: Without dead ends: 9985 [2018-01-30 00:25:51,446 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 00:25:51,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9985 states. [2018-01-30 00:25:51,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9985 to 9597. [2018-01-30 00:25:51,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9597 states. [2018-01-30 00:25:51,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9597 states to 9597 states and 10838 transitions. [2018-01-30 00:25:51,544 INFO L78 Accepts]: Start accepts. Automaton has 9597 states and 10838 transitions. Word has length 308 [2018-01-30 00:25:51,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:51,544 INFO L432 AbstractCegarLoop]: Abstraction has 9597 states and 10838 transitions. [2018-01-30 00:25:51,544 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-30 00:25:51,544 INFO L276 IsEmpty]: Start isEmpty. Operand 9597 states and 10838 transitions. [2018-01-30 00:25:51,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 316 [2018-01-30 00:25:51,549 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:51,549 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 40, 40, 39, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:51,549 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:51,549 INFO L82 PathProgramCache]: Analyzing trace with hash 1778260703, now seen corresponding path program 11 times [2018-01-30 00:25:51,549 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:51,549 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:51,550 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:51,550 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:51,550 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:51,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:51,557 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:52,543 INFO L134 CoverageAnalysis]: Checked inductivity of 5576 backedges. 0 proven. 5540 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:52,543 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:52,543 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:52,549 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 00:25:52,555 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,556 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,557 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,558 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,559 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,563 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,564 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,566 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,568 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,570 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,572 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,574 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,577 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,581 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,584 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,587 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,591 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,595 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,600 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,606 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,619 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,626 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,634 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,642 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,652 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,664 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,676 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,688 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,717 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,733 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,751 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,844 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,870 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,904 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:52,905 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:52,908 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:52,996 INFO L134 CoverageAnalysis]: Checked inductivity of 5576 backedges. 0 proven. 5540 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:53,014 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:53,014 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-30 00:25:53,014 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-30 00:25:53,014 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-30 00:25:53,015 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 00:25:53,015 INFO L87 Difference]: Start difference. First operand 9597 states and 10838 transitions. Second operand 43 states. [2018-01-30 00:25:53,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:53,496 INFO L93 Difference]: Finished difference Result 10532 states and 12001 transitions. [2018-01-30 00:25:53,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-30 00:25:53,496 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 315 [2018-01-30 00:25:53,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:53,502 INFO L225 Difference]: With dead ends: 10532 [2018-01-30 00:25:53,502 INFO L226 Difference]: Without dead ends: 10246 [2018-01-30 00:25:53,504 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 00:25:53,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10246 states. [2018-01-30 00:25:53,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10246 to 9853. [2018-01-30 00:25:53,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9853 states. [2018-01-30 00:25:53,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9853 states to 9853 states and 11126 transitions. [2018-01-30 00:25:53,607 INFO L78 Accepts]: Start accepts. Automaton has 9853 states and 11126 transitions. Word has length 315 [2018-01-30 00:25:53,607 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:53,607 INFO L432 AbstractCegarLoop]: Abstraction has 9853 states and 11126 transitions. [2018-01-30 00:25:53,607 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-30 00:25:53,607 INFO L276 IsEmpty]: Start isEmpty. Operand 9853 states and 11126 transitions. [2018-01-30 00:25:53,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 323 [2018-01-30 00:25:53,612 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:53,612 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 41, 41, 40, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:53,613 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:53,613 INFO L82 PathProgramCache]: Analyzing trace with hash -1409973038, now seen corresponding path program 12 times [2018-01-30 00:25:53,613 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:53,613 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:53,613 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:53,613 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:53,613 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:53,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:53,621 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:54,365 INFO L134 CoverageAnalysis]: Checked inductivity of 5858 backedges. 0 proven. 5822 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:54,365 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:54,365 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:54,370 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 00:25:54,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,377 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,378 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,379 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,380 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,381 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,382 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,384 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,385 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,388 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,390 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,394 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,396 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,398 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,401 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,403 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,406 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,410 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,415 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,430 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,434 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,438 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,454 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,461 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,467 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,480 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,487 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,505 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,536 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,547 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,557 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:25:54,570 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:54,573 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:54,620 INFO L134 CoverageAnalysis]: Checked inductivity of 5858 backedges. 0 proven. 5822 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:54,637 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:54,637 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-30 00:25:54,637 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-30 00:25:54,638 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-30 00:25:54,638 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 00:25:54,638 INFO L87 Difference]: Start difference. First operand 9853 states and 11126 transitions. Second operand 44 states. [2018-01-30 00:25:55,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:55,437 INFO L93 Difference]: Finished difference Result 10793 states and 12296 transitions. [2018-01-30 00:25:55,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-30 00:25:55,437 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 322 [2018-01-30 00:25:55,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:55,443 INFO L225 Difference]: With dead ends: 10793 [2018-01-30 00:25:55,443 INFO L226 Difference]: Without dead ends: 10507 [2018-01-30 00:25:55,445 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 323 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 00:25:55,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10507 states. [2018-01-30 00:25:55,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10507 to 10109. [2018-01-30 00:25:55,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10109 states. [2018-01-30 00:25:55,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10109 states to 10109 states and 11414 transitions. [2018-01-30 00:25:55,573 INFO L78 Accepts]: Start accepts. Automaton has 10109 states and 11414 transitions. Word has length 322 [2018-01-30 00:25:55,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:55,574 INFO L432 AbstractCegarLoop]: Abstraction has 10109 states and 11414 transitions. [2018-01-30 00:25:55,574 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-30 00:25:55,574 INFO L276 IsEmpty]: Start isEmpty. Operand 10109 states and 11414 transitions. [2018-01-30 00:25:55,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 330 [2018-01-30 00:25:55,579 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:55,579 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 42, 41, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:55,579 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:55,579 INFO L82 PathProgramCache]: Analyzing trace with hash -1941728385, now seen corresponding path program 13 times [2018-01-30 00:25:55,579 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:55,580 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:55,580 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:55,580 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:55,580 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:55,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:55,588 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:56,310 INFO L134 CoverageAnalysis]: Checked inductivity of 6147 backedges. 0 proven. 6111 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:56,310 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:56,310 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:56,315 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:56,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:56,339 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:56,389 INFO L134 CoverageAnalysis]: Checked inductivity of 6147 backedges. 0 proven. 6111 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:56,406 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:56,406 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-30 00:25:56,406 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-30 00:25:56,406 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-30 00:25:56,406 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 00:25:56,407 INFO L87 Difference]: Start difference. First operand 10109 states and 11414 transitions. Second operand 45 states. [2018-01-30 00:25:56,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:56,885 INFO L93 Difference]: Finished difference Result 11054 states and 12591 transitions. [2018-01-30 00:25:56,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-30 00:25:56,886 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 329 [2018-01-30 00:25:56,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:56,892 INFO L225 Difference]: With dead ends: 11054 [2018-01-30 00:25:56,892 INFO L226 Difference]: Without dead ends: 10768 [2018-01-30 00:25:56,894 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 330 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 00:25:56,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10768 states. [2018-01-30 00:25:56,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10768 to 10365. [2018-01-30 00:25:56,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10365 states. [2018-01-30 00:25:56,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10365 states to 10365 states and 11702 transitions. [2018-01-30 00:25:56,999 INFO L78 Accepts]: Start accepts. Automaton has 10365 states and 11702 transitions. Word has length 329 [2018-01-30 00:25:56,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:56,999 INFO L432 AbstractCegarLoop]: Abstraction has 10365 states and 11702 transitions. [2018-01-30 00:25:56,999 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-30 00:25:56,999 INFO L276 IsEmpty]: Start isEmpty. Operand 10365 states and 11702 transitions. [2018-01-30 00:25:57,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2018-01-30 00:25:57,005 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:57,005 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 43, 43, 42, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:57,005 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:57,005 INFO L82 PathProgramCache]: Analyzing trace with hash -606791630, now seen corresponding path program 14 times [2018-01-30 00:25:57,005 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:57,005 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:57,006 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:57,006 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:25:57,006 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:57,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:57,014 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:57,817 INFO L134 CoverageAnalysis]: Checked inductivity of 6443 backedges. 0 proven. 6407 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:57,817 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:57,817 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:57,822 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 00:25:57,827 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:57,842 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:25:57,846 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:57,848 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:57,927 INFO L134 CoverageAnalysis]: Checked inductivity of 6443 backedges. 0 proven. 6407 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:57,944 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:25:57,944 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-30 00:25:57,944 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-30 00:25:57,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-30 00:25:57,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 00:25:57,944 INFO L87 Difference]: Start difference. First operand 10365 states and 11702 transitions. Second operand 46 states. [2018-01-30 00:25:58,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:25:58,543 INFO L93 Difference]: Finished difference Result 11315 states and 12886 transitions. [2018-01-30 00:25:58,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-30 00:25:58,544 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 336 [2018-01-30 00:25:58,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:25:58,550 INFO L225 Difference]: With dead ends: 11315 [2018-01-30 00:25:58,550 INFO L226 Difference]: Without dead ends: 11029 [2018-01-30 00:25:58,553 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 381 GetRequests, 337 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 00:25:58,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11029 states. [2018-01-30 00:25:58,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11029 to 10621. [2018-01-30 00:25:58,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10621 states. [2018-01-30 00:25:58,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10621 states to 10621 states and 11990 transitions. [2018-01-30 00:25:58,661 INFO L78 Accepts]: Start accepts. Automaton has 10621 states and 11990 transitions. Word has length 336 [2018-01-30 00:25:58,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:25:58,661 INFO L432 AbstractCegarLoop]: Abstraction has 10621 states and 11990 transitions. [2018-01-30 00:25:58,661 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-30 00:25:58,661 INFO L276 IsEmpty]: Start isEmpty. Operand 10621 states and 11990 transitions. [2018-01-30 00:25:58,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 344 [2018-01-30 00:25:58,667 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:25:58,667 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 44, 44, 43, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:25:58,667 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:25:58,667 INFO L82 PathProgramCache]: Analyzing trace with hash -726043617, now seen corresponding path program 15 times [2018-01-30 00:25:58,667 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:25:58,667 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:25:58,668 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:58,668 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:25:58,668 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:25:58,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:25:58,676 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:25:59,594 INFO L134 CoverageAnalysis]: Checked inductivity of 6746 backedges. 0 proven. 6710 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 00:25:59,594 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:25:59,594 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:25:59,599 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 00:25:59,606 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,613 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,623 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,630 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,631 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,633 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,634 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,636 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,637 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,642 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,644 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,647 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,650 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,652 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,656 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,659 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,664 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,668 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,673 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,678 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,689 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,696 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,703 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,712 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,720 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,730 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,740 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,751 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,762 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,775 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,789 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,804 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,821 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 00:25:59,823 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:25:59,825 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:25:59,839 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 00:25:59,839 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 00:25:59,840 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 00:25:59,840 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 00:25:59,986 INFO L134 CoverageAnalysis]: Checked inductivity of 6746 backedges. 0 proven. 1442 refuted. 0 times theorem prover too weak. 5304 trivial. 0 not checked. [2018-01-30 00:26:00,004 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:26:00,004 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 15] total 60 [2018-01-30 00:26:00,004 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-30 00:26:00,005 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-30 00:26:00,005 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1547, Invalid=1993, Unknown=0, NotChecked=0, Total=3540 [2018-01-30 00:26:00,005 INFO L87 Difference]: Start difference. First operand 10621 states and 11990 transitions. Second operand 60 states. [2018-01-30 00:26:01,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:26:01,993 INFO L93 Difference]: Finished difference Result 11786 states and 13474 transitions. [2018-01-30 00:26:01,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-01-30 00:26:01,994 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 343 [2018-01-30 00:26:01,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:26:01,999 INFO L225 Difference]: With dead ends: 11786 [2018-01-30 00:26:01,999 INFO L226 Difference]: Without dead ends: 11500 [2018-01-30 00:26:02,001 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 430 GetRequests, 331 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2277 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=3471, Invalid=6629, Unknown=0, NotChecked=0, Total=10100 [2018-01-30 00:26:02,003 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11500 states. [2018-01-30 00:26:02,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11500 to 10901. [2018-01-30 00:26:02,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10901 states. [2018-01-30 00:26:02,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10901 states to 10901 states and 12303 transitions. [2018-01-30 00:26:02,098 INFO L78 Accepts]: Start accepts. Automaton has 10901 states and 12303 transitions. Word has length 343 [2018-01-30 00:26:02,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:26:02,099 INFO L432 AbstractCegarLoop]: Abstraction has 10901 states and 12303 transitions. [2018-01-30 00:26:02,099 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-30 00:26:02,099 INFO L276 IsEmpty]: Start isEmpty. Operand 10901 states and 12303 transitions. [2018-01-30 00:26:02,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-01-30 00:26:02,104 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:26:02,104 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 45, 45, 45, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:26:02,104 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:26:02,104 INFO L82 PathProgramCache]: Analyzing trace with hash 1538133925, now seen corresponding path program 23 times [2018-01-30 00:26:02,104 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:26:02,105 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:26:02,105 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:02,105 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:26:02,105 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:02,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:26:02,113 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:26:02,908 INFO L134 CoverageAnalysis]: Checked inductivity of 7075 backedges. 0 proven. 7020 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 00:26:02,908 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:26:02,908 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:26:02,914 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 00:26:02,919 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,925 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,930 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,933 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,936 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,939 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,941 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,944 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,951 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,969 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:02,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,017 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,027 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,038 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,050 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,064 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,079 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,096 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,116 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,135 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,156 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,179 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,204 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,230 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,260 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,293 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,326 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,398 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,451 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 00:26:03,453 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:26:03,456 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:26:03,510 INFO L134 CoverageAnalysis]: Checked inductivity of 7075 backedges. 0 proven. 7020 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 00:26:03,528 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:26:03,528 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-30 00:26:03,529 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-30 00:26:03,529 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-30 00:26:03,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 00:26:03,529 INFO L87 Difference]: Start difference. First operand 10901 states and 12303 transitions. Second operand 48 states. [2018-01-30 00:26:04,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:26:04,106 INFO L93 Difference]: Finished difference Result 11865 states and 13504 transitions. [2018-01-30 00:26:04,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-30 00:26:04,106 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 353 [2018-01-30 00:26:04,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:26:04,113 INFO L225 Difference]: With dead ends: 11865 [2018-01-30 00:26:04,113 INFO L226 Difference]: Without dead ends: 11555 [2018-01-30 00:26:04,115 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 354 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 00:26:04,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11555 states. [2018-01-30 00:26:04,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11555 to 11157. [2018-01-30 00:26:04,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11157 states. [2018-01-30 00:26:04,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11157 states to 11157 states and 12591 transitions. [2018-01-30 00:26:04,216 INFO L78 Accepts]: Start accepts. Automaton has 11157 states and 12591 transitions. Word has length 353 [2018-01-30 00:26:04,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:26:04,216 INFO L432 AbstractCegarLoop]: Abstraction has 11157 states and 12591 transitions. [2018-01-30 00:26:04,216 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-30 00:26:04,216 INFO L276 IsEmpty]: Start isEmpty. Operand 11157 states and 12591 transitions. [2018-01-30 00:26:04,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-01-30 00:26:04,222 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:26:04,222 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 46, 46, 46, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:26:04,222 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:26:04,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1784619614, now seen corresponding path program 24 times [2018-01-30 00:26:04,222 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:26:04,222 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:26:04,223 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:04,223 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:26:04,223 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:04,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:26:04,231 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:26:05,103 INFO L134 CoverageAnalysis]: Checked inductivity of 7392 backedges. 0 proven. 7337 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 00:26:05,103 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:26:05,103 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:26:05,136 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 00:26:05,143 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,144 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,145 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,146 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,147 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,148 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,151 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,152 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,154 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,160 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,166 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,168 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,171 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,174 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,177 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,186 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,190 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,194 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,198 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,203 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,207 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,212 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,219 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,224 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,230 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,250 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,291 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,301 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,312 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,323 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,335 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,351 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,368 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,386 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 00:26:05,387 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 00:26:05,390 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:26:05,447 INFO L134 CoverageAnalysis]: Checked inductivity of 7392 backedges. 0 proven. 7337 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 00:26:05,465 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:26:05,465 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-30 00:26:05,466 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-30 00:26:05,466 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-30 00:26:05,466 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 00:26:05,466 INFO L87 Difference]: Start difference. First operand 11157 states and 12591 transitions. Second operand 49 states. [2018-01-30 00:26:06,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:26:06,066 INFO L93 Difference]: Finished difference Result 12126 states and 13799 transitions. [2018-01-30 00:26:06,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-30 00:26:06,067 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 360 [2018-01-30 00:26:06,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:26:06,073 INFO L225 Difference]: With dead ends: 12126 [2018-01-30 00:26:06,074 INFO L226 Difference]: Without dead ends: 11816 [2018-01-30 00:26:06,076 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 361 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 00:26:06,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11816 states. [2018-01-30 00:26:06,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11816 to 11413. [2018-01-30 00:26:06,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11413 states. [2018-01-30 00:26:06,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11413 states to 11413 states and 12879 transitions. [2018-01-30 00:26:06,179 INFO L78 Accepts]: Start accepts. Automaton has 11413 states and 12879 transitions. Word has length 360 [2018-01-30 00:26:06,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:26:06,180 INFO L432 AbstractCegarLoop]: Abstraction has 11413 states and 12879 transitions. [2018-01-30 00:26:06,180 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-30 00:26:06,180 INFO L276 IsEmpty]: Start isEmpty. Operand 11413 states and 12879 transitions. [2018-01-30 00:26:06,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 368 [2018-01-30 00:26:06,185 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:26:06,185 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 47, 47, 47, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:26:06,185 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:26:06,185 INFO L82 PathProgramCache]: Analyzing trace with hash -1989198459, now seen corresponding path program 25 times [2018-01-30 00:26:06,186 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:26:06,186 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:26:06,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:06,186 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 00:26:06,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:06,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:26:06,194 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 00:26:07,028 INFO L134 CoverageAnalysis]: Checked inductivity of 7716 backedges. 0 proven. 7661 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 00:26:07,029 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 00:26:07,029 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 00:26:07,033 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:26:07,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:26:07,062 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 00:26:07,121 INFO L134 CoverageAnalysis]: Checked inductivity of 7716 backedges. 0 proven. 7661 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 00:26:07,138 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 00:26:07,138 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-30 00:26:07,138 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-30 00:26:07,138 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-30 00:26:07,139 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 00:26:07,139 INFO L87 Difference]: Start difference. First operand 11413 states and 12879 transitions. Second operand 50 states. [2018-01-30 00:26:07,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 00:26:07,785 INFO L93 Difference]: Finished difference Result 12387 states and 14094 transitions. [2018-01-30 00:26:07,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-30 00:26:07,786 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 367 [2018-01-30 00:26:07,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 00:26:07,793 INFO L225 Difference]: With dead ends: 12387 [2018-01-30 00:26:07,793 INFO L226 Difference]: Without dead ends: 12077 [2018-01-30 00:26:07,795 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 368 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 00:26:07,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12077 states. [2018-01-30 00:26:07,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12077 to 11669. [2018-01-30 00:26:07,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11669 states. [2018-01-30 00:26:07,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11669 states to 11669 states and 13167 transitions. [2018-01-30 00:26:07,899 INFO L78 Accepts]: Start accepts. Automaton has 11669 states and 13167 transitions. Word has length 367 [2018-01-30 00:26:07,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 00:26:07,899 INFO L432 AbstractCegarLoop]: Abstraction has 11669 states and 13167 transitions. [2018-01-30 00:26:07,899 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-30 00:26:07,900 INFO L276 IsEmpty]: Start isEmpty. Operand 11669 states and 13167 transitions. [2018-01-30 00:26:07,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2018-01-30 00:26:07,905 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 00:26:07,905 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 48, 48, 48, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 00:26:07,905 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 00:26:07,905 INFO L82 PathProgramCache]: Analyzing trace with hash -345466754, now seen corresponding path program 26 times [2018-01-30 00:26:07,906 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 00:26:07,906 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 00:26:07,906 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:07,906 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 00:26:07,906 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 00:26:07,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 00:26:07,915 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-30 00:26:08,606 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-30 00:26:08,611 WARN L185 ceAbstractionStarter]: Timeout [2018-01-30 00:26:08,611 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 12:26:08 BoogieIcfgContainer [2018-01-30 00:26:08,611 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-30 00:26:08,612 INFO L168 Benchmark]: Toolchain (without parser) took 64630.77 ms. Allocated memory was 148.9 MB in the beginning and 1.5 GB in the end (delta: 1.3 GB). Free memory was 113.9 MB in the beginning and 383.3 MB in the end (delta: -269.4 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. [2018-01-30 00:26:08,612 INFO L168 Benchmark]: CDTParser took 0.12 ms. Allocated memory is still 148.9 MB. Free memory is still 118.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-30 00:26:08,612 INFO L168 Benchmark]: CACSL2BoogieTranslator took 99.90 ms. Allocated memory is still 148.9 MB. Free memory was 113.7 MB in the beginning and 105.8 MB in the end (delta: 7.9 MB). Peak memory consumption was 7.9 MB. Max. memory is 5.3 GB. [2018-01-30 00:26:08,613 INFO L168 Benchmark]: Boogie Preprocessor took 17.17 ms. Allocated memory is still 148.9 MB. Free memory was 105.8 MB in the beginning and 104.4 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-30 00:26:08,613 INFO L168 Benchmark]: RCFGBuilder took 230.59 ms. Allocated memory is still 148.9 MB. Free memory was 104.1 MB in the beginning and 92.6 MB in the end (delta: 11.5 MB). Peak memory consumption was 11.5 MB. Max. memory is 5.3 GB. [2018-01-30 00:26:08,613 INFO L168 Benchmark]: TraceAbstraction took 64280.77 ms. Allocated memory was 148.9 MB in the beginning and 1.5 GB in the end (delta: 1.3 GB). Free memory was 92.4 MB in the beginning and 383.3 MB in the end (delta: -290.9 MB). Peak memory consumption was 1.0 GB. Max. memory is 5.3 GB. [2018-01-30 00:26:08,614 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.12 ms. Allocated memory is still 148.9 MB. Free memory is still 118.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 99.90 ms. Allocated memory is still 148.9 MB. Free memory was 113.7 MB in the beginning and 105.8 MB in the end (delta: 7.9 MB). Peak memory consumption was 7.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 17.17 ms. Allocated memory is still 148.9 MB. Free memory was 105.8 MB in the beginning and 104.4 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * RCFGBuilder took 230.59 ms. Allocated memory is still 148.9 MB. Free memory was 104.1 MB in the beginning and 92.6 MB in the end (delta: 11.5 MB). Peak memory consumption was 11.5 MB. Max. memory is 5.3 GB. * TraceAbstraction took 64280.77 ms. Allocated memory was 148.9 MB in the beginning and 1.5 GB in the end (delta: 1.3 GB). Free memory was 92.4 MB in the beginning and 383.3 MB in the end (delta: -290.9 MB). Peak memory consumption was 1.0 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 2]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 2). Cancelled while BasicCegarLoop was analyzing trace of length 375 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 41 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 32 locations, 1 error locations. TIMEOUT Result, 64.2s OverallTime, 50 OverallIterations, 49 TraceHistogramMax, 28.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3077 SDtfs, 23968 SDslu, 25055 SDs, 0 SdLazy, 45924 SolverSat, 5375 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 18.9s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 10654 GetRequests, 9099 SyntacticMatches, 5 SemanticMatches, 1550 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12634 ImplicationChecksByTransitivity, 21.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=11669occurred in iteration=49, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.7s AutomataMinimizationTime, 49 MinimizatonAttempts, 10084 StatesRemovedByMinimization, 48 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 3.5s SatisfiabilityAnalysisTime, 27.4s InterpolantComputationTime, 18475 NumberOfCodeBlocks, 18099 NumberOfCodeBlocksAsserted, 644 NumberOfCheckSat, 18379 ConstructedInterpolants, 0 QuantifiedInterpolants, 14154367 SizeOfPredicates, 149 NumberOfNonLiveVariables, 11732 ConjunctsInSsa, 1329 ConjunctsInUnsatCore, 96 InterpolantComputations, 2 PerfectInterpolantSequences, 18474/248450 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array_monotonic_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-Benchmark-0-2018-01-30_00-26-08-618.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array_monotonic_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-30_00-26-08-618.csv Completed graceful shutdown