java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-industry-pattern/array_monotonic_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-30 04:16:28,734 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-30 04:16:28,737 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-30 04:16:28,748 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-30 04:16:28,748 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-30 04:16:28,748 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-30 04:16:28,749 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-30 04:16:28,750 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-30 04:16:28,751 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-30 04:16:28,751 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-30 04:16:28,752 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-30 04:16:28,752 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-30 04:16:28,753 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-30 04:16:28,753 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-30 04:16:28,754 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-30 04:16:28,765 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-30 04:16:28,766 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-30 04:16:28,767 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-30 04:16:28,767 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-30 04:16:28,768 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-30 04:16:28,769 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-30 04:16:28,769 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-30 04:16:28,769 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-30 04:16:28,770 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-30 04:16:28,770 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-30 04:16:28,770 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-30 04:16:28,771 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-30 04:16:28,771 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-30 04:16:28,771 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-30 04:16:28,771 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-30 04:16:28,771 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-30 04:16:28,772 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-30 04:16:28,776 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-30 04:16:28,777 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-30 04:16:28,777 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-30 04:16:28,777 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-30 04:16:28,777 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-30 04:16:28,777 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-30 04:16:28,777 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-30 04:16:28,778 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-30 04:16:28,778 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-30 04:16:28,779 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 04:16:28,779 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-30 04:16:28,779 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-30 04:16:28,780 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-30 04:16:28,780 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-30 04:16:28,780 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-30 04:16:28,780 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-30 04:16:28,780 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-30 04:16:28,798 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-30 04:16:28,805 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-30 04:16:28,807 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-30 04:16:28,808 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-30 04:16:28,808 INFO L276 PluginConnector]: CDTParser initialized [2018-01-30 04:16:28,808 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-industry-pattern/array_monotonic_true-unreach-call_true-termination.i [2018-01-30 04:16:28,871 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-30 04:16:28,872 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-30 04:16:28,872 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-30 04:16:28,872 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-30 04:16:28,876 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-30 04:16:28,876 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,878 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c66a539 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28, skipping insertion in model container [2018-01-30 04:16:28,878 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,887 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 04:16:28,896 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 04:16:28,962 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 04:16:28,970 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 04:16:28,972 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28 WrapperNode [2018-01-30 04:16:28,973 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-30 04:16:28,973 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-30 04:16:28,973 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-30 04:16:28,973 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-30 04:16:28,981 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,981 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,986 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,986 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,987 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,989 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,989 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... [2018-01-30 04:16:28,990 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-30 04:16:28,990 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-30 04:16:28,990 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-30 04:16:28,990 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-30 04:16:28,991 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 04:16:29,031 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-30 04:16:29,031 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-30 04:16:29,031 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-30 04:16:29,031 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-30 04:16:29,031 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-30 04:16:29,031 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-30 04:16:29,031 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-30 04:16:29,031 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-30 04:16:29,031 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-30 04:16:29,031 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-30 04:16:29,203 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-30 04:16:29,203 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 04:16:29 BoogieIcfgContainer [2018-01-30 04:16:29,203 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-30 04:16:29,204 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-30 04:16:29,204 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-30 04:16:29,204 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-30 04:16:29,206 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 04:16:29" (1/1) ... [2018-01-30 04:16:29,208 WARN L213 ansformationObserver]: HeapSeparator: input icfg has no '#valid' array -- returning unchanged Icfg! [2018-01-30 04:16:29,225 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 30.01 04:16:29 BasicIcfg [2018-01-30 04:16:29,225 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-30 04:16:29,225 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-30 04:16:29,225 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-30 04:16:29,227 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-30 04:16:29,227 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 30.01 04:16:28" (1/4) ... [2018-01-30 04:16:29,227 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7600b0bc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 04:16:29, skipping insertion in model container [2018-01-30 04:16:29,228 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 04:16:28" (2/4) ... [2018-01-30 04:16:29,228 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7600b0bc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 04:16:29, skipping insertion in model container [2018-01-30 04:16:29,228 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 04:16:29" (3/4) ... [2018-01-30 04:16:29,228 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7600b0bc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 04:16:29, skipping insertion in model container [2018-01-30 04:16:29,228 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 30.01 04:16:29" (4/4) ... [2018-01-30 04:16:29,229 INFO L107 eAbstractionObserver]: Analyzing ICFG array_monotonic_true-unreach-call_true-termination.ileft_unchanged_by_heapseparator [2018-01-30 04:16:29,244 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-30 04:16:29,254 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-30 04:16:29,281 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-30 04:16:29,282 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-30 04:16:29,282 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-30 04:16:29,282 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-30 04:16:29,282 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-30 04:16:29,282 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-30 04:16:29,282 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-30 04:16:29,283 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-30 04:16:29,283 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-30 04:16:29,296 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states. [2018-01-30 04:16:29,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-01-30 04:16:29,301 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:29,302 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:29,302 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:29,305 INFO L82 PathProgramCache]: Analyzing trace with hash -672284335, now seen corresponding path program 1 times [2018-01-30 04:16:29,306 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:29,306 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:29,334 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:29,334 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:29,334 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:29,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:29,354 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:29,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:29,371 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 04:16:29,371 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-30 04:16:29,372 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-30 04:16:29,379 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-30 04:16:29,380 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 04:16:29,381 INFO L87 Difference]: Start difference. First operand 32 states. Second operand 2 states. [2018-01-30 04:16:29,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:29,397 INFO L93 Difference]: Finished difference Result 48 states and 57 transitions. [2018-01-30 04:16:29,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-30 04:16:29,398 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 17 [2018-01-30 04:16:29,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:29,405 INFO L225 Difference]: With dead ends: 48 [2018-01-30 04:16:29,405 INFO L226 Difference]: Without dead ends: 28 [2018-01-30 04:16:29,407 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 04:16:29,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-01-30 04:16:29,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-01-30 04:16:29,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-01-30 04:16:29,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2018-01-30 04:16:29,432 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 17 [2018-01-30 04:16:29,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:29,433 INFO L432 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2018-01-30 04:16:29,433 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-30 04:16:29,433 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2018-01-30 04:16:29,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-01-30 04:16:29,433 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:29,433 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:29,433 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:29,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1615074736, now seen corresponding path program 1 times [2018-01-30 04:16:29,434 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:29,434 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:29,435 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:29,436 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:29,436 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:29,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:29,443 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:29,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:29,503 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 04:16:29,503 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-30 04:16:29,504 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-30 04:16:29,505 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-30 04:16:29,505 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 04:16:29,505 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand 3 states. [2018-01-30 04:16:29,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:29,662 INFO L93 Difference]: Finished difference Result 53 states and 63 transitions. [2018-01-30 04:16:29,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-30 04:16:29,662 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 18 [2018-01-30 04:16:29,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:29,664 INFO L225 Difference]: With dead ends: 53 [2018-01-30 04:16:29,664 INFO L226 Difference]: Without dead ends: 41 [2018-01-30 04:16:29,664 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 04:16:29,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-01-30 04:16:29,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 30. [2018-01-30 04:16:29,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-01-30 04:16:29,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2018-01-30 04:16:29,670 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 18 [2018-01-30 04:16:29,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:29,670 INFO L432 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2018-01-30 04:16:29,670 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-30 04:16:29,670 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2018-01-30 04:16:29,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-01-30 04:16:29,670 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:29,671 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:29,671 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:29,671 INFO L82 PathProgramCache]: Analyzing trace with hash 1748423740, now seen corresponding path program 1 times [2018-01-30 04:16:29,671 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:29,671 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:29,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:29,672 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:29,672 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:29,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:29,680 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:29,743 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:29,743 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:29,744 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:29,755 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:29,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:29,776 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:29,787 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:29,803 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:29,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-30 04:16:29,804 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-30 04:16:29,804 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-30 04:16:29,804 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 04:16:29,804 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand 4 states. [2018-01-30 04:16:30,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:30,061 INFO L93 Difference]: Finished difference Result 66 states and 79 transitions. [2018-01-30 04:16:30,062 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-30 04:16:30,062 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-01-30 04:16:30,062 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:30,062 INFO L225 Difference]: With dead ends: 66 [2018-01-30 04:16:30,062 INFO L226 Difference]: Without dead ends: 54 [2018-01-30 04:16:30,063 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 04:16:30,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-30 04:16:30,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 38. [2018-01-30 04:16:30,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-01-30 04:16:30,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 43 transitions. [2018-01-30 04:16:30,066 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 43 transitions. Word has length 25 [2018-01-30 04:16:30,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:30,066 INFO L432 AbstractCegarLoop]: Abstraction has 38 states and 43 transitions. [2018-01-30 04:16:30,067 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-30 04:16:30,067 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 43 transitions. [2018-01-30 04:16:30,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-01-30 04:16:30,067 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:30,067 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:30,067 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:30,067 INFO L82 PathProgramCache]: Analyzing trace with hash -629743568, now seen corresponding path program 2 times [2018-01-30 04:16:30,068 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:30,068 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:30,068 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:30,068 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:30,068 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:30,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:30,081 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:30,135 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:30,136 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:30,136 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:30,146 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:30,152 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:30,160 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:30,161 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:30,162 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:30,166 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:30,182 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:30,183 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-30 04:16:30,183 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-30 04:16:30,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-30 04:16:30,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 04:16:30,183 INFO L87 Difference]: Start difference. First operand 38 states and 43 transitions. Second operand 5 states. [2018-01-30 04:16:30,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:30,263 INFO L93 Difference]: Finished difference Result 79 states and 95 transitions. [2018-01-30 04:16:30,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-30 04:16:30,263 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 32 [2018-01-30 04:16:30,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:30,264 INFO L225 Difference]: With dead ends: 79 [2018-01-30 04:16:30,264 INFO L226 Difference]: Without dead ends: 67 [2018-01-30 04:16:30,264 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 33 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 04:16:30,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-01-30 04:16:30,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 46. [2018-01-30 04:16:30,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-01-30 04:16:30,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 52 transitions. [2018-01-30 04:16:30,269 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 52 transitions. Word has length 32 [2018-01-30 04:16:30,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:30,269 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 52 transitions. [2018-01-30 04:16:30,269 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-30 04:16:30,270 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 52 transitions. [2018-01-30 04:16:30,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-01-30 04:16:30,270 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:30,270 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:30,270 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:30,270 INFO L82 PathProgramCache]: Analyzing trace with hash 264452540, now seen corresponding path program 3 times [2018-01-30 04:16:30,270 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:30,270 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:30,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:30,271 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:30,271 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:30,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:30,278 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:30,367 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:30,367 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:30,367 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:30,381 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:16:30,385 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:30,386 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:30,387 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:30,390 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:30,390 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:30,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:30,396 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:30,414 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:30,414 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-30 04:16:30,414 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-30 04:16:30,415 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-30 04:16:30,415 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 04:16:30,415 INFO L87 Difference]: Start difference. First operand 46 states and 52 transitions. Second operand 6 states. [2018-01-30 04:16:30,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:30,518 INFO L93 Difference]: Finished difference Result 92 states and 111 transitions. [2018-01-30 04:16:30,518 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-30 04:16:30,518 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-01-30 04:16:30,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:30,519 INFO L225 Difference]: With dead ends: 92 [2018-01-30 04:16:30,519 INFO L226 Difference]: Without dead ends: 80 [2018-01-30 04:16:30,519 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 40 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 04:16:30,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-01-30 04:16:30,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 54. [2018-01-30 04:16:30,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-01-30 04:16:30,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 61 transitions. [2018-01-30 04:16:30,523 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 61 transitions. Word has length 39 [2018-01-30 04:16:30,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:30,523 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 61 transitions. [2018-01-30 04:16:30,523 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-30 04:16:30,523 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 61 transitions. [2018-01-30 04:16:30,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-30 04:16:30,524 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:30,524 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:30,524 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:30,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1531622736, now seen corresponding path program 4 times [2018-01-30 04:16:30,524 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:30,524 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:30,525 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:30,525 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:30,525 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:30,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:30,532 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:30,644 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:30,644 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:30,644 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:30,658 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:16:30,678 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:30,679 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:30,783 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:30,784 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,824 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,824 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 04:16:30,850 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:30,853 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:30,853 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,857 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,858 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:30,885 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:30,886 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:30,887 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,934 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,934 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:30,971 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:30,973 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:30,973 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,981 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:30,981 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 04:16:31,013 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 15 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:31,030 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:31,030 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-01-30 04:16:31,030 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-30 04:16:31,030 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-30 04:16:31,030 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-01-30 04:16:31,031 INFO L87 Difference]: Start difference. First operand 54 states and 61 transitions. Second operand 13 states. [2018-01-30 04:16:31,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:31,372 INFO L93 Difference]: Finished difference Result 176 states and 216 transitions. [2018-01-30 04:16:31,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-30 04:16:31,372 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 46 [2018-01-30 04:16:31,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:31,373 INFO L225 Difference]: With dead ends: 176 [2018-01-30 04:16:31,373 INFO L226 Difference]: Without dead ends: 164 [2018-01-30 04:16:31,374 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=83, Invalid=189, Unknown=0, NotChecked=0, Total=272 [2018-01-30 04:16:31,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-01-30 04:16:31,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 101. [2018-01-30 04:16:31,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-01-30 04:16:31,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 114 transitions. [2018-01-30 04:16:31,380 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 114 transitions. Word has length 46 [2018-01-30 04:16:31,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:31,380 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 114 transitions. [2018-01-30 04:16:31,380 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-30 04:16:31,380 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 114 transitions. [2018-01-30 04:16:31,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-30 04:16:31,381 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:31,381 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:31,381 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:31,381 INFO L82 PathProgramCache]: Analyzing trace with hash 916560954, now seen corresponding path program 1 times [2018-01-30 04:16:31,381 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:31,381 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:31,382 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:31,382 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:31,382 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:31,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:31,390 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:31,441 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:31,442 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:31,442 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:31,447 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:31,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:31,460 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:31,472 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:31,490 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:31,490 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-30 04:16:31,491 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-30 04:16:31,491 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-30 04:16:31,491 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 04:16:31,491 INFO L87 Difference]: Start difference. First operand 101 states and 114 transitions. Second operand 8 states. [2018-01-30 04:16:31,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:31,618 INFO L93 Difference]: Finished difference Result 175 states and 208 transitions. [2018-01-30 04:16:31,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-30 04:16:31,618 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 54 [2018-01-30 04:16:31,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:31,619 INFO L225 Difference]: With dead ends: 175 [2018-01-30 04:16:31,619 INFO L226 Difference]: Without dead ends: 159 [2018-01-30 04:16:31,619 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 04:16:31,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-01-30 04:16:31,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 117. [2018-01-30 04:16:31,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-01-30 04:16:31,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 132 transitions. [2018-01-30 04:16:31,625 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 132 transitions. Word has length 54 [2018-01-30 04:16:31,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:31,625 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 132 transitions. [2018-01-30 04:16:31,625 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-30 04:16:31,625 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 132 transitions. [2018-01-30 04:16:31,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-01-30 04:16:31,626 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:31,626 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:31,626 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:31,626 INFO L82 PathProgramCache]: Analyzing trace with hash -65487246, now seen corresponding path program 2 times [2018-01-30 04:16:31,626 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:31,627 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:31,627 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:31,627 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:31,627 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:31,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:31,635 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:31,731 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:31,732 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:31,732 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:31,737 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:31,741 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:31,746 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:31,748 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:31,749 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:31,755 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:31,771 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:31,771 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-30 04:16:31,771 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-30 04:16:31,771 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-30 04:16:31,772 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 04:16:31,772 INFO L87 Difference]: Start difference. First operand 117 states and 132 transitions. Second operand 9 states. [2018-01-30 04:16:31,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:31,942 INFO L93 Difference]: Finished difference Result 196 states and 233 transitions. [2018-01-30 04:16:31,942 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-30 04:16:31,942 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 61 [2018-01-30 04:16:31,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:31,943 INFO L225 Difference]: With dead ends: 196 [2018-01-30 04:16:31,943 INFO L226 Difference]: Without dead ends: 180 [2018-01-30 04:16:31,943 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 04:16:31,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-01-30 04:16:31,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 133. [2018-01-30 04:16:31,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-01-30 04:16:31,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 150 transitions. [2018-01-30 04:16:31,948 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 150 transitions. Word has length 61 [2018-01-30 04:16:31,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:31,951 INFO L432 AbstractCegarLoop]: Abstraction has 133 states and 150 transitions. [2018-01-30 04:16:31,951 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-30 04:16:31,951 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 150 transitions. [2018-01-30 04:16:31,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-30 04:16:31,952 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:31,952 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:31,952 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:31,952 INFO L82 PathProgramCache]: Analyzing trace with hash 335097146, now seen corresponding path program 3 times [2018-01-30 04:16:31,952 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:31,952 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:31,953 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:31,953 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:31,953 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:31,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:31,960 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:32,100 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 161 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:32,100 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:32,100 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:32,105 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:16:32,110 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,111 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,114 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,116 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,119 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:32,119 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:32,121 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:32,131 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:32,132 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:32,135 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:32,135 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 04:16:32,181 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 38 refuted. 0 times theorem prover too weak. 123 trivial. 0 not checked. [2018-01-30 04:16:32,199 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:32,200 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 15 [2018-01-30 04:16:32,200 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-30 04:16:32,200 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-30 04:16:32,200 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=137, Unknown=0, NotChecked=0, Total=210 [2018-01-30 04:16:32,200 INFO L87 Difference]: Start difference. First operand 133 states and 150 transitions. Second operand 15 states. [2018-01-30 04:16:32,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:32,470 INFO L93 Difference]: Finished difference Result 262 states and 320 transitions. [2018-01-30 04:16:32,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-30 04:16:32,470 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-01-30 04:16:32,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:32,471 INFO L225 Difference]: With dead ends: 262 [2018-01-30 04:16:32,471 INFO L226 Difference]: Without dead ends: 246 [2018-01-30 04:16:32,472 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=154, Invalid=352, Unknown=0, NotChecked=0, Total=506 [2018-01-30 04:16:32,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-30 04:16:32,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 157. [2018-01-30 04:16:32,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-01-30 04:16:32,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 177 transitions. [2018-01-30 04:16:32,478 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 177 transitions. Word has length 68 [2018-01-30 04:16:32,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:32,478 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 177 transitions. [2018-01-30 04:16:32,478 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-30 04:16:32,478 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 177 transitions. [2018-01-30 04:16:32,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-30 04:16:32,479 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:32,479 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:32,479 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:32,479 INFO L82 PathProgramCache]: Analyzing trace with hash 380399272, now seen corresponding path program 1 times [2018-01-30 04:16:32,479 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:32,479 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:32,480 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:32,480 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:32,480 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:32,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:32,487 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:32,642 INFO L134 CoverageAnalysis]: Checked inductivity of 215 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:32,642 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:32,642 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:32,649 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:32,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:32,658 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:32,665 INFO L134 CoverageAnalysis]: Checked inductivity of 215 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:32,684 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:32,684 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-30 04:16:32,684 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-30 04:16:32,684 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-30 04:16:32,684 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 04:16:32,684 INFO L87 Difference]: Start difference. First operand 157 states and 177 transitions. Second operand 11 states. [2018-01-30 04:16:32,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:32,851 INFO L93 Difference]: Finished difference Result 250 states and 295 transitions. [2018-01-30 04:16:32,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-30 04:16:32,852 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 78 [2018-01-30 04:16:32,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:32,852 INFO L225 Difference]: With dead ends: 250 [2018-01-30 04:16:32,852 INFO L226 Difference]: Without dead ends: 226 [2018-01-30 04:16:32,853 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 04:16:32,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-01-30 04:16:32,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 173. [2018-01-30 04:16:32,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-01-30 04:16:32,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 195 transitions. [2018-01-30 04:16:32,859 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 195 transitions. Word has length 78 [2018-01-30 04:16:32,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:32,860 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 195 transitions. [2018-01-30 04:16:32,860 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-30 04:16:32,860 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 195 transitions. [2018-01-30 04:16:32,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-01-30 04:16:32,861 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:32,861 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:32,861 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:32,861 INFO L82 PathProgramCache]: Analyzing trace with hash -1659768012, now seen corresponding path program 2 times [2018-01-30 04:16:32,861 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:32,861 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:32,862 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:32,862 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:32,862 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:32,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:32,869 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:32,960 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 0 proven. 270 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:32,960 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:32,960 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:32,968 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:32,972 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:32,982 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:32,990 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:32,991 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:32,999 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 0 proven. 270 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:33,024 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:33,025 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-30 04:16:33,025 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-30 04:16:33,025 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-30 04:16:33,025 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 04:16:33,025 INFO L87 Difference]: Start difference. First operand 173 states and 195 transitions. Second operand 12 states. [2018-01-30 04:16:33,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:33,364 INFO L93 Difference]: Finished difference Result 271 states and 320 transitions. [2018-01-30 04:16:33,364 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-30 04:16:33,364 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 85 [2018-01-30 04:16:33,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:33,365 INFO L225 Difference]: With dead ends: 271 [2018-01-30 04:16:33,365 INFO L226 Difference]: Without dead ends: 247 [2018-01-30 04:16:33,365 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 04:16:33,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-01-30 04:16:33,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 189. [2018-01-30 04:16:33,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-01-30 04:16:33,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 213 transitions. [2018-01-30 04:16:33,371 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 213 transitions. Word has length 85 [2018-01-30 04:16:33,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:33,371 INFO L432 AbstractCegarLoop]: Abstraction has 189 states and 213 transitions. [2018-01-30 04:16:33,371 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-30 04:16:33,371 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 213 transitions. [2018-01-30 04:16:33,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-30 04:16:33,372 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:33,372 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:33,372 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:33,372 INFO L82 PathProgramCache]: Analyzing trace with hash -179013336, now seen corresponding path program 3 times [2018-01-30 04:16:33,372 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:33,372 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:33,373 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:33,373 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:33,373 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:33,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:33,392 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:33,699 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 335 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:33,700 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:33,700 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:33,711 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:16:33,718 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,721 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,722 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,723 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,724 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,727 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,731 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,733 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,734 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,736 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:33,737 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:33,738 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:33,746 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 335 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:33,763 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:33,763 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-30 04:16:33,763 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-30 04:16:33,763 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-30 04:16:33,763 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 04:16:33,763 INFO L87 Difference]: Start difference. First operand 189 states and 213 transitions. Second operand 13 states. [2018-01-30 04:16:33,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:33,968 INFO L93 Difference]: Finished difference Result 292 states and 345 transitions. [2018-01-30 04:16:33,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-30 04:16:33,969 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 92 [2018-01-30 04:16:33,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:33,970 INFO L225 Difference]: With dead ends: 292 [2018-01-30 04:16:33,970 INFO L226 Difference]: Without dead ends: 268 [2018-01-30 04:16:33,970 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 04:16:33,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states. [2018-01-30 04:16:33,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 205. [2018-01-30 04:16:33,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-01-30 04:16:33,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 231 transitions. [2018-01-30 04:16:33,974 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 231 transitions. Word has length 92 [2018-01-30 04:16:33,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:33,974 INFO L432 AbstractCegarLoop]: Abstraction has 205 states and 231 transitions. [2018-01-30 04:16:33,974 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-30 04:16:33,974 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 231 transitions. [2018-01-30 04:16:33,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-01-30 04:16:33,975 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:33,975 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 11, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:33,975 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:33,975 INFO L82 PathProgramCache]: Analyzing trace with hash 767629492, now seen corresponding path program 4 times [2018-01-30 04:16:33,976 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:33,976 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:33,976 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:33,976 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:33,976 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:33,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:33,983 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:34,070 INFO L134 CoverageAnalysis]: Checked inductivity of 410 backedges. 0 proven. 407 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:34,071 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:34,071 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:34,076 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:16:34,094 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:34,096 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:34,118 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:34,118 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,178 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,178 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 04:16:34,495 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,496 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,496 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,500 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,500 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,510 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,511 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,511 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,515 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,515 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,533 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,534 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,535 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,540 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,540 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,552 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,553 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,553 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,566 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,567 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,603 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,605 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,605 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,608 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,608 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,636 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,637 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,637 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,653 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,653 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,691 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,692 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,692 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,696 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,696 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,711 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,712 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,712 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,715 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,716 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:34,733 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:34,741 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:34,741 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,745 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:34,745 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 04:16:34,771 INFO L134 CoverageAnalysis]: Checked inductivity of 410 backedges. 228 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:34,787 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:34,788 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 16] total 28 [2018-01-30 04:16:34,788 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-30 04:16:34,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-30 04:16:34,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=542, Unknown=0, NotChecked=0, Total=756 [2018-01-30 04:16:34,788 INFO L87 Difference]: Start difference. First operand 205 states and 231 transitions. Second operand 28 states. [2018-01-30 04:16:35,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:35,448 INFO L93 Difference]: Finished difference Result 560 states and 668 transitions. [2018-01-30 04:16:35,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-30 04:16:35,448 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 99 [2018-01-30 04:16:35,448 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:35,450 INFO L225 Difference]: With dead ends: 560 [2018-01-30 04:16:35,450 INFO L226 Difference]: Without dead ends: 536 [2018-01-30 04:16:35,450 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 85 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 391 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=354, Invalid=1052, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 04:16:35,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 536 states. [2018-01-30 04:16:35,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 536 to 397. [2018-01-30 04:16:35,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 397 states. [2018-01-30 04:16:35,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 397 states and 449 transitions. [2018-01-30 04:16:35,462 INFO L78 Accepts]: Start accepts. Automaton has 397 states and 449 transitions. Word has length 99 [2018-01-30 04:16:35,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:35,462 INFO L432 AbstractCegarLoop]: Abstraction has 397 states and 449 transitions. [2018-01-30 04:16:35,462 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-30 04:16:35,462 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 449 transitions. [2018-01-30 04:16:35,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-01-30 04:16:35,464 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:35,464 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 11, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:35,464 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:35,464 INFO L82 PathProgramCache]: Analyzing trace with hash -1493304130, now seen corresponding path program 1 times [2018-01-30 04:16:35,464 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:35,464 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:35,465 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:35,465 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:35,465 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:35,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:35,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:35,604 INFO L134 CoverageAnalysis]: Checked inductivity of 489 backedges. 0 proven. 486 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:35,605 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:35,605 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:35,609 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:35,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:35,619 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:35,628 INFO L134 CoverageAnalysis]: Checked inductivity of 489 backedges. 0 proven. 486 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:35,647 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:35,647 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-30 04:16:35,648 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-30 04:16:35,648 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-30 04:16:35,648 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 04:16:35,648 INFO L87 Difference]: Start difference. First operand 397 states and 449 transitions. Second operand 15 states. [2018-01-30 04:16:35,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:35,929 INFO L93 Difference]: Finished difference Result 551 states and 644 transitions. [2018-01-30 04:16:35,930 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-30 04:16:35,930 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 107 [2018-01-30 04:16:35,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:35,931 INFO L225 Difference]: With dead ends: 551 [2018-01-30 04:16:35,931 INFO L226 Difference]: Without dead ends: 517 [2018-01-30 04:16:35,932 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 04:16:35,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-01-30 04:16:35,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 429. [2018-01-30 04:16:35,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 429 states. [2018-01-30 04:16:35,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 429 states to 429 states and 485 transitions. [2018-01-30 04:16:35,939 INFO L78 Accepts]: Start accepts. Automaton has 429 states and 485 transitions. Word has length 107 [2018-01-30 04:16:35,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:35,939 INFO L432 AbstractCegarLoop]: Abstraction has 429 states and 485 transitions. [2018-01-30 04:16:35,940 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-30 04:16:35,940 INFO L276 IsEmpty]: Start isEmpty. Operand 429 states and 485 transitions. [2018-01-30 04:16:35,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-01-30 04:16:35,940 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:35,940 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 13, 12, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:35,941 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:35,941 INFO L82 PathProgramCache]: Analyzing trace with hash 333348958, now seen corresponding path program 2 times [2018-01-30 04:16:35,941 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:35,941 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:35,941 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:35,941 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:35,941 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:35,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:35,947 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:36,061 INFO L134 CoverageAnalysis]: Checked inductivity of 575 backedges. 0 proven. 572 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:36,061 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:36,062 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:36,073 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:36,078 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:36,084 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:36,085 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:36,086 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:36,097 INFO L134 CoverageAnalysis]: Checked inductivity of 575 backedges. 0 proven. 572 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:36,114 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:36,114 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-30 04:16:36,114 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-30 04:16:36,115 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-30 04:16:36,115 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 04:16:36,115 INFO L87 Difference]: Start difference. First operand 429 states and 485 transitions. Second operand 16 states. [2018-01-30 04:16:36,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:36,659 INFO L93 Difference]: Finished difference Result 588 states and 687 transitions. [2018-01-30 04:16:36,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-30 04:16:36,660 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 114 [2018-01-30 04:16:36,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:36,661 INFO L225 Difference]: With dead ends: 588 [2018-01-30 04:16:36,661 INFO L226 Difference]: Without dead ends: 554 [2018-01-30 04:16:36,662 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 04:16:36,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 554 states. [2018-01-30 04:16:36,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 554 to 461. [2018-01-30 04:16:36,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-01-30 04:16:36,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 521 transitions. [2018-01-30 04:16:36,669 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 521 transitions. Word has length 114 [2018-01-30 04:16:36,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:36,669 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 521 transitions. [2018-01-30 04:16:36,669 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-30 04:16:36,669 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 521 transitions. [2018-01-30 04:16:36,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-01-30 04:16:36,677 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:36,677 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 14, 13, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:36,677 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:36,677 INFO L82 PathProgramCache]: Analyzing trace with hash -1850693442, now seen corresponding path program 3 times [2018-01-30 04:16:36,677 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:36,677 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:36,678 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:36,678 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:36,678 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:36,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:36,685 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:36,809 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 0 proven. 665 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-01-30 04:16:36,809 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:36,810 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:36,814 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:16:36,818 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,835 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,842 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,861 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,871 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,882 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,888 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,902 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,906 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,907 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,909 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,911 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,914 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:36,915 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:36,916 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:36,921 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:36,921 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:36,922 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:36,922 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 04:16:37,001 INFO L134 CoverageAnalysis]: Checked inductivity of 668 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 498 trivial. 0 not checked. [2018-01-30 04:16:37,018 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:37,018 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 9] total 24 [2018-01-30 04:16:37,018 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-30 04:16:37,018 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-30 04:16:37,019 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=340, Unknown=0, NotChecked=0, Total=552 [2018-01-30 04:16:37,019 INFO L87 Difference]: Start difference. First operand 461 states and 521 transitions. Second operand 24 states. [2018-01-30 04:16:37,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:37,823 INFO L93 Difference]: Finished difference Result 700 states and 834 transitions. [2018-01-30 04:16:37,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-30 04:16:37,824 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 121 [2018-01-30 04:16:37,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:37,825 INFO L225 Difference]: With dead ends: 700 [2018-01-30 04:16:37,825 INFO L226 Difference]: Without dead ends: 666 [2018-01-30 04:16:37,826 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 312 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=450, Invalid=956, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 04:16:37,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666 states. [2018-01-30 04:16:37,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666 to 505. [2018-01-30 04:16:37,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 505 states. [2018-01-30 04:16:37,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 505 states to 505 states and 570 transitions. [2018-01-30 04:16:37,833 INFO L78 Accepts]: Start accepts. Automaton has 505 states and 570 transitions. Word has length 121 [2018-01-30 04:16:37,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:37,833 INFO L432 AbstractCegarLoop]: Abstraction has 505 states and 570 transitions. [2018-01-30 04:16:37,833 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-30 04:16:37,833 INFO L276 IsEmpty]: Start isEmpty. Operand 505 states and 570 transitions. [2018-01-30 04:16:37,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-01-30 04:16:37,834 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:37,834 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 15, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:37,834 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:37,834 INFO L82 PathProgramCache]: Analyzing trace with hash -1779019604, now seen corresponding path program 5 times [2018-01-30 04:16:37,835 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:37,835 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:37,835 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:37,835 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:37,835 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:37,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:37,841 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:37,981 INFO L134 CoverageAnalysis]: Checked inductivity of 775 backedges. 0 proven. 765 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:37,982 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:37,982 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:37,987 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 04:16:37,991 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,993 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,995 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:37,998 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,000 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,001 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,008 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,010 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,013 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,018 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:38,018 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:38,020 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:38,035 INFO L134 CoverageAnalysis]: Checked inductivity of 775 backedges. 0 proven. 765 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:38,052 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:38,052 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-30 04:16:38,053 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-30 04:16:38,053 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-30 04:16:38,053 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 04:16:38,053 INFO L87 Difference]: Start difference. First operand 505 states and 570 transitions. Second operand 18 states. [2018-01-30 04:16:38,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:38,599 INFO L93 Difference]: Finished difference Result 678 states and 789 transitions. [2018-01-30 04:16:38,600 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-30 04:16:38,600 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 131 [2018-01-30 04:16:38,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:38,601 INFO L225 Difference]: With dead ends: 678 [2018-01-30 04:16:38,601 INFO L226 Difference]: Without dead ends: 632 [2018-01-30 04:16:38,601 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 132 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 04:16:38,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 632 states. [2018-01-30 04:16:38,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 632 to 537. [2018-01-30 04:16:38,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-01-30 04:16:38,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 606 transitions. [2018-01-30 04:16:38,609 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 606 transitions. Word has length 131 [2018-01-30 04:16:38,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:38,609 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 606 transitions. [2018-01-30 04:16:38,609 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-30 04:16:38,610 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 606 transitions. [2018-01-30 04:16:38,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-30 04:16:38,610 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:38,611 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 16, 16, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:38,611 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:38,611 INFO L82 PathProgramCache]: Analyzing trace with hash 956599200, now seen corresponding path program 6 times [2018-01-30 04:16:38,611 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:38,611 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:38,611 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:38,611 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:38,611 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:38,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:38,617 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:38,983 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 872 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:38,983 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:38,983 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:38,987 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 04:16:38,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:38,994 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:38,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:38,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:38,997 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:38,998 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:38,999 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,000 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,002 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,003 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,005 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,006 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,008 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,010 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,012 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,014 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,017 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:39,017 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:39,018 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:39,030 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 0 proven. 872 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:39,047 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:39,048 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-30 04:16:39,048 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-30 04:16:39,048 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-30 04:16:39,048 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 04:16:39,048 INFO L87 Difference]: Start difference. First operand 537 states and 606 transitions. Second operand 19 states. [2018-01-30 04:16:39,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:39,207 INFO L93 Difference]: Finished difference Result 715 states and 832 transitions. [2018-01-30 04:16:39,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-30 04:16:39,207 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 138 [2018-01-30 04:16:39,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:39,209 INFO L225 Difference]: With dead ends: 715 [2018-01-30 04:16:39,209 INFO L226 Difference]: Without dead ends: 669 [2018-01-30 04:16:39,209 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 156 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 04:16:39,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 669 states. [2018-01-30 04:16:39,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 669 to 569. [2018-01-30 04:16:39,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 569 states. [2018-01-30 04:16:39,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 569 states to 569 states and 642 transitions. [2018-01-30 04:16:39,216 INFO L78 Accepts]: Start accepts. Automaton has 569 states and 642 transitions. Word has length 138 [2018-01-30 04:16:39,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:39,216 INFO L432 AbstractCegarLoop]: Abstraction has 569 states and 642 transitions. [2018-01-30 04:16:39,216 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-30 04:16:39,217 INFO L276 IsEmpty]: Start isEmpty. Operand 569 states and 642 transitions. [2018-01-30 04:16:39,217 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 146 [2018-01-30 04:16:39,218 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:39,218 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 17, 17, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:39,218 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:39,218 INFO L82 PathProgramCache]: Analyzing trace with hash -1325410772, now seen corresponding path program 7 times [2018-01-30 04:16:39,218 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:39,218 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:39,218 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:39,218 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:39,218 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:39,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:39,224 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:39,448 INFO L134 CoverageAnalysis]: Checked inductivity of 996 backedges. 0 proven. 986 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:39,448 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:39,448 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:39,453 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:39,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:39,466 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:39,481 INFO L134 CoverageAnalysis]: Checked inductivity of 996 backedges. 0 proven. 986 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:39,497 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:39,498 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-30 04:16:39,498 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-30 04:16:39,498 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-30 04:16:39,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 04:16:39,498 INFO L87 Difference]: Start difference. First operand 569 states and 642 transitions. Second operand 20 states. [2018-01-30 04:16:40,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:40,274 INFO L93 Difference]: Finished difference Result 752 states and 875 transitions. [2018-01-30 04:16:40,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-30 04:16:40,274 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 145 [2018-01-30 04:16:40,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:40,276 INFO L225 Difference]: With dead ends: 752 [2018-01-30 04:16:40,276 INFO L226 Difference]: Without dead ends: 706 [2018-01-30 04:16:40,276 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 146 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 04:16:40,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states. [2018-01-30 04:16:40,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 601. [2018-01-30 04:16:40,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 601 states. [2018-01-30 04:16:40,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 601 states to 601 states and 678 transitions. [2018-01-30 04:16:40,291 INFO L78 Accepts]: Start accepts. Automaton has 601 states and 678 transitions. Word has length 145 [2018-01-30 04:16:40,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:40,291 INFO L432 AbstractCegarLoop]: Abstraction has 601 states and 678 transitions. [2018-01-30 04:16:40,291 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-30 04:16:40,291 INFO L276 IsEmpty]: Start isEmpty. Operand 601 states and 678 transitions. [2018-01-30 04:16:40,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-01-30 04:16:40,292 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:40,292 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 18, 18, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:40,292 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:40,293 INFO L82 PathProgramCache]: Analyzing trace with hash 1052890656, now seen corresponding path program 8 times [2018-01-30 04:16:40,293 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:40,293 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:40,293 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:40,293 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:40,293 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:40,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:40,300 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:40,470 INFO L134 CoverageAnalysis]: Checked inductivity of 1117 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:40,470 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:40,470 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:40,474 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:40,482 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:40,489 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:40,491 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:40,493 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:40,512 INFO L134 CoverageAnalysis]: Checked inductivity of 1117 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:40,529 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:40,529 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-30 04:16:40,530 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-30 04:16:40,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-30 04:16:40,530 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 04:16:40,530 INFO L87 Difference]: Start difference. First operand 601 states and 678 transitions. Second operand 21 states. [2018-01-30 04:16:40,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:40,796 INFO L93 Difference]: Finished difference Result 789 states and 918 transitions. [2018-01-30 04:16:40,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-30 04:16:40,796 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 152 [2018-01-30 04:16:40,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:40,798 INFO L225 Difference]: With dead ends: 789 [2018-01-30 04:16:40,798 INFO L226 Difference]: Without dead ends: 743 [2018-01-30 04:16:40,798 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 04:16:40,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 743 states. [2018-01-30 04:16:40,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 743 to 633. [2018-01-30 04:16:40,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 633 states. [2018-01-30 04:16:40,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 714 transitions. [2018-01-30 04:16:40,809 INFO L78 Accepts]: Start accepts. Automaton has 633 states and 714 transitions. Word has length 152 [2018-01-30 04:16:40,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:40,809 INFO L432 AbstractCegarLoop]: Abstraction has 633 states and 714 transitions. [2018-01-30 04:16:40,809 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-30 04:16:40,809 INFO L276 IsEmpty]: Start isEmpty. Operand 633 states and 714 transitions. [2018-01-30 04:16:40,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-01-30 04:16:40,810 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:40,810 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 19, 19, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:40,810 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:40,810 INFO L82 PathProgramCache]: Analyzing trace with hash 875674540, now seen corresponding path program 9 times [2018-01-30 04:16:40,810 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:40,811 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:40,811 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:40,811 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:40,811 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:40,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:40,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:41,065 INFO L134 CoverageAnalysis]: Checked inductivity of 1245 backedges. 0 proven. 1235 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:41,065 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:41,065 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:41,070 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:16:41,074 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,076 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,077 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,078 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,079 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,080 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,082 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,083 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,090 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,093 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,103 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,107 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,111 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:41,115 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:41,117 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:41,132 INFO L134 CoverageAnalysis]: Checked inductivity of 1245 backedges. 0 proven. 1235 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:41,149 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:41,149 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-30 04:16:41,149 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-30 04:16:41,149 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-30 04:16:41,150 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 04:16:41,150 INFO L87 Difference]: Start difference. First operand 633 states and 714 transitions. Second operand 22 states. [2018-01-30 04:16:41,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:41,341 INFO L93 Difference]: Finished difference Result 826 states and 961 transitions. [2018-01-30 04:16:41,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-30 04:16:41,341 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 159 [2018-01-30 04:16:41,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:41,343 INFO L225 Difference]: With dead ends: 826 [2018-01-30 04:16:41,343 INFO L226 Difference]: Without dead ends: 780 [2018-01-30 04:16:41,343 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 180 GetRequests, 160 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 04:16:41,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 780 states. [2018-01-30 04:16:41,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 780 to 665. [2018-01-30 04:16:41,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 665 states. [2018-01-30 04:16:41,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 665 states to 665 states and 750 transitions. [2018-01-30 04:16:41,350 INFO L78 Accepts]: Start accepts. Automaton has 665 states and 750 transitions. Word has length 159 [2018-01-30 04:16:41,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:41,350 INFO L432 AbstractCegarLoop]: Abstraction has 665 states and 750 transitions. [2018-01-30 04:16:41,350 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-30 04:16:41,350 INFO L276 IsEmpty]: Start isEmpty. Operand 665 states and 750 transitions. [2018-01-30 04:16:41,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-30 04:16:41,351 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:41,351 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:41,351 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:41,351 INFO L82 PathProgramCache]: Analyzing trace with hash 1344979104, now seen corresponding path program 10 times [2018-01-30 04:16:41,351 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:41,351 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:41,352 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:41,352 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:41,352 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:41,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:41,358 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:41,659 INFO L134 CoverageAnalysis]: Checked inductivity of 1380 backedges. 0 proven. 1370 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:41,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:41,659 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:41,664 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:16:41,676 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:41,678 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:41,688 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:41,688 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,690 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,691 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 04:16:41,708 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,709 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,710 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,713 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,713 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,734 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,735 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,736 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,744 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,744 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,760 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,760 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,761 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,764 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,764 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,779 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,780 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,780 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,784 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,784 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,801 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,802 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,802 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,806 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,807 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,822 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,823 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,823 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,828 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,828 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,860 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,862 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,862 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,867 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,867 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,888 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,889 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,890 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,893 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,893 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,913 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,914 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,918 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,918 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,937 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,938 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,938 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,941 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,942 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,969 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,970 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,970 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,974 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,974 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:41,994 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:41,994 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:41,995 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,998 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:41,998 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:42,017 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:42,017 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:42,018 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,021 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,021 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:42,041 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:42,042 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:42,042 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,046 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,046 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:42,064 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:42,065 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:42,065 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,078 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,079 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:42,098 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:42,098 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:42,099 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,102 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,102 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:42,313 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:42,314 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:42,315 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,319 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:42,319 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 04:16:42,407 INFO L134 CoverageAnalysis]: Checked inductivity of 1380 backedges. 904 proven. 476 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:42,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:42,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 26] total 47 [2018-01-30 04:16:42,424 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-30 04:16:42,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-30 04:16:42,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=580, Invalid=1582, Unknown=0, NotChecked=0, Total=2162 [2018-01-30 04:16:42,425 INFO L87 Difference]: Start difference. First operand 665 states and 750 transitions. Second operand 47 states. [2018-01-30 04:16:43,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:43,885 INFO L93 Difference]: Finished difference Result 1602 states and 1872 transitions. [2018-01-30 04:16:43,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-30 04:16:43,888 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 166 [2018-01-30 04:16:43,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:43,892 INFO L225 Difference]: With dead ends: 1602 [2018-01-30 04:16:43,892 INFO L226 Difference]: Without dead ends: 1556 [2018-01-30 04:16:43,893 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 206 GetRequests, 142 SyntacticMatches, 1 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1165 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=976, Invalid=3184, Unknown=0, NotChecked=0, Total=4160 [2018-01-30 04:16:43,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1556 states. [2018-01-30 04:16:43,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1556 to 1309. [2018-01-30 04:16:43,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1309 states. [2018-01-30 04:16:43,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1309 states to 1309 states and 1480 transitions. [2018-01-30 04:16:43,919 INFO L78 Accepts]: Start accepts. Automaton has 1309 states and 1480 transitions. Word has length 166 [2018-01-30 04:16:43,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:43,920 INFO L432 AbstractCegarLoop]: Abstraction has 1309 states and 1480 transitions. [2018-01-30 04:16:43,920 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-30 04:16:43,920 INFO L276 IsEmpty]: Start isEmpty. Operand 1309 states and 1480 transitions. [2018-01-30 04:16:43,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-30 04:16:43,921 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:43,921 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 21, 20, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:43,921 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:43,921 INFO L82 PathProgramCache]: Analyzing trace with hash 1290253738, now seen corresponding path program 4 times [2018-01-30 04:16:43,921 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:43,922 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:43,922 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:43,922 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:43,922 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:43,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:43,931 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:44,946 INFO L134 CoverageAnalysis]: Checked inductivity of 1522 backedges. 0 proven. 1512 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:44,946 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:44,946 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:44,951 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:16:44,974 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:44,975 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:44,998 INFO L134 CoverageAnalysis]: Checked inductivity of 1522 backedges. 0 proven. 1512 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:45,015 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:45,015 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-30 04:16:45,015 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-30 04:16:45,015 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-30 04:16:45,016 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 04:16:45,016 INFO L87 Difference]: Start difference. First operand 1309 states and 1480 transitions. Second operand 24 states. [2018-01-30 04:16:45,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:45,247 INFO L93 Difference]: Finished difference Result 1599 states and 1846 transitions. [2018-01-30 04:16:45,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-30 04:16:45,247 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 174 [2018-01-30 04:16:45,247 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:45,250 INFO L225 Difference]: With dead ends: 1599 [2018-01-30 04:16:45,250 INFO L226 Difference]: Without dead ends: 1529 [2018-01-30 04:16:45,250 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 197 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 04:16:45,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1529 states. [2018-01-30 04:16:45,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1529 to 1373. [2018-01-30 04:16:45,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1373 states. [2018-01-30 04:16:45,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1373 states to 1373 states and 1552 transitions. [2018-01-30 04:16:45,275 INFO L78 Accepts]: Start accepts. Automaton has 1373 states and 1552 transitions. Word has length 174 [2018-01-30 04:16:45,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:45,276 INFO L432 AbstractCegarLoop]: Abstraction has 1373 states and 1552 transitions. [2018-01-30 04:16:45,276 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-30 04:16:45,276 INFO L276 IsEmpty]: Start isEmpty. Operand 1373 states and 1552 transitions. [2018-01-30 04:16:45,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-01-30 04:16:45,277 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:45,277 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 22, 21, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:45,277 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:45,277 INFO L82 PathProgramCache]: Analyzing trace with hash 132459746, now seen corresponding path program 5 times [2018-01-30 04:16:45,277 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:45,277 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:45,278 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:45,278 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:45,278 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:45,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:45,286 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:45,743 INFO L134 CoverageAnalysis]: Checked inductivity of 1671 backedges. 0 proven. 1661 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:45,743 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:45,744 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:45,749 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 04:16:45,753 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,753 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,754 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,755 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,757 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,758 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,759 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,760 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,763 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,765 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,768 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,770 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,785 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:45,814 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:45,816 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:45,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1671 backedges. 0 proven. 1661 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:45,850 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:45,850 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-30 04:16:45,851 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-30 04:16:45,851 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-30 04:16:45,851 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 04:16:45,851 INFO L87 Difference]: Start difference. First operand 1373 states and 1552 transitions. Second operand 25 states. [2018-01-30 04:16:46,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:46,079 INFO L93 Difference]: Finished difference Result 1668 states and 1925 transitions. [2018-01-30 04:16:46,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-30 04:16:46,079 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 181 [2018-01-30 04:16:46,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:46,082 INFO L225 Difference]: With dead ends: 1668 [2018-01-30 04:16:46,082 INFO L226 Difference]: Without dead ends: 1598 [2018-01-30 04:16:46,083 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 205 GetRequests, 182 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 04:16:46,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1598 states. [2018-01-30 04:16:46,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1598 to 1437. [2018-01-30 04:16:46,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1437 states. [2018-01-30 04:16:46,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1437 states to 1437 states and 1624 transitions. [2018-01-30 04:16:46,119 INFO L78 Accepts]: Start accepts. Automaton has 1437 states and 1624 transitions. Word has length 181 [2018-01-30 04:16:46,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:46,120 INFO L432 AbstractCegarLoop]: Abstraction has 1437 states and 1624 transitions. [2018-01-30 04:16:46,120 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-30 04:16:46,120 INFO L276 IsEmpty]: Start isEmpty. Operand 1437 states and 1624 transitions. [2018-01-30 04:16:46,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-01-30 04:16:46,121 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:46,122 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 23, 22, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:46,122 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:46,122 INFO L82 PathProgramCache]: Analyzing trace with hash -882530646, now seen corresponding path program 6 times [2018-01-30 04:16:46,122 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:46,122 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:46,122 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:46,122 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:46,122 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:46,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:46,137 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:46,586 INFO L134 CoverageAnalysis]: Checked inductivity of 1827 backedges. 0 proven. 1817 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-01-30 04:16:46,586 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:46,586 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:46,591 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 04:16:46,596 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,599 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,600 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,601 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,603 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,606 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,607 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,609 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,610 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,614 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,622 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,624 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:46,630 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:46,632 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:46,640 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:46,640 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:46,641 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:46,641 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 04:16:46,712 INFO L134 CoverageAnalysis]: Checked inductivity of 1827 backedges. 0 proven. 437 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-01-30 04:16:46,729 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:46,729 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 11] total 35 [2018-01-30 04:16:46,729 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-30 04:16:46,730 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-30 04:16:46,730 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=487, Invalid=703, Unknown=0, NotChecked=0, Total=1190 [2018-01-30 04:16:46,730 INFO L87 Difference]: Start difference. First operand 1437 states and 1624 transitions. Second operand 35 states. [2018-01-30 04:16:47,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:47,694 INFO L93 Difference]: Finished difference Result 1852 states and 2164 transitions. [2018-01-30 04:16:47,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-30 04:16:47,694 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 188 [2018-01-30 04:16:47,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:47,697 INFO L225 Difference]: With dead ends: 1852 [2018-01-30 04:16:47,697 INFO L226 Difference]: Without dead ends: 1782 [2018-01-30 04:16:47,698 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 235 GetRequests, 180 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 726 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1058, Invalid=2134, Unknown=0, NotChecked=0, Total=3192 [2018-01-30 04:16:47,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1782 states. [2018-01-30 04:16:47,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1782 to 1517. [2018-01-30 04:16:47,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1517 states. [2018-01-30 04:16:47,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1517 states to 1517 states and 1713 transitions. [2018-01-30 04:16:47,716 INFO L78 Accepts]: Start accepts. Automaton has 1517 states and 1713 transitions. Word has length 188 [2018-01-30 04:16:47,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:47,716 INFO L432 AbstractCegarLoop]: Abstraction has 1517 states and 1713 transitions. [2018-01-30 04:16:47,716 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-30 04:16:47,716 INFO L276 IsEmpty]: Start isEmpty. Operand 1517 states and 1713 transitions. [2018-01-30 04:16:47,718 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-30 04:16:47,718 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:47,718 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 24, 24, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:47,718 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:47,718 INFO L82 PathProgramCache]: Analyzing trace with hash 1011510424, now seen corresponding path program 11 times [2018-01-30 04:16:47,718 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:47,718 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:47,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:47,719 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:47,719 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:47,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:47,725 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:47,997 INFO L134 CoverageAnalysis]: Checked inductivity of 2001 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:47,997 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:47,997 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:48,001 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 04:16:48,011 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,012 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,017 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,018 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,024 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,027 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,028 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,029 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,031 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,033 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,037 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,040 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,042 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,045 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,048 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,053 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,057 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,067 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,073 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,078 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,085 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,093 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:48,094 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:48,096 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:48,126 INFO L134 CoverageAnalysis]: Checked inductivity of 2001 backedges. 0 proven. 1980 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:48,148 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:48,148 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-30 04:16:48,148 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-30 04:16:48,149 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-30 04:16:48,149 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 04:16:48,149 INFO L87 Difference]: Start difference. First operand 1517 states and 1713 transitions. Second operand 27 states. [2018-01-30 04:16:48,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:48,462 INFO L93 Difference]: Finished difference Result 1826 states and 2103 transitions. [2018-01-30 04:16:48,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-30 04:16:48,462 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 198 [2018-01-30 04:16:48,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:48,465 INFO L225 Difference]: With dead ends: 1826 [2018-01-30 04:16:48,465 INFO L226 Difference]: Without dead ends: 1740 [2018-01-30 04:16:48,466 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 224 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 04:16:48,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1740 states. [2018-01-30 04:16:48,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1740 to 1581. [2018-01-30 04:16:48,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1581 states. [2018-01-30 04:16:48,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1581 states to 1581 states and 1785 transitions. [2018-01-30 04:16:48,482 INFO L78 Accepts]: Start accepts. Automaton has 1581 states and 1785 transitions. Word has length 198 [2018-01-30 04:16:48,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:48,482 INFO L432 AbstractCegarLoop]: Abstraction has 1581 states and 1785 transitions. [2018-01-30 04:16:48,482 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-30 04:16:48,482 INFO L276 IsEmpty]: Start isEmpty. Operand 1581 states and 1785 transitions. [2018-01-30 04:16:48,484 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 206 [2018-01-30 04:16:48,484 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:48,484 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 25, 25, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:48,484 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:48,484 INFO L82 PathProgramCache]: Analyzing trace with hash -1971421916, now seen corresponding path program 12 times [2018-01-30 04:16:48,484 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:48,484 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:48,485 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:48,485 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:48,485 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:48,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:48,492 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:48,768 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 0 proven. 2150 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:48,768 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:48,768 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:48,773 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 04:16:48,778 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,779 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,780 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,781 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,783 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,784 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,785 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,787 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,788 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,791 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,792 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,794 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,796 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,798 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,800 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,803 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,805 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,816 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:16:48,833 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:48,835 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:48,860 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 0 proven. 2150 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:48,878 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:48,878 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-30 04:16:48,879 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-30 04:16:48,879 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-30 04:16:48,879 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 04:16:48,879 INFO L87 Difference]: Start difference. First operand 1581 states and 1785 transitions. Second operand 28 states. [2018-01-30 04:16:49,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:49,284 INFO L93 Difference]: Finished difference Result 1895 states and 2182 transitions. [2018-01-30 04:16:49,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-30 04:16:49,284 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 205 [2018-01-30 04:16:49,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:49,287 INFO L225 Difference]: With dead ends: 1895 [2018-01-30 04:16:49,287 INFO L226 Difference]: Without dead ends: 1809 [2018-01-30 04:16:49,287 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 206 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 04:16:49,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1809 states. [2018-01-30 04:16:49,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1809 to 1645. [2018-01-30 04:16:49,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1645 states. [2018-01-30 04:16:49,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 1857 transitions. [2018-01-30 04:16:49,309 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 1857 transitions. Word has length 205 [2018-01-30 04:16:49,309 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:49,309 INFO L432 AbstractCegarLoop]: Abstraction has 1645 states and 1857 transitions. [2018-01-30 04:16:49,309 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-30 04:16:49,309 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 1857 transitions. [2018-01-30 04:16:49,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-01-30 04:16:49,311 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:49,311 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 26, 26, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:49,311 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:49,311 INFO L82 PathProgramCache]: Analyzing trace with hash 2075981592, now seen corresponding path program 13 times [2018-01-30 04:16:49,311 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:49,311 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:49,311 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:49,312 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:49,312 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:49,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:49,319 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:49,752 INFO L134 CoverageAnalysis]: Checked inductivity of 2348 backedges. 0 proven. 2327 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:49,752 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:49,752 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:49,757 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:49,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:49,775 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:49,804 INFO L134 CoverageAnalysis]: Checked inductivity of 2348 backedges. 0 proven. 2327 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:49,829 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:49,829 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-30 04:16:49,829 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-30 04:16:49,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-30 04:16:49,830 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 04:16:49,830 INFO L87 Difference]: Start difference. First operand 1645 states and 1857 transitions. Second operand 29 states. [2018-01-30 04:16:50,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:50,246 INFO L93 Difference]: Finished difference Result 1964 states and 2261 transitions. [2018-01-30 04:16:50,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-30 04:16:50,246 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 212 [2018-01-30 04:16:50,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:50,249 INFO L225 Difference]: With dead ends: 1964 [2018-01-30 04:16:50,249 INFO L226 Difference]: Without dead ends: 1878 [2018-01-30 04:16:50,250 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 04:16:50,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1878 states. [2018-01-30 04:16:50,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1878 to 1709. [2018-01-30 04:16:50,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1709 states. [2018-01-30 04:16:50,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1709 states to 1709 states and 1929 transitions. [2018-01-30 04:16:50,296 INFO L78 Accepts]: Start accepts. Automaton has 1709 states and 1929 transitions. Word has length 212 [2018-01-30 04:16:50,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:50,296 INFO L432 AbstractCegarLoop]: Abstraction has 1709 states and 1929 transitions. [2018-01-30 04:16:50,296 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-30 04:16:50,296 INFO L276 IsEmpty]: Start isEmpty. Operand 1709 states and 1929 transitions. [2018-01-30 04:16:50,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 220 [2018-01-30 04:16:50,298 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:50,298 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 27, 27, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:50,298 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:50,299 INFO L82 PathProgramCache]: Analyzing trace with hash -1181539676, now seen corresponding path program 14 times [2018-01-30 04:16:50,299 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:50,299 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:50,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:50,299 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:50,299 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:50,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:50,307 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:50,696 INFO L134 CoverageAnalysis]: Checked inductivity of 2532 backedges. 0 proven. 2511 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:50,696 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:50,696 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:50,701 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:50,707 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:50,721 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:50,723 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:50,725 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:50,749 INFO L134 CoverageAnalysis]: Checked inductivity of 2532 backedges. 0 proven. 2511 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:50,768 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:50,768 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-30 04:16:50,768 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-30 04:16:50,768 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-30 04:16:50,769 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 04:16:50,769 INFO L87 Difference]: Start difference. First operand 1709 states and 1929 transitions. Second operand 30 states. [2018-01-30 04:16:51,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:51,137 INFO L93 Difference]: Finished difference Result 2033 states and 2340 transitions. [2018-01-30 04:16:51,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-30 04:16:51,138 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 219 [2018-01-30 04:16:51,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:51,141 INFO L225 Difference]: With dead ends: 2033 [2018-01-30 04:16:51,141 INFO L226 Difference]: Without dead ends: 1947 [2018-01-30 04:16:51,141 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 220 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 04:16:51,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1947 states. [2018-01-30 04:16:51,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1947 to 1773. [2018-01-30 04:16:51,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1773 states. [2018-01-30 04:16:51,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1773 states to 1773 states and 2001 transitions. [2018-01-30 04:16:51,159 INFO L78 Accepts]: Start accepts. Automaton has 1773 states and 2001 transitions. Word has length 219 [2018-01-30 04:16:51,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:51,159 INFO L432 AbstractCegarLoop]: Abstraction has 1773 states and 2001 transitions. [2018-01-30 04:16:51,159 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-30 04:16:51,159 INFO L276 IsEmpty]: Start isEmpty. Operand 1773 states and 2001 transitions. [2018-01-30 04:16:51,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-01-30 04:16:51,161 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:51,161 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 28, 28, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:51,161 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:51,161 INFO L82 PathProgramCache]: Analyzing trace with hash 11215256, now seen corresponding path program 15 times [2018-01-30 04:16:51,161 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:51,161 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:51,162 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:51,162 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:51,162 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:51,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:51,169 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:51,533 INFO L134 CoverageAnalysis]: Checked inductivity of 2723 backedges. 0 proven. 2702 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:51,534 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:51,534 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:51,545 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:16:51,550 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,551 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,553 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,554 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,555 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,556 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,558 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,559 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,561 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,563 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,565 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,567 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,570 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,572 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,575 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,578 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,581 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,585 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,589 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,594 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,599 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,604 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,615 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,622 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,630 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,648 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,657 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:16:51,657 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:51,660 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:51,685 INFO L134 CoverageAnalysis]: Checked inductivity of 2723 backedges. 0 proven. 2702 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:51,702 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:51,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-30 04:16:51,703 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-30 04:16:51,703 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-30 04:16:51,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 04:16:51,703 INFO L87 Difference]: Start difference. First operand 1773 states and 2001 transitions. Second operand 31 states. [2018-01-30 04:16:52,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:52,975 INFO L93 Difference]: Finished difference Result 2102 states and 2419 transitions. [2018-01-30 04:16:52,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-30 04:16:52,975 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 226 [2018-01-30 04:16:52,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:52,978 INFO L225 Difference]: With dead ends: 2102 [2018-01-30 04:16:52,979 INFO L226 Difference]: Without dead ends: 2016 [2018-01-30 04:16:52,979 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 256 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 04:16:52,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2016 states. [2018-01-30 04:16:53,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2016 to 1837. [2018-01-30 04:16:53,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1837 states. [2018-01-30 04:16:53,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1837 states to 1837 states and 2073 transitions. [2018-01-30 04:16:53,002 INFO L78 Accepts]: Start accepts. Automaton has 1837 states and 2073 transitions. Word has length 226 [2018-01-30 04:16:53,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:53,002 INFO L432 AbstractCegarLoop]: Abstraction has 1837 states and 2073 transitions. [2018-01-30 04:16:53,002 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-30 04:16:53,002 INFO L276 IsEmpty]: Start isEmpty. Operand 1837 states and 2073 transitions. [2018-01-30 04:16:53,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-01-30 04:16:53,003 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:53,004 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 29, 29, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:53,004 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:53,004 INFO L82 PathProgramCache]: Analyzing trace with hash 1322788900, now seen corresponding path program 16 times [2018-01-30 04:16:53,004 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:53,004 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:53,004 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:53,005 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:53,005 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:53,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:53,012 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:53,777 INFO L134 CoverageAnalysis]: Checked inductivity of 2921 backedges. 0 proven. 2900 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:53,777 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:53,777 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:53,781 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:16:53,809 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:53,811 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:53,993 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:16:53,993 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:53,995 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:53,995 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 04:16:54,013 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,014 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,015 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,018 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,018 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,034 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,035 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,035 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,039 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,039 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,056 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,057 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,061 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,061 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,079 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,080 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,084 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,084 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,109 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,110 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,110 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,115 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,115 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,135 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,136 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,136 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,141 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,141 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,160 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,161 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,161 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,164 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,164 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,182 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,182 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,183 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,186 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,186 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,204 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,204 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,205 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,208 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,208 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,230 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,230 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,231 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,234 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,234 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,253 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,254 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,254 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,262 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,262 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,289 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,290 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,290 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,294 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,294 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,320 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,320 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,321 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,324 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,324 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,346 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,347 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,347 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,351 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,351 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,375 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,376 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,376 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,380 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,380 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,404 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,404 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,405 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,408 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,408 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,430 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,431 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,431 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,434 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,434 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,457 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,457 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,458 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,461 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,461 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,484 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,485 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,485 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,488 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,488 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,512 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,513 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,513 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,541 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,541 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,567 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,569 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,569 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,573 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,573 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,606 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,607 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,607 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,611 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,611 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,656 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,657 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,657 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,661 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,661 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,688 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,689 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,689 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,692 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,692 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:16:54,718 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:16:54,719 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:16:54,719 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,738 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:16:54,738 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 04:16:54,851 INFO L134 CoverageAnalysis]: Checked inductivity of 2921 backedges. 2028 proven. 893 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:16:54,870 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:54,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 36] total 66 [2018-01-30 04:16:54,870 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-30 04:16:54,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-30 04:16:54,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1125, Invalid=3165, Unknown=0, NotChecked=0, Total=4290 [2018-01-30 04:16:54,872 INFO L87 Difference]: Start difference. First operand 1837 states and 2073 transitions. Second operand 66 states. [2018-01-30 04:16:57,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:57,372 INFO L93 Difference]: Finished difference Result 4110 states and 4738 transitions. [2018-01-30 04:16:57,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-30 04:16:57,372 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 233 [2018-01-30 04:16:57,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:57,378 INFO L225 Difference]: With dead ends: 4110 [2018-01-30 04:16:57,378 INFO L226 Difference]: Without dead ends: 4024 [2018-01-30 04:16:57,380 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 290 GetRequests, 199 SyntacticMatches, 1 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2348 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1905, Invalid=6467, Unknown=0, NotChecked=0, Total=8372 [2018-01-30 04:16:57,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4024 states. [2018-01-30 04:16:57,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4024 to 3645. [2018-01-30 04:16:57,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3645 states. [2018-01-30 04:16:57,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3645 states to 3645 states and 4119 transitions. [2018-01-30 04:16:57,422 INFO L78 Accepts]: Start accepts. Automaton has 3645 states and 4119 transitions. Word has length 233 [2018-01-30 04:16:57,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:57,422 INFO L432 AbstractCegarLoop]: Abstraction has 3645 states and 4119 transitions. [2018-01-30 04:16:57,422 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-30 04:16:57,422 INFO L276 IsEmpty]: Start isEmpty. Operand 3645 states and 4119 transitions. [2018-01-30 04:16:57,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2018-01-30 04:16:57,425 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:57,425 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 30, 30, 29, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:57,425 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:57,425 INFO L82 PathProgramCache]: Analyzing trace with hash 936285742, now seen corresponding path program 7 times [2018-01-30 04:16:57,426 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:57,426 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:57,426 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:57,426 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:16:57,426 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:57,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:57,433 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:57,957 INFO L134 CoverageAnalysis]: Checked inductivity of 3126 backedges. 0 proven. 3105 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:57,957 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:57,957 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:57,961 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:57,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:57,981 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:16:58,009 INFO L134 CoverageAnalysis]: Checked inductivity of 3126 backedges. 0 proven. 3105 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:58,028 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:16:58,028 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-30 04:16:58,028 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-30 04:16:58,029 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-30 04:16:58,029 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 04:16:58,029 INFO L87 Difference]: Start difference. First operand 3645 states and 4119 transitions. Second operand 33 states. [2018-01-30 04:16:59,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:16:59,343 INFO L93 Difference]: Finished difference Result 4163 states and 4768 transitions. [2018-01-30 04:16:59,343 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-30 04:16:59,343 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 241 [2018-01-30 04:16:59,343 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:16:59,350 INFO L225 Difference]: With dead ends: 4163 [2018-01-30 04:16:59,350 INFO L226 Difference]: Without dead ends: 4021 [2018-01-30 04:16:59,351 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 242 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 04:16:59,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4021 states. [2018-01-30 04:16:59,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4021 to 3773. [2018-01-30 04:16:59,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3773 states. [2018-01-30 04:16:59,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3773 states to 3773 states and 4263 transitions. [2018-01-30 04:16:59,407 INFO L78 Accepts]: Start accepts. Automaton has 3773 states and 4263 transitions. Word has length 241 [2018-01-30 04:16:59,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:16:59,408 INFO L432 AbstractCegarLoop]: Abstraction has 3773 states and 4263 transitions. [2018-01-30 04:16:59,408 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-30 04:16:59,408 INFO L276 IsEmpty]: Start isEmpty. Operand 3773 states and 4263 transitions. [2018-01-30 04:16:59,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 249 [2018-01-30 04:16:59,411 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:16:59,411 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 31, 31, 30, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:16:59,411 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:16:59,411 INFO L82 PathProgramCache]: Analyzing trace with hash 1083866830, now seen corresponding path program 8 times [2018-01-30 04:16:59,411 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:16:59,411 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:16:59,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:59,412 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:16:59,412 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:16:59,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:16:59,419 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:16:59,941 INFO L134 CoverageAnalysis]: Checked inductivity of 3338 backedges. 0 proven. 3317 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:16:59,941 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:16:59,941 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:16:59,947 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:16:59,952 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:59,964 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:16:59,971 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:16:59,973 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:00,002 INFO L134 CoverageAnalysis]: Checked inductivity of 3338 backedges. 0 proven. 3317 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:17:00,019 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:00,019 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-30 04:17:00,019 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-30 04:17:00,019 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-30 04:17:00,019 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 04:17:00,020 INFO L87 Difference]: Start difference. First operand 3773 states and 4263 transitions. Second operand 34 states. [2018-01-30 04:17:00,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:00,345 INFO L93 Difference]: Finished difference Result 4296 states and 4919 transitions. [2018-01-30 04:17:00,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-30 04:17:00,346 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 248 [2018-01-30 04:17:00,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:00,350 INFO L225 Difference]: With dead ends: 4296 [2018-01-30 04:17:00,350 INFO L226 Difference]: Without dead ends: 4154 [2018-01-30 04:17:00,351 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 281 GetRequests, 249 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 04:17:00,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4154 states. [2018-01-30 04:17:00,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4154 to 3901. [2018-01-30 04:17:00,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3901 states. [2018-01-30 04:17:00,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3901 states to 3901 states and 4407 transitions. [2018-01-30 04:17:00,391 INFO L78 Accepts]: Start accepts. Automaton has 3901 states and 4407 transitions. Word has length 248 [2018-01-30 04:17:00,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:00,391 INFO L432 AbstractCegarLoop]: Abstraction has 3901 states and 4407 transitions. [2018-01-30 04:17:00,391 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-30 04:17:00,391 INFO L276 IsEmpty]: Start isEmpty. Operand 3901 states and 4407 transitions. [2018-01-30 04:17:00,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 256 [2018-01-30 04:17:00,394 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:00,394 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 32, 31, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:00,394 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:00,394 INFO L82 PathProgramCache]: Analyzing trace with hash -891968978, now seen corresponding path program 9 times [2018-01-30 04:17:00,394 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:00,394 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:00,395 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:00,395 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:00,395 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:00,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:00,402 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:01,086 INFO L134 CoverageAnalysis]: Checked inductivity of 3557 backedges. 0 proven. 3536 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-01-30 04:17:01,086 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:01,086 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:01,091 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:17:01,095 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,098 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,099 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,100 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,102 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,103 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,104 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,106 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,110 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,112 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,115 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,120 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,123 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,126 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,130 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,134 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,143 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,160 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,167 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,175 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,183 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,192 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:01,194 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:01,195 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:01,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:17:01,221 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:01,221 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:01,221 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 04:17:01,319 INFO L134 CoverageAnalysis]: Checked inductivity of 3557 backedges. 0 proven. 827 refuted. 0 times theorem prover too weak. 2730 trivial. 0 not checked. [2018-01-30 04:17:01,336 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:01,336 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 13] total 46 [2018-01-30 04:17:01,336 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-30 04:17:01,336 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-30 04:17:01,337 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=877, Invalid=1193, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 04:17:01,337 INFO L87 Difference]: Start difference. First operand 3901 states and 4407 transitions. Second operand 46 states. [2018-01-30 04:17:02,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:02,451 INFO L93 Difference]: Finished difference Result 4584 states and 5286 transitions. [2018-01-30 04:17:02,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-01-30 04:17:02,451 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 255 [2018-01-30 04:17:02,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:02,455 INFO L225 Difference]: With dead ends: 4584 [2018-01-30 04:17:02,455 INFO L226 Difference]: Without dead ends: 4442 [2018-01-30 04:17:02,456 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 319 GetRequests, 245 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1309 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1925, Invalid=3775, Unknown=0, NotChecked=0, Total=5700 [2018-01-30 04:17:02,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4442 states. [2018-01-30 04:17:02,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4442 to 4049. [2018-01-30 04:17:02,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4049 states. [2018-01-30 04:17:02,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4049 states to 4049 states and 4572 transitions. [2018-01-30 04:17:02,495 INFO L78 Accepts]: Start accepts. Automaton has 4049 states and 4572 transitions. Word has length 255 [2018-01-30 04:17:02,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:02,495 INFO L432 AbstractCegarLoop]: Abstraction has 4049 states and 4572 transitions. [2018-01-30 04:17:02,495 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-30 04:17:02,495 INFO L276 IsEmpty]: Start isEmpty. Operand 4049 states and 4572 transitions. [2018-01-30 04:17:02,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 266 [2018-01-30 04:17:02,498 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:02,498 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 33, 33, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:02,498 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:02,499 INFO L82 PathProgramCache]: Analyzing trace with hash 1628170268, now seen corresponding path program 17 times [2018-01-30 04:17:02,499 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:02,499 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:02,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:02,499 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:02,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:02,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:02,507 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:03,762 INFO L134 CoverageAnalysis]: Checked inductivity of 3798 backedges. 0 proven. 3762 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:03,762 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:03,762 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:03,767 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 04:17:03,771 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,772 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,773 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,774 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,775 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,776 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,777 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,779 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,783 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,785 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,821 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,828 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,834 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,841 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,849 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,891 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,903 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:03,957 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:03,960 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:04,008 INFO L134 CoverageAnalysis]: Checked inductivity of 3798 backedges. 0 proven. 3762 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:04,025 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:04,025 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-30 04:17:04,025 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-30 04:17:04,026 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-30 04:17:04,026 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 04:17:04,026 INFO L87 Difference]: Start difference. First operand 4049 states and 4572 transitions. Second operand 36 states. [2018-01-30 04:17:04,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:04,372 INFO L93 Difference]: Finished difference Result 4586 states and 5245 transitions. [2018-01-30 04:17:04,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-30 04:17:04,372 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 265 [2018-01-30 04:17:04,372 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:04,376 INFO L225 Difference]: With dead ends: 4586 [2018-01-30 04:17:04,376 INFO L226 Difference]: Without dead ends: 4424 [2018-01-30 04:17:04,377 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 300 GetRequests, 266 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 04:17:04,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4424 states. [2018-01-30 04:17:04,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4424 to 4177. [2018-01-30 04:17:04,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4177 states. [2018-01-30 04:17:04,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4177 states to 4177 states and 4716 transitions. [2018-01-30 04:17:04,415 INFO L78 Accepts]: Start accepts. Automaton has 4177 states and 4716 transitions. Word has length 265 [2018-01-30 04:17:04,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:04,416 INFO L432 AbstractCegarLoop]: Abstraction has 4177 states and 4716 transitions. [2018-01-30 04:17:04,416 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-30 04:17:04,416 INFO L276 IsEmpty]: Start isEmpty. Operand 4177 states and 4716 transitions. [2018-01-30 04:17:04,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 273 [2018-01-30 04:17:04,419 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:04,419 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 34, 34, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:04,419 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:04,419 INFO L82 PathProgramCache]: Analyzing trace with hash 38001680, now seen corresponding path program 18 times [2018-01-30 04:17:04,419 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:04,419 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:04,420 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:04,420 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:04,420 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:04,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:04,427 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:05,009 INFO L134 CoverageAnalysis]: Checked inductivity of 4031 backedges. 0 proven. 3995 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:05,010 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:05,010 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 04:17:05,041 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:05,046 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,058 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,060 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,061 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,062 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,064 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,065 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,066 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,068 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,069 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,071 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,073 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,074 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,076 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,078 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,080 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,083 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,086 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,089 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,092 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,094 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,097 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,100 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,104 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,107 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,111 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,116 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,120 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,125 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,130 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,136 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,142 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,149 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,156 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:05,164 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:05,166 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:05,213 INFO L134 CoverageAnalysis]: Checked inductivity of 4031 backedges. 0 proven. 3995 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:05,230 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:05,230 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-30 04:17:05,231 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-30 04:17:05,231 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-30 04:17:05,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 04:17:05,231 INFO L87 Difference]: Start difference. First operand 4177 states and 4716 transitions. Second operand 37 states. [2018-01-30 04:17:05,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:05,589 INFO L93 Difference]: Finished difference Result 4719 states and 5396 transitions. [2018-01-30 04:17:05,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-30 04:17:05,589 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 272 [2018-01-30 04:17:05,589 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:05,593 INFO L225 Difference]: With dead ends: 4719 [2018-01-30 04:17:05,593 INFO L226 Difference]: Without dead ends: 4557 [2018-01-30 04:17:05,594 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 273 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 04:17:05,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4557 states. [2018-01-30 04:17:05,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4557 to 4305. [2018-01-30 04:17:05,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4305 states. [2018-01-30 04:17:05,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4305 states to 4305 states and 4860 transitions. [2018-01-30 04:17:05,633 INFO L78 Accepts]: Start accepts. Automaton has 4305 states and 4860 transitions. Word has length 272 [2018-01-30 04:17:05,634 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:05,634 INFO L432 AbstractCegarLoop]: Abstraction has 4305 states and 4860 transitions. [2018-01-30 04:17:05,634 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-30 04:17:05,634 INFO L276 IsEmpty]: Start isEmpty. Operand 4305 states and 4860 transitions. [2018-01-30 04:17:05,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 280 [2018-01-30 04:17:05,637 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:05,637 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 35, 35, 35, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:05,637 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:05,637 INFO L82 PathProgramCache]: Analyzing trace with hash -1520218724, now seen corresponding path program 19 times [2018-01-30 04:17:05,637 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:05,638 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:05,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:05,638 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:05,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:05,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:05,645 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:06,228 INFO L134 CoverageAnalysis]: Checked inductivity of 4271 backedges. 0 proven. 4235 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:06,228 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:06,228 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:06,242 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:17:06,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:06,268 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:06,304 INFO L134 CoverageAnalysis]: Checked inductivity of 4271 backedges. 0 proven. 4235 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:06,323 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:06,323 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-30 04:17:06,323 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-30 04:17:06,323 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-30 04:17:06,324 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 04:17:06,324 INFO L87 Difference]: Start difference. First operand 4305 states and 4860 transitions. Second operand 38 states. [2018-01-30 04:17:06,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:06,727 INFO L93 Difference]: Finished difference Result 4852 states and 5547 transitions. [2018-01-30 04:17:06,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-30 04:17:06,728 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 279 [2018-01-30 04:17:06,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:06,732 INFO L225 Difference]: With dead ends: 4852 [2018-01-30 04:17:06,732 INFO L226 Difference]: Without dead ends: 4690 [2018-01-30 04:17:06,733 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 316 GetRequests, 280 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 04:17:06,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4690 states. [2018-01-30 04:17:06,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4690 to 4433. [2018-01-30 04:17:06,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4433 states. [2018-01-30 04:17:06,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4433 states to 4433 states and 5004 transitions. [2018-01-30 04:17:06,773 INFO L78 Accepts]: Start accepts. Automaton has 4433 states and 5004 transitions. Word has length 279 [2018-01-30 04:17:06,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:06,773 INFO L432 AbstractCegarLoop]: Abstraction has 4433 states and 5004 transitions. [2018-01-30 04:17:06,773 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-30 04:17:06,773 INFO L276 IsEmpty]: Start isEmpty. Operand 4433 states and 5004 transitions. [2018-01-30 04:17:06,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-01-30 04:17:06,777 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:06,777 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 36, 36, 36, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:06,777 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:06,777 INFO L82 PathProgramCache]: Analyzing trace with hash 1163347600, now seen corresponding path program 20 times [2018-01-30 04:17:06,777 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:06,777 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:06,779 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:06,779 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:17:06,779 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:06,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:06,787 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:07,494 INFO L134 CoverageAnalysis]: Checked inductivity of 4518 backedges. 0 proven. 4482 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:07,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:07,495 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:07,500 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:17:07,506 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:07,520 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:07,531 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:07,533 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:07,571 INFO L134 CoverageAnalysis]: Checked inductivity of 4518 backedges. 0 proven. 4482 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:07,591 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:07,591 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-30 04:17:07,592 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-30 04:17:07,592 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-30 04:17:07,592 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 04:17:07,592 INFO L87 Difference]: Start difference. First operand 4433 states and 5004 transitions. Second operand 39 states. [2018-01-30 04:17:08,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:08,105 INFO L93 Difference]: Finished difference Result 4985 states and 5698 transitions. [2018-01-30 04:17:08,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-30 04:17:08,106 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 286 [2018-01-30 04:17:08,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:08,108 INFO L225 Difference]: With dead ends: 4985 [2018-01-30 04:17:08,108 INFO L226 Difference]: Without dead ends: 4823 [2018-01-30 04:17:08,108 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 324 GetRequests, 287 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 04:17:08,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4823 states. [2018-01-30 04:17:08,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4823 to 4561. [2018-01-30 04:17:08,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4561 states. [2018-01-30 04:17:08,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4561 states to 4561 states and 5148 transitions. [2018-01-30 04:17:08,146 INFO L78 Accepts]: Start accepts. Automaton has 4561 states and 5148 transitions. Word has length 286 [2018-01-30 04:17:08,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:08,146 INFO L432 AbstractCegarLoop]: Abstraction has 4561 states and 5148 transitions. [2018-01-30 04:17:08,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-30 04:17:08,146 INFO L276 IsEmpty]: Start isEmpty. Operand 4561 states and 5148 transitions. [2018-01-30 04:17:08,149 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 294 [2018-01-30 04:17:08,150 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:08,150 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 37, 37, 37, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:08,150 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:08,150 INFO L82 PathProgramCache]: Analyzing trace with hash -2078600420, now seen corresponding path program 21 times [2018-01-30 04:17:08,150 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:08,150 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:08,150 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:08,150 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:08,150 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:08,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:08,158 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:09,027 INFO L134 CoverageAnalysis]: Checked inductivity of 4772 backedges. 0 proven. 4736 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:09,027 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:09,028 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:09,032 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:17:09,038 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,039 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,045 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,048 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,063 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,066 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,069 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,072 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,077 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,081 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,086 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,090 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,096 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,101 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,107 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,113 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,121 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,129 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,137 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,146 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,156 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,166 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,178 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,191 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,205 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,220 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,237 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,254 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,272 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,293 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:09,294 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:09,296 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:09,336 INFO L134 CoverageAnalysis]: Checked inductivity of 4772 backedges. 0 proven. 4736 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:09,354 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:09,354 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-30 04:17:09,354 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-30 04:17:09,354 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-30 04:17:09,354 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 04:17:09,354 INFO L87 Difference]: Start difference. First operand 4561 states and 5148 transitions. Second operand 40 states. [2018-01-30 04:17:09,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:09,774 INFO L93 Difference]: Finished difference Result 5118 states and 5849 transitions. [2018-01-30 04:17:09,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-30 04:17:09,775 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 293 [2018-01-30 04:17:09,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:09,777 INFO L225 Difference]: With dead ends: 5118 [2018-01-30 04:17:09,777 INFO L226 Difference]: Without dead ends: 4956 [2018-01-30 04:17:09,778 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 294 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 04:17:09,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4956 states. [2018-01-30 04:17:09,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4956 to 4689. [2018-01-30 04:17:09,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4689 states. [2018-01-30 04:17:09,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4689 states to 4689 states and 5292 transitions. [2018-01-30 04:17:09,836 INFO L78 Accepts]: Start accepts. Automaton has 4689 states and 5292 transitions. Word has length 293 [2018-01-30 04:17:09,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:09,836 INFO L432 AbstractCegarLoop]: Abstraction has 4689 states and 5292 transitions. [2018-01-30 04:17:09,836 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-30 04:17:09,836 INFO L276 IsEmpty]: Start isEmpty. Operand 4689 states and 5292 transitions. [2018-01-30 04:17:09,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 301 [2018-01-30 04:17:09,840 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:09,840 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 38, 38, 38, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:09,840 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:09,840 INFO L82 PathProgramCache]: Analyzing trace with hash -220311280, now seen corresponding path program 22 times [2018-01-30 04:17:09,840 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:09,840 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:09,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:09,841 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:09,841 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:09,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:09,848 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:10,696 INFO L134 CoverageAnalysis]: Checked inductivity of 5033 backedges. 0 proven. 4997 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:10,696 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:10,696 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:10,700 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:17:10,721 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:10,724 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:10,754 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:17:10,754 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,756 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,756 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:10, output treesize:3 [2018-01-30 04:17:10,777 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,778 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,779 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,783 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,783 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,802 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,803 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,804 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,808 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,808 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,827 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,828 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,828 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,831 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,832 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,851 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,852 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,852 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,857 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,857 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,877 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,878 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,878 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,882 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,882 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,915 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,916 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,916 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,920 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,920 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,942 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,943 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,943 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,946 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,947 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,968 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,969 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,969 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,972 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,972 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:10,994 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:10,995 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:10,995 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,999 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:10,999 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,033 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,034 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,034 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,038 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,038 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,060 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,061 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,061 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,066 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,066 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,091 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,091 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,092 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,095 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,095 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,119 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,120 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,120 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,124 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,124 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,150 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,151 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,151 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,158 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,159 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,182 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,183 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,184 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,187 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,187 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,213 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,214 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,214 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,218 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,218 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,245 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,246 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,246 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,249 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,250 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,276 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,277 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,277 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,281 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,281 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,308 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,309 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,309 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,313 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,313 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,341 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,342 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,342 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,346 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,346 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,374 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,375 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,375 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,379 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,379 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,407 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,408 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,408 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,413 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,413 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,443 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,444 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,448 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,448 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,478 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,479 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,479 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,483 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,483 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,513 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,514 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,514 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,517 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,517 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,547 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,548 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,548 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,552 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,552 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,590 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,591 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,592 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,595 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,595 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,626 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,627 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,627 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,631 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,632 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,666 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,667 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,667 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,671 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,671 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,704 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,705 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,709 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,709 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,742 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,743 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,744 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,747 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,747 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,782 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,783 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,783 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,787 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,787 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:10 [2018-01-30 04:17:11,823 INFO L700 Elim1Store]: detected not equals via solver [2018-01-30 04:17:11,824 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-01-30 04:17:11,825 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,829 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:11,829 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:16, output treesize:6 [2018-01-30 04:17:12,024 INFO L134 CoverageAnalysis]: Checked inductivity of 5033 backedges. 3600 proven. 1433 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 04:17:12,041 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:12,041 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 46] total 85 [2018-01-30 04:17:12,042 INFO L409 AbstractCegarLoop]: Interpolant automaton has 85 states [2018-01-30 04:17:12,042 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2018-01-30 04:17:12,042 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1849, Invalid=5291, Unknown=0, NotChecked=0, Total=7140 [2018-01-30 04:17:12,042 INFO L87 Difference]: Start difference. First operand 4689 states and 5292 transitions. Second operand 85 states. [2018-01-30 04:17:14,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:14,770 INFO L93 Difference]: Finished difference Result 10062 states and 11504 transitions. [2018-01-30 04:17:14,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2018-01-30 04:17:14,771 INFO L78 Accepts]: Start accepts. Automaton has 85 states. Word has length 300 [2018-01-30 04:17:14,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:14,778 INFO L225 Difference]: With dead ends: 10062 [2018-01-30 04:17:14,779 INFO L226 Difference]: Without dead ends: 9900 [2018-01-30 04:17:14,780 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 374 GetRequests, 256 SyntacticMatches, 1 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3940 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3141, Invalid=10901, Unknown=0, NotChecked=0, Total=14042 [2018-01-30 04:17:14,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9900 states. [2018-01-30 04:17:14,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9900 to 9341. [2018-01-30 04:17:14,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9341 states. [2018-01-30 04:17:14,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9341 states to 9341 states and 10550 transitions. [2018-01-30 04:17:14,878 INFO L78 Accepts]: Start accepts. Automaton has 9341 states and 10550 transitions. Word has length 300 [2018-01-30 04:17:14,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:14,878 INFO L432 AbstractCegarLoop]: Abstraction has 9341 states and 10550 transitions. [2018-01-30 04:17:14,878 INFO L433 AbstractCegarLoop]: Interpolant automaton has 85 states. [2018-01-30 04:17:14,878 INFO L276 IsEmpty]: Start isEmpty. Operand 9341 states and 10550 transitions. [2018-01-30 04:17:14,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2018-01-30 04:17:14,884 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:14,885 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 39, 39, 38, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:14,885 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:14,885 INFO L82 PathProgramCache]: Analyzing trace with hash 386977818, now seen corresponding path program 10 times [2018-01-30 04:17:14,885 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:14,885 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:14,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:14,885 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:14,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:14,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:14,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:15,679 INFO L134 CoverageAnalysis]: Checked inductivity of 5301 backedges. 0 proven. 5265 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:15,679 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:15,679 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:15,684 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 04:17:15,743 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:15,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:15,789 INFO L134 CoverageAnalysis]: Checked inductivity of 5301 backedges. 0 proven. 5265 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:15,807 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:15,807 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-30 04:17:15,807 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-30 04:17:15,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-30 04:17:15,808 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 04:17:15,808 INFO L87 Difference]: Start difference. First operand 9341 states and 10550 transitions. Second operand 42 states. [2018-01-30 04:17:16,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:16,263 INFO L93 Difference]: Finished difference Result 10271 states and 11706 transitions. [2018-01-30 04:17:16,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-30 04:17:16,264 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 308 [2018-01-30 04:17:16,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:16,269 INFO L225 Difference]: With dead ends: 10271 [2018-01-30 04:17:16,269 INFO L226 Difference]: Without dead ends: 9985 [2018-01-30 04:17:16,272 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 349 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 04:17:16,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9985 states. [2018-01-30 04:17:16,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9985 to 9597. [2018-01-30 04:17:16,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9597 states. [2018-01-30 04:17:16,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9597 states to 9597 states and 10838 transitions. [2018-01-30 04:17:16,367 INFO L78 Accepts]: Start accepts. Automaton has 9597 states and 10838 transitions. Word has length 308 [2018-01-30 04:17:16,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:16,368 INFO L432 AbstractCegarLoop]: Abstraction has 9597 states and 10838 transitions. [2018-01-30 04:17:16,368 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-30 04:17:16,368 INFO L276 IsEmpty]: Start isEmpty. Operand 9597 states and 10838 transitions. [2018-01-30 04:17:16,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 316 [2018-01-30 04:17:16,373 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:16,373 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 40, 40, 39, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:16,373 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:16,373 INFO L82 PathProgramCache]: Analyzing trace with hash -2136499630, now seen corresponding path program 11 times [2018-01-30 04:17:16,373 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:16,374 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:16,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:16,374 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:16,374 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:16,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:16,381 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:17,369 INFO L134 CoverageAnalysis]: Checked inductivity of 5576 backedges. 0 proven. 5540 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:17,369 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:17,369 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:17,376 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 04:17:17,388 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,395 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,396 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,396 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,397 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,399 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,400 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,401 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,403 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,404 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,408 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,410 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,413 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,417 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,421 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,427 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,435 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,440 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,459 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,466 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,474 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,482 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,492 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,504 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,516 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,528 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,542 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,557 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,573 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,591 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,636 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,659 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,711 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,745 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:17,746 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:17,749 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:17,821 INFO L134 CoverageAnalysis]: Checked inductivity of 5576 backedges. 0 proven. 5540 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:17,841 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:17,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-30 04:17:17,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-30 04:17:17,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-30 04:17:17,841 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 04:17:17,841 INFO L87 Difference]: Start difference. First operand 9597 states and 10838 transitions. Second operand 43 states. [2018-01-30 04:17:18,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:18,575 INFO L93 Difference]: Finished difference Result 10532 states and 12001 transitions. [2018-01-30 04:17:18,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-30 04:17:18,575 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 315 [2018-01-30 04:17:18,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:18,581 INFO L225 Difference]: With dead ends: 10532 [2018-01-30 04:17:18,581 INFO L226 Difference]: Without dead ends: 10246 [2018-01-30 04:17:18,583 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 04:17:18,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10246 states. [2018-01-30 04:17:18,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10246 to 9853. [2018-01-30 04:17:18,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9853 states. [2018-01-30 04:17:18,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9853 states to 9853 states and 11126 transitions. [2018-01-30 04:17:18,682 INFO L78 Accepts]: Start accepts. Automaton has 9853 states and 11126 transitions. Word has length 315 [2018-01-30 04:17:18,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:18,682 INFO L432 AbstractCegarLoop]: Abstraction has 9853 states and 11126 transitions. [2018-01-30 04:17:18,682 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-30 04:17:18,682 INFO L276 IsEmpty]: Start isEmpty. Operand 9853 states and 11126 transitions. [2018-01-30 04:17:18,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 323 [2018-01-30 04:17:18,687 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:18,687 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 41, 41, 40, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:18,687 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:18,688 INFO L82 PathProgramCache]: Analyzing trace with hash -1459920614, now seen corresponding path program 12 times [2018-01-30 04:17:18,688 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:18,688 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:18,688 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:18,688 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:18,688 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:18,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:18,695 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:19,428 INFO L134 CoverageAnalysis]: Checked inductivity of 5858 backedges. 0 proven. 5822 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:19,429 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:19,429 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:19,434 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 04:17:19,440 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,442 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,449 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,451 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,452 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,454 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,456 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,458 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,460 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,462 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,465 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,468 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,470 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,474 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,476 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,479 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,486 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,490 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,494 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,498 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,502 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,507 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,551 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,558 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,601 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,611 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,622 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,634 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:19,635 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:19,638 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:19,684 INFO L134 CoverageAnalysis]: Checked inductivity of 5858 backedges. 0 proven. 5822 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:19,702 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:19,702 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-30 04:17:19,702 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-30 04:17:19,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-30 04:17:19,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 04:17:19,703 INFO L87 Difference]: Start difference. First operand 9853 states and 11126 transitions. Second operand 44 states. [2018-01-30 04:17:20,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:20,202 INFO L93 Difference]: Finished difference Result 10793 states and 12296 transitions. [2018-01-30 04:17:20,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-30 04:17:20,202 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 322 [2018-01-30 04:17:20,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:20,207 INFO L225 Difference]: With dead ends: 10793 [2018-01-30 04:17:20,207 INFO L226 Difference]: Without dead ends: 10507 [2018-01-30 04:17:20,210 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 365 GetRequests, 323 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 04:17:20,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10507 states. [2018-01-30 04:17:20,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10507 to 10109. [2018-01-30 04:17:20,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10109 states. [2018-01-30 04:17:20,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10109 states to 10109 states and 11414 transitions. [2018-01-30 04:17:20,310 INFO L78 Accepts]: Start accepts. Automaton has 10109 states and 11414 transitions. Word has length 322 [2018-01-30 04:17:20,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:20,310 INFO L432 AbstractCegarLoop]: Abstraction has 10109 states and 11414 transitions. [2018-01-30 04:17:20,310 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-30 04:17:20,310 INFO L276 IsEmpty]: Start isEmpty. Operand 10109 states and 11414 transitions. [2018-01-30 04:17:20,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 330 [2018-01-30 04:17:20,316 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:20,316 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 42, 42, 41, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:20,316 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:20,316 INFO L82 PathProgramCache]: Analyzing trace with hash 1575479634, now seen corresponding path program 13 times [2018-01-30 04:17:20,316 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:20,316 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:20,316 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:20,317 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:20,317 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:20,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:20,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:21,134 INFO L134 CoverageAnalysis]: Checked inductivity of 6147 backedges. 0 proven. 6111 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:21,135 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:21,135 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:21,139 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:17:21,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:21,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:21,213 INFO L134 CoverageAnalysis]: Checked inductivity of 6147 backedges. 0 proven. 6111 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:21,229 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:21,230 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-30 04:17:21,230 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-30 04:17:21,230 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-30 04:17:21,230 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 04:17:21,230 INFO L87 Difference]: Start difference. First operand 10109 states and 11414 transitions. Second operand 45 states. [2018-01-30 04:17:21,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:21,716 INFO L93 Difference]: Finished difference Result 11054 states and 12591 transitions. [2018-01-30 04:17:21,716 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-30 04:17:21,716 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 329 [2018-01-30 04:17:21,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:21,721 INFO L225 Difference]: With dead ends: 11054 [2018-01-30 04:17:21,721 INFO L226 Difference]: Without dead ends: 10768 [2018-01-30 04:17:21,722 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 330 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 04:17:21,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10768 states. [2018-01-30 04:17:21,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10768 to 10365. [2018-01-30 04:17:21,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10365 states. [2018-01-30 04:17:21,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10365 states to 10365 states and 11702 transitions. [2018-01-30 04:17:21,821 INFO L78 Accepts]: Start accepts. Automaton has 10365 states and 11702 transitions. Word has length 329 [2018-01-30 04:17:21,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:21,822 INFO L432 AbstractCegarLoop]: Abstraction has 10365 states and 11702 transitions. [2018-01-30 04:17:21,822 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-30 04:17:21,822 INFO L276 IsEmpty]: Start isEmpty. Operand 10365 states and 11702 transitions. [2018-01-30 04:17:21,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2018-01-30 04:17:21,828 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:21,828 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 43, 43, 42, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:21,828 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:21,828 INFO L82 PathProgramCache]: Analyzing trace with hash -527158758, now seen corresponding path program 14 times [2018-01-30 04:17:21,828 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:21,828 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:21,828 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:21,829 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:17:21,829 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:21,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:21,836 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:22,563 INFO L134 CoverageAnalysis]: Checked inductivity of 6443 backedges. 0 proven. 6407 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:22,563 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:22,563 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:22,567 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 04:17:22,573 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:22,589 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:22,593 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:22,595 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:22,649 INFO L134 CoverageAnalysis]: Checked inductivity of 6443 backedges. 0 proven. 6407 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:22,666 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:22,666 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-30 04:17:22,666 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-30 04:17:22,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-30 04:17:22,667 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 04:17:22,667 INFO L87 Difference]: Start difference. First operand 10365 states and 11702 transitions. Second operand 46 states. [2018-01-30 04:17:23,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:23,341 INFO L93 Difference]: Finished difference Result 11315 states and 12886 transitions. [2018-01-30 04:17:23,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-30 04:17:23,342 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 336 [2018-01-30 04:17:23,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:23,348 INFO L225 Difference]: With dead ends: 11315 [2018-01-30 04:17:23,348 INFO L226 Difference]: Without dead ends: 11029 [2018-01-30 04:17:23,350 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 381 GetRequests, 337 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 04:17:23,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11029 states. [2018-01-30 04:17:23,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11029 to 10621. [2018-01-30 04:17:23,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10621 states. [2018-01-30 04:17:23,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10621 states to 10621 states and 11990 transitions. [2018-01-30 04:17:23,461 INFO L78 Accepts]: Start accepts. Automaton has 10621 states and 11990 transitions. Word has length 336 [2018-01-30 04:17:23,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:23,461 INFO L432 AbstractCegarLoop]: Abstraction has 10621 states and 11990 transitions. [2018-01-30 04:17:23,461 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-30 04:17:23,461 INFO L276 IsEmpty]: Start isEmpty. Operand 10621 states and 11990 transitions. [2018-01-30 04:17:23,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 344 [2018-01-30 04:17:23,467 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:23,467 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 44, 44, 43, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:23,467 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:23,468 INFO L82 PathProgramCache]: Analyzing trace with hash -1057884078, now seen corresponding path program 15 times [2018-01-30 04:17:23,468 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:23,468 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:23,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:23,468 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:23,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:23,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:23,476 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:24,338 INFO L134 CoverageAnalysis]: Checked inductivity of 6746 backedges. 0 proven. 6710 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-01-30 04:17:24,338 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:24,338 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:24,342 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 04:17:24,349 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,351 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,352 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,354 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,355 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,357 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,358 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,360 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,362 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,364 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,366 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,369 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,372 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,375 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,378 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,382 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,386 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,390 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,395 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,400 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,406 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,412 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,418 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,426 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,434 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,443 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,453 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,462 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,473 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,485 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,498 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,512 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,528 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 04:17:24,547 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:24,549 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:24,579 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-01-30 04:17:24,579 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-01-30 04:17:24,580 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-01-30 04:17:24,580 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-01-30 04:17:24,728 INFO L134 CoverageAnalysis]: Checked inductivity of 6746 backedges. 0 proven. 1442 refuted. 0 times theorem prover too weak. 5304 trivial. 0 not checked. [2018-01-30 04:17:24,745 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:24,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 15] total 60 [2018-01-30 04:17:24,746 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-30 04:17:24,746 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-30 04:17:24,746 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1547, Invalid=1993, Unknown=0, NotChecked=0, Total=3540 [2018-01-30 04:17:24,746 INFO L87 Difference]: Start difference. First operand 10621 states and 11990 transitions. Second operand 60 states. [2018-01-30 04:17:26,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:26,744 INFO L93 Difference]: Finished difference Result 11786 states and 13474 transitions. [2018-01-30 04:17:26,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-01-30 04:17:26,744 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 343 [2018-01-30 04:17:26,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:26,749 INFO L225 Difference]: With dead ends: 11786 [2018-01-30 04:17:26,749 INFO L226 Difference]: Without dead ends: 11500 [2018-01-30 04:17:26,750 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 430 GetRequests, 331 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2277 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=3471, Invalid=6629, Unknown=0, NotChecked=0, Total=10100 [2018-01-30 04:17:26,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11500 states. [2018-01-30 04:17:26,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11500 to 10901. [2018-01-30 04:17:26,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10901 states. [2018-01-30 04:17:26,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10901 states to 10901 states and 12303 transitions. [2018-01-30 04:17:26,849 INFO L78 Accepts]: Start accepts. Automaton has 10901 states and 12303 transitions. Word has length 343 [2018-01-30 04:17:26,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:26,849 INFO L432 AbstractCegarLoop]: Abstraction has 10901 states and 12303 transitions. [2018-01-30 04:17:26,849 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-30 04:17:26,849 INFO L276 IsEmpty]: Start isEmpty. Operand 10901 states and 12303 transitions. [2018-01-30 04:17:26,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-01-30 04:17:26,855 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:26,855 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 45, 45, 45, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:26,855 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:26,856 INFO L82 PathProgramCache]: Analyzing trace with hash 162185748, now seen corresponding path program 23 times [2018-01-30 04:17:26,856 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:26,856 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:26,856 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:26,856 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:26,856 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:26,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:26,864 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:27,779 INFO L134 CoverageAnalysis]: Checked inductivity of 7075 backedges. 0 proven. 7020 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 04:17:27,779 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:27,779 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:27,784 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 04:17:27,789 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,791 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,797 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,805 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,812 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,815 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,836 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,841 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,868 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,878 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,889 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,898 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,935 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:27,987 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,006 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,027 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,050 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,075 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,101 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,131 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,164 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,196 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,270 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,323 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 04:17:28,325 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:28,328 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:28,387 INFO L134 CoverageAnalysis]: Checked inductivity of 7075 backedges. 0 proven. 7020 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 04:17:28,407 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:28,407 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-30 04:17:28,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-30 04:17:28,407 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-30 04:17:28,408 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 04:17:28,408 INFO L87 Difference]: Start difference. First operand 10901 states and 12303 transitions. Second operand 48 states. [2018-01-30 04:17:29,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:29,049 INFO L93 Difference]: Finished difference Result 11865 states and 13504 transitions. [2018-01-30 04:17:29,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-30 04:17:29,049 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 353 [2018-01-30 04:17:29,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:29,055 INFO L225 Difference]: With dead ends: 11865 [2018-01-30 04:17:29,056 INFO L226 Difference]: Without dead ends: 11555 [2018-01-30 04:17:29,058 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 400 GetRequests, 354 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 04:17:29,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11555 states. [2018-01-30 04:17:29,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11555 to 11157. [2018-01-30 04:17:29,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11157 states. [2018-01-30 04:17:29,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11157 states to 11157 states and 12591 transitions. [2018-01-30 04:17:29,156 INFO L78 Accepts]: Start accepts. Automaton has 11157 states and 12591 transitions. Word has length 353 [2018-01-30 04:17:29,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:29,156 INFO L432 AbstractCegarLoop]: Abstraction has 11157 states and 12591 transitions. [2018-01-30 04:17:29,156 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-30 04:17:29,156 INFO L276 IsEmpty]: Start isEmpty. Operand 11157 states and 12591 transitions. [2018-01-30 04:17:29,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 361 [2018-01-30 04:17:29,161 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:29,162 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 46, 46, 46, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:29,162 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:29,162 INFO L82 PathProgramCache]: Analyzing trace with hash 2034858504, now seen corresponding path program 24 times [2018-01-30 04:17:29,162 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:29,162 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:29,162 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:29,162 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:29,162 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:29,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:29,171 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:30,195 INFO L134 CoverageAnalysis]: Checked inductivity of 7392 backedges. 0 proven. 7337 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 04:17:30,195 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:30,195 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:30,199 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 04:17:30,205 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,206 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,207 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,208 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,210 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,211 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,212 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,213 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,215 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,217 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,218 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,220 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,222 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,225 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,227 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,229 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,231 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,234 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,240 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,246 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,261 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,266 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,275 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,287 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,293 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,300 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,306 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,313 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,320 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,328 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,336 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,345 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,354 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,365 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,375 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,415 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,431 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,449 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 04:17:30,450 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 04:17:30,453 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:30,510 INFO L134 CoverageAnalysis]: Checked inductivity of 7392 backedges. 0 proven. 7337 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 04:17:30,527 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:30,527 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-30 04:17:30,528 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-30 04:17:30,528 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-30 04:17:30,528 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 04:17:30,528 INFO L87 Difference]: Start difference. First operand 11157 states and 12591 transitions. Second operand 49 states. [2018-01-30 04:17:31,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:31,097 INFO L93 Difference]: Finished difference Result 12126 states and 13799 transitions. [2018-01-30 04:17:31,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-30 04:17:31,097 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 360 [2018-01-30 04:17:31,098 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:31,104 INFO L225 Difference]: With dead ends: 12126 [2018-01-30 04:17:31,104 INFO L226 Difference]: Without dead ends: 11816 [2018-01-30 04:17:31,106 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 408 GetRequests, 361 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 04:17:31,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11816 states. [2018-01-30 04:17:31,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11816 to 11413. [2018-01-30 04:17:31,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11413 states. [2018-01-30 04:17:31,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11413 states to 11413 states and 12879 transitions. [2018-01-30 04:17:31,207 INFO L78 Accepts]: Start accepts. Automaton has 11413 states and 12879 transitions. Word has length 360 [2018-01-30 04:17:31,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:31,208 INFO L432 AbstractCegarLoop]: Abstraction has 11413 states and 12879 transitions. [2018-01-30 04:17:31,208 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-30 04:17:31,208 INFO L276 IsEmpty]: Start isEmpty. Operand 11413 states and 12879 transitions. [2018-01-30 04:17:31,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 368 [2018-01-30 04:17:31,214 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:31,214 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 47, 47, 47, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:31,214 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:31,214 INFO L82 PathProgramCache]: Analyzing trace with hash -711088236, now seen corresponding path program 25 times [2018-01-30 04:17:31,214 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:31,214 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:31,214 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:31,214 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 04:17:31,214 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:31,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:31,223 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 04:17:32,057 INFO L134 CoverageAnalysis]: Checked inductivity of 7716 backedges. 0 proven. 7661 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 04:17:32,057 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 04:17:32,057 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 04:17:32,062 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:17:32,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:32,090 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 04:17:32,149 INFO L134 CoverageAnalysis]: Checked inductivity of 7716 backedges. 0 proven. 7661 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-01-30 04:17:32,166 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 04:17:32,166 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-30 04:17:32,166 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-30 04:17:32,166 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-30 04:17:32,167 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 04:17:32,167 INFO L87 Difference]: Start difference. First operand 11413 states and 12879 transitions. Second operand 50 states. [2018-01-30 04:17:32,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 04:17:32,774 INFO L93 Difference]: Finished difference Result 12387 states and 14094 transitions. [2018-01-30 04:17:32,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-30 04:17:32,775 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 367 [2018-01-30 04:17:32,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 04:17:32,779 INFO L225 Difference]: With dead ends: 12387 [2018-01-30 04:17:32,779 INFO L226 Difference]: Without dead ends: 12077 [2018-01-30 04:17:32,780 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 368 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 04:17:32,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12077 states. [2018-01-30 04:17:32,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12077 to 11669. [2018-01-30 04:17:32,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11669 states. [2018-01-30 04:17:32,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11669 states to 11669 states and 13167 transitions. [2018-01-30 04:17:32,878 INFO L78 Accepts]: Start accepts. Automaton has 11669 states and 13167 transitions. Word has length 367 [2018-01-30 04:17:32,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 04:17:32,878 INFO L432 AbstractCegarLoop]: Abstraction has 11669 states and 13167 transitions. [2018-01-30 04:17:32,878 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-30 04:17:32,878 INFO L276 IsEmpty]: Start isEmpty. Operand 11669 states and 13167 transitions. [2018-01-30 04:17:32,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2018-01-30 04:17:32,884 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 04:17:32,884 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 48, 48, 48, 6, 6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 04:17:32,884 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 04:17:32,885 INFO L82 PathProgramCache]: Analyzing trace with hash 382821512, now seen corresponding path program 26 times [2018-01-30 04:17:32,885 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 04:17:32,885 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 04:17:32,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:32,885 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 04:17:32,885 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 04:17:32,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 04:17:32,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-01-30 04:17:33,658 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-30 04:17:33,661 WARN L185 ceAbstractionStarter]: Timeout [2018-01-30 04:17:33,661 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 04:17:33 BasicIcfg [2018-01-30 04:17:33,661 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-30 04:17:33,662 INFO L168 Benchmark]: Toolchain (without parser) took 64790.43 ms. Allocated memory was 150.5 MB in the beginning and 1.4 GB in the end (delta: 1.3 GB). Free memory was 116.7 MB in the beginning and 1.2 GB in the end (delta: -1.1 GB). Peak memory consumption was 223.4 MB. Max. memory is 5.3 GB. [2018-01-30 04:17:33,663 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 150.5 MB. Free memory is still 121.4 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-30 04:17:33,663 INFO L168 Benchmark]: CACSL2BoogieTranslator took 100.51 ms. Allocated memory is still 150.5 MB. Free memory was 116.5 MB in the beginning and 108.5 MB in the end (delta: 7.9 MB). Peak memory consumption was 7.9 MB. Max. memory is 5.3 GB. [2018-01-30 04:17:33,663 INFO L168 Benchmark]: Boogie Preprocessor took 16.77 ms. Allocated memory is still 150.5 MB. Free memory was 108.5 MB in the beginning and 107.1 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-30 04:17:33,663 INFO L168 Benchmark]: RCFGBuilder took 213.39 ms. Allocated memory is still 150.5 MB. Free memory was 106.9 MB in the beginning and 95.4 MB in the end (delta: 11.5 MB). Peak memory consumption was 11.5 MB. Max. memory is 5.3 GB. [2018-01-30 04:17:33,663 INFO L168 Benchmark]: IcfgTransformer took 21.21 ms. Allocated memory is still 150.5 MB. Free memory was 95.4 MB in the beginning and 94.3 MB in the end (delta: 1.1 MB). Peak memory consumption was 1.1 MB. Max. memory is 5.3 GB. [2018-01-30 04:17:33,663 INFO L168 Benchmark]: TraceAbstraction took 64436.20 ms. Allocated memory was 150.5 MB in the beginning and 1.4 GB in the end (delta: 1.3 GB). Free memory was 94.1 MB in the beginning and 1.2 GB in the end (delta: -1.1 GB). Peak memory consumption was 200.8 MB. Max. memory is 5.3 GB. [2018-01-30 04:17:33,664 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 150.5 MB. Free memory is still 121.4 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 100.51 ms. Allocated memory is still 150.5 MB. Free memory was 116.5 MB in the beginning and 108.5 MB in the end (delta: 7.9 MB). Peak memory consumption was 7.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 16.77 ms. Allocated memory is still 150.5 MB. Free memory was 108.5 MB in the beginning and 107.1 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * RCFGBuilder took 213.39 ms. Allocated memory is still 150.5 MB. Free memory was 106.9 MB in the beginning and 95.4 MB in the end (delta: 11.5 MB). Peak memory consumption was 11.5 MB. Max. memory is 5.3 GB. * IcfgTransformer took 21.21 ms. Allocated memory is still 150.5 MB. Free memory was 95.4 MB in the beginning and 94.3 MB in the end (delta: 1.1 MB). Peak memory consumption was 1.1 MB. Max. memory is 5.3 GB. * TraceAbstraction took 64436.20 ms. Allocated memory was 150.5 MB in the beginning and 1.4 GB in the end (delta: 1.3 GB). Free memory was 94.1 MB in the beginning and 1.2 GB in the end (delta: -1.1 GB). Peak memory consumption was 200.8 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 2]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 2). Cancelled while BasicCegarLoop was analyzing trace of length 375 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 47 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 32 locations, 1 error locations. TIMEOUT Result, 64.3s OverallTime, 50 OverallIterations, 49 TraceHistogramMax, 29.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3077 SDtfs, 23968 SDslu, 25055 SDs, 0 SdLazy, 45924 SolverSat, 5375 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 19.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 10654 GetRequests, 9099 SyntacticMatches, 5 SemanticMatches, 1550 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12634 ImplicationChecksByTransitivity, 21.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=11669occurred in iteration=49, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.7s AutomataMinimizationTime, 49 MinimizatonAttempts, 10084 StatesRemovedByMinimization, 48 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 3.5s SatisfiabilityAnalysisTime, 26.5s InterpolantComputationTime, 18475 NumberOfCodeBlocks, 18099 NumberOfCodeBlocksAsserted, 644 NumberOfCheckSat, 18379 ConstructedInterpolants, 0 QuantifiedInterpolants, 14154367 SizeOfPredicates, 149 NumberOfNonLiveVariables, 11732 ConjunctsInSsa, 1329 ConjunctsInUnsatCore, 96 InterpolantComputations, 2 PerfectInterpolantSequences, 18474/248450 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array_monotonic_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-30_04-17-33-671.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/array_monotonic_true-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-30_04-17-33-671.csv Completed graceful shutdown