java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-examples/sorting_bubblesort_false-unreach-call_ground.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-1cceb4a-m [2018-01-30 02:31:50,871 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-30 02:31:50,872 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-30 02:31:50,882 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-30 02:31:50,882 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-30 02:31:50,883 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-30 02:31:50,883 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-30 02:31:50,884 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-30 02:31:50,885 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-30 02:31:50,886 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-30 02:31:50,886 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-30 02:31:50,886 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-30 02:31:50,887 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-30 02:31:50,888 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-30 02:31:50,888 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-30 02:31:50,889 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-30 02:31:50,890 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-30 02:31:50,891 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-30 02:31:50,892 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-30 02:31:50,893 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-30 02:31:50,894 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-01-30 02:31:50,897 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-30 02:31:50,897 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-30 02:31:50,897 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-30 02:31:50,902 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-30 02:31:50,902 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-30 02:31:50,903 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-30 02:31:50,903 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-30 02:31:50,903 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-30 02:31:50,903 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-30 02:31:50,903 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-30 02:31:50,904 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-30 02:31:50,904 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-30 02:31:50,905 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 02:31:50,905 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-30 02:31:50,905 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-30 02:31:50,906 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-30 02:31:50,906 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-30 02:31:50,906 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-30 02:31:50,906 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-30 02:31:50,906 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-30 02:31:50,906 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-30 02:31:50,906 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-30 02:31:50,928 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-30 02:31:50,935 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-30 02:31:50,938 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-30 02:31:50,939 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-30 02:31:50,939 INFO L276 PluginConnector]: CDTParser initialized [2018-01-30 02:31:50,939 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-examples/sorting_bubblesort_false-unreach-call_ground.i [2018-01-30 02:31:51,006 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-30 02:31:51,007 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-30 02:31:51,008 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-30 02:31:51,008 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-30 02:31:51,011 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-30 02:31:51,012 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,015 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@57b49c06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51, skipping insertion in model container [2018-01-30 02:31:51,015 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,025 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 02:31:51,035 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-30 02:31:51,110 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 02:31:51,119 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-30 02:31:51,122 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51 WrapperNode [2018-01-30 02:31:51,122 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-30 02:31:51,122 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-30 02:31:51,122 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-30 02:31:51,122 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-30 02:31:51,130 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,130 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,135 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,135 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,136 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,138 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,138 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,139 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-30 02:31:51,139 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-30 02:31:51,140 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-30 02:31:51,140 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-30 02:31:51,140 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-30 02:31:51,180 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-30 02:31:51,180 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-30 02:31:51,180 INFO L136 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-01-30 02:31:51,180 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-30 02:31:51,180 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-30 02:31:51,180 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-01-30 02:31:51,180 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-30 02:31:51,180 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-30 02:31:51,180 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-30 02:31:51,508 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-30 02:31:51,508 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 02:31:51 BoogieIcfgContainer [2018-01-30 02:31:51,508 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-30 02:31:51,508 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-30 02:31:51,509 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-30 02:31:51,509 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-30 02:31:51,511 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 02:31:51" (1/1) ... [2018-01-30 02:31:51,514 WARN L213 ansformationObserver]: HeapSeparator: input icfg has no '#valid' array -- returning unchanged Icfg! [2018-01-30 02:31:51,520 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 30.01 02:31:51 BasicIcfg [2018-01-30 02:31:51,520 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-30 02:31:51,521 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-30 02:31:51,521 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-30 02:31:51,523 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-30 02:31:51,523 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 30.01 02:31:51" (1/4) ... [2018-01-30 02:31:51,523 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1964c024 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 02:31:51, skipping insertion in model container [2018-01-30 02:31:51,523 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 30.01 02:31:51" (2/4) ... [2018-01-30 02:31:51,524 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1964c024 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 30.01 02:31:51, skipping insertion in model container [2018-01-30 02:31:51,524 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 30.01 02:31:51" (3/4) ... [2018-01-30 02:31:51,524 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1964c024 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 02:31:51, skipping insertion in model container [2018-01-30 02:31:51,524 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 30.01 02:31:51" (4/4) ... [2018-01-30 02:31:51,525 INFO L107 eAbstractionObserver]: Analyzing ICFG sorting_bubblesort_false-unreach-call_ground.ileft_unchanged_by_heapseparator [2018-01-30 02:31:51,530 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-30 02:31:51,535 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-30 02:31:51,559 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-30 02:31:51,559 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-30 02:31:51,559 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-30 02:31:51,559 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-30 02:31:51,559 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-30 02:31:51,559 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-30 02:31:51,559 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-30 02:31:51,559 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-30 02:31:51,560 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-30 02:31:51,569 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states. [2018-01-30 02:31:51,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-01-30 02:31:51,573 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:51,573 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:51,573 INFO L371 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:51,576 INFO L82 PathProgramCache]: Analyzing trace with hash 1743967112, now seen corresponding path program 1 times [2018-01-30 02:31:51,577 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:51,577 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:51,606 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,606 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:51,606 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:51,626 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:51,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:51,643 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 02:31:51,644 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-30 02:31:51,645 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-30 02:31:51,652 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-30 02:31:51,652 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 02:31:51,653 INFO L87 Difference]: Start difference. First operand 44 states. Second operand 2 states. [2018-01-30 02:31:51,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:51,667 INFO L93 Difference]: Finished difference Result 82 states and 100 transitions. [2018-01-30 02:31:51,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-30 02:31:51,668 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 19 [2018-01-30 02:31:51,668 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:51,673 INFO L225 Difference]: With dead ends: 82 [2018-01-30 02:31:51,674 INFO L226 Difference]: Without dead ends: 39 [2018-01-30 02:31:51,675 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-30 02:31:51,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-01-30 02:31:51,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-01-30 02:31:51,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-01-30 02:31:51,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 44 transitions. [2018-01-30 02:31:51,698 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 44 transitions. Word has length 19 [2018-01-30 02:31:51,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:51,698 INFO L432 AbstractCegarLoop]: Abstraction has 39 states and 44 transitions. [2018-01-30 02:31:51,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-30 02:31:51,698 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 44 transitions. [2018-01-30 02:31:51,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-01-30 02:31:51,699 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:51,699 INFO L350 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:51,699 INFO L371 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:51,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1644655049, now seen corresponding path program 1 times [2018-01-30 02:31:51,700 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:51,700 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:51,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,700 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:51,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:51,705 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:51,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:51,803 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 02:31:51,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-30 02:31:51,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-30 02:31:51,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-30 02:31:51,805 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 02:31:51,805 INFO L87 Difference]: Start difference. First operand 39 states and 44 transitions. Second operand 3 states. [2018-01-30 02:31:51,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:51,830 INFO L93 Difference]: Finished difference Result 71 states and 81 transitions. [2018-01-30 02:31:51,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-30 02:31:51,832 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2018-01-30 02:31:51,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:51,832 INFO L225 Difference]: With dead ends: 71 [2018-01-30 02:31:51,833 INFO L226 Difference]: Without dead ends: 50 [2018-01-30 02:31:51,833 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 02:31:51,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-01-30 02:31:51,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 45. [2018-01-30 02:31:51,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-01-30 02:31:51,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 52 transitions. [2018-01-30 02:31:51,838 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 52 transitions. Word has length 20 [2018-01-30 02:31:51,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:51,838 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 52 transitions. [2018-01-30 02:31:51,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-30 02:31:51,838 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 52 transitions. [2018-01-30 02:31:51,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-01-30 02:31:51,839 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:51,839 INFO L350 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:51,839 INFO L371 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:51,839 INFO L82 PathProgramCache]: Analyzing trace with hash -249012782, now seen corresponding path program 1 times [2018-01-30 02:31:51,839 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:51,839 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:51,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,840 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:51,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:51,854 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:51,883 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:51,883 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-30 02:31:51,883 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-30 02:31:51,883 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-30 02:31:51,884 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-30 02:31:51,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 02:31:51,884 INFO L87 Difference]: Start difference. First operand 45 states and 52 transitions. Second operand 3 states. [2018-01-30 02:31:51,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:51,944 INFO L93 Difference]: Finished difference Result 93 states and 109 transitions. [2018-01-30 02:31:51,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-30 02:31:51,945 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-01-30 02:31:51,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:51,945 INFO L225 Difference]: With dead ends: 93 [2018-01-30 02:31:51,945 INFO L226 Difference]: Without dead ends: 54 [2018-01-30 02:31:51,946 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-30 02:31:51,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-01-30 02:31:51,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 47. [2018-01-30 02:31:51,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-01-30 02:31:51,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 54 transitions. [2018-01-30 02:31:51,952 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 54 transitions. Word has length 26 [2018-01-30 02:31:51,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:51,952 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 54 transitions. [2018-01-30 02:31:51,952 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-30 02:31:51,952 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 54 transitions. [2018-01-30 02:31:51,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-01-30 02:31:51,953 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:51,953 INFO L350 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:51,953 INFO L371 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:51,953 INFO L82 PathProgramCache]: Analyzing trace with hash -825389157, now seen corresponding path program 1 times [2018-01-30 02:31:51,953 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:51,953 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:51,954 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,954 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:51,954 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:51,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:51,962 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:52,036 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,036 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:52,037 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:52,048 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:52,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:52,062 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:52,074 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,091 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:52,091 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-01-30 02:31:52,091 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-30 02:31:52,091 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-30 02:31:52,091 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 02:31:52,091 INFO L87 Difference]: Start difference. First operand 47 states and 54 transitions. Second operand 4 states. [2018-01-30 02:31:52,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:52,175 INFO L93 Difference]: Finished difference Result 107 states and 126 transitions. [2018-01-30 02:31:52,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-30 02:31:52,175 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2018-01-30 02:31:52,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:52,176 INFO L225 Difference]: With dead ends: 107 [2018-01-30 02:31:52,176 INFO L226 Difference]: Without dead ends: 66 [2018-01-30 02:31:52,176 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-30 02:31:52,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-01-30 02:31:52,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 58. [2018-01-30 02:31:52,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-01-30 02:31:52,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 66 transitions. [2018-01-30 02:31:52,179 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 66 transitions. Word has length 30 [2018-01-30 02:31:52,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:52,180 INFO L432 AbstractCegarLoop]: Abstraction has 58 states and 66 transitions. [2018-01-30 02:31:52,180 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-30 02:31:52,180 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 66 transitions. [2018-01-30 02:31:52,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-01-30 02:31:52,180 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:52,180 INFO L350 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:52,180 INFO L371 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:52,180 INFO L82 PathProgramCache]: Analyzing trace with hash 260224228, now seen corresponding path program 2 times [2018-01-30 02:31:52,181 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:52,181 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:52,181 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:52,181 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:52,181 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:52,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:52,190 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:52,353 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,353 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:52,353 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:52,359 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:31:52,365 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:52,370 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:52,376 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:52,377 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:52,381 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,400 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:52,400 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-01-30 02:31:52,400 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-01-30 02:31:52,400 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-01-30 02:31:52,400 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 02:31:52,400 INFO L87 Difference]: Start difference. First operand 58 states and 66 transitions. Second operand 5 states. [2018-01-30 02:31:52,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:52,464 INFO L93 Difference]: Finished difference Result 130 states and 152 transitions. [2018-01-30 02:31:52,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-01-30 02:31:52,465 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 34 [2018-01-30 02:31:52,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:52,465 INFO L225 Difference]: With dead ends: 130 [2018-01-30 02:31:52,465 INFO L226 Difference]: Without dead ends: 78 [2018-01-30 02:31:52,465 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-01-30 02:31:52,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-01-30 02:31:52,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 70. [2018-01-30 02:31:52,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-01-30 02:31:52,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 80 transitions. [2018-01-30 02:31:52,472 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 80 transitions. Word has length 34 [2018-01-30 02:31:52,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:52,473 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 80 transitions. [2018-01-30 02:31:52,474 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-01-30 02:31:52,474 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 80 transitions. [2018-01-30 02:31:52,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-30 02:31:52,474 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:52,474 INFO L350 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:52,474 INFO L371 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:52,475 INFO L82 PathProgramCache]: Analyzing trace with hash -81654355, now seen corresponding path program 3 times [2018-01-30 02:31:52,475 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:52,475 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:52,475 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:52,475 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:52,475 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:52,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:52,481 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:52,530 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,530 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:52,530 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 02:31:52,538 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:52,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:52,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:52,550 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:52,551 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:52,552 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:52,562 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:52,563 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:52,567 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 2 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,585 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:52,585 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-01-30 02:31:52,585 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-30 02:31:52,586 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-30 02:31:52,586 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 02:31:52,586 INFO L87 Difference]: Start difference. First operand 70 states and 80 transitions. Second operand 6 states. [2018-01-30 02:31:52,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:52,666 INFO L93 Difference]: Finished difference Result 154 states and 180 transitions. [2018-01-30 02:31:52,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-01-30 02:31:52,666 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2018-01-30 02:31:52,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:52,667 INFO L225 Difference]: With dead ends: 154 [2018-01-30 02:31:52,667 INFO L226 Difference]: Without dead ends: 90 [2018-01-30 02:31:52,667 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-01-30 02:31:52,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-01-30 02:31:52,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 82. [2018-01-30 02:31:52,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-01-30 02:31:52,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 94 transitions. [2018-01-30 02:31:52,671 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 94 transitions. Word has length 38 [2018-01-30 02:31:52,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:52,672 INFO L432 AbstractCegarLoop]: Abstraction has 82 states and 94 transitions. [2018-01-30 02:31:52,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-30 02:31:52,672 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 94 transitions. [2018-01-30 02:31:52,672 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-01-30 02:31:52,674 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:52,674 INFO L350 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:52,674 INFO L371 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:52,674 INFO L82 PathProgramCache]: Analyzing trace with hash -496641546, now seen corresponding path program 4 times [2018-01-30 02:31:52,674 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:52,674 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:52,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:52,675 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:52,675 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:52,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:52,680 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:52,734 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:52,734 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:52,754 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:31:52,766 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:52,767 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:52,771 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:52,788 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:52,788 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2018-01-30 02:31:52,788 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-01-30 02:31:52,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-01-30 02:31:52,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-30 02:31:52,789 INFO L87 Difference]: Start difference. First operand 82 states and 94 transitions. Second operand 7 states. [2018-01-30 02:31:53,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:53,045 INFO L93 Difference]: Finished difference Result 178 states and 208 transitions. [2018-01-30 02:31:53,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-30 02:31:53,045 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 42 [2018-01-30 02:31:53,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:53,046 INFO L225 Difference]: With dead ends: 178 [2018-01-30 02:31:53,046 INFO L226 Difference]: Without dead ends: 102 [2018-01-30 02:31:53,046 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2018-01-30 02:31:53,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-01-30 02:31:53,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 94. [2018-01-30 02:31:53,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-01-30 02:31:53,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 108 transitions. [2018-01-30 02:31:53,050 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 108 transitions. Word has length 42 [2018-01-30 02:31:53,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:53,050 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 108 transitions. [2018-01-30 02:31:53,050 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-01-30 02:31:53,050 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 108 transitions. [2018-01-30 02:31:53,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-30 02:31:53,051 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:53,051 INFO L350 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:53,051 INFO L371 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:53,051 INFO L82 PathProgramCache]: Analyzing trace with hash -1360504385, now seen corresponding path program 5 times [2018-01-30 02:31:53,051 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:53,051 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:53,052 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:53,052 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:53,052 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:53,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:53,057 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:53,148 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:53,149 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:53,149 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:53,153 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:31:53,157 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:53,158 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:53,159 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:53,159 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:53,160 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:53,161 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:53,161 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:53,162 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:53,167 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 2 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:53,183 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:53,183 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2018-01-30 02:31:53,184 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-01-30 02:31:53,184 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-01-30 02:31:53,184 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 02:31:53,184 INFO L87 Difference]: Start difference. First operand 94 states and 108 transitions. Second operand 8 states. [2018-01-30 02:31:53,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:53,336 INFO L93 Difference]: Finished difference Result 202 states and 236 transitions. [2018-01-30 02:31:53,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-01-30 02:31:53,338 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-01-30 02:31:53,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:53,338 INFO L225 Difference]: With dead ends: 202 [2018-01-30 02:31:53,338 INFO L226 Difference]: Without dead ends: 114 [2018-01-30 02:31:53,339 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-01-30 02:31:53,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-30 02:31:53,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 106. [2018-01-30 02:31:53,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-01-30 02:31:53,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-01-30 02:31:53,343 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 46 [2018-01-30 02:31:53,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:53,343 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-01-30 02:31:53,343 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-01-30 02:31:53,344 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-01-30 02:31:53,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-01-30 02:31:53,344 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:53,344 INFO L350 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:53,344 INFO L371 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:53,344 INFO L82 PathProgramCache]: Analyzing trace with hash 1931726088, now seen corresponding path program 6 times [2018-01-30 02:31:53,344 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:53,345 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:53,345 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:53,345 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:53,345 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:53,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:53,352 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:53,446 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:53,446 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:53,447 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:53,454 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:31:53,461 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,466 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,466 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,467 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,468 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,469 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,470 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,470 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:53,478 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:53,480 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:53,487 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:53,504 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:53,504 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2018-01-30 02:31:53,504 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-30 02:31:53,504 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-30 02:31:53,505 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 02:31:53,505 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 9 states. [2018-01-30 02:31:53,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:53,610 INFO L93 Difference]: Finished difference Result 226 states and 264 transitions. [2018-01-30 02:31:53,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-01-30 02:31:53,610 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 50 [2018-01-30 02:31:53,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:53,611 INFO L225 Difference]: With dead ends: 226 [2018-01-30 02:31:53,611 INFO L226 Difference]: Without dead ends: 126 [2018-01-30 02:31:53,611 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-01-30 02:31:53,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-01-30 02:31:53,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 118. [2018-01-30 02:31:53,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-01-30 02:31:53,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 136 transitions. [2018-01-30 02:31:53,615 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 136 transitions. Word has length 50 [2018-01-30 02:31:53,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:53,615 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 136 transitions. [2018-01-30 02:31:53,615 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-30 02:31:53,616 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 136 transitions. [2018-01-30 02:31:53,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-01-30 02:31:53,616 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:53,616 INFO L350 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:53,616 INFO L371 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:53,616 INFO L82 PathProgramCache]: Analyzing trace with hash -93162543, now seen corresponding path program 7 times [2018-01-30 02:31:53,616 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:53,616 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:53,617 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:53,617 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:53,617 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:53,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:53,622 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:53,802 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:53,802 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:53,802 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:53,807 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:53,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:53,815 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:53,826 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 2 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:53,843 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:53,843 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2018-01-30 02:31:53,843 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-30 02:31:53,844 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-30 02:31:53,844 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-30 02:31:53,844 INFO L87 Difference]: Start difference. First operand 118 states and 136 transitions. Second operand 10 states. [2018-01-30 02:31:54,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:54,022 INFO L93 Difference]: Finished difference Result 250 states and 292 transitions. [2018-01-30 02:31:54,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-30 02:31:54,023 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-01-30 02:31:54,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:54,023 INFO L225 Difference]: With dead ends: 250 [2018-01-30 02:31:54,023 INFO L226 Difference]: Without dead ends: 138 [2018-01-30 02:31:54,024 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-01-30 02:31:54,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-01-30 02:31:54,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 130. [2018-01-30 02:31:54,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-01-30 02:31:54,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 150 transitions. [2018-01-30 02:31:54,027 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 150 transitions. Word has length 54 [2018-01-30 02:31:54,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:54,027 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 150 transitions. [2018-01-30 02:31:54,027 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-30 02:31:54,027 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 150 transitions. [2018-01-30 02:31:54,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-01-30 02:31:54,028 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:54,028 INFO L350 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:54,028 INFO L371 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:54,028 INFO L82 PathProgramCache]: Analyzing trace with hash 1494126106, now seen corresponding path program 8 times [2018-01-30 02:31:54,029 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:54,029 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:54,029 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,029 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:54,029 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:54,040 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:54,156 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 2 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,156 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:54,156 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:54,161 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:31:54,166 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:54,174 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:54,175 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:54,176 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:54,183 INFO L134 CoverageAnalysis]: Checked inductivity of 130 backedges. 2 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,200 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:54,200 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2018-01-30 02:31:54,201 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-01-30 02:31:54,201 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-01-30 02:31:54,201 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 02:31:54,201 INFO L87 Difference]: Start difference. First operand 130 states and 150 transitions. Second operand 11 states. [2018-01-30 02:31:54,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:54,308 INFO L93 Difference]: Finished difference Result 274 states and 320 transitions. [2018-01-30 02:31:54,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-01-30 02:31:54,309 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 58 [2018-01-30 02:31:54,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:54,316 INFO L225 Difference]: With dead ends: 274 [2018-01-30 02:31:54,317 INFO L226 Difference]: Without dead ends: 150 [2018-01-30 02:31:54,317 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2018-01-30 02:31:54,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-01-30 02:31:54,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 142. [2018-01-30 02:31:54,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-01-30 02:31:54,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 164 transitions. [2018-01-30 02:31:54,321 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 164 transitions. Word has length 58 [2018-01-30 02:31:54,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:54,321 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 164 transitions. [2018-01-30 02:31:54,321 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-01-30 02:31:54,321 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 164 transitions. [2018-01-30 02:31:54,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-30 02:31:54,322 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:54,322 INFO L350 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:54,322 INFO L371 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:54,322 INFO L82 PathProgramCache]: Analyzing trace with hash 2081577955, now seen corresponding path program 9 times [2018-01-30 02:31:54,322 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:54,322 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:54,322 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,322 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:54,322 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:54,328 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:54,411 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 2 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,412 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:54,412 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:54,416 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:31:54,420 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,423 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,424 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,425 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,426 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,427 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,428 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,429 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,430 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,431 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:54,431 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:54,433 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:54,439 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 2 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,455 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:54,455 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2018-01-30 02:31:54,456 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-01-30 02:31:54,456 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-01-30 02:31:54,456 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 02:31:54,456 INFO L87 Difference]: Start difference. First operand 142 states and 164 transitions. Second operand 12 states. [2018-01-30 02:31:54,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:54,572 INFO L93 Difference]: Finished difference Result 298 states and 348 transitions. [2018-01-30 02:31:54,572 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-01-30 02:31:54,572 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 62 [2018-01-30 02:31:54,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:54,572 INFO L225 Difference]: With dead ends: 298 [2018-01-30 02:31:54,573 INFO L226 Difference]: Without dead ends: 162 [2018-01-30 02:31:54,573 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-01-30 02:31:54,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-01-30 02:31:54,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 154. [2018-01-30 02:31:54,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-01-30 02:31:54,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 178 transitions. [2018-01-30 02:31:54,576 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 178 transitions. Word has length 62 [2018-01-30 02:31:54,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:54,576 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 178 transitions. [2018-01-30 02:31:54,576 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-01-30 02:31:54,576 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 178 transitions. [2018-01-30 02:31:54,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-01-30 02:31:54,577 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:54,577 INFO L350 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:54,577 INFO L371 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:54,577 INFO L82 PathProgramCache]: Analyzing trace with hash -1183310548, now seen corresponding path program 10 times [2018-01-30 02:31:54,577 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:54,577 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:54,578 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,578 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:54,578 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:54,583 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:54,731 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 2 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,731 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:54,731 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:54,738 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:31:54,745 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:54,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:54,753 INFO L134 CoverageAnalysis]: Checked inductivity of 202 backedges. 2 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,769 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:54,769 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2018-01-30 02:31:54,770 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-30 02:31:54,770 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-30 02:31:54,770 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 02:31:54,770 INFO L87 Difference]: Start difference. First operand 154 states and 178 transitions. Second operand 13 states. [2018-01-30 02:31:54,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:54,861 INFO L93 Difference]: Finished difference Result 322 states and 376 transitions. [2018-01-30 02:31:54,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-30 02:31:54,861 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 66 [2018-01-30 02:31:54,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:54,861 INFO L225 Difference]: With dead ends: 322 [2018-01-30 02:31:54,861 INFO L226 Difference]: Without dead ends: 174 [2018-01-30 02:31:54,862 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-01-30 02:31:54,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-01-30 02:31:54,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 166. [2018-01-30 02:31:54,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-01-30 02:31:54,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 192 transitions. [2018-01-30 02:31:54,864 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 192 transitions. Word has length 66 [2018-01-30 02:31:54,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:54,865 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 192 transitions. [2018-01-30 02:31:54,865 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-30 02:31:54,865 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 192 transitions. [2018-01-30 02:31:54,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-01-30 02:31:54,865 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:54,865 INFO L350 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:54,865 INFO L371 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:54,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1612321269, now seen corresponding path program 11 times [2018-01-30 02:31:54,865 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:54,866 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:54,866 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,866 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:54,866 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:54,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:54,872 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:54,955 INFO L134 CoverageAnalysis]: Checked inductivity of 244 backedges. 2 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:54,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:54,955 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:54,960 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:31:54,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:54,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:54,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:54,995 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,005 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,015 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,025 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,035 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,045 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,052 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,062 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,075 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:55,085 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:55,086 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:55,093 INFO L134 CoverageAnalysis]: Checked inductivity of 244 backedges. 2 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:55,119 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:55,119 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2018-01-30 02:31:55,119 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-30 02:31:55,119 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-30 02:31:55,119 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-30 02:31:55,119 INFO L87 Difference]: Start difference. First operand 166 states and 192 transitions. Second operand 14 states. [2018-01-30 02:31:55,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:55,282 INFO L93 Difference]: Finished difference Result 346 states and 404 transitions. [2018-01-30 02:31:55,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-01-30 02:31:55,282 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 70 [2018-01-30 02:31:55,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:55,283 INFO L225 Difference]: With dead ends: 346 [2018-01-30 02:31:55,283 INFO L226 Difference]: Without dead ends: 186 [2018-01-30 02:31:55,283 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-01-30 02:31:55,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-30 02:31:55,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 178. [2018-01-30 02:31:55,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-01-30 02:31:55,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 206 transitions. [2018-01-30 02:31:55,286 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 206 transitions. Word has length 70 [2018-01-30 02:31:55,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:55,286 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 206 transitions. [2018-01-30 02:31:55,286 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-30 02:31:55,286 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 206 transitions. [2018-01-30 02:31:55,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-01-30 02:31:55,287 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:55,287 INFO L350 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:55,287 INFO L371 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:55,287 INFO L82 PathProgramCache]: Analyzing trace with hash 1202879038, now seen corresponding path program 12 times [2018-01-30 02:31:55,287 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:55,287 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:55,287 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:55,287 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:55,288 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:55,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:55,292 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:55,415 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 2 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:55,415 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:55,415 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:55,420 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:31:55,424 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,426 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,433 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,433 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,439 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,440 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,442 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,444 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,445 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:55,445 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:55,446 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:55,454 INFO L134 CoverageAnalysis]: Checked inductivity of 290 backedges. 2 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:55,470 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:55,470 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2018-01-30 02:31:55,471 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-30 02:31:55,471 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-30 02:31:55,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 02:31:55,471 INFO L87 Difference]: Start difference. First operand 178 states and 206 transitions. Second operand 15 states. [2018-01-30 02:31:55,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:55,583 INFO L93 Difference]: Finished difference Result 370 states and 432 transitions. [2018-01-30 02:31:55,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-01-30 02:31:55,584 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-01-30 02:31:55,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:55,584 INFO L225 Difference]: With dead ends: 370 [2018-01-30 02:31:55,584 INFO L226 Difference]: Without dead ends: 198 [2018-01-30 02:31:55,585 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 75 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2018-01-30 02:31:55,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-01-30 02:31:55,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 190. [2018-01-30 02:31:55,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 190 states. [2018-01-30 02:31:55,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 220 transitions. [2018-01-30 02:31:55,587 INFO L78 Accepts]: Start accepts. Automaton has 190 states and 220 transitions. Word has length 74 [2018-01-30 02:31:55,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:55,588 INFO L432 AbstractCegarLoop]: Abstraction has 190 states and 220 transitions. [2018-01-30 02:31:55,588 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-30 02:31:55,588 INFO L276 IsEmpty]: Start isEmpty. Operand 190 states and 220 transitions. [2018-01-30 02:31:55,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-30 02:31:55,588 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:55,588 INFO L350 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:55,588 INFO L371 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:55,588 INFO L82 PathProgramCache]: Analyzing trace with hash 1625003527, now seen corresponding path program 13 times [2018-01-30 02:31:55,588 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:55,589 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:55,589 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:55,589 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:55,589 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:55,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:55,595 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:55,750 INFO L134 CoverageAnalysis]: Checked inductivity of 340 backedges. 2 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:55,750 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:55,750 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:55,756 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:55,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:55,769 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:55,784 INFO L134 CoverageAnalysis]: Checked inductivity of 340 backedges. 2 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:55,800 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:55,801 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2018-01-30 02:31:55,801 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-01-30 02:31:55,801 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-01-30 02:31:55,801 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 02:31:55,801 INFO L87 Difference]: Start difference. First operand 190 states and 220 transitions. Second operand 16 states. [2018-01-30 02:31:55,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:55,907 INFO L93 Difference]: Finished difference Result 394 states and 460 transitions. [2018-01-30 02:31:55,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-30 02:31:55,922 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 78 [2018-01-30 02:31:55,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:55,922 INFO L225 Difference]: With dead ends: 394 [2018-01-30 02:31:55,922 INFO L226 Difference]: Without dead ends: 210 [2018-01-30 02:31:55,923 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-01-30 02:31:55,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-01-30 02:31:55,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 202. [2018-01-30 02:31:55,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-01-30 02:31:55,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 234 transitions. [2018-01-30 02:31:55,926 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 234 transitions. Word has length 78 [2018-01-30 02:31:55,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:55,926 INFO L432 AbstractCegarLoop]: Abstraction has 202 states and 234 transitions. [2018-01-30 02:31:55,926 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-01-30 02:31:55,926 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 234 transitions. [2018-01-30 02:31:55,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-01-30 02:31:55,926 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:55,927 INFO L350 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:55,927 INFO L371 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:55,927 INFO L82 PathProgramCache]: Analyzing trace with hash 1158653264, now seen corresponding path program 14 times [2018-01-30 02:31:55,927 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:55,927 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:55,927 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:55,927 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:55,927 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:55,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:55,932 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:56,109 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 2 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:56,109 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:56,109 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:56,114 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:31:56,117 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:56,121 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:56,122 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:56,123 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:56,131 INFO L134 CoverageAnalysis]: Checked inductivity of 394 backedges. 2 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:56,165 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:56,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2018-01-30 02:31:56,165 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-30 02:31:56,166 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-30 02:31:56,166 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-30 02:31:56,166 INFO L87 Difference]: Start difference. First operand 202 states and 234 transitions. Second operand 17 states. [2018-01-30 02:31:56,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:56,414 INFO L93 Difference]: Finished difference Result 418 states and 488 transitions. [2018-01-30 02:31:56,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-01-30 02:31:56,415 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 82 [2018-01-30 02:31:56,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:56,416 INFO L225 Difference]: With dead ends: 418 [2018-01-30 02:31:56,416 INFO L226 Difference]: Without dead ends: 222 [2018-01-30 02:31:56,416 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2018-01-30 02:31:56,416 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-01-30 02:31:56,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 214. [2018-01-30 02:31:56,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-01-30 02:31:56,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 248 transitions. [2018-01-30 02:31:56,420 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 248 transitions. Word has length 82 [2018-01-30 02:31:56,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:56,420 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 248 transitions. [2018-01-30 02:31:56,420 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-30 02:31:56,420 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 248 transitions. [2018-01-30 02:31:56,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-01-30 02:31:56,420 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:56,420 INFO L350 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:56,421 INFO L371 AbstractCegarLoop]: === Iteration 18 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:56,421 INFO L82 PathProgramCache]: Analyzing trace with hash -962009063, now seen corresponding path program 15 times [2018-01-30 02:31:56,421 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:56,421 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:56,421 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:56,421 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:56,421 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:56,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:56,426 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:57,336 INFO L134 CoverageAnalysis]: Checked inductivity of 452 backedges. 2 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:57,336 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:57,336 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:57,340 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:31:57,344 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,347 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,348 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,349 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,350 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,351 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,352 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,353 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,354 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,354 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,355 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,356 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,357 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,358 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,363 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,364 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:31:57,365 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:57,366 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:57,380 INFO L134 CoverageAnalysis]: Checked inductivity of 452 backedges. 2 proven. 450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:57,397 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:57,397 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-01-30 02:31:57,397 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-30 02:31:57,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-30 02:31:57,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 02:31:57,397 INFO L87 Difference]: Start difference. First operand 214 states and 248 transitions. Second operand 18 states. [2018-01-30 02:31:57,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:57,559 INFO L93 Difference]: Finished difference Result 442 states and 516 transitions. [2018-01-30 02:31:57,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-30 02:31:57,559 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 86 [2018-01-30 02:31:57,559 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:57,560 INFO L225 Difference]: With dead ends: 442 [2018-01-30 02:31:57,560 INFO L226 Difference]: Without dead ends: 234 [2018-01-30 02:31:57,560 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-01-30 02:31:57,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-01-30 02:31:57,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 226. [2018-01-30 02:31:57,562 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-01-30 02:31:57,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 262 transitions. [2018-01-30 02:31:57,563 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 262 transitions. Word has length 86 [2018-01-30 02:31:57,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:57,563 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 262 transitions. [2018-01-30 02:31:57,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-30 02:31:57,563 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 262 transitions. [2018-01-30 02:31:57,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-01-30 02:31:57,564 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:57,564 INFO L350 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:57,564 INFO L371 AbstractCegarLoop]: === Iteration 19 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:57,564 INFO L82 PathProgramCache]: Analyzing trace with hash -2132697502, now seen corresponding path program 16 times [2018-01-30 02:31:57,564 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:57,564 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:57,565 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:57,565 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:57,565 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:57,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:57,569 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:57,708 INFO L134 CoverageAnalysis]: Checked inductivity of 514 backedges. 2 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:57,708 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:57,708 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:57,713 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:31:57,738 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:57,739 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:57,747 INFO L134 CoverageAnalysis]: Checked inductivity of 514 backedges. 2 proven. 512 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:57,764 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:57,764 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2018-01-30 02:31:57,765 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-30 02:31:57,765 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-30 02:31:57,765 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 02:31:57,765 INFO L87 Difference]: Start difference. First operand 226 states and 262 transitions. Second operand 19 states. [2018-01-30 02:31:57,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:57,877 INFO L93 Difference]: Finished difference Result 466 states and 544 transitions. [2018-01-30 02:31:57,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-30 02:31:57,878 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 90 [2018-01-30 02:31:57,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:57,878 INFO L225 Difference]: With dead ends: 466 [2018-01-30 02:31:57,878 INFO L226 Difference]: Without dead ends: 246 [2018-01-30 02:31:57,879 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-01-30 02:31:57,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-01-30 02:31:57,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 238. [2018-01-30 02:31:57,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-01-30 02:31:57,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 276 transitions. [2018-01-30 02:31:57,881 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 276 transitions. Word has length 90 [2018-01-30 02:31:57,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:57,882 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 276 transitions. [2018-01-30 02:31:57,882 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-30 02:31:57,882 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 276 transitions. [2018-01-30 02:31:57,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-30 02:31:57,882 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:57,882 INFO L350 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:57,882 INFO L371 AbstractCegarLoop]: === Iteration 20 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:57,882 INFO L82 PathProgramCache]: Analyzing trace with hash 1741948971, now seen corresponding path program 17 times [2018-01-30 02:31:57,883 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:57,883 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:57,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:57,883 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:57,883 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:57,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:57,887 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:58,136 INFO L134 CoverageAnalysis]: Checked inductivity of 580 backedges. 2 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:58,136 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:58,136 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:58,140 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:31:58,142 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,143 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,143 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,144 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,145 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,146 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,146 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,147 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,148 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,149 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,149 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,150 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,151 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,152 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,153 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,154 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,155 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,156 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:58,156 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:58,157 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:58,166 INFO L134 CoverageAnalysis]: Checked inductivity of 580 backedges. 2 proven. 578 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:58,183 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:58,183 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2018-01-30 02:31:58,183 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-01-30 02:31:58,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-01-30 02:31:58,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 02:31:58,183 INFO L87 Difference]: Start difference. First operand 238 states and 276 transitions. Second operand 20 states. [2018-01-30 02:31:58,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:58,283 INFO L93 Difference]: Finished difference Result 490 states and 572 transitions. [2018-01-30 02:31:58,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-01-30 02:31:58,284 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 94 [2018-01-30 02:31:58,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:58,284 INFO L225 Difference]: With dead ends: 490 [2018-01-30 02:31:58,284 INFO L226 Difference]: Without dead ends: 258 [2018-01-30 02:31:58,285 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-01-30 02:31:58,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258 states. [2018-01-30 02:31:58,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258 to 250. [2018-01-30 02:31:58,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 250 states. [2018-01-30 02:31:58,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 290 transitions. [2018-01-30 02:31:58,288 INFO L78 Accepts]: Start accepts. Automaton has 250 states and 290 transitions. Word has length 94 [2018-01-30 02:31:58,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:58,288 INFO L432 AbstractCegarLoop]: Abstraction has 250 states and 290 transitions. [2018-01-30 02:31:58,288 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-01-30 02:31:58,288 INFO L276 IsEmpty]: Start isEmpty. Operand 250 states and 290 transitions. [2018-01-30 02:31:58,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-01-30 02:31:58,288 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:58,289 INFO L350 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:58,289 INFO L371 AbstractCegarLoop]: === Iteration 21 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:58,289 INFO L82 PathProgramCache]: Analyzing trace with hash 1484416372, now seen corresponding path program 18 times [2018-01-30 02:31:58,289 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:58,289 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:58,289 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:58,289 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:58,289 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:58,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:58,294 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:58,444 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 2 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:58,445 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:58,445 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:58,450 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:31:58,454 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,472 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,477 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,477 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,478 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,479 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,479 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,480 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,481 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,482 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,483 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,484 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,499 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,509 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:31:58,524 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:58,525 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:58,533 INFO L134 CoverageAnalysis]: Checked inductivity of 650 backedges. 2 proven. 648 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:58,552 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:58,552 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2018-01-30 02:31:58,552 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-30 02:31:58,552 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-30 02:31:58,553 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 02:31:58,553 INFO L87 Difference]: Start difference. First operand 250 states and 290 transitions. Second operand 21 states. [2018-01-30 02:31:58,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:58,672 INFO L93 Difference]: Finished difference Result 514 states and 600 transitions. [2018-01-30 02:31:58,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-30 02:31:58,672 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 98 [2018-01-30 02:31:58,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:58,673 INFO L225 Difference]: With dead ends: 514 [2018-01-30 02:31:58,673 INFO L226 Difference]: Without dead ends: 270 [2018-01-30 02:31:58,673 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 99 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2018-01-30 02:31:58,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states. [2018-01-30 02:31:58,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 262. [2018-01-30 02:31:58,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 262 states. [2018-01-30 02:31:58,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 262 states to 262 states and 304 transitions. [2018-01-30 02:31:58,676 INFO L78 Accepts]: Start accepts. Automaton has 262 states and 304 transitions. Word has length 98 [2018-01-30 02:31:58,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:58,676 INFO L432 AbstractCegarLoop]: Abstraction has 262 states and 304 transitions. [2018-01-30 02:31:58,676 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-30 02:31:58,676 INFO L276 IsEmpty]: Start isEmpty. Operand 262 states and 304 transitions. [2018-01-30 02:31:58,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-01-30 02:31:58,677 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:58,677 INFO L350 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:58,677 INFO L371 AbstractCegarLoop]: === Iteration 22 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:58,677 INFO L82 PathProgramCache]: Analyzing trace with hash -1464928707, now seen corresponding path program 19 times [2018-01-30 02:31:58,677 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:58,677 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:58,678 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:58,678 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:31:58,678 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:58,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:58,682 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:59,080 INFO L134 CoverageAnalysis]: Checked inductivity of 724 backedges. 2 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:59,080 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:59,080 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:59,085 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:59,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:59,096 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:59,106 INFO L134 CoverageAnalysis]: Checked inductivity of 724 backedges. 2 proven. 722 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:59,122 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:59,122 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2018-01-30 02:31:59,123 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-01-30 02:31:59,123 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-01-30 02:31:59,123 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 02:31:59,123 INFO L87 Difference]: Start difference. First operand 262 states and 304 transitions. Second operand 22 states. [2018-01-30 02:31:59,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:31:59,328 INFO L93 Difference]: Finished difference Result 538 states and 628 transitions. [2018-01-30 02:31:59,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-30 02:31:59,328 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 102 [2018-01-30 02:31:59,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:31:59,329 INFO L225 Difference]: With dead ends: 538 [2018-01-30 02:31:59,329 INFO L226 Difference]: Without dead ends: 282 [2018-01-30 02:31:59,329 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 103 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-01-30 02:31:59,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-01-30 02:31:59,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 274. [2018-01-30 02:31:59,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 274 states. [2018-01-30 02:31:59,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 274 states to 274 states and 318 transitions. [2018-01-30 02:31:59,332 INFO L78 Accepts]: Start accepts. Automaton has 274 states and 318 transitions. Word has length 102 [2018-01-30 02:31:59,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:31:59,332 INFO L432 AbstractCegarLoop]: Abstraction has 274 states and 318 transitions. [2018-01-30 02:31:59,332 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-01-30 02:31:59,332 INFO L276 IsEmpty]: Start isEmpty. Operand 274 states and 318 transitions. [2018-01-30 02:31:59,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-01-30 02:31:59,333 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:31:59,333 INFO L350 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:31:59,333 INFO L371 AbstractCegarLoop]: === Iteration 23 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:31:59,333 INFO L82 PathProgramCache]: Analyzing trace with hash -1221854586, now seen corresponding path program 20 times [2018-01-30 02:31:59,333 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:31:59,333 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:31:59,334 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:59,334 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:31:59,334 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:31:59,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:31:59,338 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:31:59,883 INFO L134 CoverageAnalysis]: Checked inductivity of 802 backedges. 2 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:59,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:31:59,883 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:31:59,893 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:31:59,897 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:59,903 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:31:59,904 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:31:59,905 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:31:59,915 INFO L134 CoverageAnalysis]: Checked inductivity of 802 backedges. 2 proven. 800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:31:59,934 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:31:59,934 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2018-01-30 02:31:59,934 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-30 02:31:59,934 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-30 02:31:59,934 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-30 02:31:59,935 INFO L87 Difference]: Start difference. First operand 274 states and 318 transitions. Second operand 23 states. [2018-01-30 02:32:00,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:00,062 INFO L93 Difference]: Finished difference Result 562 states and 656 transitions. [2018-01-30 02:32:00,063 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-01-30 02:32:00,063 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 106 [2018-01-30 02:32:00,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:00,063 INFO L225 Difference]: With dead ends: 562 [2018-01-30 02:32:00,063 INFO L226 Difference]: Without dead ends: 294 [2018-01-30 02:32:00,064 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 107 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2018-01-30 02:32:00,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-01-30 02:32:00,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 286. [2018-01-30 02:32:00,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-01-30 02:32:00,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 332 transitions. [2018-01-30 02:32:00,067 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 332 transitions. Word has length 106 [2018-01-30 02:32:00,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:00,067 INFO L432 AbstractCegarLoop]: Abstraction has 286 states and 332 transitions. [2018-01-30 02:32:00,067 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-30 02:32:00,067 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 332 transitions. [2018-01-30 02:32:00,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-30 02:32:00,068 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:00,068 INFO L350 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:00,068 INFO L371 AbstractCegarLoop]: === Iteration 24 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:00,068 INFO L82 PathProgramCache]: Analyzing trace with hash 2072752719, now seen corresponding path program 21 times [2018-01-30 02:32:00,068 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:00,068 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:00,068 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:00,068 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:00,069 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:00,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:00,073 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:00,491 INFO L134 CoverageAnalysis]: Checked inductivity of 884 backedges. 2 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:00,492 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:00,492 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:00,496 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:00,500 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,501 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,502 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,503 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,504 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,505 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,506 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,507 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,510 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,511 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,512 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,513 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,514 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,515 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,516 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,517 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,519 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,520 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,521 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:00,521 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:00,522 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:00,532 INFO L134 CoverageAnalysis]: Checked inductivity of 884 backedges. 2 proven. 882 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:00,549 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:00,549 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2018-01-30 02:32:00,549 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-30 02:32:00,549 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-30 02:32:00,549 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 02:32:00,549 INFO L87 Difference]: Start difference. First operand 286 states and 332 transitions. Second operand 24 states. [2018-01-30 02:32:00,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:00,688 INFO L93 Difference]: Finished difference Result 586 states and 684 transitions. [2018-01-30 02:32:00,688 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-30 02:32:00,688 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 110 [2018-01-30 02:32:00,689 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:00,689 INFO L225 Difference]: With dead ends: 586 [2018-01-30 02:32:00,689 INFO L226 Difference]: Without dead ends: 306 [2018-01-30 02:32:00,690 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-01-30 02:32:00,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-01-30 02:32:00,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 298. [2018-01-30 02:32:00,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 298 states. [2018-01-30 02:32:00,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 346 transitions. [2018-01-30 02:32:00,693 INFO L78 Accepts]: Start accepts. Automaton has 298 states and 346 transitions. Word has length 110 [2018-01-30 02:32:00,693 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:00,693 INFO L432 AbstractCegarLoop]: Abstraction has 298 states and 346 transitions. [2018-01-30 02:32:00,693 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-30 02:32:00,693 INFO L276 IsEmpty]: Start isEmpty. Operand 298 states and 346 transitions. [2018-01-30 02:32:00,694 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-01-30 02:32:00,694 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:00,694 INFO L350 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:00,694 INFO L371 AbstractCegarLoop]: === Iteration 25 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:00,694 INFO L82 PathProgramCache]: Analyzing trace with hash 373841304, now seen corresponding path program 22 times [2018-01-30 02:32:00,694 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:00,694 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:00,695 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:00,695 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:00,695 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:00,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:00,700 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:01,201 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 2 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:01,201 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:01,201 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:01,206 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:01,217 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:01,218 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:01,228 INFO L134 CoverageAnalysis]: Checked inductivity of 970 backedges. 2 proven. 968 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:01,245 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:01,245 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2018-01-30 02:32:01,246 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-30 02:32:01,246 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-30 02:32:01,246 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 02:32:01,246 INFO L87 Difference]: Start difference. First operand 298 states and 346 transitions. Second operand 25 states. [2018-01-30 02:32:01,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:01,437 INFO L93 Difference]: Finished difference Result 610 states and 712 transitions. [2018-01-30 02:32:01,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-30 02:32:01,442 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 114 [2018-01-30 02:32:01,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:01,443 INFO L225 Difference]: With dead ends: 610 [2018-01-30 02:32:01,443 INFO L226 Difference]: Without dead ends: 318 [2018-01-30 02:32:01,444 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 115 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-01-30 02:32:01,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states. [2018-01-30 02:32:01,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 310. [2018-01-30 02:32:01,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 310 states. [2018-01-30 02:32:01,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 310 states to 310 states and 360 transitions. [2018-01-30 02:32:01,450 INFO L78 Accepts]: Start accepts. Automaton has 310 states and 360 transitions. Word has length 114 [2018-01-30 02:32:01,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:01,450 INFO L432 AbstractCegarLoop]: Abstraction has 310 states and 360 transitions. [2018-01-30 02:32:01,450 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-30 02:32:01,451 INFO L276 IsEmpty]: Start isEmpty. Operand 310 states and 360 transitions. [2018-01-30 02:32:01,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-30 02:32:01,451 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:01,451 INFO L350 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:01,451 INFO L371 AbstractCegarLoop]: === Iteration 26 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:01,451 INFO L82 PathProgramCache]: Analyzing trace with hash 1622948961, now seen corresponding path program 23 times [2018-01-30 02:32:01,451 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:01,452 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:01,452 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:01,452 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:01,452 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:01,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:01,457 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:01,671 INFO L134 CoverageAnalysis]: Checked inductivity of 1060 backedges. 2 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:01,672 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:01,672 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:01,679 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:01,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,683 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,684 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,684 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,686 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,687 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,688 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,688 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,690 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,691 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,692 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,693 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,694 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,695 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,696 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,697 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,698 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,701 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:01,703 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:01,704 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:01,715 INFO L134 CoverageAnalysis]: Checked inductivity of 1060 backedges. 2 proven. 1058 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:01,733 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:01,733 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2018-01-30 02:32:01,734 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-01-30 02:32:01,734 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-01-30 02:32:01,734 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-30 02:32:01,734 INFO L87 Difference]: Start difference. First operand 310 states and 360 transitions. Second operand 26 states. [2018-01-30 02:32:01,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:01,849 INFO L93 Difference]: Finished difference Result 634 states and 740 transitions. [2018-01-30 02:32:01,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-01-30 02:32:01,849 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 118 [2018-01-30 02:32:01,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:01,850 INFO L225 Difference]: With dead ends: 634 [2018-01-30 02:32:01,850 INFO L226 Difference]: Without dead ends: 330 [2018-01-30 02:32:01,850 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 119 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-01-30 02:32:01,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 330 states. [2018-01-30 02:32:01,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 330 to 322. [2018-01-30 02:32:01,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 322 states. [2018-01-30 02:32:01,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 374 transitions. [2018-01-30 02:32:01,853 INFO L78 Accepts]: Start accepts. Automaton has 322 states and 374 transitions. Word has length 118 [2018-01-30 02:32:01,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:01,854 INFO L432 AbstractCegarLoop]: Abstraction has 322 states and 374 transitions. [2018-01-30 02:32:01,854 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-01-30 02:32:01,854 INFO L276 IsEmpty]: Start isEmpty. Operand 322 states and 374 transitions. [2018-01-30 02:32:01,854 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-01-30 02:32:01,854 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:01,854 INFO L350 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:01,854 INFO L371 AbstractCegarLoop]: === Iteration 27 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:01,854 INFO L82 PathProgramCache]: Analyzing trace with hash 2099351210, now seen corresponding path program 24 times [2018-01-30 02:32:01,854 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:01,854 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:01,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:01,855 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:01,855 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:01,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:01,860 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:02,148 INFO L134 CoverageAnalysis]: Checked inductivity of 1154 backedges. 2 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:02,148 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:02,148 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:02,153 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:02,158 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,159 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,160 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,161 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,162 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,165 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,166 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,167 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,168 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,169 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,170 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,171 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,172 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,173 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,174 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,175 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,176 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,177 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,178 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,179 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,181 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,183 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:02,183 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:02,184 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:02,202 INFO L134 CoverageAnalysis]: Checked inductivity of 1154 backedges. 2 proven. 1152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:02,219 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:02,220 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2018-01-30 02:32:02,220 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-30 02:32:02,220 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-30 02:32:02,220 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 02:32:02,220 INFO L87 Difference]: Start difference. First operand 322 states and 374 transitions. Second operand 27 states. [2018-01-30 02:32:02,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:02,336 INFO L93 Difference]: Finished difference Result 658 states and 768 transitions. [2018-01-30 02:32:02,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-30 02:32:02,336 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 122 [2018-01-30 02:32:02,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:02,337 INFO L225 Difference]: With dead ends: 658 [2018-01-30 02:32:02,337 INFO L226 Difference]: Without dead ends: 342 [2018-01-30 02:32:02,338 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 123 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2018-01-30 02:32:02,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states. [2018-01-30 02:32:02,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 334. [2018-01-30 02:32:02,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 334 states. [2018-01-30 02:32:02,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 334 states to 334 states and 388 transitions. [2018-01-30 02:32:02,341 INFO L78 Accepts]: Start accepts. Automaton has 334 states and 388 transitions. Word has length 122 [2018-01-30 02:32:02,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:02,341 INFO L432 AbstractCegarLoop]: Abstraction has 334 states and 388 transitions. [2018-01-30 02:32:02,341 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-30 02:32:02,341 INFO L276 IsEmpty]: Start isEmpty. Operand 334 states and 388 transitions. [2018-01-30 02:32:02,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-01-30 02:32:02,341 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:02,342 INFO L350 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:02,345 INFO L371 AbstractCegarLoop]: === Iteration 28 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:02,345 INFO L82 PathProgramCache]: Analyzing trace with hash 1720882291, now seen corresponding path program 25 times [2018-01-30 02:32:02,345 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:02,345 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:02,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:02,346 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:02,346 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:02,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:02,350 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:02,661 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 2 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:02,661 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:02,661 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:02,666 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:02,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:02,677 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:02,689 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 2 proven. 1250 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:02,705 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:02,705 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2018-01-30 02:32:02,705 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-30 02:32:02,706 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-30 02:32:02,706 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 02:32:02,706 INFO L87 Difference]: Start difference. First operand 334 states and 388 transitions. Second operand 28 states. [2018-01-30 02:32:02,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:02,836 INFO L93 Difference]: Finished difference Result 682 states and 796 transitions. [2018-01-30 02:32:02,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-30 02:32:02,837 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 126 [2018-01-30 02:32:02,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:02,838 INFO L225 Difference]: With dead ends: 682 [2018-01-30 02:32:02,838 INFO L226 Difference]: Without dead ends: 354 [2018-01-30 02:32:02,838 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 153 GetRequests, 127 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-01-30 02:32:02,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states. [2018-01-30 02:32:02,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 346. [2018-01-30 02:32:02,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 346 states. [2018-01-30 02:32:02,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 402 transitions. [2018-01-30 02:32:02,841 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 402 transitions. Word has length 126 [2018-01-30 02:32:02,842 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:02,842 INFO L432 AbstractCegarLoop]: Abstraction has 346 states and 402 transitions. [2018-01-30 02:32:02,842 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-30 02:32:02,842 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 402 transitions. [2018-01-30 02:32:02,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-01-30 02:32:02,842 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:02,842 INFO L350 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:02,842 INFO L371 AbstractCegarLoop]: === Iteration 29 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:02,843 INFO L82 PathProgramCache]: Analyzing trace with hash -2130080324, now seen corresponding path program 26 times [2018-01-30 02:32:02,843 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:02,843 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:02,843 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:02,843 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:02,843 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:02,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:02,847 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:03,231 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 2 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:03,231 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:03,231 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:03,236 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:03,239 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:03,245 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:03,247 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:03,248 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:03,260 INFO L134 CoverageAnalysis]: Checked inductivity of 1354 backedges. 2 proven. 1352 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:03,276 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:03,276 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2018-01-30 02:32:03,277 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-30 02:32:03,277 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-30 02:32:03,277 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 02:32:03,277 INFO L87 Difference]: Start difference. First operand 346 states and 402 transitions. Second operand 29 states. [2018-01-30 02:32:03,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:03,400 INFO L93 Difference]: Finished difference Result 706 states and 824 transitions. [2018-01-30 02:32:03,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-01-30 02:32:03,400 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 130 [2018-01-30 02:32:03,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:03,401 INFO L225 Difference]: With dead ends: 706 [2018-01-30 02:32:03,401 INFO L226 Difference]: Without dead ends: 366 [2018-01-30 02:32:03,401 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2018-01-30 02:32:03,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states. [2018-01-30 02:32:03,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 358. [2018-01-30 02:32:03,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 358 states. [2018-01-30 02:32:03,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 358 states to 358 states and 416 transitions. [2018-01-30 02:32:03,404 INFO L78 Accepts]: Start accepts. Automaton has 358 states and 416 transitions. Word has length 130 [2018-01-30 02:32:03,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:03,405 INFO L432 AbstractCegarLoop]: Abstraction has 358 states and 416 transitions. [2018-01-30 02:32:03,405 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-30 02:32:03,405 INFO L276 IsEmpty]: Start isEmpty. Operand 358 states and 416 transitions. [2018-01-30 02:32:03,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-30 02:32:03,405 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:03,405 INFO L350 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:03,405 INFO L371 AbstractCegarLoop]: === Iteration 30 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:03,405 INFO L82 PathProgramCache]: Analyzing trace with hash 694205061, now seen corresponding path program 27 times [2018-01-30 02:32:03,406 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:03,406 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:03,406 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:03,406 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:03,406 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:03,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:03,410 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:04,135 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 2 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:04,135 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:04,135 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:04,142 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:04,145 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,147 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,148 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,149 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,150 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,151 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,153 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,153 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,154 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,155 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,156 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,157 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,158 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,159 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,163 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,164 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,166 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,167 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,168 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,170 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,171 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,172 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,174 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,175 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,177 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:04,177 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:04,178 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:04,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1460 backedges. 2 proven. 1458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:04,207 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:04,208 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2018-01-30 02:32:04,208 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-01-30 02:32:04,208 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-01-30 02:32:04,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 02:32:04,208 INFO L87 Difference]: Start difference. First operand 358 states and 416 transitions. Second operand 30 states. [2018-01-30 02:32:04,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:04,365 INFO L93 Difference]: Finished difference Result 730 states and 852 transitions. [2018-01-30 02:32:04,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-30 02:32:04,366 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 134 [2018-01-30 02:32:04,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:04,366 INFO L225 Difference]: With dead ends: 730 [2018-01-30 02:32:04,366 INFO L226 Difference]: Without dead ends: 378 [2018-01-30 02:32:04,367 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 135 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-01-30 02:32:04,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states. [2018-01-30 02:32:04,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 370. [2018-01-30 02:32:04,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 370 states. [2018-01-30 02:32:04,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370 states to 370 states and 430 transitions. [2018-01-30 02:32:04,370 INFO L78 Accepts]: Start accepts. Automaton has 370 states and 430 transitions. Word has length 134 [2018-01-30 02:32:04,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:04,370 INFO L432 AbstractCegarLoop]: Abstraction has 370 states and 430 transitions. [2018-01-30 02:32:04,370 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-01-30 02:32:04,370 INFO L276 IsEmpty]: Start isEmpty. Operand 370 states and 430 transitions. [2018-01-30 02:32:04,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-01-30 02:32:04,371 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:04,371 INFO L350 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:04,371 INFO L371 AbstractCegarLoop]: === Iteration 31 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:04,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1163025102, now seen corresponding path program 28 times [2018-01-30 02:32:04,371 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:04,371 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:04,372 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:04,372 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:04,372 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:04,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:04,376 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:04,689 INFO L134 CoverageAnalysis]: Checked inductivity of 1570 backedges. 2 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:04,689 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:04,689 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:04,694 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:04,706 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:04,708 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:04,723 INFO L134 CoverageAnalysis]: Checked inductivity of 1570 backedges. 2 proven. 1568 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:04,740 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:04,740 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2018-01-30 02:32:04,741 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-30 02:32:04,741 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-30 02:32:04,741 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 02:32:04,741 INFO L87 Difference]: Start difference. First operand 370 states and 430 transitions. Second operand 31 states. [2018-01-30 02:32:04,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:04,897 INFO L93 Difference]: Finished difference Result 754 states and 880 transitions. [2018-01-30 02:32:04,898 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-01-30 02:32:04,898 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 138 [2018-01-30 02:32:04,898 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:04,898 INFO L225 Difference]: With dead ends: 754 [2018-01-30 02:32:04,899 INFO L226 Difference]: Without dead ends: 390 [2018-01-30 02:32:04,899 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 168 GetRequests, 139 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2018-01-30 02:32:04,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states. [2018-01-30 02:32:04,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 382. [2018-01-30 02:32:04,902 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 382 states. [2018-01-30 02:32:04,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 382 states to 382 states and 444 transitions. [2018-01-30 02:32:04,902 INFO L78 Accepts]: Start accepts. Automaton has 382 states and 444 transitions. Word has length 138 [2018-01-30 02:32:04,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:04,902 INFO L432 AbstractCegarLoop]: Abstraction has 382 states and 444 transitions. [2018-01-30 02:32:04,902 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-30 02:32:04,903 INFO L276 IsEmpty]: Start isEmpty. Operand 382 states and 444 transitions. [2018-01-30 02:32:04,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 143 [2018-01-30 02:32:04,903 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:04,903 INFO L350 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:04,903 INFO L371 AbstractCegarLoop]: === Iteration 32 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:04,903 INFO L82 PathProgramCache]: Analyzing trace with hash -747065705, now seen corresponding path program 29 times [2018-01-30 02:32:04,903 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:04,904 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:04,904 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:04,904 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:04,904 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:04,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:04,909 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:05,203 INFO L134 CoverageAnalysis]: Checked inductivity of 1684 backedges. 2 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:05,203 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:05,203 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 02:32:05,223 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:05,226 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,228 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,229 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,230 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,230 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,231 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,232 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,233 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,233 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,234 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,235 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,236 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,237 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,238 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,239 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,240 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,241 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,242 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,243 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,244 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,246 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,247 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,248 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,249 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,251 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,252 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,253 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,255 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,257 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,259 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:05,259 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:05,260 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:05,274 INFO L134 CoverageAnalysis]: Checked inductivity of 1684 backedges. 2 proven. 1682 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:05,290 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:05,290 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2018-01-30 02:32:05,291 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-01-30 02:32:05,291 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-01-30 02:32:05,291 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-30 02:32:05,291 INFO L87 Difference]: Start difference. First operand 382 states and 444 transitions. Second operand 32 states. [2018-01-30 02:32:05,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:05,468 INFO L93 Difference]: Finished difference Result 778 states and 908 transitions. [2018-01-30 02:32:05,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-01-30 02:32:05,468 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 142 [2018-01-30 02:32:05,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:05,469 INFO L225 Difference]: With dead ends: 778 [2018-01-30 02:32:05,469 INFO L226 Difference]: Without dead ends: 402 [2018-01-30 02:32:05,469 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 173 GetRequests, 143 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-01-30 02:32:05,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states. [2018-01-30 02:32:05,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 394. [2018-01-30 02:32:05,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 394 states. [2018-01-30 02:32:05,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 394 states to 394 states and 458 transitions. [2018-01-30 02:32:05,473 INFO L78 Accepts]: Start accepts. Automaton has 394 states and 458 transitions. Word has length 142 [2018-01-30 02:32:05,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:05,473 INFO L432 AbstractCegarLoop]: Abstraction has 394 states and 458 transitions. [2018-01-30 02:32:05,473 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-01-30 02:32:05,473 INFO L276 IsEmpty]: Start isEmpty. Operand 394 states and 458 transitions. [2018-01-30 02:32:05,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-01-30 02:32:05,474 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:05,474 INFO L350 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:05,474 INFO L371 AbstractCegarLoop]: === Iteration 33 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:05,474 INFO L82 PathProgramCache]: Analyzing trace with hash 2068706784, now seen corresponding path program 30 times [2018-01-30 02:32:05,474 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:05,474 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:05,475 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:05,475 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:05,475 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:05,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:05,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:05,800 INFO L134 CoverageAnalysis]: Checked inductivity of 1802 backedges. 2 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:05,800 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:05,800 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:05,804 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:05,808 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,809 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,809 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,810 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,811 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,811 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,812 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,813 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,814 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,815 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,816 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,817 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,821 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,822 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,824 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,825 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,826 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,827 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,828 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,829 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,830 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,832 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,833 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,834 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,835 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,837 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,838 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,839 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:05,840 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:05,841 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:05,864 INFO L134 CoverageAnalysis]: Checked inductivity of 1802 backedges. 2 proven. 1800 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:05,880 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:05,881 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2018-01-30 02:32:05,881 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-30 02:32:05,881 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-30 02:32:05,881 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 02:32:05,881 INFO L87 Difference]: Start difference. First operand 394 states and 458 transitions. Second operand 33 states. [2018-01-30 02:32:06,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:06,131 INFO L93 Difference]: Finished difference Result 802 states and 936 transitions. [2018-01-30 02:32:06,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-30 02:32:06,131 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 146 [2018-01-30 02:32:06,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:06,132 INFO L225 Difference]: With dead ends: 802 [2018-01-30 02:32:06,132 INFO L226 Difference]: Without dead ends: 414 [2018-01-30 02:32:06,132 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 178 GetRequests, 147 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2018-01-30 02:32:06,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414 states. [2018-01-30 02:32:06,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414 to 406. [2018-01-30 02:32:06,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 406 states. [2018-01-30 02:32:06,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 406 states to 406 states and 472 transitions. [2018-01-30 02:32:06,136 INFO L78 Accepts]: Start accepts. Automaton has 406 states and 472 transitions. Word has length 146 [2018-01-30 02:32:06,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:06,136 INFO L432 AbstractCegarLoop]: Abstraction has 406 states and 472 transitions. [2018-01-30 02:32:06,136 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-30 02:32:06,136 INFO L276 IsEmpty]: Start isEmpty. Operand 406 states and 472 transitions. [2018-01-30 02:32:06,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-30 02:32:06,137 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:06,137 INFO L350 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:06,137 INFO L371 AbstractCegarLoop]: === Iteration 34 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:06,137 INFO L82 PathProgramCache]: Analyzing trace with hash 489451689, now seen corresponding path program 31 times [2018-01-30 02:32:06,137 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:06,137 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:06,137 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:06,137 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:06,137 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:06,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:06,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:06,489 INFO L134 CoverageAnalysis]: Checked inductivity of 1924 backedges. 2 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:06,490 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:06,490 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:06,494 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:06,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:06,508 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:06,523 INFO L134 CoverageAnalysis]: Checked inductivity of 1924 backedges. 2 proven. 1922 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:06,539 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:06,539 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2018-01-30 02:32:06,539 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-01-30 02:32:06,539 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-01-30 02:32:06,540 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 02:32:06,540 INFO L87 Difference]: Start difference. First operand 406 states and 472 transitions. Second operand 34 states. [2018-01-30 02:32:06,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:06,694 INFO L93 Difference]: Finished difference Result 826 states and 964 transitions. [2018-01-30 02:32:06,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-30 02:32:06,694 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 150 [2018-01-30 02:32:06,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:06,695 INFO L225 Difference]: With dead ends: 826 [2018-01-30 02:32:06,695 INFO L226 Difference]: Without dead ends: 426 [2018-01-30 02:32:06,696 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 183 GetRequests, 151 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-01-30 02:32:06,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states. [2018-01-30 02:32:06,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 418. [2018-01-30 02:32:06,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 418 states. [2018-01-30 02:32:06,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 418 states to 418 states and 486 transitions. [2018-01-30 02:32:06,699 INFO L78 Accepts]: Start accepts. Automaton has 418 states and 486 transitions. Word has length 150 [2018-01-30 02:32:06,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:06,699 INFO L432 AbstractCegarLoop]: Abstraction has 418 states and 486 transitions. [2018-01-30 02:32:06,699 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-01-30 02:32:06,699 INFO L276 IsEmpty]: Start isEmpty. Operand 418 states and 486 transitions. [2018-01-30 02:32:06,700 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-01-30 02:32:06,700 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:06,700 INFO L350 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:06,700 INFO L371 AbstractCegarLoop]: === Iteration 35 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:06,700 INFO L82 PathProgramCache]: Analyzing trace with hash 1649303282, now seen corresponding path program 32 times [2018-01-30 02:32:06,700 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:06,700 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:06,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:06,701 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:06,701 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:06,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:06,706 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:07,235 INFO L134 CoverageAnalysis]: Checked inductivity of 2050 backedges. 2 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:07,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:07,235 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:07,239 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:07,243 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:07,255 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:07,256 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:07,258 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:07,273 INFO L134 CoverageAnalysis]: Checked inductivity of 2050 backedges. 2 proven. 2048 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:07,289 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:07,289 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2018-01-30 02:32:07,290 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-30 02:32:07,290 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-30 02:32:07,290 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-30 02:32:07,290 INFO L87 Difference]: Start difference. First operand 418 states and 486 transitions. Second operand 35 states. [2018-01-30 02:32:07,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:07,465 INFO L93 Difference]: Finished difference Result 850 states and 992 transitions. [2018-01-30 02:32:07,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-30 02:32:07,475 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 154 [2018-01-30 02:32:07,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:07,476 INFO L225 Difference]: With dead ends: 850 [2018-01-30 02:32:07,476 INFO L226 Difference]: Without dead ends: 438 [2018-01-30 02:32:07,477 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2018-01-30 02:32:07,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states. [2018-01-30 02:32:07,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 430. [2018-01-30 02:32:07,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 430 states. [2018-01-30 02:32:07,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 500 transitions. [2018-01-30 02:32:07,481 INFO L78 Accepts]: Start accepts. Automaton has 430 states and 500 transitions. Word has length 154 [2018-01-30 02:32:07,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:07,481 INFO L432 AbstractCegarLoop]: Abstraction has 430 states and 500 transitions. [2018-01-30 02:32:07,481 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-30 02:32:07,481 INFO L276 IsEmpty]: Start isEmpty. Operand 430 states and 500 transitions. [2018-01-30 02:32:07,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-01-30 02:32:07,481 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:07,482 INFO L350 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:07,482 INFO L371 AbstractCegarLoop]: === Iteration 36 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:07,482 INFO L82 PathProgramCache]: Analyzing trace with hash 1288569019, now seen corresponding path program 33 times [2018-01-30 02:32:07,482 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:07,482 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:07,482 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:07,482 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:07,482 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:07,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:07,487 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:07,844 INFO L134 CoverageAnalysis]: Checked inductivity of 2180 backedges. 2 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:07,845 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:07,845 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:07,849 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:07,853 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,865 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,875 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,882 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,882 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,883 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,884 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,884 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,885 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,886 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,887 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,888 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,889 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,890 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,891 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,892 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,893 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,894 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,896 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,897 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,898 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,899 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,900 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,901 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,902 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,903 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,905 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,906 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,907 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,908 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,910 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,911 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,913 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,914 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,916 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:07,916 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:07,920 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:07,956 INFO L134 CoverageAnalysis]: Checked inductivity of 2180 backedges. 2 proven. 2178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:07,972 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:07,972 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2018-01-30 02:32:07,973 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-01-30 02:32:07,973 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-01-30 02:32:07,973 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 02:32:07,973 INFO L87 Difference]: Start difference. First operand 430 states and 500 transitions. Second operand 36 states. [2018-01-30 02:32:08,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:08,142 INFO L93 Difference]: Finished difference Result 874 states and 1020 transitions. [2018-01-30 02:32:08,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-30 02:32:08,142 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 158 [2018-01-30 02:32:08,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:08,143 INFO L225 Difference]: With dead ends: 874 [2018-01-30 02:32:08,143 INFO L226 Difference]: Without dead ends: 450 [2018-01-30 02:32:08,143 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 193 GetRequests, 159 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-01-30 02:32:08,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-01-30 02:32:08,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 442. [2018-01-30 02:32:08,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 442 states. [2018-01-30 02:32:08,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 442 states to 442 states and 514 transitions. [2018-01-30 02:32:08,147 INFO L78 Accepts]: Start accepts. Automaton has 442 states and 514 transitions. Word has length 158 [2018-01-30 02:32:08,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:08,147 INFO L432 AbstractCegarLoop]: Abstraction has 442 states and 514 transitions. [2018-01-30 02:32:08,147 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-01-30 02:32:08,147 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 514 transitions. [2018-01-30 02:32:08,148 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2018-01-30 02:32:08,148 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:08,148 INFO L350 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:08,148 INFO L371 AbstractCegarLoop]: === Iteration 37 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:08,148 INFO L82 PathProgramCache]: Analyzing trace with hash -945449468, now seen corresponding path program 34 times [2018-01-30 02:32:08,148 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:08,148 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:08,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:08,149 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:08,149 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:08,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:08,153 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:08,661 INFO L134 CoverageAnalysis]: Checked inductivity of 2314 backedges. 2 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:08,661 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:08,661 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:08,666 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:08,698 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:08,700 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:08,716 INFO L134 CoverageAnalysis]: Checked inductivity of 2314 backedges. 2 proven. 2312 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:08,735 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:08,735 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2018-01-30 02:32:08,735 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-30 02:32:08,736 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-30 02:32:08,736 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 02:32:08,736 INFO L87 Difference]: Start difference. First operand 442 states and 514 transitions. Second operand 37 states. [2018-01-30 02:32:09,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:09,943 INFO L93 Difference]: Finished difference Result 898 states and 1048 transitions. [2018-01-30 02:32:09,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-01-30 02:32:09,943 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 162 [2018-01-30 02:32:09,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:09,944 INFO L225 Difference]: With dead ends: 898 [2018-01-30 02:32:09,944 INFO L226 Difference]: Without dead ends: 462 [2018-01-30 02:32:09,945 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 198 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2018-01-30 02:32:09,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-01-30 02:32:09,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 454. [2018-01-30 02:32:09,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 454 states. [2018-01-30 02:32:09,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 454 states to 454 states and 528 transitions. [2018-01-30 02:32:09,948 INFO L78 Accepts]: Start accepts. Automaton has 454 states and 528 transitions. Word has length 162 [2018-01-30 02:32:09,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:09,949 INFO L432 AbstractCegarLoop]: Abstraction has 454 states and 528 transitions. [2018-01-30 02:32:09,949 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-30 02:32:09,949 INFO L276 IsEmpty]: Start isEmpty. Operand 454 states and 528 transitions. [2018-01-30 02:32:09,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-30 02:32:09,949 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:09,949 INFO L350 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:09,949 INFO L371 AbstractCegarLoop]: === Iteration 38 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:09,950 INFO L82 PathProgramCache]: Analyzing trace with hash 917462733, now seen corresponding path program 35 times [2018-01-30 02:32:09,950 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:09,950 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:09,950 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:09,950 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:09,950 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:09,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:09,955 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:10,417 INFO L134 CoverageAnalysis]: Checked inductivity of 2452 backedges. 2 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:10,417 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:10,417 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:10,423 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:10,426 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,427 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,427 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,428 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,429 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,429 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,430 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,432 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,433 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,434 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,435 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,436 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,436 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,437 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,439 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,440 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,441 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,442 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,443 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,444 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,447 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,449 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,450 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,451 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,452 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,454 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,455 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,459 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,460 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,462 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,464 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,466 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:10,467 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:10,468 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:10,492 INFO L134 CoverageAnalysis]: Checked inductivity of 2452 backedges. 2 proven. 2450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:10,509 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:10,509 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2018-01-30 02:32:10,510 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-01-30 02:32:10,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-01-30 02:32:10,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 02:32:10,510 INFO L87 Difference]: Start difference. First operand 454 states and 528 transitions. Second operand 38 states. [2018-01-30 02:32:10,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:10,932 INFO L93 Difference]: Finished difference Result 922 states and 1076 transitions. [2018-01-30 02:32:10,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-01-30 02:32:10,933 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 166 [2018-01-30 02:32:10,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:10,933 INFO L225 Difference]: With dead ends: 922 [2018-01-30 02:32:10,934 INFO L226 Difference]: Without dead ends: 474 [2018-01-30 02:32:10,934 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 203 GetRequests, 167 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-01-30 02:32:10,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states. [2018-01-30 02:32:10,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 466. [2018-01-30 02:32:10,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 466 states. [2018-01-30 02:32:10,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 542 transitions. [2018-01-30 02:32:10,938 INFO L78 Accepts]: Start accepts. Automaton has 466 states and 542 transitions. Word has length 166 [2018-01-30 02:32:10,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:10,938 INFO L432 AbstractCegarLoop]: Abstraction has 466 states and 542 transitions. [2018-01-30 02:32:10,938 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-01-30 02:32:10,938 INFO L276 IsEmpty]: Start isEmpty. Operand 466 states and 542 transitions. [2018-01-30 02:32:10,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-01-30 02:32:10,938 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:10,939 INFO L350 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:10,939 INFO L371 AbstractCegarLoop]: === Iteration 39 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:10,939 INFO L82 PathProgramCache]: Analyzing trace with hash 111516438, now seen corresponding path program 36 times [2018-01-30 02:32:10,939 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:10,939 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:10,939 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:10,939 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:10,939 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:10,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:10,944 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:12,544 INFO L134 CoverageAnalysis]: Checked inductivity of 2594 backedges. 2 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:12,545 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:12,545 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:12,549 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:12,554 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,559 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,559 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,560 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,561 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,561 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,563 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,564 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,565 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,565 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,566 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,567 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,568 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,570 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,575 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,576 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,577 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,578 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,582 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,589 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,593 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,596 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,597 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,599 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,600 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:12,602 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:12,604 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:12,621 INFO L134 CoverageAnalysis]: Checked inductivity of 2594 backedges. 2 proven. 2592 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:12,642 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:12,642 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2018-01-30 02:32:12,642 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-30 02:32:12,642 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-30 02:32:12,642 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 02:32:12,643 INFO L87 Difference]: Start difference. First operand 466 states and 542 transitions. Second operand 39 states. [2018-01-30 02:32:13,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:13,626 INFO L93 Difference]: Finished difference Result 946 states and 1104 transitions. [2018-01-30 02:32:13,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-30 02:32:13,627 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 170 [2018-01-30 02:32:13,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:13,628 INFO L225 Difference]: With dead ends: 946 [2018-01-30 02:32:13,628 INFO L226 Difference]: Without dead ends: 486 [2018-01-30 02:32:13,628 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 208 GetRequests, 171 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2018-01-30 02:32:13,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2018-01-30 02:32:13,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 478. [2018-01-30 02:32:13,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 478 states. [2018-01-30 02:32:13,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 478 states to 478 states and 556 transitions. [2018-01-30 02:32:13,632 INFO L78 Accepts]: Start accepts. Automaton has 478 states and 556 transitions. Word has length 170 [2018-01-30 02:32:13,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:13,632 INFO L432 AbstractCegarLoop]: Abstraction has 478 states and 556 transitions. [2018-01-30 02:32:13,632 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-30 02:32:13,632 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 556 transitions. [2018-01-30 02:32:13,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-30 02:32:13,633 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:13,633 INFO L350 BasicCegarLoop]: trace histogram [38, 37, 37, 37, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:13,633 INFO L371 AbstractCegarLoop]: === Iteration 40 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:13,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1025673951, now seen corresponding path program 37 times [2018-01-30 02:32:13,633 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:13,633 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:13,634 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:13,634 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:13,634 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:13,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:13,641 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:15,054 INFO L134 CoverageAnalysis]: Checked inductivity of 2740 backedges. 2 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:15,054 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:15,054 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:15,059 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:15,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:15,073 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:15,090 INFO L134 CoverageAnalysis]: Checked inductivity of 2740 backedges. 2 proven. 2738 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:15,107 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:15,107 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2018-01-30 02:32:15,107 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-01-30 02:32:15,107 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-01-30 02:32:15,108 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 02:32:15,108 INFO L87 Difference]: Start difference. First operand 478 states and 556 transitions. Second operand 40 states. [2018-01-30 02:32:15,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:15,371 INFO L93 Difference]: Finished difference Result 970 states and 1132 transitions. [2018-01-30 02:32:15,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-30 02:32:15,371 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 174 [2018-01-30 02:32:15,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:15,372 INFO L225 Difference]: With dead ends: 970 [2018-01-30 02:32:15,372 INFO L226 Difference]: Without dead ends: 498 [2018-01-30 02:32:15,373 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 213 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-01-30 02:32:15,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states. [2018-01-30 02:32:15,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 490. [2018-01-30 02:32:15,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 490 states. [2018-01-30 02:32:15,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 570 transitions. [2018-01-30 02:32:15,376 INFO L78 Accepts]: Start accepts. Automaton has 490 states and 570 transitions. Word has length 174 [2018-01-30 02:32:15,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:15,376 INFO L432 AbstractCegarLoop]: Abstraction has 490 states and 570 transitions. [2018-01-30 02:32:15,376 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-01-30 02:32:15,376 INFO L276 IsEmpty]: Start isEmpty. Operand 490 states and 570 transitions. [2018-01-30 02:32:15,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2018-01-30 02:32:15,377 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:15,377 INFO L350 BasicCegarLoop]: trace histogram [39, 38, 38, 38, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:15,377 INFO L371 AbstractCegarLoop]: === Iteration 41 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:15,377 INFO L82 PathProgramCache]: Analyzing trace with hash 144731688, now seen corresponding path program 38 times [2018-01-30 02:32:15,377 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:15,377 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:15,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:15,378 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:15,378 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:15,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:15,383 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:16,205 INFO L134 CoverageAnalysis]: Checked inductivity of 2890 backedges. 2 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:16,205 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:16,206 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:16,210 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:16,214 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:16,222 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:16,224 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:16,226 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:16,244 INFO L134 CoverageAnalysis]: Checked inductivity of 2890 backedges. 2 proven. 2888 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:16,260 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:16,260 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2018-01-30 02:32:16,261 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-01-30 02:32:16,261 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-01-30 02:32:16,261 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-30 02:32:16,261 INFO L87 Difference]: Start difference. First operand 490 states and 570 transitions. Second operand 41 states. [2018-01-30 02:32:16,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:16,461 INFO L93 Difference]: Finished difference Result 994 states and 1160 transitions. [2018-01-30 02:32:16,461 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-01-30 02:32:16,461 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 178 [2018-01-30 02:32:16,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:16,462 INFO L225 Difference]: With dead ends: 994 [2018-01-30 02:32:16,462 INFO L226 Difference]: Without dead ends: 510 [2018-01-30 02:32:16,463 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 218 GetRequests, 179 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2018-01-30 02:32:16,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 510 states. [2018-01-30 02:32:16,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 510 to 502. [2018-01-30 02:32:16,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 502 states. [2018-01-30 02:32:16,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 584 transitions. [2018-01-30 02:32:16,466 INFO L78 Accepts]: Start accepts. Automaton has 502 states and 584 transitions. Word has length 178 [2018-01-30 02:32:16,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:16,467 INFO L432 AbstractCegarLoop]: Abstraction has 502 states and 584 transitions. [2018-01-30 02:32:16,467 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-01-30 02:32:16,467 INFO L276 IsEmpty]: Start isEmpty. Operand 502 states and 584 transitions. [2018-01-30 02:32:16,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-01-30 02:32:16,467 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:16,468 INFO L350 BasicCegarLoop]: trace histogram [40, 39, 39, 39, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:16,468 INFO L371 AbstractCegarLoop]: === Iteration 42 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:16,468 INFO L82 PathProgramCache]: Analyzing trace with hash 1350141169, now seen corresponding path program 39 times [2018-01-30 02:32:16,468 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:16,468 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:16,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:16,468 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:16,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:16,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:16,474 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:17,003 INFO L134 CoverageAnalysis]: Checked inductivity of 3044 backedges. 2 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:17,004 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:17,004 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:17,008 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:17,012 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,013 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,013 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,014 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,015 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,016 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,017 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,018 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,019 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,020 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,021 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,022 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,023 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,024 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,025 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,026 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,027 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,028 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,029 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,030 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,032 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,033 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,034 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,036 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,037 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,039 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,040 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,041 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,043 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,044 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,046 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,048 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,049 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,051 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,053 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,054 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,056 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,058 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,060 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:17,060 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:17,062 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:17,086 INFO L134 CoverageAnalysis]: Checked inductivity of 3044 backedges. 2 proven. 3042 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:17,102 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:17,102 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2018-01-30 02:32:17,103 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-01-30 02:32:17,103 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-01-30 02:32:17,103 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 02:32:17,103 INFO L87 Difference]: Start difference. First operand 502 states and 584 transitions. Second operand 42 states. [2018-01-30 02:32:17,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:17,334 INFO L93 Difference]: Finished difference Result 1018 states and 1188 transitions. [2018-01-30 02:32:17,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-30 02:32:17,335 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 182 [2018-01-30 02:32:17,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:17,336 INFO L225 Difference]: With dead ends: 1018 [2018-01-30 02:32:17,336 INFO L226 Difference]: Without dead ends: 522 [2018-01-30 02:32:17,336 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 223 GetRequests, 183 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-01-30 02:32:17,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-01-30 02:32:17,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 514. [2018-01-30 02:32:17,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 514 states. [2018-01-30 02:32:17,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 514 states to 514 states and 598 transitions. [2018-01-30 02:32:17,340 INFO L78 Accepts]: Start accepts. Automaton has 514 states and 598 transitions. Word has length 182 [2018-01-30 02:32:17,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:17,340 INFO L432 AbstractCegarLoop]: Abstraction has 514 states and 598 transitions. [2018-01-30 02:32:17,340 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-01-30 02:32:17,340 INFO L276 IsEmpty]: Start isEmpty. Operand 514 states and 598 transitions. [2018-01-30 02:32:17,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-01-30 02:32:17,341 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:17,341 INFO L350 BasicCegarLoop]: trace histogram [41, 40, 40, 40, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:17,341 INFO L371 AbstractCegarLoop]: === Iteration 43 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:17,341 INFO L82 PathProgramCache]: Analyzing trace with hash 1156058938, now seen corresponding path program 40 times [2018-01-30 02:32:17,341 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:17,341 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:17,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:17,341 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:17,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:17,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:17,347 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:17,811 INFO L134 CoverageAnalysis]: Checked inductivity of 3202 backedges. 2 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:17,811 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:17,811 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:17,816 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:17,832 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:17,833 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:17,853 INFO L134 CoverageAnalysis]: Checked inductivity of 3202 backedges. 2 proven. 3200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:17,870 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:17,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2018-01-30 02:32:17,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-01-30 02:32:17,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-01-30 02:32:17,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 02:32:17,871 INFO L87 Difference]: Start difference. First operand 514 states and 598 transitions. Second operand 43 states. [2018-01-30 02:32:18,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:18,129 INFO L93 Difference]: Finished difference Result 1042 states and 1216 transitions. [2018-01-30 02:32:18,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-01-30 02:32:18,130 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 186 [2018-01-30 02:32:18,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:18,131 INFO L225 Difference]: With dead ends: 1042 [2018-01-30 02:32:18,131 INFO L226 Difference]: Without dead ends: 534 [2018-01-30 02:32:18,131 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 187 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2018-01-30 02:32:18,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2018-01-30 02:32:18,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 526. [2018-01-30 02:32:18,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 526 states. [2018-01-30 02:32:18,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 526 states to 526 states and 612 transitions. [2018-01-30 02:32:18,135 INFO L78 Accepts]: Start accepts. Automaton has 526 states and 612 transitions. Word has length 186 [2018-01-30 02:32:18,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:18,135 INFO L432 AbstractCegarLoop]: Abstraction has 526 states and 612 transitions. [2018-01-30 02:32:18,135 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-01-30 02:32:18,135 INFO L276 IsEmpty]: Start isEmpty. Operand 526 states and 612 transitions. [2018-01-30 02:32:18,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-01-30 02:32:18,136 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:18,136 INFO L350 BasicCegarLoop]: trace histogram [42, 41, 41, 41, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:18,136 INFO L371 AbstractCegarLoop]: === Iteration 44 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:18,136 INFO L82 PathProgramCache]: Analyzing trace with hash -284799741, now seen corresponding path program 41 times [2018-01-30 02:32:18,136 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:18,136 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:18,136 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:18,137 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:18,137 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:18,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:18,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:18,774 INFO L134 CoverageAnalysis]: Checked inductivity of 3364 backedges. 2 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:18,775 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:18,775 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:18,785 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:18,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,823 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,825 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,827 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,828 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,830 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,832 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,836 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,839 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,841 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,843 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,844 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,845 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,847 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,848 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,850 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,851 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,852 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,854 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,857 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,862 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,863 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,865 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,867 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:18,867 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:18,869 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:18,889 INFO L134 CoverageAnalysis]: Checked inductivity of 3364 backedges. 2 proven. 3362 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:18,908 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:18,909 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2018-01-30 02:32:18,909 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-30 02:32:18,909 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-30 02:32:18,909 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 02:32:18,910 INFO L87 Difference]: Start difference. First operand 526 states and 612 transitions. Second operand 44 states. [2018-01-30 02:32:19,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:19,181 INFO L93 Difference]: Finished difference Result 1066 states and 1244 transitions. [2018-01-30 02:32:19,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-01-30 02:32:19,181 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 190 [2018-01-30 02:32:19,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:19,182 INFO L225 Difference]: With dead ends: 1066 [2018-01-30 02:32:19,182 INFO L226 Difference]: Without dead ends: 546 [2018-01-30 02:32:19,183 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 191 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-01-30 02:32:19,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-01-30 02:32:19,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 538. [2018-01-30 02:32:19,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-01-30 02:32:19,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 626 transitions. [2018-01-30 02:32:19,186 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 626 transitions. Word has length 190 [2018-01-30 02:32:19,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:19,186 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 626 transitions. [2018-01-30 02:32:19,186 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-30 02:32:19,186 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 626 transitions. [2018-01-30 02:32:19,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-01-30 02:32:19,187 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:19,187 INFO L350 BasicCegarLoop]: trace histogram [43, 42, 42, 42, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:19,187 INFO L371 AbstractCegarLoop]: === Iteration 45 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:19,187 INFO L82 PathProgramCache]: Analyzing trace with hash -1060209076, now seen corresponding path program 42 times [2018-01-30 02:32:19,187 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:19,187 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:19,188 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:19,188 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:19,188 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:19,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:19,193 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:19,715 INFO L134 CoverageAnalysis]: Checked inductivity of 3530 backedges. 2 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:19,716 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:19,716 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:19,720 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:19,724 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,725 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,725 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,726 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,727 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,727 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,728 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,729 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,730 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,731 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,732 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,733 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,734 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,735 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,736 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,737 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,738 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,739 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,740 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,741 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,742 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,743 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,744 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,745 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,747 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,748 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,749 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,750 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,752 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,753 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,755 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,756 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,757 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,759 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,761 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,762 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,764 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,766 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,768 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,770 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,771 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,773 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,775 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:19,776 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:19,777 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:19,798 INFO L134 CoverageAnalysis]: Checked inductivity of 3530 backedges. 2 proven. 3528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:19,815 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:19,816 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2018-01-30 02:32:19,816 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-01-30 02:32:19,816 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-01-30 02:32:19,816 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 02:32:19,816 INFO L87 Difference]: Start difference. First operand 538 states and 626 transitions. Second operand 45 states. [2018-01-30 02:32:20,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:20,099 INFO L93 Difference]: Finished difference Result 1090 states and 1272 transitions. [2018-01-30 02:32:20,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-30 02:32:20,100 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 194 [2018-01-30 02:32:20,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:20,101 INFO L225 Difference]: With dead ends: 1090 [2018-01-30 02:32:20,101 INFO L226 Difference]: Without dead ends: 558 [2018-01-30 02:32:20,101 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 238 GetRequests, 195 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2018-01-30 02:32:20,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 558 states. [2018-01-30 02:32:20,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 558 to 550. [2018-01-30 02:32:20,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 550 states. [2018-01-30 02:32:20,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 640 transitions. [2018-01-30 02:32:20,105 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 640 transitions. Word has length 194 [2018-01-30 02:32:20,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:20,105 INFO L432 AbstractCegarLoop]: Abstraction has 550 states and 640 transitions. [2018-01-30 02:32:20,105 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-01-30 02:32:20,105 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 640 transitions. [2018-01-30 02:32:20,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-30 02:32:20,106 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:20,106 INFO L350 BasicCegarLoop]: trace histogram [44, 43, 43, 43, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:20,106 INFO L371 AbstractCegarLoop]: === Iteration 46 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:20,106 INFO L82 PathProgramCache]: Analyzing trace with hash 622519061, now seen corresponding path program 43 times [2018-01-30 02:32:20,106 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:20,106 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:20,107 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:20,107 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:20,107 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:20,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:20,112 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:20,648 INFO L134 CoverageAnalysis]: Checked inductivity of 3700 backedges. 2 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:20,648 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:20,648 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:20,653 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:20,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:20,669 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:20,692 INFO L134 CoverageAnalysis]: Checked inductivity of 3700 backedges. 2 proven. 3698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:20,712 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:20,712 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2018-01-30 02:32:20,712 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-01-30 02:32:20,712 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-01-30 02:32:20,713 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 02:32:20,713 INFO L87 Difference]: Start difference. First operand 550 states and 640 transitions. Second operand 46 states. [2018-01-30 02:32:21,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:21,004 INFO L93 Difference]: Finished difference Result 1114 states and 1300 transitions. [2018-01-30 02:32:21,004 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-01-30 02:32:21,004 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 198 [2018-01-30 02:32:21,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:21,005 INFO L225 Difference]: With dead ends: 1114 [2018-01-30 02:32:21,005 INFO L226 Difference]: Without dead ends: 570 [2018-01-30 02:32:21,006 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 199 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-01-30 02:32:21,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states. [2018-01-30 02:32:21,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 562. [2018-01-30 02:32:21,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 562 states. [2018-01-30 02:32:21,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 562 states to 562 states and 654 transitions. [2018-01-30 02:32:21,009 INFO L78 Accepts]: Start accepts. Automaton has 562 states and 654 transitions. Word has length 198 [2018-01-30 02:32:21,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:21,009 INFO L432 AbstractCegarLoop]: Abstraction has 562 states and 654 transitions. [2018-01-30 02:32:21,009 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-01-30 02:32:21,009 INFO L276 IsEmpty]: Start isEmpty. Operand 562 states and 654 transitions. [2018-01-30 02:32:21,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2018-01-30 02:32:21,010 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:21,010 INFO L350 BasicCegarLoop]: trace histogram [45, 44, 44, 44, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:21,010 INFO L371 AbstractCegarLoop]: === Iteration 47 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:21,010 INFO L82 PathProgramCache]: Analyzing trace with hash 262519646, now seen corresponding path program 44 times [2018-01-30 02:32:21,010 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:21,010 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:21,011 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:21,011 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:21,011 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:21,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:21,016 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:21,580 INFO L134 CoverageAnalysis]: Checked inductivity of 3874 backedges. 2 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:21,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:21,581 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:21,600 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:21,604 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:21,614 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:21,617 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:21,618 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:21,648 INFO L134 CoverageAnalysis]: Checked inductivity of 3874 backedges. 2 proven. 3872 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:21,664 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:21,665 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2018-01-30 02:32:21,665 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-01-30 02:32:21,665 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-01-30 02:32:21,665 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-30 02:32:21,665 INFO L87 Difference]: Start difference. First operand 562 states and 654 transitions. Second operand 47 states. [2018-01-30 02:32:21,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:21,888 INFO L93 Difference]: Finished difference Result 1138 states and 1328 transitions. [2018-01-30 02:32:21,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-01-30 02:32:21,888 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 202 [2018-01-30 02:32:21,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:21,889 INFO L225 Difference]: With dead ends: 1138 [2018-01-30 02:32:21,889 INFO L226 Difference]: Without dead ends: 582 [2018-01-30 02:32:21,889 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 248 GetRequests, 203 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2018-01-30 02:32:21,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2018-01-30 02:32:21,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 574. [2018-01-30 02:32:21,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 574 states. [2018-01-30 02:32:21,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 668 transitions. [2018-01-30 02:32:21,893 INFO L78 Accepts]: Start accepts. Automaton has 574 states and 668 transitions. Word has length 202 [2018-01-30 02:32:21,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:21,893 INFO L432 AbstractCegarLoop]: Abstraction has 574 states and 668 transitions. [2018-01-30 02:32:21,893 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-01-30 02:32:21,893 INFO L276 IsEmpty]: Start isEmpty. Operand 574 states and 668 transitions. [2018-01-30 02:32:21,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-01-30 02:32:21,894 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:21,894 INFO L350 BasicCegarLoop]: trace histogram [46, 45, 45, 45, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:21,894 INFO L371 AbstractCegarLoop]: === Iteration 48 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:21,894 INFO L82 PathProgramCache]: Analyzing trace with hash -1928771801, now seen corresponding path program 45 times [2018-01-30 02:32:21,894 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:21,894 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:21,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:21,895 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:21,895 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:21,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:21,900 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:22,519 INFO L134 CoverageAnalysis]: Checked inductivity of 4052 backedges. 2 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:22,519 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:22,519 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:22,525 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:22,529 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,530 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,530 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,531 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,532 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,533 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,534 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,535 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,536 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,537 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,538 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,539 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,540 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,541 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,542 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,543 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,544 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,545 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,547 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,548 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,549 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,550 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,551 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,553 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,555 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,557 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,558 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,560 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,576 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,589 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,599 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,609 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,619 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,629 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,639 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,649 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,662 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,679 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,697 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,706 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,716 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,735 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:22,744 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:22,746 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:22,770 INFO L134 CoverageAnalysis]: Checked inductivity of 4052 backedges. 2 proven. 4050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:22,787 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:22,787 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2018-01-30 02:32:22,788 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-01-30 02:32:22,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-01-30 02:32:22,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 02:32:22,788 INFO L87 Difference]: Start difference. First operand 574 states and 668 transitions. Second operand 48 states. [2018-01-30 02:32:23,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:23,125 INFO L93 Difference]: Finished difference Result 1162 states and 1356 transitions. [2018-01-30 02:32:23,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-30 02:32:23,138 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 206 [2018-01-30 02:32:23,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:23,139 INFO L225 Difference]: With dead ends: 1162 [2018-01-30 02:32:23,140 INFO L226 Difference]: Without dead ends: 594 [2018-01-30 02:32:23,140 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 207 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-01-30 02:32:23,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 594 states. [2018-01-30 02:32:23,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 594 to 586. [2018-01-30 02:32:23,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 586 states. [2018-01-30 02:32:23,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 586 states to 586 states and 682 transitions. [2018-01-30 02:32:23,146 INFO L78 Accepts]: Start accepts. Automaton has 586 states and 682 transitions. Word has length 206 [2018-01-30 02:32:23,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:23,146 INFO L432 AbstractCegarLoop]: Abstraction has 586 states and 682 transitions. [2018-01-30 02:32:23,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-01-30 02:32:23,146 INFO L276 IsEmpty]: Start isEmpty. Operand 586 states and 682 transitions. [2018-01-30 02:32:23,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 211 [2018-01-30 02:32:23,147 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:23,147 INFO L350 BasicCegarLoop]: trace histogram [47, 46, 46, 46, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:23,147 INFO L371 AbstractCegarLoop]: === Iteration 49 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:23,147 INFO L82 PathProgramCache]: Analyzing trace with hash 1388299888, now seen corresponding path program 46 times [2018-01-30 02:32:23,147 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:23,147 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:23,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:23,148 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:23,148 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:23,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:23,154 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:23,911 INFO L134 CoverageAnalysis]: Checked inductivity of 4234 backedges. 2 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:23,911 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:23,911 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:23,915 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:23,934 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:23,936 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:23,978 INFO L134 CoverageAnalysis]: Checked inductivity of 4234 backedges. 2 proven. 4232 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:23,995 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:23,995 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2018-01-30 02:32:23,996 INFO L409 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-01-30 02:32:23,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-01-30 02:32:23,996 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 02:32:23,996 INFO L87 Difference]: Start difference. First operand 586 states and 682 transitions. Second operand 49 states. [2018-01-30 02:32:24,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:24,251 INFO L93 Difference]: Finished difference Result 1186 states and 1384 transitions. [2018-01-30 02:32:24,262 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-01-30 02:32:24,262 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 210 [2018-01-30 02:32:24,262 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:24,263 INFO L225 Difference]: With dead ends: 1186 [2018-01-30 02:32:24,263 INFO L226 Difference]: Without dead ends: 606 [2018-01-30 02:32:24,264 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 211 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2018-01-30 02:32:24,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606 states. [2018-01-30 02:32:24,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606 to 598. [2018-01-30 02:32:24,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 598 states. [2018-01-30 02:32:24,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 598 states to 598 states and 696 transitions. [2018-01-30 02:32:24,268 INFO L78 Accepts]: Start accepts. Automaton has 598 states and 696 transitions. Word has length 210 [2018-01-30 02:32:24,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:24,268 INFO L432 AbstractCegarLoop]: Abstraction has 598 states and 696 transitions. [2018-01-30 02:32:24,268 INFO L433 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-01-30 02:32:24,268 INFO L276 IsEmpty]: Start isEmpty. Operand 598 states and 696 transitions. [2018-01-30 02:32:24,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-01-30 02:32:24,269 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:24,269 INFO L350 BasicCegarLoop]: trace histogram [48, 47, 47, 47, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:24,269 INFO L371 AbstractCegarLoop]: === Iteration 50 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:24,269 INFO L82 PathProgramCache]: Analyzing trace with hash 1327724857, now seen corresponding path program 47 times [2018-01-30 02:32:24,269 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:24,269 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:24,269 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:24,270 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:24,270 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:24,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:24,285 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:24,938 INFO L134 CoverageAnalysis]: Checked inductivity of 4420 backedges. 2 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:24,938 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:24,938 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:24,942 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:24,945 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,947 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,948 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,949 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,951 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,953 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,955 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,956 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,958 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,960 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,962 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,964 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,966 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,967 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,969 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,979 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,982 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,984 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,987 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,988 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,990 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,992 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,994 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,997 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:24,999 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:25,001 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:25,003 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:25,005 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:25,007 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:25,009 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:25,010 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:25,011 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:25,036 INFO L134 CoverageAnalysis]: Checked inductivity of 4420 backedges. 2 proven. 4418 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:25,055 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:25,055 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2018-01-30 02:32:25,055 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-30 02:32:25,056 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-30 02:32:25,056 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 02:32:25,056 INFO L87 Difference]: Start difference. First operand 598 states and 696 transitions. Second operand 50 states. [2018-01-30 02:32:25,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:25,491 INFO L93 Difference]: Finished difference Result 1210 states and 1412 transitions. [2018-01-30 02:32:25,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-01-30 02:32:25,491 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 214 [2018-01-30 02:32:25,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:25,492 INFO L225 Difference]: With dead ends: 1210 [2018-01-30 02:32:25,492 INFO L226 Difference]: Without dead ends: 618 [2018-01-30 02:32:25,493 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 263 GetRequests, 215 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-01-30 02:32:25,493 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states. [2018-01-30 02:32:25,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 610. [2018-01-30 02:32:25,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 610 states. [2018-01-30 02:32:25,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 610 states to 610 states and 710 transitions. [2018-01-30 02:32:25,497 INFO L78 Accepts]: Start accepts. Automaton has 610 states and 710 transitions. Word has length 214 [2018-01-30 02:32:25,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:25,497 INFO L432 AbstractCegarLoop]: Abstraction has 610 states and 710 transitions. [2018-01-30 02:32:25,497 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-30 02:32:25,497 INFO L276 IsEmpty]: Start isEmpty. Operand 610 states and 710 transitions. [2018-01-30 02:32:25,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-01-30 02:32:25,498 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:25,498 INFO L350 BasicCegarLoop]: trace histogram [49, 48, 48, 48, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:25,498 INFO L371 AbstractCegarLoop]: === Iteration 51 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:25,498 INFO L82 PathProgramCache]: Analyzing trace with hash 963551106, now seen corresponding path program 48 times [2018-01-30 02:32:25,498 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:25,498 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:25,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:25,499 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:25,499 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:25,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:25,505 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:26,222 INFO L134 CoverageAnalysis]: Checked inductivity of 4610 backedges. 2 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:26,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:26,222 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:26,226 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:26,231 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,231 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,232 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,233 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,233 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,234 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,235 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,236 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,237 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,238 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,240 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,241 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,242 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,244 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,245 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,246 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,247 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,248 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,249 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,250 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,251 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,253 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,254 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,255 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,256 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,257 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,259 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,260 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,261 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,264 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,265 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,267 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,268 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,270 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,271 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,273 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,275 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,276 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,278 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,280 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,282 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,284 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,288 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,290 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,292 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:26,293 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:26,294 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:26,329 INFO L134 CoverageAnalysis]: Checked inductivity of 4610 backedges. 2 proven. 4608 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:26,346 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:26,346 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2018-01-30 02:32:26,346 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-01-30 02:32:26,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-01-30 02:32:26,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-30 02:32:26,347 INFO L87 Difference]: Start difference. First operand 610 states and 710 transitions. Second operand 51 states. [2018-01-30 02:32:27,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:27,177 INFO L93 Difference]: Finished difference Result 1234 states and 1440 transitions. [2018-01-30 02:32:27,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-01-30 02:32:27,177 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 218 [2018-01-30 02:32:27,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:27,179 INFO L225 Difference]: With dead ends: 1234 [2018-01-30 02:32:27,179 INFO L226 Difference]: Without dead ends: 630 [2018-01-30 02:32:27,179 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2018-01-30 02:32:27,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 630 states. [2018-01-30 02:32:27,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 630 to 622. [2018-01-30 02:32:27,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 622 states. [2018-01-30 02:32:27,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 622 states to 622 states and 724 transitions. [2018-01-30 02:32:27,184 INFO L78 Accepts]: Start accepts. Automaton has 622 states and 724 transitions. Word has length 218 [2018-01-30 02:32:27,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:27,184 INFO L432 AbstractCegarLoop]: Abstraction has 622 states and 724 transitions. [2018-01-30 02:32:27,184 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-01-30 02:32:27,184 INFO L276 IsEmpty]: Start isEmpty. Operand 622 states and 724 transitions. [2018-01-30 02:32:27,185 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-01-30 02:32:27,185 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:27,185 INFO L350 BasicCegarLoop]: trace histogram [50, 49, 49, 49, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:27,185 INFO L371 AbstractCegarLoop]: === Iteration 52 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:27,185 INFO L82 PathProgramCache]: Analyzing trace with hash 565934411, now seen corresponding path program 49 times [2018-01-30 02:32:27,185 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:27,185 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:27,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:27,186 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:27,186 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:27,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:27,192 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:27,914 INFO L134 CoverageAnalysis]: Checked inductivity of 4804 backedges. 2 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:27,914 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:27,914 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:27,918 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:27,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:27,937 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:27,963 INFO L134 CoverageAnalysis]: Checked inductivity of 4804 backedges. 2 proven. 4802 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:27,979 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:27,980 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 52 [2018-01-30 02:32:27,980 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-01-30 02:32:27,980 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-01-30 02:32:27,980 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-30 02:32:27,981 INFO L87 Difference]: Start difference. First operand 622 states and 724 transitions. Second operand 52 states. [2018-01-30 02:32:28,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:28,295 INFO L93 Difference]: Finished difference Result 1258 states and 1468 transitions. [2018-01-30 02:32:28,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-01-30 02:32:28,295 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 222 [2018-01-30 02:32:28,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:28,296 INFO L225 Difference]: With dead ends: 1258 [2018-01-30 02:32:28,296 INFO L226 Difference]: Without dead ends: 642 [2018-01-30 02:32:28,297 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 273 GetRequests, 223 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-01-30 02:32:28,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 642 states. [2018-01-30 02:32:28,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 642 to 634. [2018-01-30 02:32:28,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 634 states. [2018-01-30 02:32:28,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 634 states to 634 states and 738 transitions. [2018-01-30 02:32:28,301 INFO L78 Accepts]: Start accepts. Automaton has 634 states and 738 transitions. Word has length 222 [2018-01-30 02:32:28,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:28,301 INFO L432 AbstractCegarLoop]: Abstraction has 634 states and 738 transitions. [2018-01-30 02:32:28,301 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-01-30 02:32:28,301 INFO L276 IsEmpty]: Start isEmpty. Operand 634 states and 738 transitions. [2018-01-30 02:32:28,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-01-30 02:32:28,302 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:28,302 INFO L350 BasicCegarLoop]: trace histogram [51, 50, 50, 50, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:28,302 INFO L371 AbstractCegarLoop]: === Iteration 53 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:28,302 INFO L82 PathProgramCache]: Analyzing trace with hash 17057428, now seen corresponding path program 50 times [2018-01-30 02:32:28,302 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:28,302 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:28,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:28,303 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:28,303 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:28,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:28,309 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:29,016 INFO L134 CoverageAnalysis]: Checked inductivity of 5002 backedges. 2 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:29,017 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:29,017 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:29,022 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:29,026 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:29,037 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:29,040 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:29,042 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:29,068 INFO L134 CoverageAnalysis]: Checked inductivity of 5002 backedges. 2 proven. 5000 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:29,085 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:29,085 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 53 [2018-01-30 02:32:29,086 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-01-30 02:32:29,086 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-01-30 02:32:29,086 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-30 02:32:29,086 INFO L87 Difference]: Start difference. First operand 634 states and 738 transitions. Second operand 53 states. [2018-01-30 02:32:29,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:29,459 INFO L93 Difference]: Finished difference Result 1282 states and 1496 transitions. [2018-01-30 02:32:29,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-01-30 02:32:29,460 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 226 [2018-01-30 02:32:29,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:29,461 INFO L225 Difference]: With dead ends: 1282 [2018-01-30 02:32:29,461 INFO L226 Difference]: Without dead ends: 654 [2018-01-30 02:32:29,461 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 278 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2018-01-30 02:32:29,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 654 states. [2018-01-30 02:32:29,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 654 to 646. [2018-01-30 02:32:29,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 646 states. [2018-01-30 02:32:29,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 646 states to 646 states and 752 transitions. [2018-01-30 02:32:29,466 INFO L78 Accepts]: Start accepts. Automaton has 646 states and 752 transitions. Word has length 226 [2018-01-30 02:32:29,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:29,466 INFO L432 AbstractCegarLoop]: Abstraction has 646 states and 752 transitions. [2018-01-30 02:32:29,466 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-01-30 02:32:29,466 INFO L276 IsEmpty]: Start isEmpty. Operand 646 states and 752 transitions. [2018-01-30 02:32:29,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 231 [2018-01-30 02:32:29,467 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:29,467 INFO L350 BasicCegarLoop]: trace histogram [52, 51, 51, 51, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:29,467 INFO L371 AbstractCegarLoop]: === Iteration 54 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:29,467 INFO L82 PathProgramCache]: Analyzing trace with hash 1227048797, now seen corresponding path program 51 times [2018-01-30 02:32:29,467 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:29,467 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:29,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:29,468 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:29,468 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:29,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:29,474 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:30,209 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:30,209 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:30,209 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 02:32:30,214 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:30,218 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,219 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,220 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,220 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,221 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,222 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,223 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,224 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,225 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,226 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,227 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,228 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,228 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,229 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,230 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,231 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,232 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,233 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,234 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,235 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,237 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,238 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,239 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,241 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,242 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,243 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,245 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,246 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,248 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,249 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,250 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,252 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,254 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,255 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,257 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,258 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,260 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,262 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,264 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,266 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,268 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,269 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,271 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,275 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,277 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,283 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,286 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,288 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,291 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:30,292 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:30,293 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:30,321 INFO L134 CoverageAnalysis]: Checked inductivity of 5204 backedges. 2 proven. 5202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:30,337 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:30,337 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 54 [2018-01-30 02:32:30,338 INFO L409 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-01-30 02:32:30,338 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-01-30 02:32:30,338 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-30 02:32:30,338 INFO L87 Difference]: Start difference. First operand 646 states and 752 transitions. Second operand 54 states. [2018-01-30 02:32:30,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:30,631 INFO L93 Difference]: Finished difference Result 1306 states and 1524 transitions. [2018-01-30 02:32:30,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-30 02:32:30,631 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 230 [2018-01-30 02:32:30,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:30,632 INFO L225 Difference]: With dead ends: 1306 [2018-01-30 02:32:30,632 INFO L226 Difference]: Without dead ends: 666 [2018-01-30 02:32:30,633 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 231 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-01-30 02:32:30,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 666 states. [2018-01-30 02:32:30,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 666 to 658. [2018-01-30 02:32:30,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 658 states. [2018-01-30 02:32:30,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 658 states to 658 states and 766 transitions. [2018-01-30 02:32:30,637 INFO L78 Accepts]: Start accepts. Automaton has 658 states and 766 transitions. Word has length 230 [2018-01-30 02:32:30,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:30,637 INFO L432 AbstractCegarLoop]: Abstraction has 658 states and 766 transitions. [2018-01-30 02:32:30,637 INFO L433 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-01-30 02:32:30,637 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 766 transitions. [2018-01-30 02:32:30,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-01-30 02:32:30,638 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:30,638 INFO L350 BasicCegarLoop]: trace histogram [53, 52, 52, 52, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:30,638 INFO L371 AbstractCegarLoop]: === Iteration 55 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:30,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1959967654, now seen corresponding path program 52 times [2018-01-30 02:32:30,638 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:30,639 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:30,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:30,639 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:30,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:30,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:30,655 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:31,518 INFO L134 CoverageAnalysis]: Checked inductivity of 5410 backedges. 2 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:31,518 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:31,518 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:31,522 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:31,541 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:31,543 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:31,571 INFO L134 CoverageAnalysis]: Checked inductivity of 5410 backedges. 2 proven. 5408 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:31,588 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:31,588 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55] total 55 [2018-01-30 02:32:31,588 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-01-30 02:32:31,588 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-01-30 02:32:31,589 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-30 02:32:31,589 INFO L87 Difference]: Start difference. First operand 658 states and 766 transitions. Second operand 55 states. [2018-01-30 02:32:32,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:32,050 INFO L93 Difference]: Finished difference Result 1330 states and 1552 transitions. [2018-01-30 02:32:32,050 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-01-30 02:32:32,050 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 234 [2018-01-30 02:32:32,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:32,051 INFO L225 Difference]: With dead ends: 1330 [2018-01-30 02:32:32,052 INFO L226 Difference]: Without dead ends: 678 [2018-01-30 02:32:32,052 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 288 GetRequests, 235 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2018-01-30 02:32:32,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2018-01-30 02:32:32,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 670. [2018-01-30 02:32:32,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 670 states. [2018-01-30 02:32:32,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 670 states to 670 states and 780 transitions. [2018-01-30 02:32:32,056 INFO L78 Accepts]: Start accepts. Automaton has 670 states and 780 transitions. Word has length 234 [2018-01-30 02:32:32,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:32,057 INFO L432 AbstractCegarLoop]: Abstraction has 670 states and 780 transitions. [2018-01-30 02:32:32,057 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-01-30 02:32:32,057 INFO L276 IsEmpty]: Start isEmpty. Operand 670 states and 780 transitions. [2018-01-30 02:32:32,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-01-30 02:32:32,057 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:32,058 INFO L350 BasicCegarLoop]: trace histogram [54, 53, 53, 53, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:32,058 INFO L371 AbstractCegarLoop]: === Iteration 56 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:32,058 INFO L82 PathProgramCache]: Analyzing trace with hash -1750277265, now seen corresponding path program 53 times [2018-01-30 02:32:32,058 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:32,058 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:32,058 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:32,058 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:32,058 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:32,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:32,064 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:32,892 INFO L134 CoverageAnalysis]: Checked inductivity of 5620 backedges. 2 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:32,892 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:32,893 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:32,897 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:32,900 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,905 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,906 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,907 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,908 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,909 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,910 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,911 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,912 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,913 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,914 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,915 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,916 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,917 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,918 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,919 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,920 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,921 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,922 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,923 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,924 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,926 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,927 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,928 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,929 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,931 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,932 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,934 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,935 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,937 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,938 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,940 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,942 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,944 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,946 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,948 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,950 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,952 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,954 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,957 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,959 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,961 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,963 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,965 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,968 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,970 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,975 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,980 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,983 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,986 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:32,986 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:32,989 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:33,024 INFO L134 CoverageAnalysis]: Checked inductivity of 5620 backedges. 2 proven. 5618 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:33,042 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:33,042 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 56 [2018-01-30 02:32:33,042 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-30 02:32:33,042 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-30 02:32:33,042 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-30 02:32:33,042 INFO L87 Difference]: Start difference. First operand 670 states and 780 transitions. Second operand 56 states. [2018-01-30 02:32:33,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:33,399 INFO L93 Difference]: Finished difference Result 1354 states and 1580 transitions. [2018-01-30 02:32:33,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-01-30 02:32:33,399 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 238 [2018-01-30 02:32:33,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:33,401 INFO L225 Difference]: With dead ends: 1354 [2018-01-30 02:32:33,401 INFO L226 Difference]: Without dead ends: 690 [2018-01-30 02:32:33,402 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 293 GetRequests, 239 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-01-30 02:32:33,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states. [2018-01-30 02:32:33,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 682. [2018-01-30 02:32:33,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 682 states. [2018-01-30 02:32:33,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 682 states to 682 states and 794 transitions. [2018-01-30 02:32:33,407 INFO L78 Accepts]: Start accepts. Automaton has 682 states and 794 transitions. Word has length 238 [2018-01-30 02:32:33,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:33,407 INFO L432 AbstractCegarLoop]: Abstraction has 682 states and 794 transitions. [2018-01-30 02:32:33,407 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-30 02:32:33,407 INFO L276 IsEmpty]: Start isEmpty. Operand 682 states and 794 transitions. [2018-01-30 02:32:33,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-01-30 02:32:33,408 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:33,408 INFO L350 BasicCegarLoop]: trace histogram [55, 54, 54, 54, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:33,409 INFO L371 AbstractCegarLoop]: === Iteration 57 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:33,409 INFO L82 PathProgramCache]: Analyzing trace with hash -299106632, now seen corresponding path program 54 times [2018-01-30 02:32:33,409 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:33,409 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:33,409 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:33,409 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:33,409 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:33,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:33,417 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:34,241 INFO L134 CoverageAnalysis]: Checked inductivity of 5834 backedges. 2 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:34,242 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:34,242 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-30 02:32:34,258 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:34,263 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,279 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,289 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,299 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,309 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,329 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,342 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,352 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,362 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,372 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,384 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,385 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,386 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,387 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,388 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,390 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,390 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,391 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,392 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,394 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,395 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,396 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,397 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,398 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,399 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,401 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,403 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,404 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,406 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,407 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,408 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,410 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,411 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,412 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,414 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,416 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,417 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,419 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,421 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,422 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,424 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,425 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,427 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,429 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,431 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,433 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,435 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,437 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,439 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,441 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,443 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,448 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:34,448 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:34,450 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:34,481 INFO L134 CoverageAnalysis]: Checked inductivity of 5834 backedges. 2 proven. 5832 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:34,497 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:34,498 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57] total 57 [2018-01-30 02:32:34,498 INFO L409 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-01-30 02:32:34,498 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-01-30 02:32:34,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-30 02:32:34,498 INFO L87 Difference]: Start difference. First operand 682 states and 794 transitions. Second operand 57 states. [2018-01-30 02:32:34,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:34,866 INFO L93 Difference]: Finished difference Result 1378 states and 1608 transitions. [2018-01-30 02:32:34,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-01-30 02:32:34,867 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 242 [2018-01-30 02:32:34,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:34,868 INFO L225 Difference]: With dead ends: 1378 [2018-01-30 02:32:34,868 INFO L226 Difference]: Without dead ends: 702 [2018-01-30 02:32:34,869 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 298 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2018-01-30 02:32:34,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2018-01-30 02:32:34,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 694. [2018-01-30 02:32:34,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 694 states. [2018-01-30 02:32:34,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 694 states to 694 states and 808 transitions. [2018-01-30 02:32:34,873 INFO L78 Accepts]: Start accepts. Automaton has 694 states and 808 transitions. Word has length 242 [2018-01-30 02:32:34,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:34,873 INFO L432 AbstractCegarLoop]: Abstraction has 694 states and 808 transitions. [2018-01-30 02:32:34,873 INFO L433 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-01-30 02:32:34,873 INFO L276 IsEmpty]: Start isEmpty. Operand 694 states and 808 transitions. [2018-01-30 02:32:34,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2018-01-30 02:32:34,874 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:34,874 INFO L350 BasicCegarLoop]: trace histogram [56, 55, 55, 55, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:34,874 INFO L371 AbstractCegarLoop]: === Iteration 58 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:34,874 INFO L82 PathProgramCache]: Analyzing trace with hash 1839877505, now seen corresponding path program 55 times [2018-01-30 02:32:34,874 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:34,874 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:34,875 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:34,875 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:34,878 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:34,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:34,885 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:35,762 INFO L134 CoverageAnalysis]: Checked inductivity of 6052 backedges. 2 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:35,762 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:35,762 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:35,767 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:35,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:35,787 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:35,817 INFO L134 CoverageAnalysis]: Checked inductivity of 6052 backedges. 2 proven. 6050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:35,833 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:35,834 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 58 [2018-01-30 02:32:35,834 INFO L409 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-01-30 02:32:35,834 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-01-30 02:32:35,834 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-30 02:32:35,834 INFO L87 Difference]: Start difference. First operand 694 states and 808 transitions. Second operand 58 states. [2018-01-30 02:32:36,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:36,286 INFO L93 Difference]: Finished difference Result 1402 states and 1636 transitions. [2018-01-30 02:32:36,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-01-30 02:32:36,286 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 246 [2018-01-30 02:32:36,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:36,287 INFO L225 Difference]: With dead ends: 1402 [2018-01-30 02:32:36,287 INFO L226 Difference]: Without dead ends: 714 [2018-01-30 02:32:36,288 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 303 GetRequests, 247 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-01-30 02:32:36,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 714 states. [2018-01-30 02:32:36,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 714 to 706. [2018-01-30 02:32:36,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 706 states. [2018-01-30 02:32:36,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 706 states to 706 states and 822 transitions. [2018-01-30 02:32:36,293 INFO L78 Accepts]: Start accepts. Automaton has 706 states and 822 transitions. Word has length 246 [2018-01-30 02:32:36,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:36,293 INFO L432 AbstractCegarLoop]: Abstraction has 706 states and 822 transitions. [2018-01-30 02:32:36,293 INFO L433 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-01-30 02:32:36,293 INFO L276 IsEmpty]: Start isEmpty. Operand 706 states and 822 transitions. [2018-01-30 02:32:36,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-01-30 02:32:36,294 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:36,294 INFO L350 BasicCegarLoop]: trace histogram [57, 56, 56, 56, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:36,294 INFO L371 AbstractCegarLoop]: === Iteration 59 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:36,294 INFO L82 PathProgramCache]: Analyzing trace with hash 1415712714, now seen corresponding path program 56 times [2018-01-30 02:32:36,294 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:36,294 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:36,294 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:36,294 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:36,295 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:36,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:36,301 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:37,271 INFO L134 CoverageAnalysis]: Checked inductivity of 6274 backedges. 2 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:37,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:37,271 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:37,277 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:37,281 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:37,293 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:37,296 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:37,298 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:37,332 INFO L134 CoverageAnalysis]: Checked inductivity of 6274 backedges. 2 proven. 6272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:37,349 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:37,349 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59] total 59 [2018-01-30 02:32:37,349 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-01-30 02:32:37,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-01-30 02:32:37,350 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-30 02:32:37,350 INFO L87 Difference]: Start difference. First operand 706 states and 822 transitions. Second operand 59 states. [2018-01-30 02:32:37,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:37,802 INFO L93 Difference]: Finished difference Result 1426 states and 1664 transitions. [2018-01-30 02:32:37,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-01-30 02:32:37,802 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 250 [2018-01-30 02:32:37,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:37,803 INFO L225 Difference]: With dead ends: 1426 [2018-01-30 02:32:37,803 INFO L226 Difference]: Without dead ends: 726 [2018-01-30 02:32:37,804 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 251 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2018-01-30 02:32:37,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 726 states. [2018-01-30 02:32:37,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 726 to 718. [2018-01-30 02:32:37,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 718 states. [2018-01-30 02:32:37,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 836 transitions. [2018-01-30 02:32:37,808 INFO L78 Accepts]: Start accepts. Automaton has 718 states and 836 transitions. Word has length 250 [2018-01-30 02:32:37,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:37,808 INFO L432 AbstractCegarLoop]: Abstraction has 718 states and 836 transitions. [2018-01-30 02:32:37,808 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-01-30 02:32:37,808 INFO L276 IsEmpty]: Start isEmpty. Operand 718 states and 836 transitions. [2018-01-30 02:32:37,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-01-30 02:32:37,809 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:37,809 INFO L350 BasicCegarLoop]: trace histogram [58, 57, 57, 57, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:37,809 INFO L371 AbstractCegarLoop]: === Iteration 60 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:37,809 INFO L82 PathProgramCache]: Analyzing trace with hash -1184004717, now seen corresponding path program 57 times [2018-01-30 02:32:37,809 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:37,809 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:37,810 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:37,810 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:37,810 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:37,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:37,818 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:38,749 INFO L134 CoverageAnalysis]: Checked inductivity of 6500 backedges. 2 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:38,749 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:38,749 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:38,754 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:38,758 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,759 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,759 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,760 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,761 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,762 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,762 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,763 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,764 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,765 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,765 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,766 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,767 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,768 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,769 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,770 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,771 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,772 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,773 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,774 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,775 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,776 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,777 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,778 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,779 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,781 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,782 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,783 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,784 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,786 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,787 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,789 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,790 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,792 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,794 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,795 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,797 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,799 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,801 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,803 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,805 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,807 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,809 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,811 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,813 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,815 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,817 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,820 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,822 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,824 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,826 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,829 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,832 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,834 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,836 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,839 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,842 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,844 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,847 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:38,847 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:38,849 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:38,881 INFO L134 CoverageAnalysis]: Checked inductivity of 6500 backedges. 2 proven. 6498 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:38,898 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:38,898 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 60 [2018-01-30 02:32:38,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-30 02:32:38,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-30 02:32:38,899 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-30 02:32:38,899 INFO L87 Difference]: Start difference. First operand 718 states and 836 transitions. Second operand 60 states. [2018-01-30 02:32:39,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:39,292 INFO L93 Difference]: Finished difference Result 1450 states and 1692 transitions. [2018-01-30 02:32:39,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-01-30 02:32:39,293 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 254 [2018-01-30 02:32:39,293 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:39,294 INFO L225 Difference]: With dead ends: 1450 [2018-01-30 02:32:39,294 INFO L226 Difference]: Without dead ends: 738 [2018-01-30 02:32:39,295 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 313 GetRequests, 255 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-01-30 02:32:39,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 738 states. [2018-01-30 02:32:39,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 738 to 730. [2018-01-30 02:32:39,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 730 states. [2018-01-30 02:32:39,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 730 states to 730 states and 850 transitions. [2018-01-30 02:32:39,299 INFO L78 Accepts]: Start accepts. Automaton has 730 states and 850 transitions. Word has length 254 [2018-01-30 02:32:39,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:39,300 INFO L432 AbstractCegarLoop]: Abstraction has 730 states and 850 transitions. [2018-01-30 02:32:39,300 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-30 02:32:39,300 INFO L276 IsEmpty]: Start isEmpty. Operand 730 states and 850 transitions. [2018-01-30 02:32:39,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 259 [2018-01-30 02:32:39,301 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:39,301 INFO L350 BasicCegarLoop]: trace histogram [59, 58, 58, 58, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:39,301 INFO L371 AbstractCegarLoop]: === Iteration 61 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:39,301 INFO L82 PathProgramCache]: Analyzing trace with hash 482799324, now seen corresponding path program 58 times [2018-01-30 02:32:39,301 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:39,301 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:39,301 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:39,301 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:39,301 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:39,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:39,308 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:40,288 INFO L134 CoverageAnalysis]: Checked inductivity of 6730 backedges. 2 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:40,288 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:40,288 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:40,294 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:40,317 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:40,319 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:40,359 INFO L134 CoverageAnalysis]: Checked inductivity of 6730 backedges. 2 proven. 6728 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:40,376 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:40,376 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61] total 61 [2018-01-30 02:32:40,376 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-01-30 02:32:40,376 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-01-30 02:32:40,376 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-30 02:32:40,376 INFO L87 Difference]: Start difference. First operand 730 states and 850 transitions. Second operand 61 states. [2018-01-30 02:32:40,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:40,723 INFO L93 Difference]: Finished difference Result 1474 states and 1720 transitions. [2018-01-30 02:32:40,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-01-30 02:32:40,724 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 258 [2018-01-30 02:32:40,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:40,725 INFO L225 Difference]: With dead ends: 1474 [2018-01-30 02:32:40,725 INFO L226 Difference]: Without dead ends: 750 [2018-01-30 02:32:40,726 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 259 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2018-01-30 02:32:40,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 750 states. [2018-01-30 02:32:40,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 750 to 742. [2018-01-30 02:32:40,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 742 states. [2018-01-30 02:32:40,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 742 states to 742 states and 864 transitions. [2018-01-30 02:32:40,730 INFO L78 Accepts]: Start accepts. Automaton has 742 states and 864 transitions. Word has length 258 [2018-01-30 02:32:40,730 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:40,730 INFO L432 AbstractCegarLoop]: Abstraction has 742 states and 864 transitions. [2018-01-30 02:32:40,730 INFO L433 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-01-30 02:32:40,730 INFO L276 IsEmpty]: Start isEmpty. Operand 742 states and 864 transitions. [2018-01-30 02:32:40,731 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 263 [2018-01-30 02:32:40,731 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:40,731 INFO L350 BasicCegarLoop]: trace histogram [60, 59, 59, 59, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:40,731 INFO L371 AbstractCegarLoop]: === Iteration 62 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:40,732 INFO L82 PathProgramCache]: Analyzing trace with hash -146240603, now seen corresponding path program 59 times [2018-01-30 02:32:40,732 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:40,732 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:40,732 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:40,732 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:40,732 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:40,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:40,739 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:41,770 INFO L134 CoverageAnalysis]: Checked inductivity of 6964 backedges. 2 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:41,770 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:41,770 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:41,775 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:41,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,778 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,779 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,780 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,781 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,782 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,783 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,784 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,785 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,786 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,787 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,788 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,790 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,791 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,792 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,793 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,794 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,795 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,796 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,797 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,798 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,799 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,802 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,803 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,804 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,806 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,807 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,808 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,810 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,813 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,814 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,816 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,817 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,819 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,820 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,822 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,826 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,828 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,829 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,831 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,833 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,835 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,837 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,840 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,842 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,844 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,846 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,849 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,851 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,853 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,858 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,860 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:41,860 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:41,863 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:41,903 INFO L134 CoverageAnalysis]: Checked inductivity of 6964 backedges. 2 proven. 6962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:41,920 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:41,920 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 62 [2018-01-30 02:32:41,920 INFO L409 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-01-30 02:32:41,921 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-01-30 02:32:41,921 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-30 02:32:41,921 INFO L87 Difference]: Start difference. First operand 742 states and 864 transitions. Second operand 62 states. [2018-01-30 02:32:42,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:42,432 INFO L93 Difference]: Finished difference Result 1498 states and 1748 transitions. [2018-01-30 02:32:42,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-01-30 02:32:42,432 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 262 [2018-01-30 02:32:42,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:42,434 INFO L225 Difference]: With dead ends: 1498 [2018-01-30 02:32:42,434 INFO L226 Difference]: Without dead ends: 762 [2018-01-30 02:32:42,434 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 323 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-01-30 02:32:42,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 762 states. [2018-01-30 02:32:42,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 762 to 754. [2018-01-30 02:32:42,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 754 states. [2018-01-30 02:32:42,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 754 states to 754 states and 878 transitions. [2018-01-30 02:32:42,439 INFO L78 Accepts]: Start accepts. Automaton has 754 states and 878 transitions. Word has length 262 [2018-01-30 02:32:42,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:42,439 INFO L432 AbstractCegarLoop]: Abstraction has 754 states and 878 transitions. [2018-01-30 02:32:42,439 INFO L433 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-01-30 02:32:42,439 INFO L276 IsEmpty]: Start isEmpty. Operand 754 states and 878 transitions. [2018-01-30 02:32:42,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-01-30 02:32:42,440 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:42,440 INFO L350 BasicCegarLoop]: trace histogram [61, 60, 60, 60, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:42,440 INFO L371 AbstractCegarLoop]: === Iteration 63 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:42,440 INFO L82 PathProgramCache]: Analyzing trace with hash 1252826094, now seen corresponding path program 60 times [2018-01-30 02:32:42,440 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:42,440 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:42,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:42,441 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:42,441 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:42,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:42,448 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:43,498 INFO L134 CoverageAnalysis]: Checked inductivity of 7202 backedges. 2 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:43,498 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:43,498 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:43,503 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:43,507 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,508 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,509 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,510 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,510 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,511 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,512 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,513 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,514 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,515 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,516 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,517 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,517 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,518 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,519 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,520 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,521 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,522 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,523 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,524 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,525 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,526 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,528 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,529 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,530 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,531 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,532 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,534 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,535 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,537 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,538 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,541 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,542 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,544 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,545 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,547 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,549 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,550 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,552 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,554 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,556 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,558 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,560 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,564 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,566 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,568 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,570 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,572 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,574 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,577 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,587 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,596 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,598 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:43,599 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:43,601 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:43,636 INFO L134 CoverageAnalysis]: Checked inductivity of 7202 backedges. 2 proven. 7200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:43,652 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:43,653 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63] total 63 [2018-01-30 02:32:43,653 INFO L409 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-01-30 02:32:43,653 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-01-30 02:32:43,653 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-30 02:32:43,654 INFO L87 Difference]: Start difference. First operand 754 states and 878 transitions. Second operand 63 states. [2018-01-30 02:32:44,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:44,035 INFO L93 Difference]: Finished difference Result 1522 states and 1776 transitions. [2018-01-30 02:32:44,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-01-30 02:32:44,035 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 266 [2018-01-30 02:32:44,036 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:44,037 INFO L225 Difference]: With dead ends: 1522 [2018-01-30 02:32:44,037 INFO L226 Difference]: Without dead ends: 774 [2018-01-30 02:32:44,038 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 328 GetRequests, 267 SyntacticMatches, 0 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2018-01-30 02:32:44,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 774 states. [2018-01-30 02:32:44,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 766. [2018-01-30 02:32:44,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 766 states. [2018-01-30 02:32:44,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 766 states to 766 states and 892 transitions. [2018-01-30 02:32:44,042 INFO L78 Accepts]: Start accepts. Automaton has 766 states and 892 transitions. Word has length 266 [2018-01-30 02:32:44,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:44,042 INFO L432 AbstractCegarLoop]: Abstraction has 766 states and 892 transitions. [2018-01-30 02:32:44,042 INFO L433 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-01-30 02:32:44,042 INFO L276 IsEmpty]: Start isEmpty. Operand 766 states and 892 transitions. [2018-01-30 02:32:44,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 271 [2018-01-30 02:32:44,043 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:44,043 INFO L350 BasicCegarLoop]: trace histogram [62, 61, 61, 61, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:44,043 INFO L371 AbstractCegarLoop]: === Iteration 64 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:44,044 INFO L82 PathProgramCache]: Analyzing trace with hash 831348663, now seen corresponding path program 61 times [2018-01-30 02:32:44,044 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:44,044 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:44,044 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:44,044 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:44,044 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:44,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:44,052 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:45,174 INFO L134 CoverageAnalysis]: Checked inductivity of 7444 backedges. 2 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:45,175 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:45,175 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:45,180 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:45,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:45,201 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:45,237 INFO L134 CoverageAnalysis]: Checked inductivity of 7444 backedges. 2 proven. 7442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:45,253 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:45,253 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 64 [2018-01-30 02:32:45,254 INFO L409 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-01-30 02:32:45,254 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-01-30 02:32:45,254 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-30 02:32:45,254 INFO L87 Difference]: Start difference. First operand 766 states and 892 transitions. Second operand 64 states. [2018-01-30 02:32:45,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:45,766 INFO L93 Difference]: Finished difference Result 1546 states and 1804 transitions. [2018-01-30 02:32:45,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-01-30 02:32:45,766 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 270 [2018-01-30 02:32:45,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:45,767 INFO L225 Difference]: With dead ends: 1546 [2018-01-30 02:32:45,767 INFO L226 Difference]: Without dead ends: 786 [2018-01-30 02:32:45,768 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 271 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-01-30 02:32:45,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 786 states. [2018-01-30 02:32:45,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 786 to 778. [2018-01-30 02:32:45,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 778 states. [2018-01-30 02:32:45,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 906 transitions. [2018-01-30 02:32:45,773 INFO L78 Accepts]: Start accepts. Automaton has 778 states and 906 transitions. Word has length 270 [2018-01-30 02:32:45,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:45,773 INFO L432 AbstractCegarLoop]: Abstraction has 778 states and 906 transitions. [2018-01-30 02:32:45,773 INFO L433 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-01-30 02:32:45,773 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 906 transitions. [2018-01-30 02:32:45,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-01-30 02:32:45,774 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:45,774 INFO L350 BasicCegarLoop]: trace histogram [63, 62, 62, 62, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:45,774 INFO L371 AbstractCegarLoop]: === Iteration 65 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:45,774 INFO L82 PathProgramCache]: Analyzing trace with hash 1868896000, now seen corresponding path program 62 times [2018-01-30 02:32:45,774 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:45,774 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:45,775 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:45,775 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:45,775 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:45,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:45,782 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:46,875 INFO L134 CoverageAnalysis]: Checked inductivity of 7690 backedges. 2 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:46,875 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:46,875 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:46,880 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:46,884 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:46,897 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:46,900 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:46,902 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:46,949 INFO L134 CoverageAnalysis]: Checked inductivity of 7690 backedges. 2 proven. 7688 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:46,965 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:46,965 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65] total 65 [2018-01-30 02:32:46,966 INFO L409 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-01-30 02:32:46,966 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-01-30 02:32:46,966 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-30 02:32:46,966 INFO L87 Difference]: Start difference. First operand 778 states and 906 transitions. Second operand 65 states. [2018-01-30 02:32:47,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:47,498 INFO L93 Difference]: Finished difference Result 1570 states and 1832 transitions. [2018-01-30 02:32:47,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-01-30 02:32:47,498 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 274 [2018-01-30 02:32:47,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:47,499 INFO L225 Difference]: With dead ends: 1570 [2018-01-30 02:32:47,499 INFO L226 Difference]: Without dead ends: 798 [2018-01-30 02:32:47,500 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 275 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2018-01-30 02:32:47,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 798 states. [2018-01-30 02:32:47,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 798 to 790. [2018-01-30 02:32:47,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 790 states. [2018-01-30 02:32:47,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 790 states to 790 states and 920 transitions. [2018-01-30 02:32:47,505 INFO L78 Accepts]: Start accepts. Automaton has 790 states and 920 transitions. Word has length 274 [2018-01-30 02:32:47,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:47,505 INFO L432 AbstractCegarLoop]: Abstraction has 790 states and 920 transitions. [2018-01-30 02:32:47,505 INFO L433 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-01-30 02:32:47,505 INFO L276 IsEmpty]: Start isEmpty. Operand 790 states and 920 transitions. [2018-01-30 02:32:47,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 279 [2018-01-30 02:32:47,506 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:47,506 INFO L350 BasicCegarLoop]: trace histogram [64, 63, 63, 63, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:47,506 INFO L371 AbstractCegarLoop]: === Iteration 66 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:47,506 INFO L82 PathProgramCache]: Analyzing trace with hash 9306569, now seen corresponding path program 63 times [2018-01-30 02:32:47,506 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:47,506 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:47,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:47,507 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:47,507 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:47,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:47,515 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:48,658 INFO L134 CoverageAnalysis]: Checked inductivity of 7940 backedges. 2 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:48,658 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:48,658 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:48,663 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-30 02:32:48,667 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,668 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,669 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,669 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,670 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,671 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,671 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,672 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,673 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,674 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,675 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,676 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,676 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,677 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,678 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,679 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,680 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,681 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,682 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,683 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,684 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,685 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,687 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,688 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,690 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,691 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,692 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,694 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,695 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,697 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,698 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,699 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,701 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,703 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,704 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,706 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,708 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,709 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,711 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,713 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,715 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,717 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,718 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,725 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,730 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,732 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,734 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,736 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,738 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,741 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,743 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,745 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,747 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,749 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,751 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,754 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,756 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,758 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,761 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,763 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,765 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,768 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,770 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,773 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,776 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-30 02:32:48,777 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:48,779 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:48,816 INFO L134 CoverageAnalysis]: Checked inductivity of 7940 backedges. 2 proven. 7938 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:48,835 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:48,835 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 66 [2018-01-30 02:32:48,835 INFO L409 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-01-30 02:32:48,835 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-01-30 02:32:48,836 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-30 02:32:48,836 INFO L87 Difference]: Start difference. First operand 790 states and 920 transitions. Second operand 66 states. [2018-01-30 02:32:49,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:49,417 INFO L93 Difference]: Finished difference Result 1594 states and 1860 transitions. [2018-01-30 02:32:49,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-01-30 02:32:49,417 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 278 [2018-01-30 02:32:49,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:49,418 INFO L225 Difference]: With dead ends: 1594 [2018-01-30 02:32:49,419 INFO L226 Difference]: Without dead ends: 810 [2018-01-30 02:32:49,419 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 343 GetRequests, 279 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-01-30 02:32:49,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 810 states. [2018-01-30 02:32:49,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 810 to 802. [2018-01-30 02:32:49,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 802 states. [2018-01-30 02:32:49,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 802 states to 802 states and 934 transitions. [2018-01-30 02:32:49,424 INFO L78 Accepts]: Start accepts. Automaton has 802 states and 934 transitions. Word has length 278 [2018-01-30 02:32:49,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:49,425 INFO L432 AbstractCegarLoop]: Abstraction has 802 states and 934 transitions. [2018-01-30 02:32:49,425 INFO L433 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-01-30 02:32:49,425 INFO L276 IsEmpty]: Start isEmpty. Operand 802 states and 934 transitions. [2018-01-30 02:32:49,426 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 283 [2018-01-30 02:32:49,426 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:49,426 INFO L350 BasicCegarLoop]: trace histogram [65, 64, 64, 64, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:49,426 INFO L371 AbstractCegarLoop]: === Iteration 67 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:49,426 INFO L82 PathProgramCache]: Analyzing trace with hash -1438490606, now seen corresponding path program 64 times [2018-01-30 02:32:49,426 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:49,426 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:49,427 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:49,427 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:49,427 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:49,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:49,442 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:50,629 INFO L134 CoverageAnalysis]: Checked inductivity of 8194 backedges. 2 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:50,629 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:50,629 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:50,634 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-30 02:32:50,658 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:50,660 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:50,699 INFO L134 CoverageAnalysis]: Checked inductivity of 8194 backedges. 2 proven. 8192 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:50,716 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:50,716 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67] total 67 [2018-01-30 02:32:50,716 INFO L409 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-01-30 02:32:50,716 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-01-30 02:32:50,716 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-30 02:32:50,717 INFO L87 Difference]: Start difference. First operand 802 states and 934 transitions. Second operand 67 states. [2018-01-30 02:32:51,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:51,283 INFO L93 Difference]: Finished difference Result 1618 states and 1888 transitions. [2018-01-30 02:32:51,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-01-30 02:32:51,283 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 282 [2018-01-30 02:32:51,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:51,285 INFO L225 Difference]: With dead ends: 1618 [2018-01-30 02:32:51,285 INFO L226 Difference]: Without dead ends: 822 [2018-01-30 02:32:51,286 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 283 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2018-01-30 02:32:51,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 822 states. [2018-01-30 02:32:51,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 822 to 814. [2018-01-30 02:32:51,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 814 states. [2018-01-30 02:32:51,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 948 transitions. [2018-01-30 02:32:51,292 INFO L78 Accepts]: Start accepts. Automaton has 814 states and 948 transitions. Word has length 282 [2018-01-30 02:32:51,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:51,292 INFO L432 AbstractCegarLoop]: Abstraction has 814 states and 948 transitions. [2018-01-30 02:32:51,292 INFO L433 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-01-30 02:32:51,292 INFO L276 IsEmpty]: Start isEmpty. Operand 814 states and 948 transitions. [2018-01-30 02:32:51,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-01-30 02:32:51,293 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:51,294 INFO L350 BasicCegarLoop]: trace histogram [66, 65, 65, 65, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:51,294 INFO L371 AbstractCegarLoop]: === Iteration 68 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:51,294 INFO L82 PathProgramCache]: Analyzing trace with hash -1969458725, now seen corresponding path program 65 times [2018-01-30 02:32:51,294 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:51,294 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:51,294 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:51,294 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:51,294 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:51,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:51,303 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:52,592 INFO L134 CoverageAnalysis]: Checked inductivity of 8452 backedges. 2 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:52,592 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:52,592 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:52,596 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-30 02:32:52,599 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,610 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,611 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,612 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,613 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,614 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,615 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,616 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,617 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,618 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,619 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,620 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,621 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,622 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,623 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,624 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,626 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,627 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,628 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,629 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,630 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,631 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,633 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,634 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,635 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,637 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,638 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,640 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,641 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,643 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,644 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,646 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,648 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,649 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,651 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,652 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,654 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,656 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,658 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,660 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,661 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,663 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,665 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,667 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,669 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,671 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,673 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,675 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,678 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,680 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,682 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,685 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,687 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,689 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,692 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,694 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,697 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,699 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,702 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,704 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,707 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,710 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,714 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:52,715 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:52,717 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:52,757 INFO L134 CoverageAnalysis]: Checked inductivity of 8452 backedges. 2 proven. 8450 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:52,773 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:52,773 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 68 [2018-01-30 02:32:52,774 INFO L409 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-01-30 02:32:52,774 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-01-30 02:32:52,774 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-30 02:32:52,774 INFO L87 Difference]: Start difference. First operand 814 states and 948 transitions. Second operand 68 states. [2018-01-30 02:32:53,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:53,334 INFO L93 Difference]: Finished difference Result 1642 states and 1916 transitions. [2018-01-30 02:32:53,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-01-30 02:32:53,334 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 286 [2018-01-30 02:32:53,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:53,336 INFO L225 Difference]: With dead ends: 1642 [2018-01-30 02:32:53,336 INFO L226 Difference]: Without dead ends: 834 [2018-01-30 02:32:53,337 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 353 GetRequests, 287 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-01-30 02:32:53,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 834 states. [2018-01-30 02:32:53,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 834 to 826. [2018-01-30 02:32:53,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 826 states. [2018-01-30 02:32:53,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 826 states to 826 states and 962 transitions. [2018-01-30 02:32:53,342 INFO L78 Accepts]: Start accepts. Automaton has 826 states and 962 transitions. Word has length 286 [2018-01-30 02:32:53,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:53,343 INFO L432 AbstractCegarLoop]: Abstraction has 826 states and 962 transitions. [2018-01-30 02:32:53,343 INFO L433 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-01-30 02:32:53,343 INFO L276 IsEmpty]: Start isEmpty. Operand 826 states and 962 transitions. [2018-01-30 02:32:53,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 291 [2018-01-30 02:32:53,344 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:53,344 INFO L350 BasicCegarLoop]: trace histogram [67, 66, 66, 66, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:53,344 INFO L371 AbstractCegarLoop]: === Iteration 69 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:53,344 INFO L82 PathProgramCache]: Analyzing trace with hash -1466534108, now seen corresponding path program 66 times [2018-01-30 02:32:53,344 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:53,344 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:53,344 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:53,345 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:53,345 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:53,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:53,353 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:54,551 INFO L134 CoverageAnalysis]: Checked inductivity of 8714 backedges. 2 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:54,552 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:54,552 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:54,556 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-30 02:32:54,561 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,562 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,563 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,564 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,565 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,565 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,566 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,567 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,568 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,569 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,570 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,571 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,572 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,573 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,574 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,575 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,576 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,577 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,578 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,579 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,580 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,581 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,582 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,584 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,585 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,586 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,587 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,588 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,590 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,591 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,592 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,594 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,595 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,596 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,598 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,599 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,601 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,602 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,604 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,605 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,607 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,609 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,610 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,614 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,615 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,617 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,619 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,621 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,625 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,627 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,629 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,631 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,633 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,635 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,637 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,641 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,643 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,645 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,647 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,650 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,652 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,654 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,657 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,660 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-30 02:32:54,660 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:54,663 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:54,710 INFO L134 CoverageAnalysis]: Checked inductivity of 8714 backedges. 2 proven. 8712 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:54,728 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:54,728 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69] total 69 [2018-01-30 02:32:54,728 INFO L409 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-01-30 02:32:54,729 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-01-30 02:32:54,729 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-30 02:32:54,729 INFO L87 Difference]: Start difference. First operand 826 states and 962 transitions. Second operand 69 states. [2018-01-30 02:32:55,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:55,340 INFO L93 Difference]: Finished difference Result 1666 states and 1944 transitions. [2018-01-30 02:32:55,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-01-30 02:32:55,340 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 290 [2018-01-30 02:32:55,340 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:55,342 INFO L225 Difference]: With dead ends: 1666 [2018-01-30 02:32:55,342 INFO L226 Difference]: Without dead ends: 846 [2018-01-30 02:32:55,343 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 358 GetRequests, 291 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2018-01-30 02:32:55,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 846 states. [2018-01-30 02:32:55,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 846 to 838. [2018-01-30 02:32:55,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 838 states. [2018-01-30 02:32:55,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 838 states to 838 states and 976 transitions. [2018-01-30 02:32:55,348 INFO L78 Accepts]: Start accepts. Automaton has 838 states and 976 transitions. Word has length 290 [2018-01-30 02:32:55,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:55,348 INFO L432 AbstractCegarLoop]: Abstraction has 838 states and 976 transitions. [2018-01-30 02:32:55,348 INFO L433 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-01-30 02:32:55,348 INFO L276 IsEmpty]: Start isEmpty. Operand 838 states and 976 transitions. [2018-01-30 02:32:55,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-01-30 02:32:55,349 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:55,349 INFO L350 BasicCegarLoop]: trace histogram [68, 67, 67, 67, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:55,350 INFO L371 AbstractCegarLoop]: === Iteration 70 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:55,350 INFO L82 PathProgramCache]: Analyzing trace with hash -2079674387, now seen corresponding path program 67 times [2018-01-30 02:32:55,350 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:55,350 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:55,350 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:55,350 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-30 02:32:55,350 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:55,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:55,359 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:56,642 INFO L134 CoverageAnalysis]: Checked inductivity of 8980 backedges. 2 proven. 8978 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:56,642 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:56,642 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:56,647 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:56,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:56,668 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:56,712 INFO L134 CoverageAnalysis]: Checked inductivity of 8980 backedges. 2 proven. 8978 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:56,731 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:56,731 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 70 [2018-01-30 02:32:56,731 INFO L409 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-01-30 02:32:56,732 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-01-30 02:32:56,732 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-01-30 02:32:56,732 INFO L87 Difference]: Start difference. First operand 838 states and 976 transitions. Second operand 70 states. [2018-01-30 02:32:57,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-30 02:32:57,342 INFO L93 Difference]: Finished difference Result 1690 states and 1972 transitions. [2018-01-30 02:32:57,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-01-30 02:32:57,342 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 294 [2018-01-30 02:32:57,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-30 02:32:57,343 INFO L225 Difference]: With dead ends: 1690 [2018-01-30 02:32:57,344 INFO L226 Difference]: Without dead ends: 858 [2018-01-30 02:32:57,344 INFO L553 BasicCegarLoop]: 0 DeclaredPredicates, 363 GetRequests, 295 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-01-30 02:32:57,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 858 states. [2018-01-30 02:32:57,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 858 to 850. [2018-01-30 02:32:57,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 850 states. [2018-01-30 02:32:57,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 850 states to 850 states and 990 transitions. [2018-01-30 02:32:57,350 INFO L78 Accepts]: Start accepts. Automaton has 850 states and 990 transitions. Word has length 294 [2018-01-30 02:32:57,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-30 02:32:57,350 INFO L432 AbstractCegarLoop]: Abstraction has 850 states and 990 transitions. [2018-01-30 02:32:57,350 INFO L433 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-01-30 02:32:57,350 INFO L276 IsEmpty]: Start isEmpty. Operand 850 states and 990 transitions. [2018-01-30 02:32:57,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2018-01-30 02:32:57,351 INFO L342 BasicCegarLoop]: Found error trace [2018-01-30 02:32:57,351 INFO L350 BasicCegarLoop]: trace histogram [69, 68, 68, 68, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-30 02:32:57,351 INFO L371 AbstractCegarLoop]: === Iteration 71 === [__VERIFIER_assertErr0AssertViolation]=== [2018-01-30 02:32:57,352 INFO L82 PathProgramCache]: Analyzing trace with hash -1514972106, now seen corresponding path program 68 times [2018-01-30 02:32:57,352 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-30 02:32:57,352 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-30 02:32:57,352 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:57,352 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-30 02:32:57,352 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-30 02:32:57,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-30 02:32:57,361 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-30 02:32:58,743 INFO L134 CoverageAnalysis]: Checked inductivity of 9250 backedges. 2 proven. 9248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:58,743 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-30 02:32:58,743 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-30 02:32:58,747 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-30 02:32:58,751 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:58,765 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-30 02:32:58,769 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-30 02:32:58,771 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-30 02:32:58,813 INFO L134 CoverageAnalysis]: Checked inductivity of 9250 backedges. 2 proven. 9248 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-30 02:32:58,830 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-30 02:32:58,830 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [71, 71] total 71 [2018-01-30 02:32:58,830 INFO L409 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-01-30 02:32:58,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-01-30 02:32:58,831 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2485, Invalid=2485, Unknown=0, NotChecked=0, Total=4970 [2018-01-30 02:32:58,831 INFO L87 Difference]: Start difference. First operand 850 states and 990 transitions. Second operand 71 states. Received shutdown request... [2018-01-30 02:32:59,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-01-30 02:32:59,060 WARN L491 AbstractCegarLoop]: Verification canceled [2018-01-30 02:32:59,063 WARN L185 ceAbstractionStarter]: Timeout [2018-01-30 02:32:59,064 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 30.01 02:32:59 BasicIcfg [2018-01-30 02:32:59,064 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-30 02:32:59,064 INFO L168 Benchmark]: Toolchain (without parser) took 68057.42 ms. Allocated memory was 151.0 MB in the beginning and 1.1 GB in the end (delta: 952.1 MB). Free memory was 115.9 MB in the beginning and 460.7 MB in the end (delta: -344.8 MB). Peak memory consumption was 607.3 MB. Max. memory is 5.3 GB. [2018-01-30 02:32:59,065 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 151.0 MB. Free memory is still 120.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-30 02:32:59,065 INFO L168 Benchmark]: CACSL2BoogieTranslator took 114.17 ms. Allocated memory is still 151.0 MB. Free memory was 115.9 MB in the beginning and 107.5 MB in the end (delta: 8.5 MB). Peak memory consumption was 8.5 MB. Max. memory is 5.3 GB. [2018-01-30 02:32:59,065 INFO L168 Benchmark]: Boogie Preprocessor took 17.14 ms. Allocated memory is still 151.0 MB. Free memory was 107.5 MB in the beginning and 106.1 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-30 02:32:59,066 INFO L168 Benchmark]: RCFGBuilder took 368.86 ms. Allocated memory is still 151.0 MB. Free memory was 106.1 MB in the beginning and 92.9 MB in the end (delta: 13.1 MB). Peak memory consumption was 13.1 MB. Max. memory is 5.3 GB. [2018-01-30 02:32:59,066 INFO L168 Benchmark]: IcfgTransformer took 11.93 ms. Allocated memory is still 151.0 MB. Free memory was 92.9 MB in the beginning and 91.6 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. [2018-01-30 02:32:59,066 INFO L168 Benchmark]: TraceAbstraction took 67542.96 ms. Allocated memory was 151.0 MB in the beginning and 1.1 GB in the end (delta: 952.1 MB). Free memory was 91.6 MB in the beginning and 460.7 MB in the end (delta: -369.2 MB). Peak memory consumption was 583.0 MB. Max. memory is 5.3 GB. [2018-01-30 02:32:59,067 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 151.0 MB. Free memory is still 120.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 114.17 ms. Allocated memory is still 151.0 MB. Free memory was 115.9 MB in the beginning and 107.5 MB in the end (delta: 8.5 MB). Peak memory consumption was 8.5 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 17.14 ms. Allocated memory is still 151.0 MB. Free memory was 107.5 MB in the beginning and 106.1 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * RCFGBuilder took 368.86 ms. Allocated memory is still 151.0 MB. Free memory was 106.1 MB in the beginning and 92.9 MB in the end (delta: 13.1 MB). Peak memory consumption was 13.1 MB. Max. memory is 5.3 GB. * IcfgTransformer took 11.93 ms. Allocated memory is still 151.0 MB. Free memory was 92.9 MB in the beginning and 91.6 MB in the end (delta: 1.4 MB). Peak memory consumption was 1.4 MB. Max. memory is 5.3 GB. * TraceAbstraction took 67542.96 ms. Allocated memory was 151.0 MB in the beginning and 1.1 GB in the end (delta: 952.1 MB). Free memory was 91.6 MB in the beginning and 460.7 MB in the end (delta: -369.2 MB). Peak memory consumption was 583.0 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 2]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 2). Cancelled while BasicCegarLoop was constructing difference of abstraction (850states) and interpolant automaton (currently 35 states, 71 states before enhancement), while ReachableStatesComputation was computing reachable states (391 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 44 locations, 1 error locations. TIMEOUT Result, 67.5s OverallTime, 71 OverallIterations, 69 TraceHistogramMax, 20.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2630 SDtfs, 23499 SDslu, 48338 SDs, 0 SdLazy, 18437 SolverSat, 121 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 12.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 13642 GetRequests, 11226 SyntacticMatches, 0 SemanticMatches, 2416 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 32.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=850occurred in iteration=70, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 70 MinimizatonAttempts, 548 StatesRemovedByMinimization, 69 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 2.9s SatisfiabilityAnalysisTime, 40.7s InterpolantComputationTime, 22369 NumberOfCodeBlocks, 22149 NumberOfCodeBlocksAsserted, 1328 NumberOfCheckSat, 22230 ConstructedInterpolants, 0 QuantifiedInterpolants, 12336822 SizeOfPredicates, 68 NumberOfNonLiveVariables, 14291 ConjunctsInSsa, 2482 ConjunctsInUnsatCore, 139 InterpolantComputations, 3 PerfectInterpolantSequences, 274/428810 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sorting_bubblesort_false-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-30_02-32-59-074.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sorting_bubblesort_false-unreach-call_ground.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-30_02-32-59-074.csv Completed graceful shutdown