java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/reducercommutativity/rangesum10_false-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-5f7ec6e-m [2018-01-31 10:12:11,930 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-31 10:12:11,931 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-31 10:12:11,940 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-31 10:12:11,940 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-31 10:12:11,940 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-31 10:12:11,941 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-31 10:12:11,942 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-31 10:12:11,943 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-31 10:12:11,943 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-31 10:12:11,944 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-31 10:12:11,944 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-31 10:12:11,944 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-31 10:12:11,945 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-31 10:12:11,946 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-31 10:12:11,947 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-31 10:12:11,949 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-31 10:12:11,950 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-31 10:12:11,951 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-31 10:12:11,951 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-31 10:12:11,953 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-31 10:12:11,953 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-31 10:12:11,953 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-31 10:12:11,953 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-31 10:12:11,957 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-31 10:12:11,958 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-31 10:12:11,958 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-31 10:12:11,958 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-31 10:12:11,958 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-31 10:12:11,959 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-31 10:12:11,959 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-31 10:12:11,959 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-31 10:12:11,967 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-31 10:12:11,970 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-31 10:12:11,971 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-31 10:12:11,971 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-31 10:12:11,971 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-31 10:12:11,971 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-31 10:12:11,971 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-31 10:12:11,971 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-31 10:12:11,971 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-31 10:12:11,972 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-31 10:12:11,972 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:12:11,973 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-31 10:12:11,973 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-31 10:12:11,978 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-31 10:12:11,978 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-31 10:12:11,997 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-31 10:12:12,004 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-31 10:12:12,006 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-31 10:12:12,006 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-31 10:12:12,007 INFO L276 PluginConnector]: CDTParser initialized [2018-01-31 10:12:12,007 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/rangesum10_false-unreach-call_true-termination.i [2018-01-31 10:12:12,075 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-31 10:12:12,075 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-31 10:12:12,076 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-31 10:12:12,076 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-31 10:12:12,079 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-31 10:12:12,080 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,082 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@116486b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12, skipping insertion in model container [2018-01-31 10:12:12,082 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,103 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:12:12,114 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:12:12,188 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:12:12,203 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:12:12,206 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12 WrapperNode [2018-01-31 10:12:12,207 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-31 10:12:12,207 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-31 10:12:12,207 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-31 10:12:12,207 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-31 10:12:12,215 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,215 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,222 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,222 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,224 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,226 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,227 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,228 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-31 10:12:12,228 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-31 10:12:12,228 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-31 10:12:12,228 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-31 10:12:12,229 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:12:12,265 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-31 10:12:12,265 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-31 10:12:12,265 INFO L136 BoogieDeclarations]: Found implementation of procedure init_nondet [2018-01-31 10:12:12,265 INFO L136 BoogieDeclarations]: Found implementation of procedure rangesum [2018-01-31 10:12:12,265 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-31 10:12:12,265 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-31 10:12:12,265 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-31 10:12:12,265 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure init_nondet [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure rangesum [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-31 10:12:12,266 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-31 10:12:12,690 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-31 10:12:12,691 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:12:12 BoogieIcfgContainer [2018-01-31 10:12:12,691 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-31 10:12:12,691 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-31 10:12:12,691 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-31 10:12:12,692 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-31 10:12:12,694 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:12:12" (1/1) ... [2018-01-31 10:12:12,699 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-01-31 10:12:12,699 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-01-31 10:12:12,699 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing [2018-01-31 10:12:12,725 INFO L162 apSepIcfgTransformer]: finished StoreIndexFreezer, created 13 freeze vars and freeze var literals (each corresponds to one heap write) [2018-01-31 10:12:12,746 INFO L221 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-01-31 10:12:12,779 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-31 10:12:20,005 INFO L314 AbstractInterpreter]: Visited 104 different actions 756 times. Merged at 73 different actions 393 times. Never widened. Found 75 fixpoints after 15 different actions. Largest state had 65 variables. [2018-01-31 10:12:20,007 INFO L229 apSepIcfgTransformer]: finished equality analysis [2018-01-31 10:12:20,012 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 10 [2018-01-31 10:12:20,013 INFO L241 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-01-31 10:12:20,013 INFO L242 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-01-31 10:12:20,013 INFO L244 apSepIcfgTransformer]: select infos: Set: ((select |v_#memory_int_19| v_init_nondet_~x.base_2), at (SUMMARY for call write~int(#t~nondet1, ~x.base, ~x.offset + ~i~3 * 4, 4); srcloc: L7')) ((select (select |v_#memory_int_11| |v_main_~#x~8.base_11|) |v_main_~#x~8.offset_11|), at (SUMMARY for call #t~mem11 := read~int(~#x~8.base, ~#x~8.offset + 0, 4); srcloc: L42)) ((select (select |v_#memory_int_12| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4)), at (SUMMARY for call #t~mem14 := read~int(~#x~8.base, ~#x~8.offset + (~i~9 + 1) * 4, 4); srcloc: L44)) ((select |v_#memory_int_10| |v_main_~#x~8.base_9|), at (SUMMARY for call write~int(~temp~8, ~#x~8.base, ~#x~8.offset + 4, 4); srcloc: L40'''''')) ((select (select |v_#memory_int_5| |v_main_~#x~8.base_6|) |v_main_~#x~8.offset_6|), at (SUMMARY for call #t~mem6 := read~int(~#x~8.base, ~#x~8.offset + 0, 4); srcloc: L40)) ((select |v_#memory_int_8| |v_main_~#x~8.base_8|), at (SUMMARY for call write~int(#t~mem8, ~#x~8.base, ~#x~8.offset + 0, 4); srcloc: L40'''')) ((select (select |v_#memory_int_17| v_rangesum_~x.base_2) (+ v_rangesum_~x.offset_2 (* 4 v_rangesum_~i~5_6))), at (SUMMARY for call #t~mem4 := read~int(~x.base, ~x.offset + ~i~5 * 4, 4); srcloc: L19)) ((select |v_#memory_int_16| |v_main_~#x~8.base_14|), at (SUMMARY for call write~int(~temp~8, ~#x~8.base, ~#x~8.offset + 36, 4); srcloc: L43''''''')) ((select |v_#memory_int_14| |v_main_~#x~8.base_13|), at (SUMMARY for call write~int(#t~mem14, ~#x~8.base, ~#x~8.offset + ~i~9 * 4, 4); srcloc: L44')) ((select (select |v_#memory_int_6| |v_main_~#x~8.base_7|) (+ |v_main_~#x~8.offset_7| 4)), at (SUMMARY for call #t~mem8 := read~int(~#x~8.base, ~#x~8.offset + 4, 4); srcloc: L40''')) [2018-01-31 10:12:20,025 INFO L547 PartitionManager]: partitioning result: [2018-01-31 10:12:20,025 INFO L552 PartitionManager]: location blocks for array group [#memory_int] [2018-01-31 10:12:20,025 INFO L562 PartitionManager]: at dimension 0 [2018-01-31 10:12:20,025 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 6 [2018-01-31 10:12:20,026 INFO L564 PartitionManager]: # location blocks :3 [2018-01-31 10:12:20,026 INFO L562 PartitionManager]: at dimension 1 [2018-01-31 10:12:20,026 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 6 [2018-01-31 10:12:20,026 INFO L564 PartitionManager]: # location blocks :2 [2018-01-31 10:12:20,026 INFO L86 ransitionTransformer]: executing heap partitioning transformation [2018-01-31 10:12:20,038 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:12:20 BasicIcfg [2018-01-31 10:12:20,038 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-31 10:12:20,038 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-31 10:12:20,039 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-31 10:12:20,040 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-31 10:12:20,044 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 31.01 10:12:12" (1/4) ... [2018-01-31 10:12:20,044 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@30202aed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:12:20, skipping insertion in model container [2018-01-31 10:12:20,044 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:12:12" (2/4) ... [2018-01-31 10:12:20,045 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@30202aed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:12:20, skipping insertion in model container [2018-01-31 10:12:20,045 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:12:12" (3/4) ... [2018-01-31 10:12:20,045 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@30202aed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:12:20, skipping insertion in model container [2018-01-31 10:12:20,045 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:12:20" (4/4) ... [2018-01-31 10:12:20,046 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg [2018-01-31 10:12:20,051 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-31 10:12:20,057 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-31 10:12:20,158 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-31 10:12:20,158 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-31 10:12:20,159 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-31 10:12:20,159 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-31 10:12:20,159 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-31 10:12:20,159 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-31 10:12:20,159 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-31 10:12:20,159 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-31 10:12:20,159 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-31 10:12:20,166 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states. [2018-01-31 10:12:20,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-01-31 10:12:20,170 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:20,171 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:20,171 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation]=== [2018-01-31 10:12:20,174 INFO L82 PathProgramCache]: Analyzing trace with hash -1073882414, now seen corresponding path program 1 times [2018-01-31 10:12:20,175 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:20,175 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:20,203 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:20,204 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:20,204 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:20,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:20,233 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:20,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:20,257 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:12:20,258 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-31 10:12:20,258 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-31 10:12:20,264 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-31 10:12:20,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:12:20,265 INFO L87 Difference]: Start difference. First operand 88 states. Second operand 2 states. [2018-01-31 10:12:20,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:20,281 INFO L93 Difference]: Finished difference Result 157 states and 187 transitions. [2018-01-31 10:12:20,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-31 10:12:20,282 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 35 [2018-01-31 10:12:20,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:20,287 INFO L225 Difference]: With dead ends: 157 [2018-01-31 10:12:20,287 INFO L226 Difference]: Without dead ends: 81 [2018-01-31 10:12:20,289 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:12:20,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-01-31 10:12:20,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-01-31 10:12:20,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-01-31 10:12:20,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 92 transitions. [2018-01-31 10:12:20,313 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 92 transitions. Word has length 35 [2018-01-31 10:12:20,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:20,313 INFO L432 AbstractCegarLoop]: Abstraction has 81 states and 92 transitions. [2018-01-31 10:12:20,313 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-31 10:12:20,314 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 92 transitions. [2018-01-31 10:12:20,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-31 10:12:20,315 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:20,315 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:20,315 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation]=== [2018-01-31 10:12:20,315 INFO L82 PathProgramCache]: Analyzing trace with hash -173460809, now seen corresponding path program 1 times [2018-01-31 10:12:20,316 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:20,316 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:20,316 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:20,316 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:20,316 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:20,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:20,330 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:20,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:20,504 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:12:20,504 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-01-31 10:12:20,505 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-01-31 10:12:20,505 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-01-31 10:12:20,506 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-31 10:12:20,506 INFO L87 Difference]: Start difference. First operand 81 states and 92 transitions. Second operand 4 states. [2018-01-31 10:12:20,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:20,777 INFO L93 Difference]: Finished difference Result 117 states and 132 transitions. [2018-01-31 10:12:20,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-01-31 10:12:20,777 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 36 [2018-01-31 10:12:20,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:20,778 INFO L225 Difference]: With dead ends: 117 [2018-01-31 10:12:20,778 INFO L226 Difference]: Without dead ends: 88 [2018-01-31 10:12:20,779 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-01-31 10:12:20,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-01-31 10:12:20,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 83. [2018-01-31 10:12:20,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-01-31 10:12:20,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 94 transitions. [2018-01-31 10:12:20,784 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 94 transitions. Word has length 36 [2018-01-31 10:12:20,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:20,784 INFO L432 AbstractCegarLoop]: Abstraction has 83 states and 94 transitions. [2018-01-31 10:12:20,784 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-01-31 10:12:20,784 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 94 transitions. [2018-01-31 10:12:20,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-01-31 10:12:20,785 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:20,785 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:20,785 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation]=== [2018-01-31 10:12:20,785 INFO L82 PathProgramCache]: Analyzing trace with hash 858737893, now seen corresponding path program 1 times [2018-01-31 10:12:20,785 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:20,785 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:20,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:20,786 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:20,786 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:20,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:20,795 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:21,114 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:21,114 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:21,114 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-31 10:12:21,128 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:21,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:21,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:21,328 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:21,345 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:21,345 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 9 [2018-01-31 10:12:21,347 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-01-31 10:12:21,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-01-31 10:12:21,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-01-31 10:12:21,347 INFO L87 Difference]: Start difference. First operand 83 states and 94 transitions. Second operand 9 states. [2018-01-31 10:12:21,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:21,472 INFO L93 Difference]: Finished difference Result 125 states and 140 transitions. [2018-01-31 10:12:21,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-31 10:12:21,473 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 44 [2018-01-31 10:12:21,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:21,475 INFO L225 Difference]: With dead ends: 125 [2018-01-31 10:12:21,475 INFO L226 Difference]: Without dead ends: 96 [2018-01-31 10:12:21,476 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 42 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-01-31 10:12:21,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-01-31 10:12:21,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 91. [2018-01-31 10:12:21,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-01-31 10:12:21,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 102 transitions. [2018-01-31 10:12:21,480 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 102 transitions. Word has length 44 [2018-01-31 10:12:21,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:21,480 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 102 transitions. [2018-01-31 10:12:21,480 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-01-31 10:12:21,480 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 102 transitions. [2018-01-31 10:12:21,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-01-31 10:12:21,481 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:21,481 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:21,481 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation]=== [2018-01-31 10:12:21,481 INFO L82 PathProgramCache]: Analyzing trace with hash 575101203, now seen corresponding path program 2 times [2018-01-31 10:12:21,481 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:21,481 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:21,482 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:21,482 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:21,482 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:21,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:21,491 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:21,678 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:21,678 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:21,678 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:21,688 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:12:21,707 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:21,712 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:21,712 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:21,717 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:21,755 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:21,783 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:21,784 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 13 [2018-01-31 10:12:21,784 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-01-31 10:12:21,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-01-31 10:12:21,784 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2018-01-31 10:12:21,784 INFO L87 Difference]: Start difference. First operand 91 states and 102 transitions. Second operand 13 states. [2018-01-31 10:12:22,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:22,286 INFO L93 Difference]: Finished difference Result 133 states and 148 transitions. [2018-01-31 10:12:22,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-01-31 10:12:22,286 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 52 [2018-01-31 10:12:22,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:22,287 INFO L225 Difference]: With dead ends: 133 [2018-01-31 10:12:22,287 INFO L226 Difference]: Without dead ends: 104 [2018-01-31 10:12:22,287 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 48 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=181, Unknown=0, NotChecked=0, Total=272 [2018-01-31 10:12:22,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-01-31 10:12:22,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 99. [2018-01-31 10:12:22,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-01-31 10:12:22,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 110 transitions. [2018-01-31 10:12:22,294 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 110 transitions. Word has length 52 [2018-01-31 10:12:22,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:22,294 INFO L432 AbstractCegarLoop]: Abstraction has 99 states and 110 transitions. [2018-01-31 10:12:22,295 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-01-31 10:12:22,295 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 110 transitions. [2018-01-31 10:12:22,296 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-01-31 10:12:22,296 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:22,296 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:22,296 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation]=== [2018-01-31 10:12:22,296 INFO L82 PathProgramCache]: Analyzing trace with hash 1390368577, now seen corresponding path program 3 times [2018-01-31 10:12:22,296 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:22,296 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:22,297 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:22,297 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:22,297 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:22,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:22,317 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:22,444 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:22,444 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:22,444 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:22,449 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:12:22,458 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:22,468 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:22,470 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:22,473 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:12:22,473 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:22,476 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:22,573 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:22,590 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:22,590 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-01-31 10:12:22,590 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-31 10:12:22,590 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-31 10:12:22,591 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=200, Unknown=0, NotChecked=0, Total=272 [2018-01-31 10:12:22,591 INFO L87 Difference]: Start difference. First operand 99 states and 110 transitions. Second operand 17 states. [2018-01-31 10:12:22,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:22,726 INFO L93 Difference]: Finished difference Result 141 states and 156 transitions. [2018-01-31 10:12:22,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-31 10:12:22,726 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 60 [2018-01-31 10:12:22,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:22,727 INFO L225 Difference]: With dead ends: 141 [2018-01-31 10:12:22,727 INFO L226 Difference]: Without dead ends: 112 [2018-01-31 10:12:22,728 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 54 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=159, Invalid=347, Unknown=0, NotChecked=0, Total=506 [2018-01-31 10:12:22,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-01-31 10:12:22,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 107. [2018-01-31 10:12:22,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-01-31 10:12:22,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 118 transitions. [2018-01-31 10:12:22,731 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 118 transitions. Word has length 60 [2018-01-31 10:12:22,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:22,731 INFO L432 AbstractCegarLoop]: Abstraction has 107 states and 118 transitions. [2018-01-31 10:12:22,731 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-31 10:12:22,731 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 118 transitions. [2018-01-31 10:12:22,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-01-31 10:12:22,732 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:22,733 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:22,733 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation]=== [2018-01-31 10:12:22,733 INFO L82 PathProgramCache]: Analyzing trace with hash -2031794321, now seen corresponding path program 4 times [2018-01-31 10:12:22,733 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:22,733 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:22,733 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:22,733 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:22,734 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:22,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:22,741 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:22,882 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:22,882 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:22,882 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:22,886 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:12:22,902 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:22,904 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:22,977 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:22,994 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:22,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 21 [2018-01-31 10:12:22,994 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:12:22,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:12:22,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=315, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:12:22,995 INFO L87 Difference]: Start difference. First operand 107 states and 118 transitions. Second operand 21 states. [2018-01-31 10:12:23,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:23,205 INFO L93 Difference]: Finished difference Result 149 states and 164 transitions. [2018-01-31 10:12:23,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-01-31 10:12:23,206 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 68 [2018-01-31 10:12:23,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:23,206 INFO L225 Difference]: With dead ends: 149 [2018-01-31 10:12:23,207 INFO L226 Difference]: Without dead ends: 120 [2018-01-31 10:12:23,207 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 60 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=245, Invalid=567, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:12:23,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-01-31 10:12:23,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 115. [2018-01-31 10:12:23,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-01-31 10:12:23,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 126 transitions. [2018-01-31 10:12:23,211 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 126 transitions. Word has length 68 [2018-01-31 10:12:23,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:23,211 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 126 transitions. [2018-01-31 10:12:23,211 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:12:23,211 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 126 transitions. [2018-01-31 10:12:23,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-01-31 10:12:23,224 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:23,224 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:23,225 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation]=== [2018-01-31 10:12:23,225 INFO L82 PathProgramCache]: Analyzing trace with hash -1303959139, now seen corresponding path program 5 times [2018-01-31 10:12:23,225 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:23,225 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:23,225 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:23,225 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:23,225 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:23,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:23,240 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:23,432 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:23,433 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:23,433 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:23,438 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:12:23,445 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:23,446 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:23,450 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:23,455 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:23,457 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:23,463 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:23,464 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:23,465 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:23,564 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:23,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:23,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 25 [2018-01-31 10:12:23,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-31 10:12:23,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-31 10:12:23,582 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=456, Unknown=0, NotChecked=0, Total=600 [2018-01-31 10:12:23,582 INFO L87 Difference]: Start difference. First operand 115 states and 126 transitions. Second operand 25 states. [2018-01-31 10:12:23,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:23,883 INFO L93 Difference]: Finished difference Result 157 states and 172 transitions. [2018-01-31 10:12:23,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-31 10:12:23,884 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 76 [2018-01-31 10:12:23,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:23,884 INFO L225 Difference]: With dead ends: 157 [2018-01-31 10:12:23,884 INFO L226 Difference]: Without dead ends: 128 [2018-01-31 10:12:23,885 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 66 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 281 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=349, Invalid=841, Unknown=0, NotChecked=0, Total=1190 [2018-01-31 10:12:23,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-01-31 10:12:23,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 123. [2018-01-31 10:12:23,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-01-31 10:12:23,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 134 transitions. [2018-01-31 10:12:23,891 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 134 transitions. Word has length 76 [2018-01-31 10:12:23,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:23,891 INFO L432 AbstractCegarLoop]: Abstraction has 123 states and 134 transitions. [2018-01-31 10:12:23,891 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-31 10:12:23,891 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 134 transitions. [2018-01-31 10:12:23,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-01-31 10:12:23,892 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:23,892 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:23,892 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation]=== [2018-01-31 10:12:23,892 INFO L82 PathProgramCache]: Analyzing trace with hash -84738613, now seen corresponding path program 6 times [2018-01-31 10:12:23,892 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:23,892 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:23,893 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:23,893 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:23,893 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:23,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:23,907 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:24,165 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:24,165 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:24,165 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:24,170 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:12:24,180 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,189 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,201 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,208 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,221 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,230 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,239 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:12:24,250 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:24,252 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:24,358 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:24,375 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:24,375 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15] total 29 [2018-01-31 10:12:24,375 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-31 10:12:24,376 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-31 10:12:24,376 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=189, Invalid=623, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:12:24,376 INFO L87 Difference]: Start difference. First operand 123 states and 134 transitions. Second operand 29 states. [2018-01-31 10:12:24,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:24,649 INFO L93 Difference]: Finished difference Result 165 states and 180 transitions. [2018-01-31 10:12:24,649 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-01-31 10:12:24,650 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 84 [2018-01-31 10:12:24,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:24,650 INFO L225 Difference]: With dead ends: 165 [2018-01-31 10:12:24,650 INFO L226 Difference]: Without dead ends: 136 [2018-01-31 10:12:24,651 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 72 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 403 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=471, Invalid=1169, Unknown=0, NotChecked=0, Total=1640 [2018-01-31 10:12:24,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-01-31 10:12:24,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 131. [2018-01-31 10:12:24,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-01-31 10:12:24,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 142 transitions. [2018-01-31 10:12:24,655 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 142 transitions. Word has length 84 [2018-01-31 10:12:24,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:24,655 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 142 transitions. [2018-01-31 10:12:24,655 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-31 10:12:24,655 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 142 transitions. [2018-01-31 10:12:24,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-01-31 10:12:24,656 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:24,656 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:24,656 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation]=== [2018-01-31 10:12:24,656 INFO L82 PathProgramCache]: Analyzing trace with hash -1193884679, now seen corresponding path program 7 times [2018-01-31 10:12:24,656 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:24,656 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:24,656 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:24,656 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:24,657 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:24,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:24,664 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:24,883 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:24,883 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:24,883 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:24,887 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:24,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:24,904 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:25,047 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:25,064 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:25,064 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17] total 33 [2018-01-31 10:12:25,064 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-31 10:12:25,065 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-31 10:12:25,065 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=240, Invalid=816, Unknown=0, NotChecked=0, Total=1056 [2018-01-31 10:12:25,065 INFO L87 Difference]: Start difference. First operand 131 states and 142 transitions. Second operand 33 states. [2018-01-31 10:12:25,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:25,420 INFO L93 Difference]: Finished difference Result 173 states and 188 transitions. [2018-01-31 10:12:25,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-31 10:12:25,423 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 92 [2018-01-31 10:12:25,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:25,424 INFO L225 Difference]: With dead ends: 173 [2018-01-31 10:12:25,424 INFO L226 Difference]: Without dead ends: 144 [2018-01-31 10:12:25,424 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 124 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 547 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=611, Invalid=1551, Unknown=0, NotChecked=0, Total=2162 [2018-01-31 10:12:25,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-01-31 10:12:25,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 139. [2018-01-31 10:12:25,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-01-31 10:12:25,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 150 transitions. [2018-01-31 10:12:25,427 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 150 transitions. Word has length 92 [2018-01-31 10:12:25,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:25,427 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 150 transitions. [2018-01-31 10:12:25,427 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-31 10:12:25,427 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 150 transitions. [2018-01-31 10:12:25,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-01-31 10:12:25,428 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:25,428 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:25,428 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation]=== [2018-01-31 10:12:25,428 INFO L82 PathProgramCache]: Analyzing trace with hash 1977646119, now seen corresponding path program 8 times [2018-01-31 10:12:25,428 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:25,428 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:25,429 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:25,429 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:12:25,429 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:25,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:12:25,437 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:12:25,659 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:25,660 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:12:25,660 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:12:25,669 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:12:25,680 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:25,688 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:12:25,689 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:12:25,691 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:12:25,885 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:12:25,904 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:12:25,904 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19] total 37 [2018-01-31 10:12:25,904 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-31 10:12:25,905 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-31 10:12:25,905 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=297, Invalid=1035, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:12:25,905 INFO L87 Difference]: Start difference. First operand 139 states and 150 transitions. Second operand 37 states. [2018-01-31 10:12:26,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:12:26,272 INFO L93 Difference]: Finished difference Result 176 states and 191 transitions. [2018-01-31 10:12:26,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-01-31 10:12:26,273 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 100 [2018-01-31 10:12:26,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:12:26,273 INFO L225 Difference]: With dead ends: 176 [2018-01-31 10:12:26,273 INFO L226 Difference]: Without dead ends: 147 [2018-01-31 10:12:26,274 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 84 SyntacticMatches, 1 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 713 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=769, Invalid=1987, Unknown=0, NotChecked=0, Total=2756 [2018-01-31 10:12:26,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-01-31 10:12:26,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-01-31 10:12:26,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-01-31 10:12:26,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 158 transitions. [2018-01-31 10:12:26,279 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 158 transitions. Word has length 100 [2018-01-31 10:12:26,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:12:26,279 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 158 transitions. [2018-01-31 10:12:26,279 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-31 10:12:26,279 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 158 transitions. [2018-01-31 10:12:26,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-01-31 10:12:26,280 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:12:26,280 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:12:26,280 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation]=== [2018-01-31 10:12:26,280 INFO L82 PathProgramCache]: Analyzing trace with hash -302111147, now seen corresponding path program 9 times [2018-01-31 10:12:26,280 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:12:26,280 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:12:26,281 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:26,281 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:12:26,281 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:12:26,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:12:26,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:12:26,340 INFO L410 BasicCegarLoop]: Counterexample might be feasible [2018-01-31 10:12:26,342 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base] [2018-01-31 10:12:26,342 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,342 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] mainENTRY-->L31: Formula: (and (= (select |v_#valid_10| |v_main_~#x~8.base_3|) 0) (= |v_main_~#x~8.offset_3| 0) (not (= |v_main_~#x~8.base_3| 0)) (= |v_#valid_9| (store |v_#valid_10| |v_main_~#x~8.base_3| 1)) (= |v_#length_3| (store |v_#length_4| |v_main_~#x~8.base_3| 40))) InVars {#length=|v_#length_4|, #valid=|v_#valid_10|} OutVars{#length=|v_#length_3|, main_~#x~8.base=|v_main_~#x~8.base_3|, main_~#x~8.offset=|v_main_~#x~8.offset_3|, #valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid, #length, main_~#x~8.base, main_~#x~8.offset] [2018-01-31 10:12:26,342 INFO L84 mationBacktranslator]: Skipped ATE [433] [433] L31-->L32: Formula: true InVars {} OutVars{#memory_int=|v_#memory_int_3|} AuxVars[] AssignedVars[#memory_int] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [439] [439] L32-->L34: Formula: true InVars {} OutVars{main_~temp~8=v_main_~temp~8_1} AuxVars[] AssignedVars[main_~temp~8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [443] [443] L34-->L35: Formula: true InVars {} OutVars{main_~ret~8=v_main_~ret~8_1} AuxVars[] AssignedVars[main_~ret~8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L35-->L36: Formula: true InVars {} OutVars{main_~ret2~8=v_main_~ret2~8_1} AuxVars[] AssignedVars[main_~ret2~8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [451] [451] L36-->L38: Formula: true InVars {} OutVars{main_~ret5~8=v_main_~ret5~8_1} AuxVars[] AssignedVars[main_~ret5~8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L38-->L38': Formula: true InVars {} OutVars{main_#t~ret5=|v_main_#t~ret5_1|} AuxVars[] AssignedVars[main_#t~ret5] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L38'-->L38'': Formula: (and (<= 0 (+ |v_main_#t~ret5_2| 2147483648)) (<= |v_main_#t~ret5_2| 2147483647)) InVars {main_#t~ret5=|v_main_#t~ret5_2|} OutVars{main_#t~ret5=|v_main_#t~ret5_2|} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [473] [473] L38''-->L38''': Formula: (= v_main_~ret~8_2 |v_main_#t~ret5_3|) InVars {main_#t~ret5=|v_main_#t~ret5_3|} OutVars{main_~ret~8=v_main_~ret~8_2, main_#t~ret5=|v_main_#t~ret5_3|} AuxVars[] AssignedVars[main_~ret~8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [479] [479] L38'''-->L40: Formula: true InVars {} OutVars{main_#t~ret5=|v_main_#t~ret5_4|} AuxVars[] AssignedVars[main_#t~ret5] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [485] [485] L40-->L40': Formula: (= (select (select |v_#memory_int_part_locs_30_locs_30_3| |v_main_~#x~8.base_6|) |v_main_~#x~8.offset_6|) |v_main_#t~mem6_1|) InVars {#memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_3|, main_~#x~8.base=|v_main_~#x~8.base_6|, main_~#x~8.offset=|v_main_~#x~8.offset_6|} OutVars{main_#t~mem6=|v_main_#t~mem6_1|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_3|, main_~#x~8.base=|v_main_~#x~8.base_6|, main_~#x~8.offset=|v_main_~#x~8.offset_6|} AuxVars[] AssignedVars[main_#t~mem6] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [491] [491] L40'-->L40'': Formula: (= v_main_~temp~8_2 |v_main_#t~mem6_2|) InVars {main_#t~mem6=|v_main_#t~mem6_2|} OutVars{main_~temp~8=v_main_~temp~8_2, main_#t~mem6=|v_main_#t~mem6_2|} AuxVars[] AssignedVars[main_~temp~8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [497] [497] L40''-->L40''': Formula: true InVars {} OutVars{main_#t~mem6=|v_main_#t~mem6_3|} AuxVars[] AssignedVars[main_#t~mem6] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [503] [503] L40'''-->L40'''': Formula: (= |v_main_#t~mem8_1| (select (select |v_#memory_int_part_locs_30_locs_92_3| |v_main_~#x~8.base_7|) (+ |v_main_~#x~8.offset_7| 4))) InVars {#memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_3|, main_~#x~8.base=|v_main_~#x~8.base_7|, main_~#x~8.offset=|v_main_~#x~8.offset_7|} OutVars{main_#t~mem8=|v_main_#t~mem8_1|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_3|, main_~#x~8.base=|v_main_~#x~8.base_7|, main_~#x~8.offset=|v_main_~#x~8.offset_7|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:12:26,343 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L40''''-->L40''''': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_4| |v_#memory_int_part_locs_30_locs_30_5|) (= |v_#memory_int_part_locs_30_locs_92_4| |v_#memory_int_part_locs_30_locs_92_5|) (= |v_#memory_int_part_locs_54_locs_92_3| (store |v_#memory_int_part_locs_54_locs_92_4| |v_main_~#x~8.base_8| (store (select |v_#memory_int_part_locs_30_locs_92_5| |v_main_~#x~8.base_8|) |v_main_~#x~8.offset_8| |v_main_#t~mem8_2|))) (= |v_#memory_int_part_locs_33_locs_30_3| |v_#memory_int_part_locs_33_locs_30_4|) (= |v_#memory_int_part_locs_33_locs_92_3| |v_#memory_int_part_locs_33_locs_92_4|) (= |v_#memory_int_part_locs_54_locs_30_3| (store |v_#memory_int_part_locs_54_locs_30_4| |v_main_~#x~8.base_8| (select |v_#memory_int_part_locs_30_locs_30_5| |v_main_~#x~8.base_8|)))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_4|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_5|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_4|, main_#t~mem8=|v_main_#t~mem8_2|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_4|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_5|, main_~#x~8.base=|v_main_~#x~8.base_8|, main_~#x~8.offset=|v_main_~#x~8.offset_8|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_4|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_3|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_4|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_3|, #memory_int=|v_#memory_int_7|, main_#t~mem8=|v_main_#t~mem8_2|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_3|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_4|, main_~#x~8.base=|v_main_~#x~8.base_8|, main_~#x~8.offset=|v_main_~#x~8.offset_8|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_3|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [519] [519] L40'''''-->L40'''''': Formula: true InVars {} OutVars{main_#t~mem8=|v_main_#t~mem8_3|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [529] [529] L40''''''-->L40''''''': Formula: (and (= |v_#memory_int_part_locs_33_locs_92_5| |v_#memory_int_part_locs_33_locs_92_6|) (= |v_#memory_int_part_locs_30_locs_30_6| |v_#memory_int_part_locs_30_locs_30_7|) (= |v_#memory_int_part_locs_54_locs_92_5| (store |v_#memory_int_part_locs_54_locs_92_6| |v_main_~#x~8.base_9| (store (select |v_#memory_int_part_locs_54_locs_92_6| |v_main_~#x~8.base_9|) (+ |v_main_~#x~8.offset_9| 4) v_main_~temp~8_3))) (= |v_#memory_int_part_locs_54_locs_30_5| (store |v_#memory_int_part_locs_54_locs_30_6| |v_main_~#x~8.base_9| (select |v_#memory_int_part_locs_54_locs_30_6| |v_main_~#x~8.base_9|))) (= |v_#memory_int_part_locs_30_locs_92_6| |v_#memory_int_part_locs_30_locs_92_7|) (= |v_#memory_int_part_locs_33_locs_30_5| |v_#memory_int_part_locs_33_locs_30_6|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_6|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_7|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_6|, main_~temp~8=v_main_~temp~8_3, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_6|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_7|, main_~#x~8.base=|v_main_~#x~8.base_9|, main_~#x~8.offset=|v_main_~#x~8.offset_9|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_6|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_5|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_6|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_5|, #memory_int=|v_#memory_int_9|, main_~temp~8=v_main_~temp~8_3, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_5|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_6|, main_~#x~8.base=|v_main_~#x~8.base_9|, main_~#x~8.offset=|v_main_~#x~8.offset_9|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_5|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [537] [537] L40'''''''-->L41: Formula: true InVars {} OutVars{main_#t~ret10=|v_main_#t~ret10_1|} AuxVars[] AssignedVars[main_#t~ret10] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L41-->L41': Formula: (and (<= |v_main_#t~ret10_2| 2147483647) (<= 0 (+ |v_main_#t~ret10_2| 2147483648))) InVars {main_#t~ret10=|v_main_#t~ret10_2|} OutVars{main_#t~ret10=|v_main_#t~ret10_2|} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L41'-->L41'': Formula: (= v_main_~ret2~8_2 |v_main_#t~ret10_3|) InVars {main_#t~ret10=|v_main_#t~ret10_3|} OutVars{main_#t~ret10=|v_main_#t~ret10_3|, main_~ret2~8=v_main_~ret2~8_2} AuxVars[] AssignedVars[main_~ret2~8] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [559] [559] L41''-->L42: Formula: true InVars {} OutVars{main_#t~ret10=|v_main_#t~ret10_4|} AuxVars[] AssignedVars[main_#t~ret10] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L42-->L42': Formula: (= (select (select |v_#memory_int_part_locs_54_locs_92_8| |v_main_~#x~8.base_11|) |v_main_~#x~8.offset_11|) |v_main_#t~mem11_1|) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_8|, main_~#x~8.base=|v_main_~#x~8.base_11|, main_~#x~8.offset=|v_main_~#x~8.offset_11|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_8|, main_~#x~8.base=|v_main_~#x~8.base_11|, main_~#x~8.offset=|v_main_~#x~8.offset_11|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L42'-->L42'': Formula: (= v_main_~temp~8_4 |v_main_#t~mem11_2|) InVars {main_#t~mem11=|v_main_#t~mem11_2|} OutVars{main_~temp~8=v_main_~temp~8_4, main_#t~mem11=|v_main_#t~mem11_2|} AuxVars[] AssignedVars[main_~temp~8] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [577] [577] L42''-->L43: Formula: true InVars {} OutVars{main_#t~mem11=|v_main_#t~mem11_3|} AuxVars[] AssignedVars[main_#t~mem11] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [581] [581] L43-->L43'''''': Formula: (= v_main_~i~9_1 0) InVars {} OutVars{main_~i~9=v_main_~i~9_1} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,345 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,346 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,347 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,347 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,347 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,347 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,347 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,351 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,351 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,351 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,351 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,352 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,353 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [593] [593] L43'-->L44: Formula: (< v_main_~i~9_3 9) InVars {main_~i~9=v_main_~i~9_3} OutVars{main_~i~9=v_main_~i~9_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [597] [597] L44-->L44': Formula: (= |v_main_#t~mem14_1| (select (select |v_#memory_int_part_locs_54_locs_92_11| |v_main_~#x~8.base_12|) (+ |v_main_~#x~8.offset_12| (* 4 v_main_~i~9_4) 4))) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_11|, main_~i~9=v_main_~i~9_4, main_#t~mem14=|v_main_#t~mem14_1|, main_~#x~8.base=|v_main_~#x~8.base_12|, main_~#x~8.offset=|v_main_~#x~8.offset_12|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,355 INFO L84 mationBacktranslator]: Skipped ATE [603] [603] L44'-->L44'': Formula: (and (= |v_#memory_int_part_locs_30_locs_30_10| |v_#memory_int_part_locs_30_locs_30_11|) (= |v_#memory_int_part_locs_33_locs_30_9| |v_#memory_int_part_locs_33_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13| (select |v_#memory_int_part_locs_54_locs_30_9| |v_main_~#x~8.base_13|)) |v_#memory_int_part_locs_54_locs_30_10|) (= (store |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13| (store (select |v_#memory_int_part_locs_54_locs_92_12| |v_main_~#x~8.base_13|) (+ |v_main_~#x~8.offset_13| (* 4 v_main_~i~9_5)) |v_main_#t~mem14_2|)) |v_#memory_int_part_locs_54_locs_92_13|) (= |v_#memory_int_part_locs_33_locs_92_9| |v_#memory_int_part_locs_33_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_92_10| |v_#memory_int_part_locs_30_locs_92_11|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_12|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_10|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_9|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_9|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_10|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_9|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_13|, main_~i~9=v_main_~i~9_5, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_11|, main_#t~mem14=|v_main_#t~mem14_2|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_10|, #memory_int=|v_#memory_int_13|, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_10|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_11|, main_~#x~8.base=|v_main_~#x~8.base_13|, main_~#x~8.offset=|v_main_~#x~8.offset_13|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_10|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [605] [605] L44''-->L43''': Formula: true InVars {} OutVars{main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem14] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [607] [607] L43'''-->L43'''': Formula: (= |v_main_#t~post12_1| v_main_~i~9_6) InVars {main_~i~9=v_main_~i~9_6} OutVars{main_~i~9=v_main_~i~9_6, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [609] [609] L43''''-->L43''''': Formula: (= v_main_~i~9_7 (+ |v_main_#t~post12_2| 1)) InVars {main_#t~post12=|v_main_#t~post12_2|} OutVars{main_~i~9=v_main_~i~9_7, main_#t~post12=|v_main_#t~post12_2|} AuxVars[] AssignedVars[main_~i~9] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [611] [611] L43'''''-->L43'''''': Formula: true InVars {} OutVars{main_#t~post12=|v_main_#t~post12_3|} AuxVars[] AssignedVars[main_#t~post12] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [585] [585] L43''''''-->L43': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [591] [591] L43'-->L43''''''': Formula: (not (< v_main_~i~9_2 9)) InVars {main_~i~9=v_main_~i~9_2} OutVars{main_~i~9=v_main_~i~9_2} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [595] [595] L43'''''''-->L46: Formula: (and (= |v_#memory_int_part_locs_33_locs_30_7| |v_#memory_int_part_locs_33_locs_30_8|) (= |v_#memory_int_part_locs_30_locs_92_8| |v_#memory_int_part_locs_30_locs_92_9|) (= (store |v_#memory_int_part_locs_54_locs_30_7| |v_main_~#x~8.base_14| (select |v_#memory_int_part_locs_54_locs_30_7| |v_main_~#x~8.base_14|)) |v_#memory_int_part_locs_54_locs_30_8|) (= |v_#memory_int_part_locs_33_locs_92_7| |v_#memory_int_part_locs_33_locs_92_8|) (= (store |v_#memory_int_part_locs_54_locs_92_9| |v_main_~#x~8.base_14| (store (select |v_#memory_int_part_locs_54_locs_92_9| |v_main_~#x~8.base_14|) (+ |v_main_~#x~8.offset_14| 36) v_main_~temp~8_5)) |v_#memory_int_part_locs_54_locs_92_10|) (= |v_#memory_int_part_locs_30_locs_30_8| |v_#memory_int_part_locs_30_locs_30_9|)) InVars {#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_9|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_8|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_7|, main_~temp~8=v_main_~temp~8_5, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_7|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_8|, main_~#x~8.base=|v_main_~#x~8.base_14|, main_~#x~8.offset=|v_main_~#x~8.offset_14|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_7|} OutVars{#memory_int_part_locs_54_locs_92=|v_#memory_int_part_locs_54_locs_92_10|, #memory_int_part_locs_30_locs_92=|v_#memory_int_part_locs_30_locs_92_9|, #memory_int_part_locs_33_locs_30=|v_#memory_int_part_locs_33_locs_30_8|, #memory_int=|v_#memory_int_15|, main_~temp~8=v_main_~temp~8_5, #memory_int_part_locs_54_locs_30=|v_#memory_int_part_locs_54_locs_30_8|, #memory_int_part_locs_30_locs_30=|v_#memory_int_part_locs_30_locs_30_9|, main_~#x~8.base=|v_main_~#x~8.base_14|, main_~#x~8.offset=|v_main_~#x~8.offset_14|, #memory_int_part_locs_33_locs_92=|v_#memory_int_part_locs_33_locs_92_8|} AuxVars[] AssignedVars[#memory_int_part_locs_54_locs_92, #memory_int_part_locs_30_locs_92, #memory_int_part_locs_33_locs_30, #memory_int, #memory_int_part_locs_54_locs_30, #memory_int_part_locs_30_locs_30, #memory_int_part_locs_33_locs_92] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [599] [599] L46-->L47: Formula: true InVars {} OutVars{main_#t~ret16=|v_main_#t~ret16_1|} AuxVars[] AssignedVars[main_#t~ret16] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [551] [551] L47-->L47': Formula: (and (<= 0 (+ |v_main_#t~ret16_2| 2147483648)) (<= |v_main_#t~ret16_2| 2147483647)) InVars {main_#t~ret16=|v_main_#t~ret16_2|} OutVars{main_#t~ret16=|v_main_#t~ret16_2|} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L47'-->L47'': Formula: (= v_main_~ret5~8_2 |v_main_#t~ret16_3|) InVars {main_#t~ret16=|v_main_#t~ret16_3|} OutVars{main_#t~ret16=|v_main_#t~ret16_3|, main_~ret5~8=v_main_~ret5~8_2} AuxVars[] AssignedVars[main_~ret5~8] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [561] [561] L47''-->L49: Formula: true InVars {} OutVars{main_#t~ret16=|v_main_#t~ret16_4|} AuxVars[] AssignedVars[main_#t~ret16] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L49-->L50: Formula: (or (not (= v_main_~ret2~8_3 v_main_~ret~8_3)) (not (= v_main_~ret5~8_3 v_main_~ret~8_3))) InVars {main_~ret5~8=v_main_~ret5~8_3, main_~ret~8=v_main_~ret~8_3, main_~ret2~8=v_main_~ret2~8_3} OutVars{main_~ret5~8=v_main_~ret5~8_3, main_~ret~8=v_main_~ret~8_3, main_~ret2~8=v_main_~ret2~8_3} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,356 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L50-->mainErr0AssertViolation: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:12:26,360 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:12:26 BasicIcfg [2018-01-31 10:12:26,360 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-31 10:12:26,360 INFO L168 Benchmark]: Toolchain (without parser) took 14285.18 ms. Allocated memory was 150.5 MB in the beginning and 1.0 GB in the end (delta: 860.4 MB). Free memory was 115.2 MB in the beginning and 499.1 MB in the end (delta: -383.9 MB). Peak memory consumption was 476.5 MB. Max. memory is 5.3 GB. [2018-01-31 10:12:26,360 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 150.5 MB. Free memory is still 120.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:12:26,360 INFO L168 Benchmark]: CACSL2BoogieTranslator took 130.92 ms. Allocated memory is still 150.5 MB. Free memory was 115.0 MB in the beginning and 106.2 MB in the end (delta: 8.8 MB). Peak memory consumption was 8.8 MB. Max. memory is 5.3 GB. [2018-01-31 10:12:26,361 INFO L168 Benchmark]: Boogie Preprocessor took 20.82 ms. Allocated memory is still 150.5 MB. Free memory was 106.2 MB in the beginning and 104.5 MB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 5.3 GB. [2018-01-31 10:12:26,361 INFO L168 Benchmark]: RCFGBuilder took 462.85 ms. Allocated memory is still 150.5 MB. Free memory was 104.5 MB in the beginning and 84.5 MB in the end (delta: 19.9 MB). Peak memory consumption was 19.9 MB. Max. memory is 5.3 GB. [2018-01-31 10:12:26,361 INFO L168 Benchmark]: IcfgTransformer took 7346.98 ms. Allocated memory was 150.5 MB in the beginning and 855.1 MB in the end (delta: 704.6 MB). Free memory was 84.5 MB in the beginning and 280.7 MB in the end (delta: -196.1 MB). Peak memory consumption was 508.5 MB. Max. memory is 5.3 GB. [2018-01-31 10:12:26,361 INFO L168 Benchmark]: TraceAbstraction took 6321.17 ms. Allocated memory was 855.1 MB in the beginning and 1.0 GB in the end (delta: 155.7 MB). Free memory was 280.7 MB in the beginning and 499.1 MB in the end (delta: -218.4 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:12:26,361 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 150.5 MB. Free memory is still 120.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 130.92 ms. Allocated memory is still 150.5 MB. Free memory was 115.0 MB in the beginning and 106.2 MB in the end (delta: 8.8 MB). Peak memory consumption was 8.8 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 20.82 ms. Allocated memory is still 150.5 MB. Free memory was 106.2 MB in the beginning and 104.5 MB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 5.3 GB. * RCFGBuilder took 462.85 ms. Allocated memory is still 150.5 MB. Free memory was 104.5 MB in the beginning and 84.5 MB in the end (delta: 19.9 MB). Peak memory consumption was 19.9 MB. Max. memory is 5.3 GB. * IcfgTransformer took 7346.98 ms. Allocated memory was 150.5 MB in the beginning and 855.1 MB in the end (delta: 704.6 MB). Free memory was 84.5 MB in the beginning and 280.7 MB in the end (delta: -196.1 MB). Peak memory consumption was 508.5 MB. Max. memory is 5.3 GB. * TraceAbstraction took 6321.17 ms. Allocated memory was 855.1 MB in the beginning and 1.0 GB in the end (delta: 155.7 MB). Free memory was 280.7 MB in the beginning and 499.1 MB in the end (delta: -218.4 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 87 LocStat_MAX_WEQGRAPH_SIZE : 2 LocStat_MAX_SIZEOF_WEQEDGELABEL : 1 LocStat_NO_SUPPORTING_EQUALITIES : 1657 LocStat_NO_SUPPORTING_DISEQUALITIES : 2978 LocStat_NO_DISJUNCTIONS : -174 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 118 TransStat_MAX_WEQGRAPH_SIZE : 2 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 175 TransStat_NO_SUPPORTING_DISEQUALITIES : 7 TransStat_NO_DISJUNCTIONS : 116 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.307602 RENAME_VARIABLES(MILLISECONDS) : 0.264847 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.292436 PROJECTAWAY(MILLISECONDS) : 0.092364 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.040382 DISJOIN(MILLISECONDS) : 0.561082 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.279583 ADD_EQUALITY(MILLISECONDS) : 0.005224 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.002502 #CONJOIN_DISJUNCTIVE : 1043 #RENAME_VARIABLES : 2297 #UNFREEZE : 0 #CONJOIN : 1493 #PROJECTAWAY : 1424 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 225 #RENAME_VARIABLES_DISJUNCTIVE : 2331 #ADD_EQUALITY : 180 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 6 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 6 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 3 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 6 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 2 COUNT_ARRAY_READS for [#memory_int] : 10 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 50]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: - StatisticsResult: Ultimate Automizer benchmark data CFG has 5 procedures, 88 locations, 1 error locations. UNSAFE Result, 6.2s OverallTime, 11 OverallIterations, 10 TraceHistogramMax, 2.5s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 831 SDtfs, 876 SDslu, 3281 SDs, 0 SdLazy, 899 SolverSat, 144 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 759 GetRequests, 508 SyntacticMatches, 9 SemanticMatches, 242 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2288 ImplicationChecksByTransitivity, 3.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=147occurred in iteration=10, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 10 MinimizatonAttempts, 40 StatesRemovedByMinimization, 8 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 2.7s InterpolantComputationTime, 1331 NumberOfCodeBlocks, 1326 NumberOfCodeBlocksAsserted, 35 NumberOfCheckSat, 1205 ConstructedInterpolants, 0 QuantifiedInterpolants, 352545 SizeOfPredicates, 81 NumberOfNonLiveVariables, 1173 ConjunctsInSsa, 90 ConjunctsInUnsatCore, 18 InterpolantComputations, 2 PerfectInterpolantSequences, 0/1488 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum10_false-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-31_10-12-26-366.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum10_false-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-31_10-12-26-366.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum10_false-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-31_10-12-26-366.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum10_false-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-31_10-12-26-366.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/rangesum10_false-unreach-call_true-termination.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-31_10-12-26-366.csv Received shutdown request...