java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/reducercommutativity/sep10_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-5f7ec6e-m [2018-01-31 10:19:14,862 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-31 10:19:14,863 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-31 10:19:14,873 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-31 10:19:14,874 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-31 10:19:14,874 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-31 10:19:14,875 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-31 10:19:14,876 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-31 10:19:14,877 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-31 10:19:14,877 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-31 10:19:14,878 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-31 10:19:14,878 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-31 10:19:14,879 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-31 10:19:14,879 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-31 10:19:14,880 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-31 10:19:14,881 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-31 10:19:14,882 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-31 10:19:14,883 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-31 10:19:14,884 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-31 10:19:14,884 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-31 10:19:14,885 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-31 10:19:14,886 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-31 10:19:14,886 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-31 10:19:14,886 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-31 10:19:14,887 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-31 10:19:14,887 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-31 10:19:14,888 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-31 10:19:14,888 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-31 10:19:14,888 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-31 10:19:14,888 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-31 10:19:14,888 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-31 10:19:14,889 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-31 10:19:14,894 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-31 10:19:14,894 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-31 10:19:14,894 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-31 10:19:14,894 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-31 10:19:14,895 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-31 10:19:14,895 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-31 10:19:14,895 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-31 10:19:14,895 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-31 10:19:14,895 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-31 10:19:14,895 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-31 10:19:14,895 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-31 10:19:14,895 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-31 10:19:14,896 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-31 10:19:14,896 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:19:14,897 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-31 10:19:14,897 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-31 10:19:14,898 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-31 10:19:14,898 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-31 10:19:14,898 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-31 10:19:14,898 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-31 10:19:14,917 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-31 10:19:14,923 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-31 10:19:14,925 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-31 10:19:14,926 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-31 10:19:14,926 INFO L276 PluginConnector]: CDTParser initialized [2018-01-31 10:19:14,926 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sep10_true-unreach-call.i [2018-01-31 10:19:14,989 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-31 10:19:14,990 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-31 10:19:14,991 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-31 10:19:14,991 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-31 10:19:14,994 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-31 10:19:14,995 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:19:14" (1/1) ... [2018-01-31 10:19:14,996 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3bb441a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:14, skipping insertion in model container [2018-01-31 10:19:14,996 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:19:14" (1/1) ... [2018-01-31 10:19:15,005 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:19:15,015 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:19:15,086 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:19:15,098 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:19:15,102 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15 WrapperNode [2018-01-31 10:19:15,102 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-31 10:19:15,103 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-31 10:19:15,103 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-31 10:19:15,103 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-31 10:19:15,111 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,111 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,117 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,117 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,119 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,121 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,121 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,122 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-31 10:19:15,123 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-31 10:19:15,123 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-31 10:19:15,123 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-31 10:19:15,123 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:19:15,166 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-31 10:19:15,166 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-31 10:19:15,166 INFO L136 BoogieDeclarations]: Found implementation of procedure sep [2018-01-31 10:19:15,166 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-31 10:19:15,166 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure sep [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-31 10:19:15,167 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-31 10:19:15,543 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-31 10:19:15,543 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:19:15 BoogieIcfgContainer [2018-01-31 10:19:15,543 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-31 10:19:15,543 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-31 10:19:15,543 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-31 10:19:15,544 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-31 10:19:15,546 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:19:15" (1/1) ... [2018-01-31 10:19:15,551 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-01-31 10:19:15,551 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-01-31 10:19:15,551 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing [2018-01-31 10:19:15,576 INFO L162 apSepIcfgTransformer]: finished StoreIndexFreezer, created 13 freeze vars and freeze var literals (each corresponds to one heap write) [2018-01-31 10:19:15,593 INFO L221 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-01-31 10:19:15,626 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-31 10:20:00,832 INFO L314 AbstractInterpreter]: Visited 97 different actions 931 times. Merged at 71 different actions 448 times. Widened at 1 different actions 1 times. Found 80 fixpoints after 14 different actions. Largest state had 68 variables. [2018-01-31 10:20:00,833 INFO L229 apSepIcfgTransformer]: finished equality analysis [2018-01-31 10:20:00,839 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 10 [2018-01-31 10:20:00,840 INFO L241 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-01-31 10:20:00,840 INFO L242 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-01-31 10:20:00,840 INFO L244 apSepIcfgTransformer]: select infos: Set: ((select |v_#memory_int_4| |v_main_~#x~5.base_2|), at (SUMMARY for call write~int(#t~nondet5, ~#x~5.base, ~#x~5.offset + ~i~6 * 4, 4); srcloc: L27')) ((select (select |v_#memory_int_6| |v_main_~#x~5.base_5|) (+ |v_main_~#x~5.offset_5| 4)), at (SUMMARY for call #t~mem10 := read~int(~#x~5.base, ~#x~5.offset + 4, 4); srcloc: L32''')) ((select (select |v_#memory_int_11| |v_main_~#x~5.base_9|) |v_main_~#x~5.offset_9|), at (SUMMARY for call #t~mem13 := read~int(~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L34)) ((select (select |v_#memory_int_5| |v_main_~#x~5.base_4|) |v_main_~#x~5.offset_4|), at (SUMMARY for call #t~mem8 := read~int(~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L32)) ((select |v_#memory_int_14| |v_main_~#x~5.base_11|), at (SUMMARY for call write~int(#t~mem16, ~#x~5.base, ~#x~5.offset + ~i~7 * 4, 4); srcloc: L36')) ((select (select |v_#memory_int_12| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)), at (SUMMARY for call #t~mem16 := read~int(~#x~5.base, ~#x~5.offset + (~i~7 + 1) * 4, 4); srcloc: L36)) ((select |v_#memory_int_10| |v_main_~#x~5.base_7|), at (SUMMARY for call write~int(~temp~5, ~#x~5.base, ~#x~5.offset + 4, 4); srcloc: L32'''''')) ((select (select |v_#memory_int_17| v_sep_~x.base_1) (+ v_sep_~x.offset_1 (* 4 v_sep_~i~4_2))), at (SUMMARY for call #t~mem1 := read~int(~x.base, ~x.offset + ~i~4 * 4, 4); srcloc: L9)) ((select |v_#memory_int_8| |v_main_~#x~5.base_6|), at (SUMMARY for call write~int(#t~mem10, ~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L32'''')) ((select |v_#memory_int_16| |v_main_~#x~5.base_12|), at (SUMMARY for call write~int(~temp~5, ~#x~5.base, ~#x~5.offset + 36, 4); srcloc: L35''''''')) [2018-01-31 10:20:00,858 INFO L547 PartitionManager]: partitioning result: [2018-01-31 10:20:00,859 INFO L552 PartitionManager]: location blocks for array group [#memory_int] [2018-01-31 10:20:00,859 INFO L562 PartitionManager]: at dimension 0 [2018-01-31 10:20:00,859 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 5 [2018-01-31 10:20:00,859 INFO L564 PartitionManager]: # location blocks :1 [2018-01-31 10:20:00,859 INFO L562 PartitionManager]: at dimension 1 [2018-01-31 10:20:00,859 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 5 [2018-01-31 10:20:00,859 INFO L564 PartitionManager]: # location blocks :1 [2018-01-31 10:20:00,860 INFO L86 ransitionTransformer]: executing heap partitioning transformation [2018-01-31 10:20:00,872 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:20:00 BasicIcfg [2018-01-31 10:20:00,872 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-31 10:20:00,873 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-31 10:20:00,873 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-31 10:20:00,875 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-31 10:20:00,875 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 31.01 10:19:14" (1/4) ... [2018-01-31 10:20:00,875 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a489414 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:20:00, skipping insertion in model container [2018-01-31 10:20:00,880 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:19:15" (2/4) ... [2018-01-31 10:20:00,880 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a489414 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:20:00, skipping insertion in model container [2018-01-31 10:20:00,880 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:19:15" (3/4) ... [2018-01-31 10:20:00,881 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a489414 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:20:00, skipping insertion in model container [2018-01-31 10:20:00,881 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:20:00" (4/4) ... [2018-01-31 10:20:00,881 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg [2018-01-31 10:20:00,886 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-31 10:20:00,891 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-31 10:20:00,976 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-31 10:20:00,976 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-31 10:20:00,976 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-31 10:20:00,977 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-31 10:20:00,977 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-31 10:20:00,977 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-31 10:20:00,977 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-31 10:20:00,977 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-31 10:20:00,977 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-31 10:20:00,984 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states. [2018-01-31 10:20:00,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-31 10:20:00,988 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:00,989 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:00,989 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation]=== [2018-01-31 10:20:00,991 INFO L82 PathProgramCache]: Analyzing trace with hash -1929961395, now seen corresponding path program 1 times [2018-01-31 10:20:00,992 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:00,992 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:01,020 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,021 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:01,021 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:01,044 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:01,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:20:01,071 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:20:01,071 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-31 10:20:01,072 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-31 10:20:01,081 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-31 10:20:01,081 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:20:01,083 INFO L87 Difference]: Start difference. First operand 83 states. Second operand 2 states. [2018-01-31 10:20:01,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:01,100 INFO L93 Difference]: Finished difference Result 146 states and 173 transitions. [2018-01-31 10:20:01,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-31 10:20:01,102 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 36 [2018-01-31 10:20:01,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:01,108 INFO L225 Difference]: With dead ends: 146 [2018-01-31 10:20:01,108 INFO L226 Difference]: Without dead ends: 76 [2018-01-31 10:20:01,110 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:20:01,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-01-31 10:20:01,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2018-01-31 10:20:01,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-01-31 10:20:01,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 85 transitions. [2018-01-31 10:20:01,138 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 85 transitions. Word has length 36 [2018-01-31 10:20:01,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:01,138 INFO L432 AbstractCegarLoop]: Abstraction has 76 states and 85 transitions. [2018-01-31 10:20:01,138 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-31 10:20:01,138 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 85 transitions. [2018-01-31 10:20:01,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-31 10:20:01,140 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:01,140 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:01,140 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation]=== [2018-01-31 10:20:01,140 INFO L82 PathProgramCache]: Analyzing trace with hash -2081485741, now seen corresponding path program 1 times [2018-01-31 10:20:01,140 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:01,140 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:01,143 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,143 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:01,143 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:01,155 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:01,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:20:01,215 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:20:01,216 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-31 10:20:01,217 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-31 10:20:01,217 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-31 10:20:01,217 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-31 10:20:01,217 INFO L87 Difference]: Start difference. First operand 76 states and 85 transitions. Second operand 3 states. [2018-01-31 10:20:01,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:01,325 INFO L93 Difference]: Finished difference Result 139 states and 156 transitions. [2018-01-31 10:20:01,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-31 10:20:01,326 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-01-31 10:20:01,326 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:01,327 INFO L225 Difference]: With dead ends: 139 [2018-01-31 10:20:01,327 INFO L226 Difference]: Without dead ends: 83 [2018-01-31 10:20:01,328 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-31 10:20:01,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-31 10:20:01,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 78. [2018-01-31 10:20:01,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-01-31 10:20:01,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 87 transitions. [2018-01-31 10:20:01,334 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 87 transitions. Word has length 38 [2018-01-31 10:20:01,334 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:01,334 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 87 transitions. [2018-01-31 10:20:01,334 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-31 10:20:01,334 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 87 transitions. [2018-01-31 10:20:01,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-31 10:20:01,335 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:01,335 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:01,335 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation]=== [2018-01-31 10:20:01,335 INFO L82 PathProgramCache]: Analyzing trace with hash -351365841, now seen corresponding path program 1 times [2018-01-31 10:20:01,335 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:01,335 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:01,336 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,336 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:01,336 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:01,347 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:01,407 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:20:01,407 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:01,407 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-01-31 10:20:01,422 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:01,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:01,448 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:01,492 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-31 10:20:01,510 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-31 10:20:01,510 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-01-31 10:20:01,510 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-31 10:20:01,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-31 10:20:01,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-01-31 10:20:01,511 INFO L87 Difference]: Start difference. First operand 78 states and 87 transitions. Second operand 6 states. [2018-01-31 10:20:01,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:01,742 INFO L93 Difference]: Finished difference Result 154 states and 172 transitions. [2018-01-31 10:20:01,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-31 10:20:01,743 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-01-31 10:20:01,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:01,743 INFO L225 Difference]: With dead ends: 154 [2018-01-31 10:20:01,743 INFO L226 Difference]: Without dead ends: 98 [2018-01-31 10:20:01,744 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-01-31 10:20:01,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-01-31 10:20:01,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 88. [2018-01-31 10:20:01,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-31 10:20:01,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 97 transitions. [2018-01-31 10:20:01,752 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 97 transitions. Word has length 46 [2018-01-31 10:20:01,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:01,752 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 97 transitions. [2018-01-31 10:20:01,752 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-31 10:20:01,753 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 97 transitions. [2018-01-31 10:20:01,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-31 10:20:01,753 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:01,754 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:01,754 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation]=== [2018-01-31 10:20:01,754 INFO L82 PathProgramCache]: Analyzing trace with hash -577067975, now seen corresponding path program 1 times [2018-01-31 10:20:01,754 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:01,754 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:01,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,755 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:01,755 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:01,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:01,765 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:01,858 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-31 10:20:01,858 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:01,858 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:01,864 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:01,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:01,895 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:01,970 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-31 10:20:01,987 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:01,988 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 7] total 10 [2018-01-31 10:20:01,988 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-31 10:20:01,988 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-31 10:20:01,988 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-01-31 10:20:01,988 INFO L87 Difference]: Start difference. First operand 88 states and 97 transitions. Second operand 10 states. [2018-01-31 10:20:02,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:02,306 INFO L93 Difference]: Finished difference Result 172 states and 190 transitions. [2018-01-31 10:20:02,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-31 10:20:02,307 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 62 [2018-01-31 10:20:02,307 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:02,308 INFO L225 Difference]: With dead ends: 172 [2018-01-31 10:20:02,308 INFO L226 Difference]: Without dead ends: 114 [2018-01-31 10:20:02,308 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=60, Invalid=180, Unknown=0, NotChecked=0, Total=240 [2018-01-31 10:20:02,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-31 10:20:02,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 104. [2018-01-31 10:20:02,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-01-31 10:20:02,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 113 transitions. [2018-01-31 10:20:02,312 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 113 transitions. Word has length 62 [2018-01-31 10:20:02,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:02,312 INFO L432 AbstractCegarLoop]: Abstraction has 104 states and 113 transitions. [2018-01-31 10:20:02,312 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-31 10:20:02,312 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 113 transitions. [2018-01-31 10:20:02,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-31 10:20:02,313 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:02,314 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:02,314 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation]=== [2018-01-31 10:20:02,314 INFO L82 PathProgramCache]: Analyzing trace with hash 1689178435, now seen corresponding path program 2 times [2018-01-31 10:20:02,314 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:02,314 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:02,314 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:02,315 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:02,315 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:02,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:02,329 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:02,458 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-01-31 10:20:02,458 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:02,459 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:02,463 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:20:02,473 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:02,494 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:02,501 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:02,505 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:02,633 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-31 10:20:02,649 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:02,649 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 9] total 14 [2018-01-31 10:20:02,650 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-31 10:20:02,650 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-31 10:20:02,650 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=144, Unknown=0, NotChecked=0, Total=182 [2018-01-31 10:20:02,650 INFO L87 Difference]: Start difference. First operand 104 states and 113 transitions. Second operand 14 states. [2018-01-31 10:20:02,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:02,928 INFO L93 Difference]: Finished difference Result 196 states and 214 transitions. [2018-01-31 10:20:02,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-31 10:20:02,929 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 78 [2018-01-31 10:20:02,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:02,929 INFO L225 Difference]: With dead ends: 196 [2018-01-31 10:20:02,929 INFO L226 Difference]: Without dead ends: 130 [2018-01-31 10:20:02,930 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=432, Unknown=0, NotChecked=0, Total=552 [2018-01-31 10:20:02,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-01-31 10:20:02,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 120. [2018-01-31 10:20:02,933 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-01-31 10:20:02,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-01-31 10:20:02,934 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 78 [2018-01-31 10:20:02,934 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:02,934 INFO L432 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-01-31 10:20:02,934 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-31 10:20:02,934 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-01-31 10:20:02,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-31 10:20:02,936 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:02,936 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:02,936 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation]=== [2018-01-31 10:20:02,936 INFO L82 PathProgramCache]: Analyzing trace with hash 1052580941, now seen corresponding path program 3 times [2018-01-31 10:20:02,936 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:02,936 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:02,937 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:02,937 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:02,937 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:02,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:02,948 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:03,084 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-01-31 10:20:03,084 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:03,084 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:03,090 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:20:03,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:03,105 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:03,108 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:03,117 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:03,127 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:03,129 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:03,212 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:20:03,228 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:03,229 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 18 [2018-01-31 10:20:03,229 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-31 10:20:03,229 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-31 10:20:03,229 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=248, Unknown=0, NotChecked=0, Total=306 [2018-01-31 10:20:03,229 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 18 states. [2018-01-31 10:20:03,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:03,536 INFO L93 Difference]: Finished difference Result 220 states and 238 transitions. [2018-01-31 10:20:03,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-31 10:20:03,536 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 94 [2018-01-31 10:20:03,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:03,537 INFO L225 Difference]: With dead ends: 220 [2018-01-31 10:20:03,537 INFO L226 Difference]: Without dead ends: 146 [2018-01-31 10:20:03,537 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 158 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=200, Invalid=792, Unknown=0, NotChecked=0, Total=992 [2018-01-31 10:20:03,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-01-31 10:20:03,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 136. [2018-01-31 10:20:03,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-01-31 10:20:03,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 145 transitions. [2018-01-31 10:20:03,541 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 145 transitions. Word has length 94 [2018-01-31 10:20:03,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:03,542 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 145 transitions. [2018-01-31 10:20:03,542 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-31 10:20:03,542 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 145 transitions. [2018-01-31 10:20:03,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-31 10:20:03,542 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:03,543 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:03,543 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation]=== [2018-01-31 10:20:03,543 INFO L82 PathProgramCache]: Analyzing trace with hash -1204320937, now seen corresponding path program 4 times [2018-01-31 10:20:03,543 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:03,543 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:03,543 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:03,544 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:03,544 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:03,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:03,555 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:03,659 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:20:03,659 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:03,659 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:03,666 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:20:03,687 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:03,689 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:03,916 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:20:03,933 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:03,933 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 15 [2018-01-31 10:20:03,933 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-31 10:20:03,933 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-31 10:20:03,933 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=147, Unknown=0, NotChecked=0, Total=210 [2018-01-31 10:20:03,933 INFO L87 Difference]: Start difference. First operand 136 states and 145 transitions. Second operand 15 states. [2018-01-31 10:20:04,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:04,052 INFO L93 Difference]: Finished difference Result 231 states and 248 transitions. [2018-01-31 10:20:04,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-31 10:20:04,055 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 110 [2018-01-31 10:20:04,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:04,055 INFO L225 Difference]: With dead ends: 231 [2018-01-31 10:20:04,055 INFO L226 Difference]: Without dead ends: 149 [2018-01-31 10:20:04,056 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=196, Invalid=404, Unknown=0, NotChecked=0, Total=600 [2018-01-31 10:20:04,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-01-31 10:20:04,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 144. [2018-01-31 10:20:04,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-31 10:20:04,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2018-01-31 10:20:04,060 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 110 [2018-01-31 10:20:04,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:04,060 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2018-01-31 10:20:04,060 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-31 10:20:04,061 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2018-01-31 10:20:04,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-31 10:20:04,061 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:04,061 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 6, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:04,061 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation]=== [2018-01-31 10:20:04,061 INFO L82 PathProgramCache]: Analyzing trace with hash 2034864691, now seen corresponding path program 5 times [2018-01-31 10:20:04,062 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:04,062 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:04,062 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:04,062 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:04,062 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:04,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:04,072 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:04,367 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:20:04,367 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:04,368 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:04,373 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:20:04,379 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,380 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,382 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,384 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,389 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,406 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,424 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:04,425 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:04,426 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:04,536 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:20:04,552 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:04,553 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 24 [2018-01-31 10:20:04,553 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-31 10:20:04,553 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-31 10:20:04,553 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=455, Unknown=0, NotChecked=0, Total=552 [2018-01-31 10:20:04,553 INFO L87 Difference]: Start difference. First operand 144 states and 153 transitions. Second operand 24 states. [2018-01-31 10:20:04,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:04,931 INFO L93 Difference]: Finished difference Result 252 states and 270 transitions. [2018-01-31 10:20:04,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-31 10:20:04,944 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 118 [2018-01-31 10:20:04,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:04,944 INFO L225 Difference]: With dead ends: 252 [2018-01-31 10:20:04,944 INFO L226 Difference]: Without dead ends: 170 [2018-01-31 10:20:04,945 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 331 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2018-01-31 10:20:04,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-01-31 10:20:04,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 160. [2018-01-31 10:20:04,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-01-31 10:20:04,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 169 transitions. [2018-01-31 10:20:04,951 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 169 transitions. Word has length 118 [2018-01-31 10:20:04,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:04,951 INFO L432 AbstractCegarLoop]: Abstraction has 160 states and 169 transitions. [2018-01-31 10:20:04,951 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-31 10:20:04,951 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 169 transitions. [2018-01-31 10:20:04,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-31 10:20:04,952 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:04,952 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:04,952 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation]=== [2018-01-31 10:20:04,952 INFO L82 PathProgramCache]: Analyzing trace with hash 1359274301, now seen corresponding path program 6 times [2018-01-31 10:20:04,952 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:04,952 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:04,953 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:04,953 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:04,953 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:04,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:04,963 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:05,102 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-01-31 10:20:05,102 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:05,102 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:05,106 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:20:05,116 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,119 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,121 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,123 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,126 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,153 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,164 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,212 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:20:05,213 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:05,215 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:05,398 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:20:05,417 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:05,418 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13] total 28 [2018-01-31 10:20:05,418 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-31 10:20:05,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-31 10:20:05,418 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-01-31 10:20:05,419 INFO L87 Difference]: Start difference. First operand 160 states and 169 transitions. Second operand 28 states. [2018-01-31 10:20:05,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:05,947 INFO L93 Difference]: Finished difference Result 276 states and 294 transitions. [2018-01-31 10:20:05,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-31 10:20:05,947 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 134 [2018-01-31 10:20:05,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:05,948 INFO L225 Difference]: With dead ends: 276 [2018-01-31 10:20:05,948 INFO L226 Difference]: Without dead ends: 186 [2018-01-31 10:20:05,949 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=495, Invalid=2157, Unknown=0, NotChecked=0, Total=2652 [2018-01-31 10:20:05,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-31 10:20:05,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 176. [2018-01-31 10:20:05,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-31 10:20:05,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 185 transitions. [2018-01-31 10:20:05,953 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 185 transitions. Word has length 134 [2018-01-31 10:20:05,953 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:05,953 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 185 transitions. [2018-01-31 10:20:05,953 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-31 10:20:05,953 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 185 transitions. [2018-01-31 10:20:05,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-31 10:20:05,954 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:05,954 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:05,954 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation]=== [2018-01-31 10:20:05,955 INFO L82 PathProgramCache]: Analyzing trace with hash -1132442041, now seen corresponding path program 7 times [2018-01-31 10:20:05,955 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:05,955 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:05,955 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:05,955 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:05,955 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:05,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:05,965 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:06,124 INFO L134 CoverageAnalysis]: Checked inductivity of 372 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:20:06,124 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:06,124 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:06,130 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:06,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:06,151 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:06,176 INFO L134 CoverageAnalysis]: Checked inductivity of 372 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:20:06,193 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:06,193 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 21 [2018-01-31 10:20:06,193 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:20:06,193 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:20:06,193 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:20:06,193 INFO L87 Difference]: Start difference. First operand 176 states and 185 transitions. Second operand 21 states. [2018-01-31 10:20:06,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:06,409 INFO L93 Difference]: Finished difference Result 287 states and 304 transitions. [2018-01-31 10:20:06,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-31 10:20:06,410 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 150 [2018-01-31 10:20:06,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:06,410 INFO L225 Difference]: With dead ends: 287 [2018-01-31 10:20:06,410 INFO L226 Difference]: Without dead ends: 189 [2018-01-31 10:20:06,411 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=427, Invalid=905, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:20:06,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-01-31 10:20:06,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 184. [2018-01-31 10:20:06,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-01-31 10:20:06,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 193 transitions. [2018-01-31 10:20:06,414 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 193 transitions. Word has length 150 [2018-01-31 10:20:06,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:06,414 INFO L432 AbstractCegarLoop]: Abstraction has 184 states and 193 transitions. [2018-01-31 10:20:06,414 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:20:06,414 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 193 transitions. [2018-01-31 10:20:06,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-01-31 10:20:06,415 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:06,415 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 9, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:06,415 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation]=== [2018-01-31 10:20:06,415 INFO L82 PathProgramCache]: Analyzing trace with hash -549761245, now seen corresponding path program 8 times [2018-01-31 10:20:06,415 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:06,415 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:06,416 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:06,416 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:06,416 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:06,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:06,425 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:06,688 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:20:06,689 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:06,689 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:06,706 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:20:06,714 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:06,724 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:06,733 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:06,735 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:06,763 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:20:06,780 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:06,780 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 23 [2018-01-31 10:20:06,780 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-31 10:20:06,781 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-31 10:20:06,781 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=363, Unknown=0, NotChecked=0, Total=506 [2018-01-31 10:20:06,781 INFO L87 Difference]: Start difference. First operand 184 states and 193 transitions. Second operand 23 states. [2018-01-31 10:20:07,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:07,039 INFO L93 Difference]: Finished difference Result 290 states and 307 transitions. [2018-01-31 10:20:07,040 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-31 10:20:07,040 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 158 [2018-01-31 10:20:07,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:07,040 INFO L225 Difference]: With dead ends: 290 [2018-01-31 10:20:07,040 INFO L226 Difference]: Without dead ends: 192 [2018-01-31 10:20:07,041 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 157 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 303 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=524, Invalid=1116, Unknown=0, NotChecked=0, Total=1640 [2018-01-31 10:20:07,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192 states. [2018-01-31 10:20:07,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192 to 192. [2018-01-31 10:20:07,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-01-31 10:20:07,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 201 transitions. [2018-01-31 10:20:07,044 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 201 transitions. Word has length 158 [2018-01-31 10:20:07,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:07,044 INFO L432 AbstractCegarLoop]: Abstraction has 192 states and 201 transitions. [2018-01-31 10:20:07,044 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-31 10:20:07,044 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 201 transitions. [2018-01-31 10:20:07,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-31 10:20:07,045 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:07,045 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:07,045 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation]=== [2018-01-31 10:20:07,045 INFO L82 PathProgramCache]: Analyzing trace with hash -2117749761, now seen corresponding path program 9 times [2018-01-31 10:20:07,045 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:07,045 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:07,046 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:07,046 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:07,046 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:07,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:07,054 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:07,259 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:20:07,259 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:07,259 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:07,264 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:20:07,273 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,276 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,279 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,294 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,318 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,345 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,407 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:07,408 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:07,410 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:07,453 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:20:07,470 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:07,471 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 17 [2018-01-31 10:20:07,471 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-01-31 10:20:07,471 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-01-31 10:20:07,471 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-01-31 10:20:07,471 INFO L87 Difference]: Start difference. First operand 192 states and 201 transitions. Second operand 17 states. [2018-01-31 10:20:07,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:07,679 INFO L93 Difference]: Finished difference Result 234 states and 246 transitions. [2018-01-31 10:20:07,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-01-31 10:20:07,679 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 166 [2018-01-31 10:20:07,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:07,680 INFO L225 Difference]: With dead ends: 234 [2018-01-31 10:20:07,680 INFO L226 Difference]: Without dead ends: 205 [2018-01-31 10:20:07,680 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 165 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 144 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=263, Invalid=549, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:20:07,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-01-31 10:20:07,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 200. [2018-01-31 10:20:07,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 200 states. [2018-01-31 10:20:07,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 209 transitions. [2018-01-31 10:20:07,683 INFO L78 Accepts]: Start accepts. Automaton has 200 states and 209 transitions. Word has length 166 [2018-01-31 10:20:07,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:07,683 INFO L432 AbstractCegarLoop]: Abstraction has 200 states and 209 transitions. [2018-01-31 10:20:07,683 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-01-31 10:20:07,683 INFO L276 IsEmpty]: Start isEmpty. Operand 200 states and 209 transitions. [2018-01-31 10:20:07,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-01-31 10:20:07,684 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:07,684 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:07,684 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation]=== [2018-01-31 10:20:07,685 INFO L82 PathProgramCache]: Analyzing trace with hash 1893966381, now seen corresponding path program 10 times [2018-01-31 10:20:07,685 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:07,685 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:07,685 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:07,685 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:07,685 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:07,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:07,693 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:07,876 INFO L134 CoverageAnalysis]: Checked inductivity of 562 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:20:07,876 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:07,876 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:07,881 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:20:07,897 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:07,899 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:07,924 INFO L134 CoverageAnalysis]: Checked inductivity of 562 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:20:07,941 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:07,941 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 19 [2018-01-31 10:20:07,941 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-01-31 10:20:07,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-01-31 10:20:07,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-01-31 10:20:07,941 INFO L87 Difference]: Start difference. First operand 200 states and 209 transitions. Second operand 19 states. [2018-01-31 10:20:08,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:08,152 INFO L93 Difference]: Finished difference Result 242 states and 254 transitions. [2018-01-31 10:20:08,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-01-31 10:20:08,152 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 174 [2018-01-31 10:20:08,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:08,153 INFO L225 Difference]: With dead ends: 242 [2018-01-31 10:20:08,153 INFO L226 Difference]: Without dead ends: 213 [2018-01-31 10:20:08,153 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 204 GetRequests, 173 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 191 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=340, Invalid=716, Unknown=0, NotChecked=0, Total=1056 [2018-01-31 10:20:08,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-01-31 10:20:08,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 208. [2018-01-31 10:20:08,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208 states. [2018-01-31 10:20:08,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 217 transitions. [2018-01-31 10:20:08,156 INFO L78 Accepts]: Start accepts. Automaton has 208 states and 217 transitions. Word has length 174 [2018-01-31 10:20:08,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:08,156 INFO L432 AbstractCegarLoop]: Abstraction has 208 states and 217 transitions. [2018-01-31 10:20:08,156 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-01-31 10:20:08,156 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 217 transitions. [2018-01-31 10:20:08,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-01-31 10:20:08,157 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:08,157 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:08,157 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation]=== [2018-01-31 10:20:08,158 INFO L82 PathProgramCache]: Analyzing trace with hash 914326107, now seen corresponding path program 11 times [2018-01-31 10:20:08,158 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:08,158 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:08,158 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:08,158 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:08,158 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:08,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:08,166 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:08,573 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:20:08,573 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:08,573 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:08,578 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:20:08,584 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,601 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,608 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,617 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,621 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,628 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,679 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,728 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,762 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:08,945 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:09,256 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:09,259 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:09,262 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:09,319 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 380 trivial. 0 not checked. [2018-01-31 10:20:09,337 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:09,337 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 21 [2018-01-31 10:20:09,338 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:20:09,338 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:20:09,338 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:20:09,338 INFO L87 Difference]: Start difference. First operand 208 states and 217 transitions. Second operand 21 states. [2018-01-31 10:20:09,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:09,581 INFO L93 Difference]: Finished difference Result 245 states and 257 transitions. [2018-01-31 10:20:09,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-31 10:20:09,583 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 182 [2018-01-31 10:20:09,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:09,584 INFO L225 Difference]: With dead ends: 245 [2018-01-31 10:20:09,584 INFO L226 Difference]: Without dead ends: 216 [2018-01-31 10:20:09,584 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 181 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=427, Invalid=905, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:20:09,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-01-31 10:20:09,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 216. [2018-01-31 10:20:09,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-01-31 10:20:09,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 225 transitions. [2018-01-31 10:20:09,587 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 225 transitions. Word has length 182 [2018-01-31 10:20:09,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:09,587 INFO L432 AbstractCegarLoop]: Abstraction has 216 states and 225 transitions. [2018-01-31 10:20:09,587 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:20:09,587 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 225 transitions. [2018-01-31 10:20:09,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-01-31 10:20:09,588 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:09,588 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:09,588 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation]=== [2018-01-31 10:20:09,588 INFO L82 PathProgramCache]: Analyzing trace with hash -1232644983, now seen corresponding path program 12 times [2018-01-31 10:20:09,588 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:09,588 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:09,589 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:09,589 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:09,589 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:09,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:20:09,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:20:09,647 INFO L410 BasicCegarLoop]: Counterexample might be feasible [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [389] [389] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [395] [395] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [401] [401] mainENTRY-->L20: Formula: (and (= |v_#length_3| (store |v_#length_4| |v_main_~#x~5.base_1| 40)) (not (= 0 |v_main_~#x~5.base_1|)) (= |v_main_~#x~5.offset_1| 0) (= (store |v_#valid_8| |v_main_~#x~5.base_1| 1) |v_#valid_7|) (= 0 (select |v_#valid_8| |v_main_~#x~5.base_1|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_8|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_1|, #length=|v_#length_3|, main_~#x~5.offset=|v_main_~#x~5.offset_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[main_~#x~5.base, main_~#x~5.offset, #valid, #length] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L20-->L22: Formula: true InVars {} OutVars{main_~temp~5=v_main_~temp~5_1} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [409] [409] L22-->L23: Formula: true InVars {} OutVars{main_~ret~5=v_main_~ret~5_1} AuxVars[] AssignedVars[main_~ret~5] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L23-->L24: Formula: true InVars {} OutVars{main_~ret2~5=v_main_~ret2~5_1} AuxVars[] AssignedVars[main_~ret2~5] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [413] [413] L24-->L26: Formula: true InVars {} OutVars{main_~ret5~5=v_main_~ret5~5_1} AuxVars[] AssignedVars[main_~ret5~5] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [415] [415] L26-->L26'''''': Formula: (= v_main_~i~6_1 0) InVars {} OutVars{main_~i~6=v_main_~i~6_1} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,649 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,650 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,651 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,652 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,653 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 10) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [421] [421] L26'-->L26''''''': Formula: (not (< v_main_~i~6_2 10)) InVars {main_~i~6=v_main_~i~6_2} OutVars{main_~i~6=v_main_~i~6_2} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [425] [425] L26'''''''-->L30: Formula: true InVars {} OutVars{main_#t~ret7=|v_main_#t~ret7_1|} AuxVars[] AssignedVars[main_#t~ret7] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [431] [431] L30-->L30': Formula: (and (<= |v_main_#t~ret7_2| 2147483647) (<= 0 (+ |v_main_#t~ret7_2| 2147483648))) InVars {main_#t~ret7=|v_main_#t~ret7_2|} OutVars{main_#t~ret7=|v_main_#t~ret7_2|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [437] [437] L30'-->L30'': Formula: (= v_main_~ret~5_2 |v_main_#t~ret7_3|) InVars {main_#t~ret7=|v_main_#t~ret7_3|} OutVars{main_#t~ret7=|v_main_#t~ret7_3|, main_~ret~5=v_main_~ret~5_2} AuxVars[] AssignedVars[main_~ret~5] [2018-01-31 10:20:09,654 INFO L84 mationBacktranslator]: Skipped ATE [443] [443] L30''-->L32: Formula: true InVars {} OutVars{main_#t~ret7=|v_main_#t~ret7_4|} AuxVars[] AssignedVars[main_#t~ret7] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [449] [449] L32-->L32': Formula: (= |v_main_#t~mem8_1| (select (select |v_#memory_int_part_locs_87_locs_92_3| |v_main_~#x~5.base_4|) |v_main_~#x~5.offset_4|)) InVars {main_~#x~5.base=|v_main_~#x~5.base_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_3|, main_~#x~5.offset=|v_main_~#x~5.offset_4|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_4|, main_#t~mem8=|v_main_#t~mem8_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_3|, main_~#x~5.offset=|v_main_~#x~5.offset_4|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L32'-->L32'': Formula: (= v_main_~temp~5_2 |v_main_#t~mem8_2|) InVars {main_#t~mem8=|v_main_#t~mem8_2|} OutVars{main_~temp~5=v_main_~temp~5_2, main_#t~mem8=|v_main_#t~mem8_2|} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L32''-->L32''': Formula: true InVars {} OutVars{main_#t~mem8=|v_main_#t~mem8_3|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [473] [473] L32'''-->L32'''': Formula: (= |v_main_#t~mem10_1| (select (select |v_#memory_int_part_locs_87_locs_92_5| |v_main_~#x~5.base_5|) (+ |v_main_~#x~5.offset_5| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_5|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_5|, main_~#x~5.offset=|v_main_~#x~5.offset_5|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_5|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_5|, main_#t~mem10=|v_main_#t~mem10_1|, main_~#x~5.offset=|v_main_~#x~5.offset_5|} AuxVars[] AssignedVars[main_#t~mem10] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [479] [479] L32''''-->L32''''': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_6| |v_main_~#x~5.base_6| (store (select |v_#memory_int_part_locs_87_locs_92_6| |v_main_~#x~5.base_6|) |v_main_~#x~5.offset_6| |v_main_#t~mem10_2|)) |v_#memory_int_part_locs_87_locs_92_7|) InVars {main_~#x~5.base=|v_main_~#x~5.base_6|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_6|, main_#t~mem10=|v_main_#t~mem10_2|, main_~#x~5.offset=|v_main_~#x~5.offset_6|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_6|, #memory_int=|v_#memory_int_7|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_7|, main_#t~mem10=|v_main_#t~mem10_2|, main_~#x~5.offset=|v_main_~#x~5.offset_6|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [489] [489] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~mem10=|v_main_#t~mem10_3|} AuxVars[] AssignedVars[main_#t~mem10] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [499] [499] L32''''''-->L32''''''': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_8| |v_main_~#x~5.base_7| (store (select |v_#memory_int_part_locs_87_locs_92_8| |v_main_~#x~5.base_7|) (+ |v_main_~#x~5.offset_7| 4) v_main_~temp~5_3)) |v_#memory_int_part_locs_87_locs_92_9|) InVars {main_~#x~5.base=|v_main_~#x~5.base_7|, main_~temp~5=v_main_~temp~5_3, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_8|, main_~#x~5.offset=|v_main_~#x~5.offset_7|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_7|, #memory_int=|v_#memory_int_9|, main_~temp~5=v_main_~temp~5_3, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_9|, main_~#x~5.offset=|v_main_~#x~5.offset_7|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32'''''''-->L33: Formula: true InVars {} OutVars{main_#t~ret12=|v_main_#t~ret12_1|} AuxVars[] AssignedVars[main_#t~ret12] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [485] [485] L33-->L33': Formula: (and (<= 0 (+ |v_main_#t~ret12_2| 2147483648)) (<= |v_main_#t~ret12_2| 2147483647)) InVars {main_#t~ret12=|v_main_#t~ret12_2|} OutVars{main_#t~ret12=|v_main_#t~ret12_2|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [495] [495] L33'-->L33'': Formula: (= v_main_~ret2~5_2 |v_main_#t~ret12_3|) InVars {main_#t~ret12=|v_main_#t~ret12_3|} OutVars{main_#t~ret12=|v_main_#t~ret12_3|, main_~ret2~5=v_main_~ret2~5_2} AuxVars[] AssignedVars[main_~ret2~5] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [505] [505] L33''-->L34: Formula: true InVars {} OutVars{main_#t~ret12=|v_main_#t~ret12_4|} AuxVars[] AssignedVars[main_#t~ret12] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L34-->L34': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_10| |v_main_~#x~5.base_9|) |v_main_~#x~5.offset_9|) |v_main_#t~mem13_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_9|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_10|, main_~#x~5.offset=|v_main_~#x~5.offset_9|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_10|, main_~#x~5.offset=|v_main_~#x~5.offset_9|} AuxVars[] AssignedVars[main_#t~mem13] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [525] [525] L34'-->L34'': Formula: (= v_main_~temp~5_4 |v_main_#t~mem13_2|) InVars {main_#t~mem13=|v_main_#t~mem13_2|} OutVars{main_~temp~5=v_main_~temp~5_4, main_#t~mem13=|v_main_#t~mem13_2|} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L34''-->L35: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|} AuxVars[] AssignedVars[main_#t~mem13] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [541] [541] L35-->L35'''''': Formula: (= v_main_~i~7_1 0) InVars {} OutVars{main_~i~7=v_main_~i~7_1} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,655 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,656 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,657 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,658 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 9) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,659 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [551] [551] L35'-->L35''''''': Formula: (not (< v_main_~i~7_2 9)) InVars {main_~i~7=v_main_~i~7_2} OutVars{main_~i~7=v_main_~i~7_2} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [555] [555] L35'''''''-->L38: Formula: (= (store |v_#memory_int_part_locs_87_locs_92_11| |v_main_~#x~5.base_12| (store (select |v_#memory_int_part_locs_87_locs_92_11| |v_main_~#x~5.base_12|) (+ |v_main_~#x~5.offset_12| 36) v_main_~temp~5_5)) |v_#memory_int_part_locs_87_locs_92_12|) InVars {main_~#x~5.base=|v_main_~#x~5.base_12|, main_~temp~5=v_main_~temp~5_5, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_11|, main_~#x~5.offset=|v_main_~#x~5.offset_12|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_12|, #memory_int=|v_#memory_int_15|, main_~temp~5=v_main_~temp~5_5, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_12|, main_~#x~5.offset=|v_main_~#x~5.offset_12|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [559] [559] L38-->L39: Formula: true InVars {} OutVars{main_#t~ret18=|v_main_#t~ret18_1|} AuxVars[] AssignedVars[main_#t~ret18] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [487] [487] L39-->L39': Formula: (and (<= |v_main_#t~ret18_2| 2147483647) (<= 0 (+ |v_main_#t~ret18_2| 2147483648))) InVars {main_#t~ret18=|v_main_#t~ret18_2|} OutVars{main_#t~ret18=|v_main_#t~ret18_2|} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [497] [497] L39'-->L39'': Formula: (= v_main_~ret5~5_2 |v_main_#t~ret18_3|) InVars {main_#t~ret18=|v_main_#t~ret18_3|} OutVars{main_#t~ret18=|v_main_#t~ret18_3|, main_~ret5~5=v_main_~ret5~5_2} AuxVars[] AssignedVars[main_~ret5~5] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [507] [507] L39''-->L41: Formula: true InVars {} OutVars{main_#t~ret18=|v_main_#t~ret18_4|} AuxVars[] AssignedVars[main_#t~ret18] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [519] [519] L41-->L42: Formula: (or (not (= v_main_~ret2~5_3 v_main_~ret~5_3)) (not (= v_main_~ret5~5_3 v_main_~ret~5_3))) InVars {main_~ret~5=v_main_~ret~5_3, main_~ret5~5=v_main_~ret5~5_3, main_~ret2~5=v_main_~ret2~5_3} OutVars{main_~ret~5=v_main_~ret~5_3, main_~ret5~5=v_main_~ret5~5_3, main_~ret2~5=v_main_~ret2~5_3} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,660 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L42-->mainErr0AssertViolation: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:20:09,663 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:20:09 BasicIcfg [2018-01-31 10:20:09,663 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-31 10:20:09,664 INFO L168 Benchmark]: Toolchain (without parser) took 54674.24 ms. Allocated memory was 148.9 MB in the beginning and 2.1 GB in the end (delta: 1.9 GB). Free memory was 113.8 MB in the beginning and 987.3 MB in the end (delta: -873.5 MB). Peak memory consumption was 1.0 GB. Max. memory is 5.3 GB. [2018-01-31 10:20:09,664 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 148.9 MB. Free memory is still 118.5 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:20:09,664 INFO L168 Benchmark]: CACSL2BoogieTranslator took 111.67 ms. Allocated memory is still 148.9 MB. Free memory was 113.6 MB in the beginning and 104.9 MB in the end (delta: 8.7 MB). Peak memory consumption was 8.7 MB. Max. memory is 5.3 GB. [2018-01-31 10:20:09,664 INFO L168 Benchmark]: Boogie Preprocessor took 19.94 ms. Allocated memory is still 148.9 MB. Free memory was 104.9 MB in the beginning and 103.3 MB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 5.3 GB. [2018-01-31 10:20:09,664 INFO L168 Benchmark]: RCFGBuilder took 420.56 ms. Allocated memory is still 148.9 MB. Free memory was 103.3 MB in the beginning and 83.8 MB in the end (delta: 19.4 MB). Peak memory consumption was 19.4 MB. Max. memory is 5.3 GB. [2018-01-31 10:20:09,665 INFO L168 Benchmark]: IcfgTransformer took 45328.95 ms. Allocated memory was 148.9 MB in the beginning and 2.1 GB in the end (delta: 1.9 GB). Free memory was 83.6 MB in the beginning and 1.8 GB in the end (delta: -1.7 GB). Peak memory consumption was 217.2 MB. Max. memory is 5.3 GB. [2018-01-31 10:20:09,665 INFO L168 Benchmark]: TraceAbstraction took 8790.53 ms. Allocated memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 5.8 MB). Free memory was 1.8 GB in the beginning and 987.3 MB in the end (delta: 783.8 MB). Peak memory consumption was 789.6 MB. Max. memory is 5.3 GB. [2018-01-31 10:20:09,665 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 148.9 MB. Free memory is still 118.5 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 111.67 ms. Allocated memory is still 148.9 MB. Free memory was 113.6 MB in the beginning and 104.9 MB in the end (delta: 8.7 MB). Peak memory consumption was 8.7 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 19.94 ms. Allocated memory is still 148.9 MB. Free memory was 104.9 MB in the beginning and 103.3 MB in the end (delta: 1.7 MB). Peak memory consumption was 1.7 MB. Max. memory is 5.3 GB. * RCFGBuilder took 420.56 ms. Allocated memory is still 148.9 MB. Free memory was 103.3 MB in the beginning and 83.8 MB in the end (delta: 19.4 MB). Peak memory consumption was 19.4 MB. Max. memory is 5.3 GB. * IcfgTransformer took 45328.95 ms. Allocated memory was 148.9 MB in the beginning and 2.1 GB in the end (delta: 1.9 GB). Free memory was 83.6 MB in the beginning and 1.8 GB in the end (delta: -1.7 GB). Peak memory consumption was 217.2 MB. Max. memory is 5.3 GB. * TraceAbstraction took 8790.53 ms. Allocated memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 5.8 MB). Free memory was 1.8 GB in the beginning and 987.3 MB in the end (delta: 783.8 MB). Peak memory consumption was 789.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 82 LocStat_MAX_WEQGRAPH_SIZE : 3 LocStat_MAX_SIZEOF_WEQEDGELABEL : 2 LocStat_NO_SUPPORTING_EQUALITIES : 1540 LocStat_NO_SUPPORTING_DISEQUALITIES : 3717 LocStat_NO_DISJUNCTIONS : -164 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 108 TransStat_MAX_WEQGRAPH_SIZE : 2 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 166 TransStat_NO_SUPPORTING_DISEQUALITIES : 7 TransStat_NO_DISJUNCTIONS : 106 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.008320 RENAME_VARIABLES(MILLISECONDS) : 0.203994 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.000352 PROJECTAWAY(MILLISECONDS) : 0.069939 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.048180 DISJOIN(MILLISECONDS) : 0.772220 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.218891 ADD_EQUALITY(MILLISECONDS) : 0.012078 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.002174 #CONJOIN_DISJUNCTIVE : 1415 #RENAME_VARIABLES : 3043 #UNFREEZE : 0 #CONJOIN : 1854 #PROJECTAWAY : 1760 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 435 #RENAME_VARIABLES_DISJUNCTIVE : 3088 #ADD_EQUALITY : 171 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 5 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 5 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 10 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 42]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 83 locations, 1 error locations. UNSAFE Result, 8.6s OverallTime, 15 OverallIterations, 11 TraceHistogramMax, 3.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1116 SDtfs, 528 SDslu, 11184 SDs, 0 SdLazy, 1297 SolverSat, 126 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1791 GetRequests, 1436 SyntacticMatches, 0 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2297 ImplicationChecksByTransitivity, 4.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=216occurred in iteration=14, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 14 MinimizatonAttempts, 85 StatesRemovedByMinimization, 11 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 1.2s SatisfiabilityAnalysisTime, 3.2s InterpolantComputationTime, 3208 NumberOfCodeBlocks, 3143 NumberOfCodeBlocksAsserted, 61 NumberOfCheckSat, 2992 ConstructedInterpolants, 0 QuantifiedInterpolants, 697166 SizeOfPredicates, 134 NumberOfNonLiveVariables, 2064 ConjunctsInSsa, 148 ConjunctsInUnsatCore, 26 InterpolantComputations, 3 PerfectInterpolantSequences, 3524/6508 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep10_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-31_10-20-09-670.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep10_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-31_10-20-09-670.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep10_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-31_10-20-09-670.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep10_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-31_10-20-09-670.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep10_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-31_10-20-09-670.csv Received shutdown request...