java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/reducercommutativity/sep20_true-unreach-call.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-5f7ec6e-m [2018-01-31 10:20:10,917 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-01-31 10:20:10,918 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-01-31 10:20:10,931 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-01-31 10:20:10,931 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-01-31 10:20:10,932 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-01-31 10:20:10,933 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-01-31 10:20:10,935 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-01-31 10:20:10,936 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-01-31 10:20:10,936 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-01-31 10:20:10,937 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-01-31 10:20:10,937 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-01-31 10:20:10,937 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-01-31 10:20:10,938 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-01-31 10:20:10,938 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-01-31 10:20:10,940 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-01-31 10:20:10,942 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-01-31 10:20:10,943 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-01-31 10:20:10,944 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-01-31 10:20:10,949 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-01-31 10:20:10,950 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-01-31 10:20:10,950 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-01-31 10:20:10,950 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-01-31 10:20:10,951 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-01-31 10:20:10,951 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-01-31 10:20:10,952 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-01-31 10:20:10,952 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-01-31 10:20:10,952 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-01-31 10:20:10,952 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-01-31 10:20:10,953 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-01-31 10:20:10,953 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-01-31 10:20:10,953 INFO L98 SettingsManager]: Beginning loading settings from /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf [2018-01-31 10:20:10,965 INFO L110 SettingsManager]: Loading preferences was successful [2018-01-31 10:20:10,965 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-01-31 10:20:10,966 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-01-31 10:20:10,966 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-01-31 10:20:10,966 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-01-31 10:20:10,966 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-01-31 10:20:10,966 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-01-31 10:20:10,967 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-01-31 10:20:10,967 INFO L133 SettingsManager]: * sizeof long=4 [2018-01-31 10:20:10,967 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-01-31 10:20:10,968 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-01-31 10:20:10,968 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-01-31 10:20:10,968 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-01-31 10:20:10,968 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * sizeof long double=12 [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-01-31 10:20:10,969 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-01-31 10:20:10,969 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:20:10,969 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-01-31 10:20:10,970 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-01-31 10:20:10,971 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-01-31 10:20:10,971 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-01-31 10:20:10,996 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-01-31 10:20:11,003 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-01-31 10:20:11,005 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-01-31 10:20:11,006 INFO L271 PluginConnector]: Initializing CDTParser... [2018-01-31 10:20:11,006 INFO L276 PluginConnector]: CDTParser initialized [2018-01-31 10:20:11,007 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/reducercommutativity/sep20_true-unreach-call.i [2018-01-31 10:20:11,070 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-01-31 10:20:11,071 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-01-31 10:20:11,072 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-01-31 10:20:11,072 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-01-31 10:20:11,075 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-01-31 10:20:11,076 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,078 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3d35538b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11, skipping insertion in model container [2018-01-31 10:20:11,078 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,087 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:20:11,096 INFO L153 Dispatcher]: Using SV-COMP mode [2018-01-31 10:20:11,168 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:20:11,181 INFO L450 PostProcessor]: Settings: Checked method=main [2018-01-31 10:20:11,185 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11 WrapperNode [2018-01-31 10:20:11,185 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-01-31 10:20:11,185 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-01-31 10:20:11,186 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-01-31 10:20:11,186 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-01-31 10:20:11,194 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,194 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,200 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,200 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,202 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,204 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,204 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,205 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-01-31 10:20:11,206 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-01-31 10:20:11,206 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-01-31 10:20:11,206 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-01-31 10:20:11,206 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (1/1) ... No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-01-31 10:20:11,246 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-01-31 10:20:11,246 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-01-31 10:20:11,246 INFO L136 BoogieDeclarations]: Found implementation of procedure sep [2018-01-31 10:20:11,246 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-01-31 10:20:11,247 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-01-31 10:20:11,247 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-01-31 10:20:11,247 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure sep [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-01-31 10:20:11,248 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-01-31 10:20:11,249 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-01-31 10:20:11,660 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-01-31 10:20:11,661 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:20:11 BoogieIcfgContainer [2018-01-31 10:20:11,661 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-01-31 10:20:11,661 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-01-31 10:20:11,661 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-01-31 10:20:11,662 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-01-31 10:20:11,663 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:20:11" (1/1) ... [2018-01-31 10:20:11,668 INFO L103 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-01-31 10:20:11,668 INFO L104 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-01-31 10:20:11,669 INFO L150 apSepIcfgTransformer]: starting freeze-var-style preprocessing [2018-01-31 10:20:11,693 INFO L162 apSepIcfgTransformer]: finished StoreIndexFreezer, created 13 freeze vars and freeze var literals (each corresponds to one heap write) [2018-01-31 10:20:11,711 INFO L221 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-01-31 10:20:11,744 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-01-31 10:20:57,412 INFO L314 AbstractInterpreter]: Visited 97 different actions 931 times. Merged at 71 different actions 448 times. Widened at 1 different actions 1 times. Found 80 fixpoints after 14 different actions. Largest state had 68 variables. [2018-01-31 10:20:57,414 INFO L229 apSepIcfgTransformer]: finished equality analysis [2018-01-31 10:20:57,420 INFO L244 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 10 [2018-01-31 10:20:57,420 INFO L241 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-01-31 10:20:57,420 INFO L242 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-01-31 10:20:57,421 INFO L244 apSepIcfgTransformer]: select infos: Set: ((select |v_#memory_int_4| |v_main_~#x~5.base_2|), at (SUMMARY for call write~int(#t~nondet5, ~#x~5.base, ~#x~5.offset + ~i~6 * 4, 4); srcloc: L27')) ((select (select |v_#memory_int_6| |v_main_~#x~5.base_5|) (+ |v_main_~#x~5.offset_5| 4)), at (SUMMARY for call #t~mem10 := read~int(~#x~5.base, ~#x~5.offset + 4, 4); srcloc: L32''')) ((select (select |v_#memory_int_11| |v_main_~#x~5.base_9|) |v_main_~#x~5.offset_9|), at (SUMMARY for call #t~mem13 := read~int(~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L34)) ((select (select |v_#memory_int_5| |v_main_~#x~5.base_4|) |v_main_~#x~5.offset_4|), at (SUMMARY for call #t~mem8 := read~int(~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L32)) ((select |v_#memory_int_14| |v_main_~#x~5.base_11|), at (SUMMARY for call write~int(#t~mem16, ~#x~5.base, ~#x~5.offset + ~i~7 * 4, 4); srcloc: L36')) ((select (select |v_#memory_int_12| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4)), at (SUMMARY for call #t~mem16 := read~int(~#x~5.base, ~#x~5.offset + (~i~7 + 1) * 4, 4); srcloc: L36)) ((select |v_#memory_int_10| |v_main_~#x~5.base_7|), at (SUMMARY for call write~int(~temp~5, ~#x~5.base, ~#x~5.offset + 4, 4); srcloc: L32'''''')) ((select (select |v_#memory_int_17| v_sep_~x.base_1) (+ v_sep_~x.offset_1 (* 4 v_sep_~i~4_2))), at (SUMMARY for call #t~mem1 := read~int(~x.base, ~x.offset + ~i~4 * 4, 4); srcloc: L9)) ((select |v_#memory_int_8| |v_main_~#x~5.base_6|), at (SUMMARY for call write~int(#t~mem10, ~#x~5.base, ~#x~5.offset + 0, 4); srcloc: L32'''')) ((select |v_#memory_int_16| |v_main_~#x~5.base_12|), at (SUMMARY for call write~int(~temp~5, ~#x~5.base, ~#x~5.offset + 76, 4); srcloc: L35''''''')) [2018-01-31 10:20:57,439 INFO L547 PartitionManager]: partitioning result: [2018-01-31 10:20:57,439 INFO L552 PartitionManager]: location blocks for array group [#memory_int] [2018-01-31 10:20:57,439 INFO L562 PartitionManager]: at dimension 0 [2018-01-31 10:20:57,439 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 5 [2018-01-31 10:20:57,439 INFO L564 PartitionManager]: # location blocks :1 [2018-01-31 10:20:57,439 INFO L562 PartitionManager]: at dimension 1 [2018-01-31 10:20:57,439 INFO L563 PartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 5 [2018-01-31 10:20:57,439 INFO L564 PartitionManager]: # location blocks :1 [2018-01-31 10:20:57,440 INFO L86 ransitionTransformer]: executing heap partitioning transformation [2018-01-31 10:20:57,450 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:20:57 BasicIcfg [2018-01-31 10:20:57,450 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-01-31 10:20:57,451 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-01-31 10:20:57,451 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-01-31 10:20:57,452 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-01-31 10:20:57,457 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 31.01 10:20:11" (1/4) ... [2018-01-31 10:20:57,457 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e3c4f5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:20:57, skipping insertion in model container [2018-01-31 10:20:57,457 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.01 10:20:11" (2/4) ... [2018-01-31 10:20:57,458 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e3c4f5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 31.01 10:20:57, skipping insertion in model container [2018-01-31 10:20:57,458 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.01 10:20:11" (3/4) ... [2018-01-31 10:20:57,458 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e3c4f5d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:20:57, skipping insertion in model container [2018-01-31 10:20:57,458 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 31.01 10:20:57" (4/4) ... [2018-01-31 10:20:57,459 INFO L107 eAbstractionObserver]: Analyzing ICFG HeapSeparatedIcfg [2018-01-31 10:20:57,467 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-01-31 10:20:57,472 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-01-31 10:20:57,558 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-01-31 10:20:57,558 INFO L323 AbstractCegarLoop]: Hoare is true [2018-01-31 10:20:57,559 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-01-31 10:20:57,559 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-01-31 10:20:57,559 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-01-31 10:20:57,559 INFO L327 AbstractCegarLoop]: Difference is false [2018-01-31 10:20:57,559 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-01-31 10:20:57,559 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-01-31 10:20:57,559 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-01-31 10:20:57,567 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states. [2018-01-31 10:20:57,573 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-01-31 10:20:57,573 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:57,573 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:57,577 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolation]=== [2018-01-31 10:20:57,579 INFO L82 PathProgramCache]: Analyzing trace with hash -1929961395, now seen corresponding path program 1 times [2018-01-31 10:20:57,580 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:57,580 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:57,610 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:57,610 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:57,610 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:57,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:57,638 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:57,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:20:57,667 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:20:57,667 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-01-31 10:20:57,668 INFO L409 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-01-31 10:20:57,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-01-31 10:20:57,674 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:20:57,676 INFO L87 Difference]: Start difference. First operand 83 states. Second operand 2 states. [2018-01-31 10:20:57,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:57,695 INFO L93 Difference]: Finished difference Result 146 states and 173 transitions. [2018-01-31 10:20:57,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-01-31 10:20:57,696 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 36 [2018-01-31 10:20:57,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:57,702 INFO L225 Difference]: With dead ends: 146 [2018-01-31 10:20:57,702 INFO L226 Difference]: Without dead ends: 76 [2018-01-31 10:20:57,706 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-01-31 10:20:57,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-01-31 10:20:57,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2018-01-31 10:20:57,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 76 states. [2018-01-31 10:20:57,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 85 transitions. [2018-01-31 10:20:57,736 INFO L78 Accepts]: Start accepts. Automaton has 76 states and 85 transitions. Word has length 36 [2018-01-31 10:20:57,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:57,737 INFO L432 AbstractCegarLoop]: Abstraction has 76 states and 85 transitions. [2018-01-31 10:20:57,737 INFO L433 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-01-31 10:20:57,737 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 85 transitions. [2018-01-31 10:20:57,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-01-31 10:20:57,738 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:57,738 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:57,739 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolation]=== [2018-01-31 10:20:57,739 INFO L82 PathProgramCache]: Analyzing trace with hash -2081485741, now seen corresponding path program 1 times [2018-01-31 10:20:57,739 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:57,739 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:57,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:57,740 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:57,740 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:57,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:57,750 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:57,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:20:57,811 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-01-31 10:20:57,812 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-01-31 10:20:57,812 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-01-31 10:20:57,813 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-01-31 10:20:57,813 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-31 10:20:57,813 INFO L87 Difference]: Start difference. First operand 76 states and 85 transitions. Second operand 3 states. [2018-01-31 10:20:57,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:57,883 INFO L93 Difference]: Finished difference Result 139 states and 156 transitions. [2018-01-31 10:20:57,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-01-31 10:20:57,883 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-01-31 10:20:57,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:57,884 INFO L225 Difference]: With dead ends: 139 [2018-01-31 10:20:57,884 INFO L226 Difference]: Without dead ends: 83 [2018-01-31 10:20:57,885 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-01-31 10:20:57,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-01-31 10:20:57,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 78. [2018-01-31 10:20:57,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-01-31 10:20:57,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 87 transitions. [2018-01-31 10:20:57,889 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 87 transitions. Word has length 38 [2018-01-31 10:20:57,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:57,889 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 87 transitions. [2018-01-31 10:20:57,889 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-01-31 10:20:57,890 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 87 transitions. [2018-01-31 10:20:57,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-01-31 10:20:57,891 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:57,891 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:57,891 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolation]=== [2018-01-31 10:20:57,891 INFO L82 PathProgramCache]: Analyzing trace with hash -351365841, now seen corresponding path program 1 times [2018-01-31 10:20:57,891 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:57,891 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:57,892 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:57,892 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:57,892 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:57,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:57,901 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:57,967 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-01-31 10:20:57,968 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:57,968 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:57,981 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:58,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:58,008 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:58,038 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-31 10:20:58,055 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-01-31 10:20:58,056 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-01-31 10:20:58,056 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-01-31 10:20:58,056 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-01-31 10:20:58,056 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-01-31 10:20:58,056 INFO L87 Difference]: Start difference. First operand 78 states and 87 transitions. Second operand 6 states. [2018-01-31 10:20:58,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:58,302 INFO L93 Difference]: Finished difference Result 154 states and 172 transitions. [2018-01-31 10:20:58,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-01-31 10:20:58,303 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-01-31 10:20:58,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:58,304 INFO L225 Difference]: With dead ends: 154 [2018-01-31 10:20:58,304 INFO L226 Difference]: Without dead ends: 98 [2018-01-31 10:20:58,304 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-01-31 10:20:58,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-01-31 10:20:58,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 88. [2018-01-31 10:20:58,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-01-31 10:20:58,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 97 transitions. [2018-01-31 10:20:58,310 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 97 transitions. Word has length 46 [2018-01-31 10:20:58,310 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:58,310 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 97 transitions. [2018-01-31 10:20:58,310 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-01-31 10:20:58,310 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 97 transitions. [2018-01-31 10:20:58,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-01-31 10:20:58,311 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:58,311 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:58,312 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolation]=== [2018-01-31 10:20:58,312 INFO L82 PathProgramCache]: Analyzing trace with hash -577067975, now seen corresponding path program 1 times [2018-01-31 10:20:58,312 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:58,312 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:58,312 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:58,312 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:58,313 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:58,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:58,323 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:58,383 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-31 10:20:58,383 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:58,383 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:58,389 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:58,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:58,415 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:58,534 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-01-31 10:20:58,555 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:58,555 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 7] total 10 [2018-01-31 10:20:58,555 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-01-31 10:20:58,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-01-31 10:20:58,556 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-01-31 10:20:58,556 INFO L87 Difference]: Start difference. First operand 88 states and 97 transitions. Second operand 10 states. [2018-01-31 10:20:58,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:58,911 INFO L93 Difference]: Finished difference Result 172 states and 190 transitions. [2018-01-31 10:20:58,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-01-31 10:20:58,911 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 62 [2018-01-31 10:20:58,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:58,912 INFO L225 Difference]: With dead ends: 172 [2018-01-31 10:20:58,912 INFO L226 Difference]: Without dead ends: 114 [2018-01-31 10:20:58,912 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=60, Invalid=180, Unknown=0, NotChecked=0, Total=240 [2018-01-31 10:20:58,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-01-31 10:20:58,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 104. [2018-01-31 10:20:58,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-01-31 10:20:58,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 113 transitions. [2018-01-31 10:20:58,917 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 113 transitions. Word has length 62 [2018-01-31 10:20:58,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:58,917 INFO L432 AbstractCegarLoop]: Abstraction has 104 states and 113 transitions. [2018-01-31 10:20:58,917 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-01-31 10:20:58,917 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 113 transitions. [2018-01-31 10:20:58,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-01-31 10:20:58,919 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:58,919 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:58,919 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolation]=== [2018-01-31 10:20:58,919 INFO L82 PathProgramCache]: Analyzing trace with hash 1689178435, now seen corresponding path program 2 times [2018-01-31 10:20:58,919 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:58,919 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:58,920 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:58,920 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:20:58,920 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:58,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:58,944 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:59,052 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-01-31 10:20:59,053 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:59,053 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:59,058 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:20:59,071 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:59,084 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:20:59,094 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:59,095 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:59,199 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-01-31 10:20:59,215 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:59,215 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 9] total 14 [2018-01-31 10:20:59,216 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-01-31 10:20:59,216 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-01-31 10:20:59,216 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=144, Unknown=0, NotChecked=0, Total=182 [2018-01-31 10:20:59,216 INFO L87 Difference]: Start difference. First operand 104 states and 113 transitions. Second operand 14 states. [2018-01-31 10:20:59,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:20:59,531 INFO L93 Difference]: Finished difference Result 196 states and 214 transitions. [2018-01-31 10:20:59,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-01-31 10:20:59,531 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 78 [2018-01-31 10:20:59,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:20:59,532 INFO L225 Difference]: With dead ends: 196 [2018-01-31 10:20:59,532 INFO L226 Difference]: Without dead ends: 130 [2018-01-31 10:20:59,532 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=432, Unknown=0, NotChecked=0, Total=552 [2018-01-31 10:20:59,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-01-31 10:20:59,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 120. [2018-01-31 10:20:59,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-01-31 10:20:59,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-01-31 10:20:59,536 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 78 [2018-01-31 10:20:59,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:20:59,536 INFO L432 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-01-31 10:20:59,536 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-01-31 10:20:59,536 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-01-31 10:20:59,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-01-31 10:20:59,537 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:20:59,537 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:20:59,537 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolation]=== [2018-01-31 10:20:59,537 INFO L82 PathProgramCache]: Analyzing trace with hash 1052580941, now seen corresponding path program 3 times [2018-01-31 10:20:59,538 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:20:59,538 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:20:59,538 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:59,538 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:20:59,538 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:20:59,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:20:59,549 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:20:59,734 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-01-31 10:20:59,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:20:59,734 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:20:59,741 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:20:59,749 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:59,757 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:59,760 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:59,769 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:20:59,770 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:20:59,771 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:20:59,840 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:20:59,858 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:20:59,858 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 18 [2018-01-31 10:20:59,858 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-01-31 10:20:59,858 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-01-31 10:20:59,858 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=248, Unknown=0, NotChecked=0, Total=306 [2018-01-31 10:20:59,858 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 18 states. [2018-01-31 10:21:00,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:00,183 INFO L93 Difference]: Finished difference Result 220 states and 238 transitions. [2018-01-31 10:21:00,185 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-01-31 10:21:00,185 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 94 [2018-01-31 10:21:00,185 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:00,186 INFO L225 Difference]: With dead ends: 220 [2018-01-31 10:21:00,186 INFO L226 Difference]: Without dead ends: 146 [2018-01-31 10:21:00,186 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 158 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=200, Invalid=792, Unknown=0, NotChecked=0, Total=992 [2018-01-31 10:21:00,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-01-31 10:21:00,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 136. [2018-01-31 10:21:00,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-01-31 10:21:00,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 145 transitions. [2018-01-31 10:21:00,194 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 145 transitions. Word has length 94 [2018-01-31 10:21:00,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:00,194 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 145 transitions. [2018-01-31 10:21:00,194 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-01-31 10:21:00,194 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 145 transitions. [2018-01-31 10:21:00,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-01-31 10:21:00,195 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:00,195 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:00,195 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolation]=== [2018-01-31 10:21:00,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1204320937, now seen corresponding path program 4 times [2018-01-31 10:21:00,195 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:00,195 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:00,196 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:00,196 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:00,196 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:00,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:00,224 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:00,413 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:21:00,413 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:00,413 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:00,424 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:21:00,443 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:00,445 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:00,471 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:21:00,488 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:00,488 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 15 [2018-01-31 10:21:00,488 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-01-31 10:21:00,488 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-01-31 10:21:00,489 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=147, Unknown=0, NotChecked=0, Total=210 [2018-01-31 10:21:00,489 INFO L87 Difference]: Start difference. First operand 136 states and 145 transitions. Second operand 15 states. [2018-01-31 10:21:00,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:00,622 INFO L93 Difference]: Finished difference Result 231 states and 248 transitions. [2018-01-31 10:21:00,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-01-31 10:21:00,631 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 110 [2018-01-31 10:21:00,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:00,632 INFO L225 Difference]: With dead ends: 231 [2018-01-31 10:21:00,632 INFO L226 Difference]: Without dead ends: 149 [2018-01-31 10:21:00,633 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 103 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=196, Invalid=404, Unknown=0, NotChecked=0, Total=600 [2018-01-31 10:21:00,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-01-31 10:21:00,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 144. [2018-01-31 10:21:00,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-01-31 10:21:00,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2018-01-31 10:21:00,637 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 110 [2018-01-31 10:21:00,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:00,637 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2018-01-31 10:21:00,638 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-01-31 10:21:00,638 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2018-01-31 10:21:00,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-01-31 10:21:00,638 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:00,638 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 6, 5, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:00,638 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolation]=== [2018-01-31 10:21:00,639 INFO L82 PathProgramCache]: Analyzing trace with hash 2034864691, now seen corresponding path program 5 times [2018-01-31 10:21:00,639 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:00,639 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:00,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:00,639 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:00,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:00,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:00,652 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:00,773 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-01-31 10:21:00,773 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:00,773 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:00,778 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:21:00,784 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,801 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,811 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,824 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,838 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,855 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,874 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:00,880 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:00,882 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:01,133 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:21:01,150 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:01,150 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 24 [2018-01-31 10:21:01,151 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-01-31 10:21:01,151 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-01-31 10:21:01,151 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=455, Unknown=0, NotChecked=0, Total=552 [2018-01-31 10:21:01,151 INFO L87 Difference]: Start difference. First operand 144 states and 153 transitions. Second operand 24 states. [2018-01-31 10:21:01,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:01,572 INFO L93 Difference]: Finished difference Result 252 states and 270 transitions. [2018-01-31 10:21:01,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-01-31 10:21:01,576 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 118 [2018-01-31 10:21:01,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:01,577 INFO L225 Difference]: With dead ends: 252 [2018-01-31 10:21:01,577 INFO L226 Difference]: Without dead ends: 170 [2018-01-31 10:21:01,578 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 152 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 331 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2018-01-31 10:21:01,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-01-31 10:21:01,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 160. [2018-01-31 10:21:01,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-01-31 10:21:01,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 169 transitions. [2018-01-31 10:21:01,586 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 169 transitions. Word has length 118 [2018-01-31 10:21:01,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:01,586 INFO L432 AbstractCegarLoop]: Abstraction has 160 states and 169 transitions. [2018-01-31 10:21:01,586 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-01-31 10:21:01,586 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 169 transitions. [2018-01-31 10:21:01,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-01-31 10:21:01,586 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:01,587 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:01,587 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolation]=== [2018-01-31 10:21:01,587 INFO L82 PathProgramCache]: Analyzing trace with hash 1359274301, now seen corresponding path program 6 times [2018-01-31 10:21:01,587 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:01,587 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:01,588 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:01,588 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:01,588 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:01,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:01,606 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:01,805 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-01-31 10:21:01,805 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:01,805 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:01,811 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:21:01,818 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,820 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,823 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,825 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,830 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,851 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,865 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,904 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:01,905 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:01,907 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:02,090 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:02,109 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:02,109 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 13] total 28 [2018-01-31 10:21:02,110 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-01-31 10:21:02,110 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-01-31 10:21:02,110 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=629, Unknown=0, NotChecked=0, Total=756 [2018-01-31 10:21:02,110 INFO L87 Difference]: Start difference. First operand 160 states and 169 transitions. Second operand 28 states. [2018-01-31 10:21:02,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:02,681 INFO L93 Difference]: Finished difference Result 276 states and 294 transitions. [2018-01-31 10:21:02,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-01-31 10:21:02,683 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 134 [2018-01-31 10:21:02,683 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:02,683 INFO L225 Difference]: With dead ends: 276 [2018-01-31 10:21:02,683 INFO L226 Difference]: Without dead ends: 186 [2018-01-31 10:21:02,684 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 174 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=495, Invalid=2157, Unknown=0, NotChecked=0, Total=2652 [2018-01-31 10:21:02,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-01-31 10:21:02,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 176. [2018-01-31 10:21:02,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-01-31 10:21:02,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 185 transitions. [2018-01-31 10:21:02,698 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 185 transitions. Word has length 134 [2018-01-31 10:21:02,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:02,698 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 185 transitions. [2018-01-31 10:21:02,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-01-31 10:21:02,698 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 185 transitions. [2018-01-31 10:21:02,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2018-01-31 10:21:02,699 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:02,699 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:02,699 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolation]=== [2018-01-31 10:21:02,699 INFO L82 PathProgramCache]: Analyzing trace with hash -1132442041, now seen corresponding path program 7 times [2018-01-31 10:21:02,699 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:02,699 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:02,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:02,700 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:02,700 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:02,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:02,723 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:02,936 INFO L134 CoverageAnalysis]: Checked inductivity of 372 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:21:02,936 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:02,936 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:02,942 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:02,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:02,960 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:02,992 INFO L134 CoverageAnalysis]: Checked inductivity of 372 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:21:03,009 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:03,009 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 21 [2018-01-31 10:21:03,010 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-01-31 10:21:03,010 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-01-31 10:21:03,010 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-01-31 10:21:03,010 INFO L87 Difference]: Start difference. First operand 176 states and 185 transitions. Second operand 21 states. [2018-01-31 10:21:03,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:03,232 INFO L93 Difference]: Finished difference Result 287 states and 304 transitions. [2018-01-31 10:21:03,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-01-31 10:21:03,234 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 150 [2018-01-31 10:21:03,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:03,235 INFO L225 Difference]: With dead ends: 287 [2018-01-31 10:21:03,235 INFO L226 Difference]: Without dead ends: 189 [2018-01-31 10:21:03,236 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 149 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 244 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=427, Invalid=905, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:21:03,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-01-31 10:21:03,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 184. [2018-01-31 10:21:03,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-01-31 10:21:03,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 193 transitions. [2018-01-31 10:21:03,239 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 193 transitions. Word has length 150 [2018-01-31 10:21:03,239 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:03,239 INFO L432 AbstractCegarLoop]: Abstraction has 184 states and 193 transitions. [2018-01-31 10:21:03,239 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-01-31 10:21:03,239 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 193 transitions. [2018-01-31 10:21:03,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-01-31 10:21:03,240 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:03,240 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 9, 9, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:03,240 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolation]=== [2018-01-31 10:21:03,241 INFO L82 PathProgramCache]: Analyzing trace with hash -549761245, now seen corresponding path program 8 times [2018-01-31 10:21:03,241 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:03,241 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:03,241 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:03,241 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:03,241 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:03,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:03,251 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:03,462 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:21:03,462 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:03,462 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:03,474 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:21:03,487 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:03,501 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:03,503 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:03,505 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:03,536 INFO L134 CoverageAnalysis]: Checked inductivity of 438 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:21:03,553 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:03,553 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 23 [2018-01-31 10:21:03,553 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-01-31 10:21:03,554 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-01-31 10:21:03,554 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=143, Invalid=363, Unknown=0, NotChecked=0, Total=506 [2018-01-31 10:21:03,554 INFO L87 Difference]: Start difference. First operand 184 states and 193 transitions. Second operand 23 states. [2018-01-31 10:21:03,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:03,812 INFO L93 Difference]: Finished difference Result 295 states and 312 transitions. [2018-01-31 10:21:03,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-01-31 10:21:03,818 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 158 [2018-01-31 10:21:03,818 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:03,819 INFO L225 Difference]: With dead ends: 295 [2018-01-31 10:21:03,819 INFO L226 Difference]: Without dead ends: 197 [2018-01-31 10:21:03,819 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 196 GetRequests, 157 SyntacticMatches, 0 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 303 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=524, Invalid=1116, Unknown=0, NotChecked=0, Total=1640 [2018-01-31 10:21:03,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-01-31 10:21:03,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 192. [2018-01-31 10:21:03,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-01-31 10:21:03,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 201 transitions. [2018-01-31 10:21:03,822 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 201 transitions. Word has length 158 [2018-01-31 10:21:03,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:03,823 INFO L432 AbstractCegarLoop]: Abstraction has 192 states and 201 transitions. [2018-01-31 10:21:03,823 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-01-31 10:21:03,823 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 201 transitions. [2018-01-31 10:21:03,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-01-31 10:21:03,824 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:03,824 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 10, 10, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:03,824 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolation]=== [2018-01-31 10:21:03,824 INFO L82 PathProgramCache]: Analyzing trace with hash -2117749761, now seen corresponding path program 9 times [2018-01-31 10:21:03,824 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:03,824 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:03,825 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:03,825 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:03,825 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:03,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:03,833 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:04,267 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-01-31 10:21:04,268 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:04,268 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:04,273 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:21:04,281 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,284 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,287 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,300 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,320 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,366 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,419 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:04,420 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:04,422 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:04,730 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 74 proven. 132 refuted. 0 times theorem prover too weak. 306 trivial. 0 not checked. [2018-01-31 10:21:04,747 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:04,748 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 18] total 39 [2018-01-31 10:21:04,748 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-31 10:21:04,748 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-31 10:21:04,748 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=1238, Unknown=0, NotChecked=0, Total=1482 [2018-01-31 10:21:04,748 INFO L87 Difference]: Start difference. First operand 192 states and 201 transitions. Second operand 39 states. [2018-01-31 10:21:06,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:06,167 INFO L93 Difference]: Finished difference Result 316 states and 334 transitions. [2018-01-31 10:21:06,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-01-31 10:21:06,167 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 166 [2018-01-31 10:21:06,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:06,168 INFO L225 Difference]: With dead ends: 316 [2018-01-31 10:21:06,168 INFO L226 Difference]: Without dead ends: 218 [2018-01-31 10:21:06,170 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 230 GetRequests, 151 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1311 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1152, Invalid=5328, Unknown=0, NotChecked=0, Total=6480 [2018-01-31 10:21:06,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-01-31 10:21:06,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 208. [2018-01-31 10:21:06,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208 states. [2018-01-31 10:21:06,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 217 transitions. [2018-01-31 10:21:06,173 INFO L78 Accepts]: Start accepts. Automaton has 208 states and 217 transitions. Word has length 166 [2018-01-31 10:21:06,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:06,173 INFO L432 AbstractCegarLoop]: Abstraction has 208 states and 217 transitions. [2018-01-31 10:21:06,173 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-31 10:21:06,173 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 217 transitions. [2018-01-31 10:21:06,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-01-31 10:21:06,174 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:06,175 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 11, 11, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:06,175 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolation]=== [2018-01-31 10:21:06,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1814089481, now seen corresponding path program 10 times [2018-01-31 10:21:06,175 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:06,175 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:06,175 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:06,175 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:06,175 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:06,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:06,185 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:06,449 INFO L134 CoverageAnalysis]: Checked inductivity of 644 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:06,449 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:06,449 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:06,455 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:21:06,528 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:06,530 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:06,561 INFO L134 CoverageAnalysis]: Checked inductivity of 644 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:06,580 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:06,580 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 27 [2018-01-31 10:21:06,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-31 10:21:06,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-31 10:21:06,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=507, Unknown=0, NotChecked=0, Total=702 [2018-01-31 10:21:06,581 INFO L87 Difference]: Start difference. First operand 208 states and 217 transitions. Second operand 27 states. [2018-01-31 10:21:06,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:06,907 INFO L93 Difference]: Finished difference Result 327 states and 344 transitions. [2018-01-31 10:21:06,907 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-31 10:21:06,907 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 182 [2018-01-31 10:21:06,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:06,908 INFO L225 Difference]: With dead ends: 327 [2018-01-31 10:21:06,908 INFO L226 Difference]: Without dead ends: 221 [2018-01-31 10:21:06,909 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 181 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 439 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=748, Invalid=1604, Unknown=0, NotChecked=0, Total=2352 [2018-01-31 10:21:06,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states. [2018-01-31 10:21:06,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 216. [2018-01-31 10:21:06,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-01-31 10:21:06,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 225 transitions. [2018-01-31 10:21:06,912 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 225 transitions. Word has length 182 [2018-01-31 10:21:06,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:06,912 INFO L432 AbstractCegarLoop]: Abstraction has 216 states and 225 transitions. [2018-01-31 10:21:06,912 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-31 10:21:06,912 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 225 transitions. [2018-01-31 10:21:06,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2018-01-31 10:21:06,913 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:06,913 INFO L351 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 12, 12, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:06,913 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolation]=== [2018-01-31 10:21:06,913 INFO L82 PathProgramCache]: Analyzing trace with hash 138502117, now seen corresponding path program 11 times [2018-01-31 10:21:06,913 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:06,913 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:06,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:06,914 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:06,914 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:06,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:06,922 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:07,193 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:07,194 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:07,194 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:07,198 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:21:07,205 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,206 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,207 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,208 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,210 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,213 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,219 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,223 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,264 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,280 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,288 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,311 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,350 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:07,351 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:07,353 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:07,412 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:07,429 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:07,430 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 29 [2018-01-31 10:21:07,430 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-31 10:21:07,430 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-31 10:21:07,430 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=224, Invalid=588, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:21:07,430 INFO L87 Difference]: Start difference. First operand 216 states and 225 transitions. Second operand 29 states. [2018-01-31 10:21:07,821 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:07,821 INFO L93 Difference]: Finished difference Result 335 states and 352 transitions. [2018-01-31 10:21:07,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-31 10:21:07,822 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 190 [2018-01-31 10:21:07,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:07,822 INFO L225 Difference]: With dead ends: 335 [2018-01-31 10:21:07,822 INFO L226 Difference]: Without dead ends: 229 [2018-01-31 10:21:07,823 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 516 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=875, Invalid=1881, Unknown=0, NotChecked=0, Total=2756 [2018-01-31 10:21:07,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-01-31 10:21:07,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 224. [2018-01-31 10:21:07,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-01-31 10:21:07,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 233 transitions. [2018-01-31 10:21:07,826 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 233 transitions. Word has length 190 [2018-01-31 10:21:07,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:07,826 INFO L432 AbstractCegarLoop]: Abstraction has 224 states and 233 transitions. [2018-01-31 10:21:07,826 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-31 10:21:07,826 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 233 transitions. [2018-01-31 10:21:07,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-01-31 10:21:07,827 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:07,827 INFO L351 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 13, 13, 13, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:07,827 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolation]=== [2018-01-31 10:21:07,827 INFO L82 PathProgramCache]: Analyzing trace with hash 1839289537, now seen corresponding path program 12 times [2018-01-31 10:21:07,827 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:07,827 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:07,828 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:07,828 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:07,828 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:07,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:07,836 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:08,347 INFO L134 CoverageAnalysis]: Checked inductivity of 832 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:08,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:08,348 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:08,355 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:21:08,365 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,367 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,369 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,373 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,381 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,402 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,417 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,543 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,583 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,612 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,639 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:08,694 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:09,053 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:09,369 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:09,370 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:09,373 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:09,408 INFO L134 CoverageAnalysis]: Checked inductivity of 832 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:09,426 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:09,426 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 31 [2018-01-31 10:21:09,427 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-31 10:21:09,427 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-31 10:21:09,427 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=255, Invalid=675, Unknown=0, NotChecked=0, Total=930 [2018-01-31 10:21:09,427 INFO L87 Difference]: Start difference. First operand 224 states and 233 transitions. Second operand 31 states. [2018-01-31 10:21:09,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:09,789 INFO L93 Difference]: Finished difference Result 343 states and 360 transitions. [2018-01-31 10:21:09,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-31 10:21:09,800 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 198 [2018-01-31 10:21:09,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:09,801 INFO L225 Difference]: With dead ends: 343 [2018-01-31 10:21:09,801 INFO L226 Difference]: Without dead ends: 237 [2018-01-31 10:21:09,802 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 252 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 599 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1012, Invalid=2180, Unknown=0, NotChecked=0, Total=3192 [2018-01-31 10:21:09,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-01-31 10:21:09,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 232. [2018-01-31 10:21:09,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-01-31 10:21:09,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 241 transitions. [2018-01-31 10:21:09,807 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 241 transitions. Word has length 198 [2018-01-31 10:21:09,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:09,807 INFO L432 AbstractCegarLoop]: Abstraction has 232 states and 241 transitions. [2018-01-31 10:21:09,807 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-31 10:21:09,807 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 241 transitions. [2018-01-31 10:21:09,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-01-31 10:21:09,808 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:09,808 INFO L351 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 14, 14, 14, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:09,808 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolation]=== [2018-01-31 10:21:09,808 INFO L82 PathProgramCache]: Analyzing trace with hash -1466126947, now seen corresponding path program 13 times [2018-01-31 10:21:09,808 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:09,808 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:09,809 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:09,809 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:09,809 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:09,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:09,819 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:10,822 INFO L134 CoverageAnalysis]: Checked inductivity of 938 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:10,822 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:10,822 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:10,827 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:10,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:10,850 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:10,887 INFO L134 CoverageAnalysis]: Checked inductivity of 938 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:10,903 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:10,903 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 33 [2018-01-31 10:21:10,904 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-31 10:21:10,904 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-31 10:21:10,904 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=288, Invalid=768, Unknown=0, NotChecked=0, Total=1056 [2018-01-31 10:21:10,904 INFO L87 Difference]: Start difference. First operand 232 states and 241 transitions. Second operand 33 states. [2018-01-31 10:21:11,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:11,376 INFO L93 Difference]: Finished difference Result 351 states and 368 transitions. [2018-01-31 10:21:11,376 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-31 10:21:11,376 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 206 [2018-01-31 10:21:11,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:11,377 INFO L225 Difference]: With dead ends: 351 [2018-01-31 10:21:11,377 INFO L226 Difference]: Without dead ends: 245 [2018-01-31 10:21:11,378 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 264 GetRequests, 205 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 688 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1159, Invalid=2501, Unknown=0, NotChecked=0, Total=3660 [2018-01-31 10:21:11,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-01-31 10:21:11,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 240. [2018-01-31 10:21:11,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. [2018-01-31 10:21:11,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 249 transitions. [2018-01-31 10:21:11,381 INFO L78 Accepts]: Start accepts. Automaton has 240 states and 249 transitions. Word has length 206 [2018-01-31 10:21:11,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:11,381 INFO L432 AbstractCegarLoop]: Abstraction has 240 states and 249 transitions. [2018-01-31 10:21:11,381 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-31 10:21:11,381 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 249 transitions. [2018-01-31 10:21:11,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-01-31 10:21:11,382 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:11,382 INFO L351 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 15, 15, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:11,382 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolation]=== [2018-01-31 10:21:11,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1450218887, now seen corresponding path program 14 times [2018-01-31 10:21:11,382 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:11,382 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:11,382 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:11,382 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:11,382 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:11,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:11,391 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:12,138 INFO L134 CoverageAnalysis]: Checked inductivity of 1052 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:12,138 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:12,138 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:12,143 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:21:12,152 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:12,164 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:12,166 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:12,168 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:12,211 INFO L134 CoverageAnalysis]: Checked inductivity of 1052 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:12,229 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:12,229 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 35 [2018-01-31 10:21:12,230 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-31 10:21:12,230 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-31 10:21:12,230 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=323, Invalid=867, Unknown=0, NotChecked=0, Total=1190 [2018-01-31 10:21:12,230 INFO L87 Difference]: Start difference. First operand 240 states and 249 transitions. Second operand 35 states. [2018-01-31 10:21:12,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:12,728 INFO L93 Difference]: Finished difference Result 359 states and 376 transitions. [2018-01-31 10:21:12,729 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-31 10:21:12,729 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 214 [2018-01-31 10:21:12,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:12,730 INFO L225 Difference]: With dead ends: 359 [2018-01-31 10:21:12,730 INFO L226 Difference]: Without dead ends: 253 [2018-01-31 10:21:12,731 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 276 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 783 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1316, Invalid=2844, Unknown=0, NotChecked=0, Total=4160 [2018-01-31 10:21:12,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2018-01-31 10:21:12,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 248. [2018-01-31 10:21:12,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 248 states. [2018-01-31 10:21:12,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 248 states to 248 states and 257 transitions. [2018-01-31 10:21:12,737 INFO L78 Accepts]: Start accepts. Automaton has 248 states and 257 transitions. Word has length 214 [2018-01-31 10:21:12,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:12,737 INFO L432 AbstractCegarLoop]: Abstraction has 248 states and 257 transitions. [2018-01-31 10:21:12,738 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-31 10:21:12,738 INFO L276 IsEmpty]: Start isEmpty. Operand 248 states and 257 transitions. [2018-01-31 10:21:12,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 223 [2018-01-31 10:21:12,738 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:12,738 INFO L351 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 16, 16, 16, 8, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:12,738 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolation]=== [2018-01-31 10:21:12,738 INFO L82 PathProgramCache]: Analyzing trace with hash 1154845525, now seen corresponding path program 15 times [2018-01-31 10:21:12,739 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:12,739 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:12,739 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:12,739 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:12,739 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:12,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:12,759 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:13,281 INFO L134 CoverageAnalysis]: Checked inductivity of 1174 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2018-01-31 10:21:13,281 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:13,282 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:13,286 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:21:13,298 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,300 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,303 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,309 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,316 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,373 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,433 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,587 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:13,588 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:13,590 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:13,884 INFO L134 CoverageAnalysis]: Checked inductivity of 1174 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 992 trivial. 0 not checked. [2018-01-31 10:21:13,902 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:13,902 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 17] total 50 [2018-01-31 10:21:13,903 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-01-31 10:21:13,903 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-01-31 10:21:13,903 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=402, Invalid=2048, Unknown=0, NotChecked=0, Total=2450 [2018-01-31 10:21:13,903 INFO L87 Difference]: Start difference. First operand 248 states and 257 transitions. Second operand 50 states. [2018-01-31 10:21:15,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:15,017 INFO L93 Difference]: Finished difference Result 380 states and 398 transitions. [2018-01-31 10:21:15,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2018-01-31 10:21:15,017 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 222 [2018-01-31 10:21:15,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:15,018 INFO L225 Difference]: With dead ends: 380 [2018-01-31 10:21:15,018 INFO L226 Difference]: Without dead ends: 274 [2018-01-31 10:21:15,020 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 302 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1782 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1760, Invalid=7360, Unknown=0, NotChecked=0, Total=9120 [2018-01-31 10:21:15,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-01-31 10:21:15,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 264. [2018-01-31 10:21:15,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 264 states. [2018-01-31 10:21:15,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 273 transitions. [2018-01-31 10:21:15,023 INFO L78 Accepts]: Start accepts. Automaton has 264 states and 273 transitions. Word has length 222 [2018-01-31 10:21:15,023 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:15,023 INFO L432 AbstractCegarLoop]: Abstraction has 264 states and 273 transitions. [2018-01-31 10:21:15,023 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-01-31 10:21:15,023 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 273 transitions. [2018-01-31 10:21:15,023 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-01-31 10:21:15,024 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:15,024 INFO L351 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 17, 17, 17, 9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:15,024 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolation]=== [2018-01-31 10:21:15,024 INFO L82 PathProgramCache]: Analyzing trace with hash -634737569, now seen corresponding path program 16 times [2018-01-31 10:21:15,024 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:15,024 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:15,024 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:15,024 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:15,024 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:15,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:15,033 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:16,016 INFO L134 CoverageAnalysis]: Checked inductivity of 1362 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 240 trivial. 0 not checked. [2018-01-31 10:21:16,017 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:16,017 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:16,022 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:21:16,140 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:16,143 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:16,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1362 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 240 trivial. 0 not checked. [2018-01-31 10:21:16,209 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:16,209 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 39 [2018-01-31 10:21:16,209 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-31 10:21:16,209 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-31 10:21:16,210 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=399, Invalid=1083, Unknown=0, NotChecked=0, Total=1482 [2018-01-31 10:21:16,210 INFO L87 Difference]: Start difference. First operand 264 states and 273 transitions. Second operand 39 states. [2018-01-31 10:21:16,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:16,818 INFO L93 Difference]: Finished difference Result 391 states and 408 transitions. [2018-01-31 10:21:16,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-31 10:21:16,833 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 238 [2018-01-31 10:21:16,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:16,834 INFO L225 Difference]: With dead ends: 391 [2018-01-31 10:21:16,834 INFO L226 Difference]: Without dead ends: 277 [2018-01-31 10:21:16,835 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 308 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 991 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1660, Invalid=3596, Unknown=0, NotChecked=0, Total=5256 [2018-01-31 10:21:16,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-01-31 10:21:16,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 272. [2018-01-31 10:21:16,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 272 states. [2018-01-31 10:21:16,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 272 states to 272 states and 281 transitions. [2018-01-31 10:21:16,838 INFO L78 Accepts]: Start accepts. Automaton has 272 states and 281 transitions. Word has length 238 [2018-01-31 10:21:16,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:16,838 INFO L432 AbstractCegarLoop]: Abstraction has 272 states and 281 transitions. [2018-01-31 10:21:16,838 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-31 10:21:16,838 INFO L276 IsEmpty]: Start isEmpty. Operand 272 states and 281 transitions. [2018-01-31 10:21:16,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2018-01-31 10:21:16,839 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:16,839 INFO L351 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 18, 18, 18, 9, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:16,839 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolation]=== [2018-01-31 10:21:16,839 INFO L82 PathProgramCache]: Analyzing trace with hash 647166267, now seen corresponding path program 17 times [2018-01-31 10:21:16,839 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:16,839 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:16,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:16,840 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:16,840 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:16,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:16,861 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:17,489 INFO L134 CoverageAnalysis]: Checked inductivity of 1500 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 240 trivial. 0 not checked. [2018-01-31 10:21:17,489 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:17,489 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:17,494 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:21:17,507 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,508 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,509 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,511 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,513 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,514 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,517 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,519 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,523 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,526 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,534 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,543 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,551 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,625 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:17,700 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:18,065 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:18,259 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:18,360 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:19,476 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:19,479 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:19,485 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:19,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1500 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 1260 trivial. 0 not checked. [2018-01-31 10:21:19,852 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:19,852 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 19] total 56 [2018-01-31 10:21:19,852 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-01-31 10:21:19,853 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-01-31 10:21:19,853 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=497, Invalid=2583, Unknown=0, NotChecked=0, Total=3080 [2018-01-31 10:21:19,853 INFO L87 Difference]: Start difference. First operand 272 states and 281 transitions. Second operand 56 states. [2018-01-31 10:21:21,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:21,224 INFO L93 Difference]: Finished difference Result 412 states and 430 transitions. [2018-01-31 10:21:21,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2018-01-31 10:21:21,224 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 246 [2018-01-31 10:21:21,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:21,225 INFO L225 Difference]: With dead ends: 412 [2018-01-31 10:21:21,225 INFO L226 Difference]: Without dead ends: 298 [2018-01-31 10:21:21,227 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2283 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2205, Invalid=9351, Unknown=0, NotChecked=0, Total=11556 [2018-01-31 10:21:21,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states. [2018-01-31 10:21:21,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 288. [2018-01-31 10:21:21,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 288 states. [2018-01-31 10:21:21,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 288 states to 288 states and 297 transitions. [2018-01-31 10:21:21,233 INFO L78 Accepts]: Start accepts. Automaton has 288 states and 297 transitions. Word has length 246 [2018-01-31 10:21:21,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:21,233 INFO L432 AbstractCegarLoop]: Abstraction has 288 states and 297 transitions. [2018-01-31 10:21:21,233 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-01-31 10:21:21,243 INFO L276 IsEmpty]: Start isEmpty. Operand 288 states and 297 transitions. [2018-01-31 10:21:21,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 263 [2018-01-31 10:21:21,244 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:21,244 INFO L351 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 19, 19, 19, 10, 9, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:21,244 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolation]=== [2018-01-31 10:21:21,245 INFO L82 PathProgramCache]: Analyzing trace with hash 1727070277, now seen corresponding path program 18 times [2018-01-31 10:21:21,245 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:21,245 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:21,245 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:21,245 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:21,245 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:21,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:21,271 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:21,958 INFO L134 CoverageAnalysis]: Checked inductivity of 1712 backedges. 0 proven. 1406 refuted. 0 times theorem prover too weak. 306 trivial. 0 not checked. [2018-01-31 10:21:21,958 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:21,958 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:21,962 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:21:21,973 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:21,977 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:21,985 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:21,992 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:21,995 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,027 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,042 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,060 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,160 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,193 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,319 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:22,560 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:23,052 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:23,702 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:24,889 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:25,539 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:26,243 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:27,286 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:29,018 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:29,021 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:29,031 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:30,414 INFO L134 CoverageAnalysis]: Checked inductivity of 1712 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 1406 trivial. 0 not checked. [2018-01-31 10:21:30,435 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:30,435 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 21] total 60 [2018-01-31 10:21:30,436 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-01-31 10:21:30,436 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-01-31 10:21:30,436 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=559, Invalid=2981, Unknown=0, NotChecked=0, Total=3540 [2018-01-31 10:21:30,436 INFO L87 Difference]: Start difference. First operand 288 states and 297 transitions. Second operand 60 states. [2018-01-31 10:21:31,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:31,974 INFO L93 Difference]: Finished difference Result 431 states and 449 transitions. [2018-01-31 10:21:31,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2018-01-31 10:21:31,975 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 262 [2018-01-31 10:21:31,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:31,975 INFO L225 Difference]: With dead ends: 431 [2018-01-31 10:21:31,976 INFO L226 Difference]: Without dead ends: 309 [2018-01-31 10:21:31,977 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 358 GetRequests, 244 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2657 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=2495, Invalid=10845, Unknown=0, NotChecked=0, Total=13340 [2018-01-31 10:21:31,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states. [2018-01-31 10:21:31,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 304. [2018-01-31 10:21:31,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 304 states. [2018-01-31 10:21:31,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 304 states to 304 states and 313 transitions. [2018-01-31 10:21:31,980 INFO L78 Accepts]: Start accepts. Automaton has 304 states and 313 transitions. Word has length 262 [2018-01-31 10:21:31,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:31,980 INFO L432 AbstractCegarLoop]: Abstraction has 304 states and 313 transitions. [2018-01-31 10:21:31,980 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-01-31 10:21:31,980 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 313 transitions. [2018-01-31 10:21:31,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 279 [2018-01-31 10:21:31,981 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:31,981 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 11, 10, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:31,981 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolation]=== [2018-01-31 10:21:31,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1269357233, now seen corresponding path program 19 times [2018-01-31 10:21:31,982 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:31,982 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:31,982 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:31,982 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:31,982 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:31,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:31,996 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:32,426 INFO L134 CoverageAnalysis]: Checked inductivity of 1940 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:32,426 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:32,426 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:32,430 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:32,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:32,462 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:32,852 INFO L134 CoverageAnalysis]: Checked inductivity of 1940 backedges. 0 proven. 380 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:32,869 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:32,869 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 25 [2018-01-31 10:21:32,869 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-01-31 10:21:32,869 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-01-31 10:21:32,869 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=432, Unknown=0, NotChecked=0, Total=600 [2018-01-31 10:21:32,869 INFO L87 Difference]: Start difference. First operand 304 states and 313 transitions. Second operand 25 states. [2018-01-31 10:21:33,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:33,551 INFO L93 Difference]: Finished difference Result 346 states and 358 transitions. [2018-01-31 10:21:33,551 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-01-31 10:21:33,551 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 278 [2018-01-31 10:21:33,551 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:33,552 INFO L225 Difference]: With dead ends: 346 [2018-01-31 10:21:33,552 INFO L226 Difference]: Without dead ends: 317 [2018-01-31 10:21:33,552 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 320 GetRequests, 277 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 368 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=631, Invalid=1349, Unknown=0, NotChecked=0, Total=1980 [2018-01-31 10:21:33,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2018-01-31 10:21:33,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 312. [2018-01-31 10:21:33,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-01-31 10:21:33,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 321 transitions. [2018-01-31 10:21:33,556 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 321 transitions. Word has length 278 [2018-01-31 10:21:33,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:33,556 INFO L432 AbstractCegarLoop]: Abstraction has 312 states and 321 transitions. [2018-01-31 10:21:33,556 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-01-31 10:21:33,556 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 321 transitions. [2018-01-31 10:21:33,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-01-31 10:21:33,557 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:33,557 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 12, 11, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:33,557 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolation]=== [2018-01-31 10:21:33,557 INFO L82 PathProgramCache]: Analyzing trace with hash 215401341, now seen corresponding path program 20 times [2018-01-31 10:21:33,557 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:33,557 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:33,558 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:33,558 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:33,558 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:33,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:33,568 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:33,965 INFO L134 CoverageAnalysis]: Checked inductivity of 2022 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:33,965 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:33,965 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:33,970 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:21:33,981 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:33,997 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:34,000 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:34,002 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:34,119 INFO L134 CoverageAnalysis]: Checked inductivity of 2022 backedges. 0 proven. 462 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:34,135 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:34,136 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 27 [2018-01-31 10:21:34,136 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-01-31 10:21:34,136 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-01-31 10:21:34,136 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=507, Unknown=0, NotChecked=0, Total=702 [2018-01-31 10:21:34,136 INFO L87 Difference]: Start difference. First operand 312 states and 321 transitions. Second operand 27 states. [2018-01-31 10:21:34,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:34,489 INFO L93 Difference]: Finished difference Result 354 states and 366 transitions. [2018-01-31 10:21:34,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-01-31 10:21:34,490 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 286 [2018-01-31 10:21:34,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:34,491 INFO L225 Difference]: With dead ends: 354 [2018-01-31 10:21:34,491 INFO L226 Difference]: Without dead ends: 325 [2018-01-31 10:21:34,491 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 439 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=748, Invalid=1604, Unknown=0, NotChecked=0, Total=2352 [2018-01-31 10:21:34,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2018-01-31 10:21:34,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 320. [2018-01-31 10:21:34,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 320 states. [2018-01-31 10:21:34,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 320 states to 320 states and 329 transitions. [2018-01-31 10:21:34,495 INFO L78 Accepts]: Start accepts. Automaton has 320 states and 329 transitions. Word has length 286 [2018-01-31 10:21:34,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:34,495 INFO L432 AbstractCegarLoop]: Abstraction has 320 states and 329 transitions. [2018-01-31 10:21:34,495 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-01-31 10:21:34,495 INFO L276 IsEmpty]: Start isEmpty. Operand 320 states and 329 transitions. [2018-01-31 10:21:34,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-01-31 10:21:34,496 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:34,497 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 13, 12, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:34,497 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolation]=== [2018-01-31 10:21:34,501 INFO L82 PathProgramCache]: Analyzing trace with hash 1461998507, now seen corresponding path program 21 times [2018-01-31 10:21:34,501 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:34,501 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:34,501 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:34,501 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:34,501 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:34,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:34,511 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:34,975 INFO L134 CoverageAnalysis]: Checked inductivity of 2112 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:34,975 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:34,975 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:34,980 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:21:34,990 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,001 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,015 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,028 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,042 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,055 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,068 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,085 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,110 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,152 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,217 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,262 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,330 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:21:35,336 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:35,339 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:35,393 INFO L134 CoverageAnalysis]: Checked inductivity of 2112 backedges. 0 proven. 552 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:35,411 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:35,411 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 29 [2018-01-31 10:21:35,411 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-01-31 10:21:35,411 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-01-31 10:21:35,412 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=224, Invalid=588, Unknown=0, NotChecked=0, Total=812 [2018-01-31 10:21:35,412 INFO L87 Difference]: Start difference. First operand 320 states and 329 transitions. Second operand 29 states. [2018-01-31 10:21:35,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:35,743 INFO L93 Difference]: Finished difference Result 362 states and 374 transitions. [2018-01-31 10:21:35,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-01-31 10:21:35,743 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 294 [2018-01-31 10:21:35,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:35,744 INFO L225 Difference]: With dead ends: 362 [2018-01-31 10:21:35,744 INFO L226 Difference]: Without dead ends: 333 [2018-01-31 10:21:35,745 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 293 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 516 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=875, Invalid=1881, Unknown=0, NotChecked=0, Total=2756 [2018-01-31 10:21:35,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2018-01-31 10:21:35,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 328. [2018-01-31 10:21:35,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 328 states. [2018-01-31 10:21:35,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 337 transitions. [2018-01-31 10:21:35,748 INFO L78 Accepts]: Start accepts. Automaton has 328 states and 337 transitions. Word has length 294 [2018-01-31 10:21:35,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:35,748 INFO L432 AbstractCegarLoop]: Abstraction has 328 states and 337 transitions. [2018-01-31 10:21:35,748 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-01-31 10:21:35,748 INFO L276 IsEmpty]: Start isEmpty. Operand 328 states and 337 transitions. [2018-01-31 10:21:35,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 303 [2018-01-31 10:21:35,749 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:35,749 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 14, 13, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:35,749 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolation]=== [2018-01-31 10:21:35,749 INFO L82 PathProgramCache]: Analyzing trace with hash 657315289, now seen corresponding path program 22 times [2018-01-31 10:21:35,749 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:35,750 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:35,750 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:35,750 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:35,750 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:35,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:35,760 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:36,239 INFO L134 CoverageAnalysis]: Checked inductivity of 2210 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:36,239 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:36,239 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:36,244 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-01-31 10:21:36,793 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:36,796 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:36,940 INFO L134 CoverageAnalysis]: Checked inductivity of 2210 backedges. 0 proven. 650 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:36,958 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:36,958 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 31 [2018-01-31 10:21:36,959 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-01-31 10:21:36,959 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-01-31 10:21:36,959 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=255, Invalid=675, Unknown=0, NotChecked=0, Total=930 [2018-01-31 10:21:36,959 INFO L87 Difference]: Start difference. First operand 328 states and 337 transitions. Second operand 31 states. [2018-01-31 10:21:37,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:37,324 INFO L93 Difference]: Finished difference Result 370 states and 382 transitions. [2018-01-31 10:21:37,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-01-31 10:21:37,324 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 302 [2018-01-31 10:21:37,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:37,325 INFO L225 Difference]: With dead ends: 370 [2018-01-31 10:21:37,325 INFO L226 Difference]: Without dead ends: 341 [2018-01-31 10:21:37,325 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 356 GetRequests, 301 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 599 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1012, Invalid=2180, Unknown=0, NotChecked=0, Total=3192 [2018-01-31 10:21:37,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states. [2018-01-31 10:21:37,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 336. [2018-01-31 10:21:37,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 336 states. [2018-01-31 10:21:37,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 336 states to 336 states and 345 transitions. [2018-01-31 10:21:37,339 INFO L78 Accepts]: Start accepts. Automaton has 336 states and 345 transitions. Word has length 302 [2018-01-31 10:21:37,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:37,339 INFO L432 AbstractCegarLoop]: Abstraction has 336 states and 345 transitions. [2018-01-31 10:21:37,339 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-01-31 10:21:37,339 INFO L276 IsEmpty]: Start isEmpty. Operand 336 states and 345 transitions. [2018-01-31 10:21:37,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2018-01-31 10:21:37,340 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:37,341 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 15, 14, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:37,341 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolation]=== [2018-01-31 10:21:37,341 INFO L82 PathProgramCache]: Analyzing trace with hash 1122060807, now seen corresponding path program 23 times [2018-01-31 10:21:37,341 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:37,341 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:37,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:37,341 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:37,341 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:37,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:37,362 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:37,956 INFO L134 CoverageAnalysis]: Checked inductivity of 2316 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:37,956 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:37,956 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:37,961 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-01-31 10:21:37,971 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,972 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,973 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,974 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,976 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,978 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,981 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,985 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:37,996 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:38,022 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:38,069 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:38,223 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:38,409 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:38,561 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:39,142 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:39,496 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:39,668 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:40,222 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:40,293 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:41,078 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:43,603 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:43,609 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:43,617 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:43,700 INFO L134 CoverageAnalysis]: Checked inductivity of 2316 backedges. 0 proven. 756 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:43,723 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:43,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 33 [2018-01-31 10:21:43,723 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-01-31 10:21:43,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-01-31 10:21:43,724 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=288, Invalid=768, Unknown=0, NotChecked=0, Total=1056 [2018-01-31 10:21:43,724 INFO L87 Difference]: Start difference. First operand 336 states and 345 transitions. Second operand 33 states. [2018-01-31 10:21:44,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:44,139 INFO L93 Difference]: Finished difference Result 378 states and 390 transitions. [2018-01-31 10:21:44,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-01-31 10:21:44,140 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 310 [2018-01-31 10:21:44,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:44,141 INFO L225 Difference]: With dead ends: 378 [2018-01-31 10:21:44,141 INFO L226 Difference]: Without dead ends: 349 [2018-01-31 10:21:44,141 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 368 GetRequests, 309 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 688 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1159, Invalid=2501, Unknown=0, NotChecked=0, Total=3660 [2018-01-31 10:21:44,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states. [2018-01-31 10:21:44,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 344. [2018-01-31 10:21:44,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 344 states. [2018-01-31 10:21:44,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 344 states to 344 states and 353 transitions. [2018-01-31 10:21:44,155 INFO L78 Accepts]: Start accepts. Automaton has 344 states and 353 transitions. Word has length 310 [2018-01-31 10:21:44,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:44,155 INFO L432 AbstractCegarLoop]: Abstraction has 344 states and 353 transitions. [2018-01-31 10:21:44,155 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-01-31 10:21:44,155 INFO L276 IsEmpty]: Start isEmpty. Operand 344 states and 353 transitions. [2018-01-31 10:21:44,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 319 [2018-01-31 10:21:44,157 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:44,157 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 16, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:44,157 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolation]=== [2018-01-31 10:21:44,157 INFO L82 PathProgramCache]: Analyzing trace with hash -1574129611, now seen corresponding path program 24 times [2018-01-31 10:21:44,157 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:44,157 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:44,157 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:44,157 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:44,158 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:44,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:44,178 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:44,869 INFO L134 CoverageAnalysis]: Checked inductivity of 2430 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:44,869 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:44,869 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:44,874 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-01-31 10:21:44,885 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:44,891 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:44,894 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:44,897 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:44,909 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:44,920 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:44,968 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:45,041 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:45,079 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:45,163 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:45,339 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:45,831 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:46,437 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:46,890 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:47,789 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:49,166 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:51,013 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:52,143 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:53,168 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:55,623 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:56,940 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-01-31 10:21:56,942 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:56,952 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:57,015 INFO L134 CoverageAnalysis]: Checked inductivity of 2430 backedges. 0 proven. 870 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:57,035 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:57,035 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 35 [2018-01-31 10:21:57,035 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-01-31 10:21:57,036 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-01-31 10:21:57,036 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=323, Invalid=867, Unknown=0, NotChecked=0, Total=1190 [2018-01-31 10:21:57,036 INFO L87 Difference]: Start difference. First operand 344 states and 353 transitions. Second operand 35 states. [2018-01-31 10:21:57,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:57,503 INFO L93 Difference]: Finished difference Result 386 states and 398 transitions. [2018-01-31 10:21:57,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-01-31 10:21:57,503 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 318 [2018-01-31 10:21:57,504 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:57,504 INFO L225 Difference]: With dead ends: 386 [2018-01-31 10:21:57,504 INFO L226 Difference]: Without dead ends: 357 [2018-01-31 10:21:57,505 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 380 GetRequests, 317 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 783 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1316, Invalid=2844, Unknown=0, NotChecked=0, Total=4160 [2018-01-31 10:21:57,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2018-01-31 10:21:57,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 352. [2018-01-31 10:21:57,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 352 states. [2018-01-31 10:21:57,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 352 states to 352 states and 361 transitions. [2018-01-31 10:21:57,508 INFO L78 Accepts]: Start accepts. Automaton has 352 states and 361 transitions. Word has length 318 [2018-01-31 10:21:57,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:57,508 INFO L432 AbstractCegarLoop]: Abstraction has 352 states and 361 transitions. [2018-01-31 10:21:57,509 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-01-31 10:21:57,509 INFO L276 IsEmpty]: Start isEmpty. Operand 352 states and 361 transitions. [2018-01-31 10:21:57,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 327 [2018-01-31 10:21:57,510 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:57,510 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 17, 16, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:57,510 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolation]=== [2018-01-31 10:21:57,510 INFO L82 PathProgramCache]: Analyzing trace with hash 1862142051, now seen corresponding path program 25 times [2018-01-31 10:21:57,510 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:57,510 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:57,510 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:57,510 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:21:57,511 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:57,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:57,521 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:58,101 INFO L134 CoverageAnalysis]: Checked inductivity of 2552 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:58,101 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:58,101 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:58,107 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:58,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:58,139 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:58,215 INFO L134 CoverageAnalysis]: Checked inductivity of 2552 backedges. 0 proven. 992 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:58,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:58,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 37 [2018-01-31 10:21:58,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-01-31 10:21:58,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-01-31 10:21:58,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=360, Invalid=972, Unknown=0, NotChecked=0, Total=1332 [2018-01-31 10:21:58,233 INFO L87 Difference]: Start difference. First operand 352 states and 361 transitions. Second operand 37 states. [2018-01-31 10:21:58,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:21:58,761 INFO L93 Difference]: Finished difference Result 394 states and 406 transitions. [2018-01-31 10:21:58,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-01-31 10:21:58,761 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 326 [2018-01-31 10:21:58,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:21:58,762 INFO L225 Difference]: With dead ends: 394 [2018-01-31 10:21:58,762 INFO L226 Difference]: Without dead ends: 365 [2018-01-31 10:21:58,762 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 325 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 884 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1483, Invalid=3209, Unknown=0, NotChecked=0, Total=4692 [2018-01-31 10:21:58,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 365 states. [2018-01-31 10:21:58,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 365 to 360. [2018-01-31 10:21:58,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2018-01-31 10:21:58,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 369 transitions. [2018-01-31 10:21:58,766 INFO L78 Accepts]: Start accepts. Automaton has 360 states and 369 transitions. Word has length 326 [2018-01-31 10:21:58,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:21:58,767 INFO L432 AbstractCegarLoop]: Abstraction has 360 states and 369 transitions. [2018-01-31 10:21:58,767 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-01-31 10:21:58,767 INFO L276 IsEmpty]: Start isEmpty. Operand 360 states and 369 transitions. [2018-01-31 10:21:58,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 335 [2018-01-31 10:21:58,768 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:21:58,768 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 18, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:21:58,768 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolation]=== [2018-01-31 10:21:58,768 INFO L82 PathProgramCache]: Analyzing trace with hash 88298129, now seen corresponding path program 26 times [2018-01-31 10:21:58,768 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:21:58,768 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:21:58,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:58,769 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-01-31 10:21:58,769 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:21:58,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:21:58,779 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:21:59,384 INFO L134 CoverageAnalysis]: Checked inductivity of 2682 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:59,384 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:21:59,384 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:21:59,389 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-01-31 10:21:59,401 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:59,420 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-01-31 10:21:59,434 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:21:59,436 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:21:59,802 INFO L134 CoverageAnalysis]: Checked inductivity of 2682 backedges. 0 proven. 1122 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:21:59,821 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:21:59,821 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 39 [2018-01-31 10:21:59,822 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-01-31 10:21:59,822 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-01-31 10:21:59,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=399, Invalid=1083, Unknown=0, NotChecked=0, Total=1482 [2018-01-31 10:21:59,822 INFO L87 Difference]: Start difference. First operand 360 states and 369 transitions. Second operand 39 states. [2018-01-31 10:22:00,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:22:00,374 INFO L93 Difference]: Finished difference Result 402 states and 414 transitions. [2018-01-31 10:22:00,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-01-31 10:22:00,374 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 334 [2018-01-31 10:22:00,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:22:00,375 INFO L225 Difference]: With dead ends: 402 [2018-01-31 10:22:00,375 INFO L226 Difference]: Without dead ends: 373 [2018-01-31 10:22:00,376 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 333 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 991 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1660, Invalid=3596, Unknown=0, NotChecked=0, Total=5256 [2018-01-31 10:22:00,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 373 states. [2018-01-31 10:22:00,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 373 to 368. [2018-01-31 10:22:00,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-01-31 10:22:00,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 377 transitions. [2018-01-31 10:22:00,386 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 377 transitions. Word has length 334 [2018-01-31 10:22:00,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:22:00,387 INFO L432 AbstractCegarLoop]: Abstraction has 368 states and 377 transitions. [2018-01-31 10:22:00,387 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-01-31 10:22:00,387 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 377 transitions. [2018-01-31 10:22:00,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 343 [2018-01-31 10:22:00,388 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:22:00,388 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 19, 18, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:22:00,388 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolation]=== [2018-01-31 10:22:00,388 INFO L82 PathProgramCache]: Analyzing trace with hash -219509057, now seen corresponding path program 27 times [2018-01-31 10:22:00,388 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:22:00,388 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:22:00,389 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:22:00,389 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:22:00,389 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:22:00,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-01-31 10:22:00,406 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-01-31 10:22:01,050 INFO L134 CoverageAnalysis]: Checked inductivity of 2820 backedges. 0 proven. 1260 refuted. 0 times theorem prover too weak. 1560 trivial. 0 not checked. [2018-01-31 10:22:01,050 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-01-31 10:22:01,051 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-01-31 10:22:01,056 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-01-31 10:22:01,067 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,070 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,077 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,088 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,097 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,138 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,157 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,224 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,413 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,629 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:01,845 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:02,165 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:02,419 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:02,742 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:03,113 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:03,359 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:03,524 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:04,618 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:05,381 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-01-31 10:22:05,383 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-01-31 10:22:05,389 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-01-31 10:22:05,560 INFO L134 CoverageAnalysis]: Checked inductivity of 2820 backedges. 154 proven. 1260 refuted. 0 times theorem prover too weak. 1406 trivial. 0 not checked. [2018-01-31 10:22:05,580 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-01-31 10:22:05,580 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 42] total 44 [2018-01-31 10:22:05,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-01-31 10:22:05,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-01-31 10:22:05,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=1445, Unknown=0, NotChecked=0, Total=1892 [2018-01-31 10:22:05,581 INFO L87 Difference]: Start difference. First operand 368 states and 377 transitions. Second operand 44 states. [2018-01-31 10:22:07,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-01-31 10:22:07,553 INFO L93 Difference]: Finished difference Result 405 states and 417 transitions. [2018-01-31 10:22:07,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-01-31 10:22:07,554 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 342 [2018-01-31 10:22:07,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-01-31 10:22:07,555 INFO L225 Difference]: With dead ends: 405 [2018-01-31 10:22:07,555 INFO L226 Difference]: Without dead ends: 376 [2018-01-31 10:22:07,556 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 437 GetRequests, 338 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2370 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2679, Invalid=7421, Unknown=0, NotChecked=0, Total=10100 [2018-01-31 10:22:07,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 376 states. [2018-01-31 10:22:07,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 376 to 376. [2018-01-31 10:22:07,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 376 states. [2018-01-31 10:22:07,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 385 transitions. [2018-01-31 10:22:07,559 INFO L78 Accepts]: Start accepts. Automaton has 376 states and 385 transitions. Word has length 342 [2018-01-31 10:22:07,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-01-31 10:22:07,559 INFO L432 AbstractCegarLoop]: Abstraction has 376 states and 385 transitions. [2018-01-31 10:22:07,559 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-01-31 10:22:07,559 INFO L276 IsEmpty]: Start isEmpty. Operand 376 states and 385 transitions. [2018-01-31 10:22:07,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 351 [2018-01-31 10:22:07,560 INFO L343 BasicCegarLoop]: Found error trace [2018-01-31 10:22:07,560 INFO L351 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-01-31 10:22:07,561 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolation]=== [2018-01-31 10:22:07,561 INFO L82 PathProgramCache]: Analyzing trace with hash -136200979, now seen corresponding path program 28 times [2018-01-31 10:22:07,561 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-01-31 10:22:07,561 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-01-31 10:22:07,561 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:22:07,561 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-01-31 10:22:07,561 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-01-31 10:22:07,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:22:07,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-01-31 10:22:07,753 INFO L410 BasicCegarLoop]: Counterexample might be feasible [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [389] [389] ULTIMATE.startENTRY-->L1: Formula: true InVars {} OutVars{#NULL.offset=|v_#NULL.offset_2|, #NULL.base=|v_#NULL.base_2|, #valid=|v_#valid_3|} AuxVars[] AssignedVars[#valid, #NULL.offset, #NULL.base] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [395] [395] L1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [401] [401] mainENTRY-->L20: Formula: (and (not (= 0 |v_main_~#x~5.base_1|)) (= |v_#length_3| (store |v_#length_4| |v_main_~#x~5.base_1| 80)) (= |v_main_~#x~5.offset_1| 0) (= (store |v_#valid_8| |v_main_~#x~5.base_1| 1) |v_#valid_7|) (= 0 (select |v_#valid_8| |v_main_~#x~5.base_1|))) InVars {#length=|v_#length_4|, #valid=|v_#valid_8|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_1|, #length=|v_#length_3|, main_~#x~5.offset=|v_main_~#x~5.offset_1|, #valid=|v_#valid_7|} AuxVars[] AssignedVars[main_~#x~5.base, main_~#x~5.offset, #valid, #length] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [405] [405] L20-->L22: Formula: true InVars {} OutVars{main_~temp~5=v_main_~temp~5_1} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [409] [409] L22-->L23: Formula: true InVars {} OutVars{main_~ret~5=v_main_~ret~5_1} AuxVars[] AssignedVars[main_~ret~5] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [411] [411] L23-->L24: Formula: true InVars {} OutVars{main_~ret2~5=v_main_~ret2~5_1} AuxVars[] AssignedVars[main_~ret2~5] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [413] [413] L24-->L26: Formula: true InVars {} OutVars{main_~ret5~5=v_main_~ret5~5_1} AuxVars[] AssignedVars[main_~ret5~5] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [415] [415] L26-->L26'''''': Formula: (= v_main_~i~6_1 0) InVars {} OutVars{main_~i~6=v_main_~i~6_1} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,755 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,756 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,757 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,758 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,759 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,760 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,761 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,762 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,763 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,764 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [423] [423] L26'-->L27: Formula: (< v_main_~i~6_3 20) InVars {main_~i~6=v_main_~i~6_3} OutVars{main_~i~6=v_main_~i~6_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [429] [429] L27-->L27': Formula: (and (<= |v_main_#t~nondet5_1| 2147483647) (<= 0 (+ |v_main_#t~nondet5_1| 2147483648))) InVars {main_#t~nondet5=|v_main_#t~nondet5_1|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_1|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [435] [435] L27'-->L27'': Formula: (= |v_#memory_int_part_locs_87_locs_92_1| (store |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2| (store (select |v_#memory_int_part_locs_87_locs_92_2| |v_main_~#x~5.base_2|) (+ (* 4 v_main_~i~6_4) |v_main_~#x~5.offset_2|) |v_main_#t~nondet5_2|))) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_2|, main_~i~6=v_main_~i~6_4, main_~#x~5.offset=|v_main_~#x~5.offset_2|} OutVars{main_#t~nondet5=|v_main_#t~nondet5_2|, main_~#x~5.base=|v_main_~#x~5.base_2|, main_~#x~5.offset=|v_main_~#x~5.offset_2|, #memory_int=|v_#memory_int_3|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_1|, main_~i~6=v_main_~i~6_4} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [441] [441] L27''-->L26''': Formula: true InVars {} OutVars{main_#t~nondet5=|v_main_#t~nondet5_3|} AuxVars[] AssignedVars[main_#t~nondet5] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [447] [447] L26'''-->L26'''': Formula: (= |v_main_#t~post4_1| v_main_~i~6_5) InVars {main_~i~6=v_main_~i~6_5} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~6=v_main_~i~6_5} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [455] [455] L26''''-->L26''''': Formula: (= v_main_~i~6_6 (+ |v_main_#t~post4_2| 1)) InVars {main_#t~post4=|v_main_#t~post4_2|} OutVars{main_#t~post4=|v_main_#t~post4_2|, main_~i~6=v_main_~i~6_6} AuxVars[] AssignedVars[main_~i~6] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [465] [465] L26'''''-->L26'''''': Formula: true InVars {} OutVars{main_#t~post4=|v_main_#t~post4_3|} AuxVars[] AssignedVars[main_#t~post4] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [417] [417] L26''''''-->L26': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [421] [421] L26'-->L26''''''': Formula: (not (< v_main_~i~6_2 20)) InVars {main_~i~6=v_main_~i~6_2} OutVars{main_~i~6=v_main_~i~6_2} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [425] [425] L26'''''''-->L30: Formula: true InVars {} OutVars{main_#t~ret7=|v_main_#t~ret7_1|} AuxVars[] AssignedVars[main_#t~ret7] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [431] [431] L30-->L30': Formula: (and (<= |v_main_#t~ret7_2| 2147483647) (<= 0 (+ |v_main_#t~ret7_2| 2147483648))) InVars {main_#t~ret7=|v_main_#t~ret7_2|} OutVars{main_#t~ret7=|v_main_#t~ret7_2|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [437] [437] L30'-->L30'': Formula: (= v_main_~ret~5_2 |v_main_#t~ret7_3|) InVars {main_#t~ret7=|v_main_#t~ret7_3|} OutVars{main_#t~ret7=|v_main_#t~ret7_3|, main_~ret~5=v_main_~ret~5_2} AuxVars[] AssignedVars[main_~ret~5] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [443] [443] L30''-->L32: Formula: true InVars {} OutVars{main_#t~ret7=|v_main_#t~ret7_4|} AuxVars[] AssignedVars[main_#t~ret7] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [449] [449] L32-->L32': Formula: (= |v_main_#t~mem8_1| (select (select |v_#memory_int_part_locs_87_locs_92_3| |v_main_~#x~5.base_4|) |v_main_~#x~5.offset_4|)) InVars {main_~#x~5.base=|v_main_~#x~5.base_4|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_3|, main_~#x~5.offset=|v_main_~#x~5.offset_4|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_4|, main_#t~mem8=|v_main_#t~mem8_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_3|, main_~#x~5.offset=|v_main_~#x~5.offset_4|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [457] [457] L32'-->L32'': Formula: (= v_main_~temp~5_2 |v_main_#t~mem8_2|) InVars {main_#t~mem8=|v_main_#t~mem8_2|} OutVars{main_~temp~5=v_main_~temp~5_2, main_#t~mem8=|v_main_#t~mem8_2|} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [467] [467] L32''-->L32''': Formula: true InVars {} OutVars{main_#t~mem8=|v_main_#t~mem8_3|} AuxVars[] AssignedVars[main_#t~mem8] [2018-01-31 10:22:07,765 INFO L84 mationBacktranslator]: Skipped ATE [473] [473] L32'''-->L32'''': Formula: (= |v_main_#t~mem10_1| (select (select |v_#memory_int_part_locs_87_locs_92_5| |v_main_~#x~5.base_5|) (+ |v_main_~#x~5.offset_5| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_5|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_5|, main_~#x~5.offset=|v_main_~#x~5.offset_5|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_5|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_5|, main_#t~mem10=|v_main_#t~mem10_1|, main_~#x~5.offset=|v_main_~#x~5.offset_5|} AuxVars[] AssignedVars[main_#t~mem10] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [479] [479] L32''''-->L32''''': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_6| |v_main_~#x~5.base_6| (store (select |v_#memory_int_part_locs_87_locs_92_6| |v_main_~#x~5.base_6|) |v_main_~#x~5.offset_6| |v_main_#t~mem10_2|)) |v_#memory_int_part_locs_87_locs_92_7|) InVars {main_~#x~5.base=|v_main_~#x~5.base_6|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_6|, main_#t~mem10=|v_main_#t~mem10_2|, main_~#x~5.offset=|v_main_~#x~5.offset_6|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_6|, #memory_int=|v_#memory_int_7|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_7|, main_#t~mem10=|v_main_#t~mem10_2|, main_~#x~5.offset=|v_main_~#x~5.offset_6|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [489] [489] L32'''''-->L32'''''': Formula: true InVars {} OutVars{main_#t~mem10=|v_main_#t~mem10_3|} AuxVars[] AssignedVars[main_#t~mem10] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [499] [499] L32''''''-->L32''''''': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_8| |v_main_~#x~5.base_7| (store (select |v_#memory_int_part_locs_87_locs_92_8| |v_main_~#x~5.base_7|) (+ |v_main_~#x~5.offset_7| 4) v_main_~temp~5_3)) |v_#memory_int_part_locs_87_locs_92_9|) InVars {main_~#x~5.base=|v_main_~#x~5.base_7|, main_~temp~5=v_main_~temp~5_3, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_8|, main_~#x~5.offset=|v_main_~#x~5.offset_7|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_7|, #memory_int=|v_#memory_int_9|, main_~temp~5=v_main_~temp~5_3, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_9|, main_~#x~5.offset=|v_main_~#x~5.offset_7|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [509] [509] L32'''''''-->L33: Formula: true InVars {} OutVars{main_#t~ret12=|v_main_#t~ret12_1|} AuxVars[] AssignedVars[main_#t~ret12] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [485] [485] L33-->L33': Formula: (and (<= 0 (+ |v_main_#t~ret12_2| 2147483648)) (<= |v_main_#t~ret12_2| 2147483647)) InVars {main_#t~ret12=|v_main_#t~ret12_2|} OutVars{main_#t~ret12=|v_main_#t~ret12_2|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [495] [495] L33'-->L33'': Formula: (= v_main_~ret2~5_2 |v_main_#t~ret12_3|) InVars {main_#t~ret12=|v_main_#t~ret12_3|} OutVars{main_#t~ret12=|v_main_#t~ret12_3|, main_~ret2~5=v_main_~ret2~5_2} AuxVars[] AssignedVars[main_~ret2~5] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [505] [505] L33''-->L34: Formula: true InVars {} OutVars{main_#t~ret12=|v_main_#t~ret12_4|} AuxVars[] AssignedVars[main_#t~ret12] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [517] [517] L34-->L34': Formula: (= (select (select |v_#memory_int_part_locs_87_locs_92_10| |v_main_~#x~5.base_9|) |v_main_~#x~5.offset_9|) |v_main_#t~mem13_1|) InVars {main_~#x~5.base=|v_main_~#x~5.base_9|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_10|, main_~#x~5.offset=|v_main_~#x~5.offset_9|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_10|, main_~#x~5.offset=|v_main_~#x~5.offset_9|} AuxVars[] AssignedVars[main_#t~mem13] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [525] [525] L34'-->L34'': Formula: (= v_main_~temp~5_4 |v_main_#t~mem13_2|) InVars {main_#t~mem13=|v_main_#t~mem13_2|} OutVars{main_~temp~5=v_main_~temp~5_4, main_#t~mem13=|v_main_#t~mem13_2|} AuxVars[] AssignedVars[main_~temp~5] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [535] [535] L34''-->L35: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|} AuxVars[] AssignedVars[main_#t~mem13] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [541] [541] L35-->L35'''''': Formula: (= v_main_~i~7_1 0) InVars {} OutVars{main_~i~7=v_main_~i~7_1} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,766 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,767 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,768 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,769 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,770 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,771 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,772 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,773 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,774 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [553] [553] L35'-->L36: Formula: (< v_main_~i~7_3 19) InVars {main_~i~7=v_main_~i~7_3} OutVars{main_~i~7=v_main_~i~7_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [557] [557] L36-->L36': Formula: (= |v_main_#t~mem16_1| (select (select |v_#memory_int_part_locs_87_locs_92_13| |v_main_~#x~5.base_10|) (+ (* 4 v_main_~i~7_4) |v_main_~#x~5.offset_10| 4))) InVars {main_~#x~5.base=|v_main_~#x~5.base_10|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} OutVars{main_~#x~5.base=|v_main_~#x~5.base_10|, main_#t~mem16=|v_main_#t~mem16_1|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_13|, main_~#x~5.offset=|v_main_~#x~5.offset_10|, main_~i~7=v_main_~i~7_4} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [563] [563] L36'-->L36'': Formula: (= (store |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11| (store (select |v_#memory_int_part_locs_87_locs_92_14| |v_main_~#x~5.base_11|) (+ (* 4 v_main_~i~7_5) |v_main_~#x~5.offset_11|) |v_main_#t~mem16_2|)) |v_#memory_int_part_locs_87_locs_92_15|) InVars {main_~#x~5.base=|v_main_~#x~5.base_11|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_14|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, main_~i~7=v_main_~i~7_5} OutVars{main_~#x~5.base=|v_main_~#x~5.base_11|, main_~#x~5.offset=|v_main_~#x~5.offset_11|, #memory_int=|v_#memory_int_13|, main_#t~mem16=|v_main_#t~mem16_2|, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_15|, main_~i~7=v_main_~i~7_5} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [565] [565] L36''-->L35''': Formula: true InVars {} OutVars{main_#t~mem16=|v_main_#t~mem16_3|} AuxVars[] AssignedVars[main_#t~mem16] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [567] [567] L35'''-->L35'''': Formula: (= |v_main_#t~post14_1| v_main_~i~7_6) InVars {main_~i~7=v_main_~i~7_6} OutVars{main_#t~post14=|v_main_#t~post14_1|, main_~i~7=v_main_~i~7_6} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [569] [569] L35''''-->L35''''': Formula: (= v_main_~i~7_7 (+ |v_main_#t~post14_2| 1)) InVars {main_#t~post14=|v_main_#t~post14_2|} OutVars{main_~i~7=v_main_~i~7_7, main_#t~post14=|v_main_#t~post14_2|} AuxVars[] AssignedVars[main_~i~7] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [571] [571] L35'''''-->L35'''''': Formula: true InVars {} OutVars{main_#t~post14=|v_main_#t~post14_3|} AuxVars[] AssignedVars[main_#t~post14] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [545] [545] L35''''''-->L35': Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [551] [551] L35'-->L35''''''': Formula: (not (< v_main_~i~7_2 19)) InVars {main_~i~7=v_main_~i~7_2} OutVars{main_~i~7=v_main_~i~7_2} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [555] [555] L35'''''''-->L38: Formula: (= (store |v_#memory_int_part_locs_87_locs_92_11| |v_main_~#x~5.base_12| (store (select |v_#memory_int_part_locs_87_locs_92_11| |v_main_~#x~5.base_12|) (+ |v_main_~#x~5.offset_12| 76) v_main_~temp~5_5)) |v_#memory_int_part_locs_87_locs_92_12|) InVars {main_~#x~5.base=|v_main_~#x~5.base_12|, main_~temp~5=v_main_~temp~5_5, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_11|, main_~#x~5.offset=|v_main_~#x~5.offset_12|} OutVars{main_~#x~5.base=|v_main_~#x~5.base_12|, #memory_int=|v_#memory_int_15|, main_~temp~5=v_main_~temp~5_5, #memory_int_part_locs_87_locs_92=|v_#memory_int_part_locs_87_locs_92_12|, main_~#x~5.offset=|v_main_~#x~5.offset_12|} AuxVars[] AssignedVars[#memory_int, #memory_int_part_locs_87_locs_92] [2018-01-31 10:22:07,775 INFO L84 mationBacktranslator]: Skipped ATE [559] [559] L38-->L39: Formula: true InVars {} OutVars{main_#t~ret18=|v_main_#t~ret18_1|} AuxVars[] AssignedVars[main_#t~ret18] [2018-01-31 10:22:07,776 INFO L84 mationBacktranslator]: Skipped ATE [487] [487] L39-->L39': Formula: (and (<= |v_main_#t~ret18_2| 2147483647) (<= 0 (+ |v_main_#t~ret18_2| 2147483648))) InVars {main_#t~ret18=|v_main_#t~ret18_2|} OutVars{main_#t~ret18=|v_main_#t~ret18_2|} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,776 INFO L84 mationBacktranslator]: Skipped ATE [497] [497] L39'-->L39'': Formula: (= v_main_~ret5~5_2 |v_main_#t~ret18_3|) InVars {main_#t~ret18=|v_main_#t~ret18_3|} OutVars{main_#t~ret18=|v_main_#t~ret18_3|, main_~ret5~5=v_main_~ret5~5_2} AuxVars[] AssignedVars[main_~ret5~5] [2018-01-31 10:22:07,776 INFO L84 mationBacktranslator]: Skipped ATE [507] [507] L39''-->L41: Formula: true InVars {} OutVars{main_#t~ret18=|v_main_#t~ret18_4|} AuxVars[] AssignedVars[main_#t~ret18] [2018-01-31 10:22:07,776 INFO L84 mationBacktranslator]: Skipped ATE [519] [519] L41-->L42: Formula: (or (not (= v_main_~ret2~5_3 v_main_~ret~5_3)) (not (= v_main_~ret5~5_3 v_main_~ret~5_3))) InVars {main_~ret~5=v_main_~ret~5_3, main_~ret5~5=v_main_~ret5~5_3, main_~ret2~5=v_main_~ret2~5_3} OutVars{main_~ret~5=v_main_~ret~5_3, main_~ret5~5=v_main_~ret5~5_3, main_~ret2~5=v_main_~ret2~5_3} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,776 INFO L84 mationBacktranslator]: Skipped ATE [527] [527] L42-->mainErr0AssertViolation: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-01-31 10:22:07,779 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 31.01 10:22:07 BasicIcfg [2018-01-31 10:22:07,779 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-01-31 10:22:07,780 INFO L168 Benchmark]: Toolchain (without parser) took 116709.03 ms. Allocated memory was 148.4 MB in the beginning and 2.1 GB in the end (delta: 1.9 GB). Free memory was 113.5 MB in the beginning and 2.0 GB in the end (delta: -1.9 GB). Peak memory consumption was 1.9 GB. Max. memory is 5.3 GB. [2018-01-31 10:22:07,780 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 148.4 MB. Free memory is still 118.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-01-31 10:22:07,780 INFO L168 Benchmark]: CACSL2BoogieTranslator took 113.51 ms. Allocated memory is still 148.4 MB. Free memory was 113.3 MB in the beginning and 104.6 MB in the end (delta: 8.7 MB). Peak memory consumption was 8.7 MB. Max. memory is 5.3 GB. [2018-01-31 10:22:07,780 INFO L168 Benchmark]: Boogie Preprocessor took 20.16 ms. Allocated memory is still 148.4 MB. Free memory was 104.6 MB in the beginning and 102.8 MB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 5.3 GB. [2018-01-31 10:22:07,780 INFO L168 Benchmark]: RCFGBuilder took 455.17 ms. Allocated memory is still 148.4 MB. Free memory was 102.8 MB in the beginning and 83.4 MB in the end (delta: 19.4 MB). Peak memory consumption was 19.4 MB. Max. memory is 5.3 GB. [2018-01-31 10:22:07,780 INFO L168 Benchmark]: IcfgTransformer took 45789.10 ms. Allocated memory was 148.4 MB in the beginning and 2.1 GB in the end (delta: 1.9 GB). Free memory was 83.4 MB in the beginning and 1.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 842.8 MB. Max. memory is 5.3 GB. [2018-01-31 10:22:07,781 INFO L168 Benchmark]: TraceAbstraction took 70328.65 ms. Allocated memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 23.6 MB). Free memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: -829.1 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. [2018-01-31 10:22:07,781 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 148.4 MB. Free memory is still 118.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 113.51 ms. Allocated memory is still 148.4 MB. Free memory was 113.3 MB in the beginning and 104.6 MB in the end (delta: 8.7 MB). Peak memory consumption was 8.7 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 20.16 ms. Allocated memory is still 148.4 MB. Free memory was 104.6 MB in the beginning and 102.8 MB in the end (delta: 1.8 MB). Peak memory consumption was 1.8 MB. Max. memory is 5.3 GB. * RCFGBuilder took 455.17 ms. Allocated memory is still 148.4 MB. Free memory was 102.8 MB in the beginning and 83.4 MB in the end (delta: 19.4 MB). Peak memory consumption was 19.4 MB. Max. memory is 5.3 GB. * IcfgTransformer took 45789.10 ms. Allocated memory was 148.4 MB in the beginning and 2.1 GB in the end (delta: 1.9 GB). Free memory was 83.4 MB in the beginning and 1.1 GB in the end (delta: -1.1 GB). Peak memory consumption was 842.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 70328.65 ms. Allocated memory was 2.1 GB in the beginning and 2.1 GB in the end (delta: 23.6 MB). Free memory was 1.1 GB in the beginning and 2.0 GB in the end (delta: -829.1 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 82 LocStat_MAX_WEQGRAPH_SIZE : 3 LocStat_MAX_SIZEOF_WEQEDGELABEL : 2 LocStat_NO_SUPPORTING_EQUALITIES : 1540 LocStat_NO_SUPPORTING_DISEQUALITIES : 3717 LocStat_NO_DISJUNCTIONS : -164 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 108 TransStat_MAX_WEQGRAPH_SIZE : 2 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 166 TransStat_NO_SUPPORTING_DISEQUALITIES : 7 TransStat_NO_DISJUNCTIONS : 106 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 0.008465 RENAME_VARIABLES(MILLISECONDS) : 0.209983 UNFREEZE(MILLISECONDS) : 0.000000 CONJOIN(MILLISECONDS) : 0.000518 PROJECTAWAY(MILLISECONDS) : 0.072473 ADD_WEAK_EQUALITY(MILLISECONDS) : 0.049534 DISJOIN(MILLISECONDS) : 0.794779 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 0.226568 ADD_EQUALITY(MILLISECONDS) : 0.028218 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.000000 ADD_DISEQUALITY(MILLISECONDS) : 0.002265 #CONJOIN_DISJUNCTIVE : 1415 #RENAME_VARIABLES : 3043 #UNFREEZE : 0 #CONJOIN : 1854 #PROJECTAWAY : 1760 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 435 #RENAME_VARIABLES_DISJUNCTIVE : 3088 #ADD_EQUALITY : 171 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 5 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 5 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 10 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 42]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 83 locations, 1 error locations. UNSAFE Result, 70.2s OverallTime, 31 OverallIterations, 21 TraceHistogramMax, 16.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2380 SDtfs, 2394 SDslu, 44965 SDs, 0 SdLazy, 5212 SolverSat, 556 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 4.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 7306 GetRequests, 5750 SyntacticMatches, 0 SemanticMatches, 1556 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21405 ImplicationChecksByTransitivity, 25.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=376occurred in iteration=30, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 30 MinimizatonAttempts, 185 StatesRemovedByMinimization, 28 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 34.5s SatisfiabilityAnalysisTime, 16.9s InterpolantComputationTime, 12152 NumberOfCodeBlocks, 11952 NumberOfCodeBlocksAsserted, 228 NumberOfCheckSat, 11744 ConstructedInterpolants, 0 QuantifiedInterpolants, 5225054 SizeOfPredicates, 601 NumberOfNonLiveVariables, 8145 ConjunctsInSsa, 652 ConjunctsInUnsatCore, 58 InterpolantComputations, 3 PerfectInterpolantSequences, 36522/66208 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep20_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-01-31_10-22-07-786.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep20_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-01-31_10-22-07-786.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep20_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-01-31_10-22-07-786.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep20_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-01-31_10-22-07-786.csv Written .csv to /home/daniel/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/sep20_true-unreach-call.i_svcomp-Reach-32bit-Automizer_Camel+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-01-31_10-22-07-786.csv Received shutdown request...