java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-835382a-m [2018-04-05 19:21:56,794 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-05 19:21:56,796 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-05 19:21:56,811 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-04-05 19:21:56,839 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf [2018-04-05 19:21:56,864 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-05 19:21:56,864 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-05 19:21:56,865 INFO L131 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2018-04-05 19:21:56,865 INFO L133 SettingsManager]: * ultimate.logging.details=de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation=DEBUG; [2018-04-05 19:21:56,865 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-04-05 19:21:56,866 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-04-05 19:21:56,866 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-04-05 19:21:56,866 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-04-05 19:21:56,866 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-04-05 19:21:56,866 INFO L131 SettingsManager]: Preferences of LTL2Aut differ from their defaults: [2018-04-05 19:21:56,867 INFO L133 SettingsManager]: * Property to check=[] a a: x > 42 [2018-04-05 19:21:56,867 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-05 19:21:56,867 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-05 19:21:56,867 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-05 19:21:56,867 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-05 19:21:56,868 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-05 19:21:56,868 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-05 19:21:56,868 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-05 19:21:56,868 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-04-05 19:21:56,868 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-05 19:21:56,868 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-05 19:21:56,869 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-05 19:21:56,869 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-04-05 19:21:56,869 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-04-05 19:21:56,869 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-05 19:21:56,869 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-05 19:21:56,870 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-05 19:21:56,870 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-05 19:21:56,870 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-05 19:21:56,870 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-04-05 19:21:56,870 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-04-05 19:21:56,871 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:21:56,871 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-04-05 19:21:56,872 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-04-05 19:21:56,872 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-04-05 19:21:56,872 INFO L131 SettingsManager]: Preferences of Boogie Printer differ from their defaults: [2018-04-05 19:21:56,872 INFO L133 SettingsManager]: * Dump path:=C:\Users\alex\AppData\Local\Temp\ [2018-04-05 19:21:56,905 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-05 19:21:56,917 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-05 19:21:56,921 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-05 19:21:56,923 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-05 19:21:56,923 INFO L276 PluginConnector]: CDTParser initialized [2018-04-05 19:21:56,924 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,255 INFO L225 CDTParser]: Created temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGfcc8dfd61 [2018-04-05 19:21:57,412 INFO L287 CDTParser]: IsIndexed: true [2018-04-05 19:21:57,413 INFO L288 CDTParser]: Found 1 translation units. [2018-04-05 19:21:57,413 INFO L168 CDTParser]: Scanning diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,424 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-05 19:21:57,424 INFO L215 ultiparseSymbolTable]: [2018-04-05 19:21:57,424 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-05 19:21:57,425 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,425 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,425 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,425 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff ('diff') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,425 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-05 19:21:57,425 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,426 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____socklen_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__size_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____intptr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,427 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsword_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,428 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,429 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uint in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____useconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_set in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____qaddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,430 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,431 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__register_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,432 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ushort in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,433 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,434 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,435 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ulong in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__wchar_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__lldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,436 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__div_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,437 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,438 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,439 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-05 19:21:57,456 INFO L330 CDTParser]: Deleted temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGfcc8dfd61 [2018-04-05 19:21:57,461 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-05 19:21:57,463 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-04-05 19:21:57,464 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-05 19:21:57,464 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-05 19:21:57,468 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-05 19:21:57,469 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,471 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1109c630 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57, skipping insertion in model container [2018-04-05 19:21:57,471 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,485 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-05 19:21:57,514 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-05 19:21:57,678 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-05 19:21:57,729 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-05 19:21:57,737 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-05 19:21:57,780 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57 WrapperNode [2018-04-05 19:21:57,781 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-05 19:21:57,782 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-05 19:21:57,782 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-05 19:21:57,782 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-05 19:21:57,792 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,792 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,807 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,807 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,818 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,824 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,827 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... [2018-04-05 19:21:57,832 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-05 19:21:57,832 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-05 19:21:57,833 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-05 19:21:57,833 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-05 19:21:57,834 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-05 19:21:57,964 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-05 19:21:57,964 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-05 19:21:57,964 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-05 19:21:57,964 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-05 19:21:57,964 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-05 19:21:57,964 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-05 19:21:57,964 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-05 19:21:57,965 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-05 19:21:57,966 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-05 19:21:57,967 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-05 19:21:57,968 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-05 19:21:57,969 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-05 19:21:57,970 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-05 19:21:57,971 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-05 19:21:57,972 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-05 19:21:57,973 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-05 19:21:57,974 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-05 19:21:57,975 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-05 19:21:57,976 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-05 19:21:57,977 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-05 19:21:57,978 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-05 19:21:57,978 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-05 19:21:57,978 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-05 19:21:57,978 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-05 19:21:58,303 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-05 19:21:58,304 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 05.04 07:21:58 BoogieIcfgContainer [2018-04-05 19:21:58,304 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-05 19:21:58,304 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-04-05 19:21:58,304 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-04-05 19:21:58,305 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-04-05 19:21:58,308 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 05.04 07:21:58" (1/1) ... [2018-04-05 19:21:58,314 INFO L139 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-04-05 19:21:58,314 INFO L140 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-04-05 19:21:58,328 INFO L299 apSepIcfgTransformer]: Heap separator: starting memloc-array-style preprocessing [2018-04-05 19:21:58,348 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-05 19:21:58,362 INFO L332 apSepIcfgTransformer]: finished MemlocArrayUpdater, created 2 location literals (each corresponds to one heap write) [2018-04-05 19:21:58,371 INFO L100 SccComputation]: Graph consists of 1 InCaSumBalls and 111 non ball SCCs. Number of states in SCCs 112. [2018-04-05 19:21:58,388 INFO L412 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-04-05 19:21:58,388 DEBUG L416 apSepIcfgTransformer]: storeIndexInfoToLocLiteral: Map: (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) : |mll_L558'_0| (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) : |mll_L558'_1| [2018-04-05 19:21:58,391 DEBUG L418 apSepIcfgTransformer]: edgeToIndexToStoreIndexInfo: NestedMap2: (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 : (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2) : (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) [2018-04-05 19:21:58,441 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=2) [2018-04-05 19:24:19,751 INFO L314 AbstractInterpreter]: Visited 90 different actions 1237 times. Merged at 58 different actions 758 times. Widened at 3 different actions 19 times. Found 112 fixpoints after 18 different actions. Largest state had 46 variables. [2018-04-05 19:24:19,753 INFO L424 apSepIcfgTransformer]: finished equality analysis [2018-04-05 19:24:19,761 INFO L195 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 4 [2018-04-05 19:24:19,762 INFO L434 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-04-05 19:24:19,762 INFO L435 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-04-05 19:24:19,762 INFO L437 apSepIcfgTransformer]: select infos: Set: ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-05 19:24:19,817 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_32 [2018-04-05 19:24:19,817 DEBUG L374 HeapPartitionManager]: with contents [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-05 19:24:19,817 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-05 19:24:19,818 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-05 19:24:19,818 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-05 19:24:19,818 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_31 [2018-04-05 19:24:19,818 DEBUG L374 HeapPartitionManager]: with contents [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-05 19:24:19,818 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-05 19:24:19,818 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-05 19:24:19,818 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-05 19:24:19,818 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-05 19:24:19,818 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-05 19:24:19,818 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-05 19:24:19,819 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-05 19:24:19,819 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-05 19:24:19,819 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-05 19:24:19,819 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-05 19:24:19,819 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-05 19:24:19,820 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-05 19:24:19,820 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-05 19:24:19,820 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-05 19:24:19,820 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-05 19:24:19,820 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-05 19:24:19,820 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-05 19:24:19,821 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-05 19:24:19,821 INFO L330 HeapPartitionManager]: partitioning result: [2018-04-05 19:24:19,821 INFO L335 HeapPartitionManager]: location blocks for array group [#memory_int] [2018-04-05 19:24:19,821 INFO L344 HeapPartitionManager]: at dimension 0 [2018-04-05 19:24:19,821 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-05 19:24:19,822 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-05 19:24:19,822 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-05 19:24:19,822 DEBUG L356 HeapPartitionManager]: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-05 19:24:19,822 INFO L344 HeapPartitionManager]: at dimension 1 [2018-04-05 19:24:19,822 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-05 19:24:19,823 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-05 19:24:19,823 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-05 19:24:19,823 DEBUG L356 HeapPartitionManager]: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-05 19:24:19,824 INFO L131 ransitionTransformer]: executing heap partitioning transformation [2018-04-05 19:24:19,826 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,827 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,827 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,827 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,827 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,827 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,827 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,827 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,827 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,828 DEBUG L281 ransitionTransformer]: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] [2018-04-05 19:24:19,828 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,828 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,828 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,828 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,828 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,828 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,828 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,828 DEBUG L281 ransitionTransformer]: Formula: (and (<= 0 (+ |v_main_#t~nondet8_1| 2147483648)) (<= |v_main_#t~nondet8_1| 2147483647)) InVars {main_#t~nondet8=|v_main_#t~nondet8_1|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_1|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,829 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,829 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,829 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,829 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] [2018-04-05 19:24:19,829 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,829 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,829 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,829 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Alen~0_1 |v_main_#t~nondet8_2|) InVars {main_#t~nondet8=|v_main_#t~nondet8_2|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_2|, main_~Alen~0=v_main_~Alen~0_1} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-05 19:24:19,829 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,830 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,830 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,830 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,830 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,830 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,830 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,830 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~nondet8=|v_main_#t~nondet8_3|} AuxVars[] AssignedVars[main_#t~nondet8] [2018-04-05 19:24:19,830 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,830 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,830 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,831 DEBUG L281 ransitionTransformer]: Formula: (and (<= |v_main_#t~nondet9_1| 2147483647) (<= 0 (+ |v_main_#t~nondet9_1| 2147483648))) InVars {main_#t~nondet9=|v_main_#t~nondet9_1|} OutVars{main_#t~nondet9=|v_main_#t~nondet9_1|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,831 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,831 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,831 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,831 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Blen~0_1 |v_main_#t~nondet9_2|) InVars {main_#t~nondet9=|v_main_#t~nondet9_2|} OutVars{main_~Blen~0=v_main_~Blen~0_1, main_#t~nondet9=|v_main_#t~nondet9_2|} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-05 19:24:19,831 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,831 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,832 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,832 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~nondet9=|v_main_#t~nondet9_3|} AuxVars[] AssignedVars[main_#t~nondet9] [2018-04-05 19:24:19,832 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,832 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,832 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,832 DEBUG L281 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Alen~0_2) (< v_main_~Alen~0_2 1)) InVars {main_~Alen~0=v_main_~Alen~0_2} OutVars{main_~Alen~0=v_main_~Alen~0_2} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,833 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,833 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,833 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,833 DEBUG L281 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Alen~0_4)) (not (< v_main_~Alen~0_4 1))) InVars {main_~Alen~0=v_main_~Alen~0_4} OutVars{main_~Alen~0=v_main_~Alen~0_4} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,833 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,833 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,833 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,833 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Alen~0_3 1) InVars {} OutVars{main_~Alen~0=v_main_~Alen~0_3} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-05 19:24:19,833 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,834 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,834 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,834 DEBUG L281 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Blen~0_2) (< v_main_~Blen~0_2 1)) InVars {main_~Blen~0=v_main_~Blen~0_2} OutVars{main_~Blen~0=v_main_~Blen~0_2} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,834 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,834 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,834 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,834 DEBUG L281 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Blen~0_4)) (not (< v_main_~Blen~0_4 1))) InVars {main_~Blen~0=v_main_~Blen~0_4} OutVars{main_~Blen~0=v_main_~Blen~0_4} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,834 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,835 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,835 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,835 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Blen~0_3 1) InVars {} OutVars{main_~Blen~0=v_main_~Blen~0_3} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-05 19:24:19,835 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,835 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,836 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,836 DEBUG L281 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc10.base_1|)) (= (store |v_#valid_12| |v_main_#t~malloc10.base_1| 1) |v_#valid_11|) (= |v_main_#t~malloc10.offset_1| 0) (= 0 (select |v_#valid_12| |v_main_#t~malloc10.base_1|)) (= |v_#length_9| (store |v_#length_10| |v_main_#t~malloc10.base_1| (* 4 v_main_~Alen~0_5)))) InVars {#length=|v_#length_10|, main_~Alen~0=v_main_~Alen~0_5, #valid=|v_#valid_12|} OutVars{#length=|v_#length_9|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_1|, main_~Alen~0=v_main_~Alen~0_5, main_#t~malloc10.base=|v_main_#t~malloc10.base_1|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc10.offset, main_#t~malloc10.base] [2018-04-05 19:24:19,836 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,836 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,836 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,836 DEBUG L281 ransitionTransformer]: Formula: (and (= v_main_~A~0.offset_1 |v_main_#t~malloc10.offset_2|) (= v_main_~A~0.base_1 |v_main_#t~malloc10.base_2|)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|} OutVars{main_~A~0.offset=v_main_~A~0.offset_1, main_~A~0.base=v_main_~A~0.base_1, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|, main_#t~malloc10.base=|v_main_#t~malloc10.base_2|} AuxVars[] AssignedVars[main_~A~0.offset, main_~A~0.base] [2018-04-05 19:24:19,836 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,836 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,836 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,837 DEBUG L281 ransitionTransformer]: Formula: (and (= |v_main_#t~malloc11.offset_1| 0) (not (= |v_main_#t~malloc11.base_1| 0)) (= (store |v_#valid_14| |v_main_#t~malloc11.base_1| 1) |v_#valid_13|) (= |v_#length_11| (store |v_#length_12| |v_main_#t~malloc11.base_1| (* 4 v_main_~Blen~0_5))) (= 0 (select |v_#valid_14| |v_main_#t~malloc11.base_1|))) InVars {#length=|v_#length_12|, main_~Blen~0=v_main_~Blen~0_5, #valid=|v_#valid_14|} OutVars{#length=|v_#length_11|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_1|, main_~Blen~0=v_main_~Blen~0_5, main_#t~malloc11.base=|v_main_#t~malloc11.base_1|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc11.offset, main_#t~malloc11.base] [2018-04-05 19:24:19,837 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,837 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,837 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,837 DEBUG L281 ransitionTransformer]: Formula: (and (= v_main_~B~0.offset_1 |v_main_#t~malloc11.offset_2|) (= v_main_~B~0.base_1 |v_main_#t~malloc11.base_2|)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_2|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|} OutVars{main_~B~0.offset=v_main_~B~0.offset_1, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|, main_~B~0.base=v_main_~B~0.base_1, main_#t~malloc11.base=|v_main_#t~malloc11.base_2|} AuxVars[] AssignedVars[main_~B~0.offset, main_~B~0.base] [2018-04-05 19:24:19,837 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,837 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,837 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,838 DEBUG L281 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc12.base_1|)) (= |v_#valid_15| (store |v_#valid_16| |v_main_#t~malloc12.base_1| 1)) (= 0 |v_main_#t~malloc12.offset_1|) (= 0 (select |v_#valid_16| |v_main_#t~malloc12.base_1|)) (= |v_#length_13| (store |v_#length_14| |v_main_#t~malloc12.base_1| (* 4 v_main_~Alen~0_6)))) InVars {#length=|v_#length_14|, main_~Alen~0=v_main_~Alen~0_6, #valid=|v_#valid_16|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_1|, #length=|v_#length_13|, main_~Alen~0=v_main_~Alen~0_6, main_#t~malloc12.base=|v_main_#t~malloc12.base_1|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[main_#t~malloc12.offset, #valid, #length, main_#t~malloc12.base] [2018-04-05 19:24:19,838 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,838 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,838 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,838 DEBUG L281 ransitionTransformer]: Formula: (and (= v_main_~D~0.base_1 |v_main_#t~malloc12.base_2|) (= v_main_~D~0.offset_1 |v_main_#t~malloc12.offset_2|)) InVars {main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_~D~0.base=v_main_~D~0.base_1, main_~D~0.offset=v_main_~D~0.offset_1, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} AuxVars[] AssignedVars[main_~D~0.base, main_~D~0.offset] [2018-04-05 19:24:19,838 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,838 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,839 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,839 DEBUG L281 ransitionTransformer]: Formula: (and (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1| v_main_~A~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1| v_main_~B~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1| v_main_~A~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1| v_main_~B~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1| v_main_~Blen~0_7) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1| v_main_~D~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1| v_main_~Alen~0_8) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1| v_main_~D~0.base_3)) InVars {main_~B~0.offset=v_main_~B~0.offset_3, main_~A~0.offset=v_main_~A~0.offset_3, main_~Blen~0=v_main_~Blen~0_7, main_~Alen~0=v_main_~Alen~0_8, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~B~0.base=v_main_~B~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen] [2018-04-05 19:24:19,839 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,839 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,840 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,840 DEBUG L281 ransitionTransformer]: Formula: (= |v_main_#res_1| 0) InVars {} OutVars{main_#res=|v_main_#res_1|} AuxVars[] AssignedVars[main_#res] [2018-04-05 19:24:19,840 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,840 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,840 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,840 DEBUG L281 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base] [2018-04-05 19:24:19,841 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,841 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,841 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,841 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_17| (store |v_#valid_18| |v_main_#t~malloc10.base_3| 0)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_18|} OutVars{main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_17|} AuxVars[] AssignedVars[#valid] [2018-04-05 19:24:19,841 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,841 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,842 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,842 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen] [2018-04-05 19:24:19,842 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,842 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,842 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,842 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~malloc10.base=|v_main_#t~malloc10.base_4|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_4|} AuxVars[] AssignedVars[main_#t~malloc10.offset, main_#t~malloc10.base] [2018-04-05 19:24:19,842 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,843 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,843 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,843 DEBUG L281 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset] [2018-04-05 19:24:19,843 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,843 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,844 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,844 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_19| (store |v_#valid_20| |v_main_#t~malloc11.base_3| 0)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_20|} OutVars{main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_19|} AuxVars[] AssignedVars[#valid] [2018-04-05 19:24:19,844 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,844 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,844 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,844 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen] [2018-04-05 19:24:19,844 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,845 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,845 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,845 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~malloc11.base=|v_main_#t~malloc11.base_4|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_4|} AuxVars[] AssignedVars[main_#t~malloc11.offset, main_#t~malloc11.base] [2018-04-05 19:24:19,845 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,845 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,845 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,846 DEBUG L281 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset] [2018-04-05 19:24:19,846 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,846 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,846 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,846 DEBUG L281 ransitionTransformer]: Formula: (= (store |v_#valid_22| |v_main_#t~malloc12.base_3| 0) |v_#valid_21|) InVars {main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_22|} OutVars{main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_21|} AuxVars[] AssignedVars[#valid] [2018-04-05 19:24:19,846 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,847 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,847 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,847 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-05 19:24:19,847 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,847 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,847 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,848 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_4|, main_#t~malloc12.base=|v_main_#t~malloc12.base_4|} AuxVars[] AssignedVars[main_#t~malloc12.offset, main_#t~malloc12.base] [2018-04-05 19:24:19,848 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,848 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,848 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,848 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-05 19:24:19,848 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,848 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,848 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,849 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_23| |old(#valid)|) InVars {#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,849 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,849 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,849 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,849 DEBUG L281 ransitionTransformer]: Formula: (not (= |v_#valid_24| |old(#valid)|)) InVars {#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,849 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,849 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,849 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,849 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0] [2018-04-05 19:24:19,849 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,850 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,850 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,850 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0] [2018-04-05 19:24:19,850 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,850 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,850 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,850 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-05 19:24:19,850 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,850 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,850 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,850 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,851 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,851 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,851 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,851 DEBUG L281 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,851 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,851 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,851 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,851 DEBUG L281 ransitionTransformer]: Formula: (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,851 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,852 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,852 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,852 DEBUG L281 ransitionTransformer]: Formula: (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,852 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,852 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,852 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,852 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,853 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,853 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,853 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,853 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-05 19:24:19,853 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,853 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,854 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,854 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-05 19:24:19,854 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,854 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,854 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,854 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,854 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,854 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,855 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,855 DEBUG L281 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,855 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,855 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,855 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,855 DEBUG L281 ransitionTransformer]: Formula: (or (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3)) (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,856 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,856 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,856 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,856 DEBUG L281 ransitionTransformer]: Formula: (and (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3) (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,856 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,856 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,857 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,857 DEBUG L281 ransitionTransformer]: Formula: (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,857 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,857 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,857 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,857 DEBUG L281 ransitionTransformer]: Formula: (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,857 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,858 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,860 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,860 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-05 19:24:19,860 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-05 19:24:19,860 DEBUG L289 ransitionTransformer]: old formula: [2018-04-05 19:24:19,860 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-05 19:24:19,861 DEBUG L291 ransitionTransformer]: new formula: [2018-04-05 19:24:19,861 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-05 19:24:19,861 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-05 19:24:19,861 DEBUG L297 ransitionTransformer]: old invars: [2018-04-05 19:24:19,861 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|} [2018-04-05 19:24:19,861 DEBUG L299 ransitionTransformer]: new invars: [2018-04-05 19:24:19,861 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} [2018-04-05 19:24:19,861 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-05 19:24:19,861 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-05 19:24:19,861 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-05 19:24:19,862 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-05 19:24:19,862 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-05 19:24:19,862 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,862 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,862 DEBUG L281 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3))) InVars {#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} OutVars{#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,862 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,862 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,862 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,863 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0 4) (select |v_#length_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4))))) InVars {#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} OutVars{#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,863 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,863 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,864 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,864 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5] [2018-04-05 19:24:19,864 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-05 19:24:19,864 DEBUG L289 ransitionTransformer]: old formula: [2018-04-05 19:24:19,864 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-05 19:24:19,864 DEBUG L291 ransitionTransformer]: new formula: [2018-04-05 19:24:19,864 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-05 19:24:19,864 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-05 19:24:19,865 DEBUG L297 ransitionTransformer]: old invars: [2018-04-05 19:24:19,865 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|} [2018-04-05 19:24:19,865 DEBUG L299 ransitionTransformer]: new invars: [2018-04-05 19:24:19,865 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} [2018-04-05 19:24:19,865 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-05 19:24:19,865 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-05 19:24:19,865 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-05 19:24:19,865 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-05 19:24:19,865 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-05 19:24:19,865 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,865 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,866 DEBUG L281 ransitionTransformer]: Formula: (not (= (select |v_#valid_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6) 1)) InVars {#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} OutVars{#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,866 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,866 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,866 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,866 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0 4) (select |v_#length_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7))))) InVars {#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} OutVars{#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,866 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,866 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,866 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,866 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7] [2018-04-05 19:24:19,867 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,867 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,867 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,867 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-05 19:24:19,867 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-05 19:24:19,867 DEBUG L289 ransitionTransformer]: old formula: [2018-04-05 19:24:19,867 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-05 19:24:19,867 DEBUG L291 ransitionTransformer]: new formula: [2018-04-05 19:24:19,868 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-05 19:24:19,868 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-05 19:24:19,868 DEBUG L297 ransitionTransformer]: old invars: [2018-04-05 19:24:19,868 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-05 19:24:19,868 DEBUG L299 ransitionTransformer]: new invars: [2018-04-05 19:24:19,868 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-05 19:24:19,868 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-05 19:24:19,868 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-05 19:24:19,868 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-05 19:24:19,868 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-05 19:24:19,868 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-05 19:24:19,868 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,869 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,869 DEBUG L281 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,869 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,869 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,869 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,869 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5))) (or (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0 4) (select |v_#length_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4))) (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,869 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,869 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,871 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,871 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} AuxVars[] AssignedVars[#memory_int_part_locs_32_locs_31] [2018-04-05 19:24:19,871 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-05 19:24:19,871 DEBUG L289 ransitionTransformer]: old formula: [2018-04-05 19:24:19,871 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_4|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-05 19:24:19,871 DEBUG L291 ransitionTransformer]: new formula: [2018-04-05 19:24:19,871 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-05 19:24:19,871 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-05 19:24:19,871 DEBUG L297 ransitionTransformer]: old invars: [2018-04-05 19:24:19,872 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-05 19:24:19,872 DEBUG L299 ransitionTransformer]: new invars: [2018-04-05 19:24:19,872 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-05 19:24:19,872 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-05 19:24:19,872 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-05 19:24:19,872 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-05 19:24:19,872 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-05 19:24:19,872 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-05 19:24:19,872 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,872 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,873 DEBUG L281 ransitionTransformer]: Formula: (not (= (select |v_#valid_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3) 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,873 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,873 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,873 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,873 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0 4) (select |v_#length_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,873 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,873 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,874 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,874 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-05 19:24:19,874 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,874 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,874 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,874 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,874 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,874 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,874 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,875 DEBUG L281 ransitionTransformer]: Formula: (not (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,875 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,875 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,875 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,875 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5] [2018-04-05 19:24:19,875 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,875 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,875 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,875 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7] [2018-04-05 19:24:19,875 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,876 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,876 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,876 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-05 19:24:19,876 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,876 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,876 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,877 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_5|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-05 19:24:19,877 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,877 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,877 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,877 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6] [2018-04-05 19:24:19,877 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,877 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,878 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,878 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-05 19:24:19,878 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,878 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,878 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,878 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_5|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-05 19:24:19,878 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,879 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,879 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,879 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-05 19:24:19,879 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,879 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,879 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,880 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5 1) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-05 19:24:19,880 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,880 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,880 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,880 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4] [2018-04-05 19:24:19,880 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,880 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,881 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,881 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6] [2018-04-05 19:24:19,881 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,881 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,881 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,881 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-05 19:24:19,882 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,882 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,882 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,882 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4] [2018-04-05 19:24:19,882 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,882 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,882 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,883 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,883 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,883 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,883 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,883 DEBUG L281 ransitionTransformer]: Formula: (= |v_ULTIMATE.start_#t~ret13_2| |v_main_#resOutParam_1|) InVars {main_#res=|v_main_#resOutParam_1|} OutVars{ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|} AuxVars[] AssignedVars[ULTIMATE.start_#t~ret13] [2018-04-05 19:24:19,883 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,883 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,884 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-05 19:24:19,884 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-05 19:24:19,884 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-05 19:24:19,884 DEBUG L310 ransitionTransformer]: [2018-04-05 19:24:19,885 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-05 19:24:19,903 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 05.04 07:24:19 BasicIcfg [2018-04-05 19:24:19,903 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-04-05 19:24:19,904 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-05 19:24:19,904 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-05 19:24:19,907 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-05 19:24:19,907 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 05.04 07:21:57" (1/4) ... [2018-04-05 19:24:19,908 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@458c6b54 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 05.04 07:24:19, skipping insertion in model container [2018-04-05 19:24:19,908 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 05.04 07:21:57" (2/4) ... [2018-04-05 19:24:19,908 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@458c6b54 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 05.04 07:24:19, skipping insertion in model container [2018-04-05 19:24:19,908 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 05.04 07:21:58" (3/4) ... [2018-04-05 19:24:19,909 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@458c6b54 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 05.04 07:24:19, skipping insertion in model container [2018-04-05 19:24:19,909 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 05.04 07:24:19" (4/4) ... [2018-04-05 19:24:19,910 INFO L107 eAbstractionObserver]: Analyzing ICFG memPartitionedIcfg [2018-04-05 19:24:19,920 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-05 19:24:19,928 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 9 error locations. [2018-04-05 19:24:19,965 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-05 19:24:19,965 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-05 19:24:19,966 INFO L370 AbstractCegarLoop]: Hoare is true [2018-04-05 19:24:19,966 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-05 19:24:19,966 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-05 19:24:19,966 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-05 19:24:19,966 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-05 19:24:19,966 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-05 19:24:19,966 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-05 19:24:19,966 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-05 19:24:19,975 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states. [2018-04-05 19:24:19,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-05 19:24:19,980 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:19,981 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:19,981 INFO L408 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:19,985 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476875, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:20,005 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:20,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:20,059 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:20,088 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:20,089 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,094 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,094 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-05 19:24:20,113 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,114 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-05 19:24:20,116 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,151 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:20,151 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-05 19:24:20,196 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2018-04-05 19:24:20,197 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,202 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:20,202 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:21, output treesize:20 [2018-04-05 19:24:20,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:20,268 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:20,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:20,378 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:20,378 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-05 19:24:20,380 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-05 19:24:20,387 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-05 19:24:20,387 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-05 19:24:20,389 INFO L87 Difference]: Start difference. First operand 82 states. Second operand 11 states. [2018-04-05 19:24:20,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:20,617 INFO L93 Difference]: Finished difference Result 129 states and 143 transitions. [2018-04-05 19:24:20,618 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-05 19:24:20,620 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-05 19:24:20,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:20,631 INFO L225 Difference]: With dead ends: 129 [2018-04-05 19:24:20,632 INFO L226 Difference]: Without dead ends: 77 [2018-04-05 19:24:20,635 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 64 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-05 19:24:20,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-04-05 19:24:20,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-04-05 19:24:20,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-04-05 19:24:20,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-04-05 19:24:20,676 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 38 [2018-04-05 19:24:20,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:20,676 INFO L459 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-04-05 19:24:20,676 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-05 19:24:20,677 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-04-05 19:24:20,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-05 19:24:20,678 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:20,678 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:20,678 INFO L408 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:20,678 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476876, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:20,688 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:20,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:20,718 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:20,725 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:20,726 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,735 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:20,735 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,742 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,743 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-05 19:24:20,777 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,778 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,779 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-05 19:24:20,779 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,799 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-05 19:24:20,800 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,817 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:20,817 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:35 [2018-04-05 19:24:20,841 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,842 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,842 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:20,843 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-04-05 19:24:20,843 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 34 [2018-04-05 19:24:20,858 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:20,877 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:20,877 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:48, output treesize:40 [2018-04-05 19:24:21,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:21,029 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:21,255 INFO L682 Elim1Store]: detected equality via solver [2018-04-05 19:24:21,256 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 30 [2018-04-05 19:24:21,269 INFO L682 Elim1Store]: detected equality via solver [2018-04-05 19:24:21,269 INFO L682 Elim1Store]: detected equality via solver [2018-04-05 19:24:21,270 INFO L682 Elim1Store]: detected equality via solver [2018-04-05 19:24:21,270 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 10 [2018-04-05 19:24:21,271 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,278 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,288 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 24 [2018-04-05 19:24:21,305 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 30 [2018-04-05 19:24:21,344 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 9 [2018-04-05 19:24:21,345 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,348 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,349 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,354 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,354 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:42, output treesize:5 [2018-04-05 19:24:21,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:21,387 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:21,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 9] imperfect sequences [] total 16 [2018-04-05 19:24:21,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-05 19:24:21,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-05 19:24:21,389 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-04-05 19:24:21,389 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 17 states. [2018-04-05 19:24:21,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:21,899 INFO L93 Difference]: Finished difference Result 118 states and 131 transitions. [2018-04-05 19:24:21,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-05 19:24:21,899 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 38 [2018-04-05 19:24:21,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:21,903 INFO L225 Difference]: With dead ends: 118 [2018-04-05 19:24:21,904 INFO L226 Difference]: Without dead ends: 116 [2018-04-05 19:24:21,904 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 59 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2018-04-05 19:24:21,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-04-05 19:24:21,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 86. [2018-04-05 19:24:21,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-05 19:24:21,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 94 transitions. [2018-04-05 19:24:21,916 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 94 transitions. Word has length 38 [2018-04-05 19:24:21,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:21,916 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 94 transitions. [2018-04-05 19:24:21,916 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-05 19:24:21,917 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 94 transitions. [2018-04-05 19:24:21,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-05 19:24:21,918 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:21,918 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:21,918 INFO L408 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:21,918 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273898, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:21,925 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:21,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:21,944 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:21,949 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:21,949 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,951 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,951 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-05 19:24:21,958 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:21,959 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:21,960 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-05 19:24:21,960 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:21,965 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:21,965 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-05 19:24:22,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:22,002 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:22,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:22,079 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:22,080 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-05 19:24:22,080 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-05 19:24:22,080 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-05 19:24:22,080 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-05 19:24:22,080 INFO L87 Difference]: Start difference. First operand 86 states and 94 transitions. Second operand 11 states. [2018-04-05 19:24:22,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:22,174 INFO L93 Difference]: Finished difference Result 86 states and 94 transitions. [2018-04-05 19:24:22,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-05 19:24:22,175 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 39 [2018-04-05 19:24:22,175 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:22,176 INFO L225 Difference]: With dead ends: 86 [2018-04-05 19:24:22,176 INFO L226 Difference]: Without dead ends: 85 [2018-04-05 19:24:22,176 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-05 19:24:22,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-05 19:24:22,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-05 19:24:22,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-05 19:24:22,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 93 transitions. [2018-04-05 19:24:22,182 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 93 transitions. Word has length 39 [2018-04-05 19:24:22,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:22,183 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 93 transitions. [2018-04-05 19:24:22,183 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-05 19:24:22,183 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 93 transitions. [2018-04-05 19:24:22,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-05 19:24:22,184 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:22,184 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:22,184 INFO L408 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:22,184 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273899, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:22,189 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:22,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:22,212 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:22,237 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:22,238 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:22,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:22,245 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:22,250 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:22,250 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:19 [2018-04-05 19:24:22,275 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:22,276 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:22,277 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-05 19:24:22,277 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:22,286 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-05 19:24:22,286 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:22,292 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:22,293 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:32, output treesize:25 [2018-04-05 19:24:22,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:22,391 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:24,523 WARN L148 SmtUtils]: Spent 2032ms on a formula simplification that was a NOOP. DAG size: 26 [2018-04-05 19:24:24,532 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-04-05 19:24:24,532 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:24,536 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-04-05 19:24:24,548 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-04-05 19:24:24,548 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:24,549 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-04-05 19:24:24,549 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:24,552 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:24,555 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:24,556 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:25, output treesize:5 [2018-04-05 19:24:24,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:24,586 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:24,587 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 14 [2018-04-05 19:24:24,587 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-05 19:24:24,587 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-05 19:24:24,587 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2018-04-05 19:24:24,587 INFO L87 Difference]: Start difference. First operand 85 states and 93 transitions. Second operand 15 states. [2018-04-05 19:24:24,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:24,963 INFO L93 Difference]: Finished difference Result 136 states and 152 transitions. [2018-04-05 19:24:24,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-05 19:24:24,980 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 39 [2018-04-05 19:24:24,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:24,982 INFO L225 Difference]: With dead ends: 136 [2018-04-05 19:24:24,982 INFO L226 Difference]: Without dead ends: 135 [2018-04-05 19:24:24,983 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=91, Invalid=371, Unknown=0, NotChecked=0, Total=462 [2018-04-05 19:24:24,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-04-05 19:24:24,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 89. [2018-04-05 19:24:24,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-05 19:24:24,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 98 transitions. [2018-04-05 19:24:24,995 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 98 transitions. Word has length 39 [2018-04-05 19:24:24,995 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:24,995 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 98 transitions. [2018-04-05 19:24:24,995 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-05 19:24:24,996 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 98 transitions. [2018-04-05 19:24:24,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-05 19:24:24,997 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:24,997 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:24,997 INFO L408 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:24,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1252082927, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:25,005 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:25,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:25,025 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:25,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:25,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:25,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:25,132 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:25,132 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 10 [2018-04-05 19:24:25,133 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-05 19:24:25,133 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-05 19:24:25,133 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-04-05 19:24:25,133 INFO L87 Difference]: Start difference. First operand 89 states and 98 transitions. Second operand 10 states. [2018-04-05 19:24:25,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:25,287 INFO L93 Difference]: Finished difference Result 203 states and 226 transitions. [2018-04-05 19:24:25,287 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-05 19:24:25,287 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 40 [2018-04-05 19:24:25,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:25,288 INFO L225 Difference]: With dead ends: 203 [2018-04-05 19:24:25,288 INFO L226 Difference]: Without dead ends: 151 [2018-04-05 19:24:25,289 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 67 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=76, Invalid=164, Unknown=0, NotChecked=0, Total=240 [2018-04-05 19:24:25,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-04-05 19:24:25,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 88. [2018-04-05 19:24:25,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-05 19:24:25,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 95 transitions. [2018-04-05 19:24:25,301 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 95 transitions. Word has length 40 [2018-04-05 19:24:25,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:25,301 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 95 transitions. [2018-04-05 19:24:25,301 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-05 19:24:25,301 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 95 transitions. [2018-04-05 19:24:25,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-04-05 19:24:25,302 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:25,302 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:25,302 INFO L408 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:25,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1717465618, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:25,308 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:25,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:25,326 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:25,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:25,348 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:25,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:25,428 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:25,428 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 10 [2018-04-05 19:24:25,428 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-05 19:24:25,429 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-05 19:24:25,429 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-04-05 19:24:25,429 INFO L87 Difference]: Start difference. First operand 88 states and 95 transitions. Second operand 10 states. [2018-04-05 19:24:25,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:25,652 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-04-05 19:24:25,652 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-05 19:24:25,652 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-04-05 19:24:25,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:25,653 INFO L225 Difference]: With dead ends: 128 [2018-04-05 19:24:25,654 INFO L226 Difference]: Without dead ends: 117 [2018-04-05 19:24:25,654 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 74 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-04-05 19:24:25,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-05 19:24:25,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 88. [2018-04-05 19:24:25,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-05 19:24:25,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 94 transitions. [2018-04-05 19:24:25,667 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 94 transitions. Word has length 43 [2018-04-05 19:24:25,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:25,667 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 94 transitions. [2018-04-05 19:24:25,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-05 19:24:25,667 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 94 transitions. [2018-04-05 19:24:25,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-04-05 19:24:25,668 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:25,668 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:25,668 INFO L408 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:25,669 INFO L82 PathProgramCache]: Analyzing trace with hash 29055424, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:25,676 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:25,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:25,693 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:25,697 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:25,698 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:25,703 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:25,723 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:25,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [] total 3 [2018-04-05 19:24:25,723 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-05 19:24:25,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-05 19:24:25,723 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-05 19:24:25,724 INFO L87 Difference]: Start difference. First operand 88 states and 94 transitions. Second operand 3 states. [2018-04-05 19:24:25,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:25,739 INFO L93 Difference]: Finished difference Result 147 states and 159 transitions. [2018-04-05 19:24:25,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-05 19:24:25,739 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-04-05 19:24:25,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:25,740 INFO L225 Difference]: With dead ends: 147 [2018-04-05 19:24:25,740 INFO L226 Difference]: Without dead ends: 98 [2018-04-05 19:24:25,740 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-05 19:24:25,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-05 19:24:25,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 89. [2018-04-05 19:24:25,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-05 19:24:25,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 94 transitions. [2018-04-05 19:24:25,750 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 94 transitions. Word has length 48 [2018-04-05 19:24:25,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:25,750 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 94 transitions. [2018-04-05 19:24:25,750 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-05 19:24:25,750 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 94 transitions. [2018-04-05 19:24:25,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-05 19:24:25,751 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:25,751 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:25,751 INFO L408 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:25,752 INFO L82 PathProgramCache]: Analyzing trace with hash -1793713475, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:25,760 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:25,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:25,788 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:25,791 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:25,791 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:25,796 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:25,796 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:25,799 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:25,800 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-05 19:24:25,812 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:25,813 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:25,813 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-05 19:24:25,813 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:25,820 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-05 19:24:25,820 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:25,825 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:25,826 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-05 19:24:26,086 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:26,087 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:29,681 WARN L148 SmtUtils]: Spent 3209ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-05 19:24:33,000 WARN L148 SmtUtils]: Spent 3279ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-05 19:24:33,014 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-05 19:24:33,034 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:24:33,034 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 23 [2018-04-05 19:24:33,035 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-05 19:24:33,035 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-05 19:24:33,035 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=484, Unknown=0, NotChecked=0, Total=552 [2018-04-05 19:24:33,035 INFO L87 Difference]: Start difference. First operand 89 states and 94 transitions. Second operand 24 states. [2018-04-05 19:24:37,212 WARN L151 SmtUtils]: Spent 4102ms on a formula simplification. DAG size of input: 57 DAG size of output 56 [2018-04-05 19:24:38,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:38,536 INFO L93 Difference]: Finished difference Result 123 states and 131 transitions. [2018-04-05 19:24:38,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-05 19:24:38,536 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 49 [2018-04-05 19:24:38,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:38,538 INFO L225 Difference]: With dead ends: 123 [2018-04-05 19:24:38,538 INFO L226 Difference]: Without dead ends: 122 [2018-04-05 19:24:38,538 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 160 ImplicationChecksByTransitivity, 12.0s TimeCoverageRelationStatistics Valid=270, Invalid=1136, Unknown=0, NotChecked=0, Total=1406 [2018-04-05 19:24:38,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-04-05 19:24:38,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 86. [2018-04-05 19:24:38,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-05 19:24:38,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 91 transitions. [2018-04-05 19:24:38,552 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 91 transitions. Word has length 49 [2018-04-05 19:24:38,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:38,552 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 91 transitions. [2018-04-05 19:24:38,552 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-05 19:24:38,552 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 91 transitions. [2018-04-05 19:24:38,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-05 19:24:38,553 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:38,554 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:38,554 INFO L408 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:38,554 INFO L82 PathProgramCache]: Analyzing trace with hash 229425471, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:38,561 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:38,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:38,584 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:38,588 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:38,589 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:38,590 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:38,590 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-05 19:24:38,604 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-05 19:24:38,604 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:38,610 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-05 19:24:38,630 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:38,631 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5, 5] imperfect sequences [] total 5 [2018-04-05 19:24:38,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-05 19:24:38,631 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-05 19:24:38,631 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-05 19:24:38,631 INFO L87 Difference]: Start difference. First operand 86 states and 91 transitions. Second operand 6 states. [2018-04-05 19:24:38,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:38,700 INFO L93 Difference]: Finished difference Result 86 states and 91 transitions. [2018-04-05 19:24:38,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-05 19:24:38,700 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 50 [2018-04-05 19:24:38,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:38,701 INFO L225 Difference]: With dead ends: 86 [2018-04-05 19:24:38,701 INFO L226 Difference]: Without dead ends: 85 [2018-04-05 19:24:38,702 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-04-05 19:24:38,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-05 19:24:38,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-05 19:24:38,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-05 19:24:38,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-04-05 19:24:38,715 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 50 [2018-04-05 19:24:38,716 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:38,716 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-04-05 19:24:38,716 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-05 19:24:38,716 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-04-05 19:24:38,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-05 19:24:38,717 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:38,717 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:38,717 INFO L408 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:38,718 INFO L82 PathProgramCache]: Analyzing trace with hash 229425472, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:38,730 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:38,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:38,759 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:38,773 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:38,774 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:38,780 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:38,780 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-04-05 19:24:38,857 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-05 19:24:38,857 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:38,925 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-05 19:24:38,946 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:38,946 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 12 [2018-04-05 19:24:38,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-05 19:24:38,946 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-05 19:24:38,946 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-04-05 19:24:38,946 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 13 states. [2018-04-05 19:24:39,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:39,102 INFO L93 Difference]: Finished difference Result 121 states and 130 transitions. [2018-04-05 19:24:39,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-05 19:24:39,103 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 50 [2018-04-05 19:24:39,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:39,104 INFO L225 Difference]: With dead ends: 121 [2018-04-05 19:24:39,104 INFO L226 Difference]: Without dead ends: 120 [2018-04-05 19:24:39,104 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 87 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2018-04-05 19:24:39,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-04-05 19:24:39,116 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 114. [2018-04-05 19:24:39,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-05 19:24:39,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-04-05 19:24:39,117 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 50 [2018-04-05 19:24:39,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:39,117 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-04-05 19:24:39,117 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-05 19:24:39,117 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-04-05 19:24:39,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-05 19:24:39,118 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:39,118 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:39,118 INFO L408 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:39,118 INFO L82 PathProgramCache]: Analyzing trace with hash -72993622, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:39,124 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:39,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:39,142 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:39,145 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-05 19:24:39,145 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:39,150 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:39,150 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:39,153 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:39,154 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-05 19:24:39,167 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:39,167 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:39,168 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-05 19:24:39,168 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:39,175 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-05 19:24:39,175 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:39,181 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:39,181 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-05 19:24:39,201 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 23 treesize of output 30 [2018-04-05 19:24:39,202 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-04-05 19:24:39,219 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-04-05 19:24:39,219 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:30, output treesize:52 [2018-04-05 19:24:39,441 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-05 19:24:39,441 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:41,348 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-05 19:24:41,368 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:24:41,368 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 24 [2018-04-05 19:24:41,368 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-05 19:24:41,369 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-05 19:24:41,369 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=531, Unknown=1, NotChecked=0, Total=600 [2018-04-05 19:24:41,369 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 25 states. [2018-04-05 19:24:44,890 WARN L151 SmtUtils]: Spent 3458ms on a formula simplification. DAG size of input: 65 DAG size of output 60 [2018-04-05 19:24:46,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:46,045 INFO L93 Difference]: Finished difference Result 145 states and 159 transitions. [2018-04-05 19:24:46,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-05 19:24:46,045 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 56 [2018-04-05 19:24:46,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:46,046 INFO L225 Difference]: With dead ends: 145 [2018-04-05 19:24:46,046 INFO L226 Difference]: Without dead ends: 144 [2018-04-05 19:24:46,047 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 88 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 157 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=274, Invalid=1207, Unknown=1, NotChecked=0, Total=1482 [2018-04-05 19:24:46,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-04-05 19:24:46,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 107. [2018-04-05 19:24:46,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-04-05 19:24:46,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 116 transitions. [2018-04-05 19:24:46,060 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 116 transitions. Word has length 56 [2018-04-05 19:24:46,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:46,061 INFO L459 AbstractCegarLoop]: Abstraction has 107 states and 116 transitions. [2018-04-05 19:24:46,061 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-05 19:24:46,061 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 116 transitions. [2018-04-05 19:24:46,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-05 19:24:46,061 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:46,062 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:46,062 INFO L408 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:46,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1791438736, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:46,068 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:46,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:46,087 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:46,124 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:46,125 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-05 19:24:46,144 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:46,145 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:46,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-05 19:24:46,148 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-05 19:24:46,149 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:46,160 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:46,166 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:46,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:46,174 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-05 19:24:46,260 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:46,267 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:46,285 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:46,285 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:46,328 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_32| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_32| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_32| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_32|))))) is different from false [2018-04-05 19:24:46,332 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_31| Int) (|v_main_#t~malloc12.base_32| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_31| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_31|))) (not (= (select .cse0 |v_main_#t~malloc12.base_32|) 0)) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_32| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_31| 0) |v_main_#t~malloc12.base_32| 0) |c_old(#valid)|)))) is different from false [2018-04-05 19:24:46,337 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_31| Int) (|v_main_#t~malloc10.base_29| Int) (|v_main_#t~malloc12.base_32| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_29| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_31| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_32| 1) |v_main_#t~malloc10.base_29| 0) |v_main_#t~malloc11.base_31| 0) |v_main_#t~malloc12.base_32| 0) |c_old(#valid)|) (not (= (select |c_#valid| |v_main_#t~malloc10.base_29|) 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_31|))) (not (= (select .cse0 |v_main_#t~malloc12.base_32|) 0)))))) is different from false [2018-04-05 19:24:46,355 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:46,377 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:46,377 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-05 19:24:46,378 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-05 19:24:46,378 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-05 19:24:46,378 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-05 19:24:46,378 INFO L87 Difference]: Start difference. First operand 107 states and 116 transitions. Second operand 16 states. [2018-04-05 19:24:46,404 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc11.base_31| Int) (|v_main_#t~malloc10.base_29| Int) (|v_main_#t~malloc12.base_32| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_29| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_31| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_32| 1) |v_main_#t~malloc10.base_29| 0) |v_main_#t~malloc11.base_31| 0) |v_main_#t~malloc12.base_32| 0) |c_old(#valid)|) (not (= (select |c_#valid| |v_main_#t~malloc10.base_29|) 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_31|))) (not (= (select .cse0 |v_main_#t~malloc12.base_32|) 0)))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-05 19:24:46,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:46,928 INFO L93 Difference]: Finished difference Result 199 states and 216 transitions. [2018-04-05 19:24:46,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-05 19:24:46,928 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-04-05 19:24:46,928 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:46,929 INFO L225 Difference]: With dead ends: 199 [2018-04-05 19:24:46,929 INFO L226 Difference]: Without dead ends: 188 [2018-04-05 19:24:46,930 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 107 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=228, Unknown=9, NotChecked=210, Total=506 [2018-04-05 19:24:46,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-04-05 19:24:46,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 185. [2018-04-05 19:24:46,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-04-05 19:24:46,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 202 transitions. [2018-04-05 19:24:46,966 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 202 transitions. Word has length 61 [2018-04-05 19:24:46,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:46,967 INFO L459 AbstractCegarLoop]: Abstraction has 185 states and 202 transitions. [2018-04-05 19:24:46,967 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-05 19:24:46,967 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 202 transitions. [2018-04-05 19:24:46,968 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-05 19:24:46,968 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:46,968 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:46,969 INFO L408 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:46,969 INFO L82 PathProgramCache]: Analyzing trace with hash -1032331687, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:46,983 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:47,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:47,005 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:47,054 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:47,054 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-05 19:24:47,070 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:47,070 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:47,071 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-05 19:24:47,073 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-05 19:24:47,073 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:47,082 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:47,088 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:47,095 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:47,095 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-05 19:24:47,147 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:47,152 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:47,164 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:47,165 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:47,201 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_34| Int)) (or (= |c_old(#valid)| (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_34| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_34| 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_34|))))) is different from false [2018-04-05 19:24:47,205 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_34| Int) (|v_main_#t~malloc11.base_33| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_33| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_34| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_33| 0) |v_main_#t~malloc12.base_34| 0) |c_old(#valid)|) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_34|))) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_33|)))))) is different from false [2018-04-05 19:24:47,210 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_34| Int) (|v_main_#t~malloc10.base_31| Int) (|v_main_#t~malloc11.base_33| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_31| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_33| 1))) (or (not (= (select .cse0 |v_main_#t~malloc12.base_34|) 0)) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_34| 1) |v_main_#t~malloc10.base_31| 0) |v_main_#t~malloc11.base_33| 0) |v_main_#t~malloc12.base_34| 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_33|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_31|) 0)))))) is different from false [2018-04-05 19:24:47,228 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:47,249 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:47,249 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-05 19:24:47,249 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-05 19:24:47,250 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-05 19:24:47,250 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-05 19:24:47,250 INFO L87 Difference]: Start difference. First operand 185 states and 202 transitions. Second operand 16 states. [2018-04-05 19:24:47,264 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc12.base_34| Int) (|v_main_#t~malloc10.base_31| Int) (|v_main_#t~malloc11.base_33| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_31| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_33| 1))) (or (not (= (select .cse0 |v_main_#t~malloc12.base_34|) 0)) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_34| 1) |v_main_#t~malloc10.base_31| 0) |v_main_#t~malloc11.base_33| 0) |v_main_#t~malloc12.base_34| 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_33|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_31|) 0)))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-05 19:24:47,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:47,971 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-05 19:24:47,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-05 19:24:47,971 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-05 19:24:47,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:47,973 INFO L225 Difference]: With dead ends: 277 [2018-04-05 19:24:47,974 INFO L226 Difference]: Without dead ends: 266 [2018-04-05 19:24:47,974 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=228, Unknown=9, NotChecked=210, Total=506 [2018-04-05 19:24:47,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-05 19:24:48,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-05 19:24:48,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-05 19:24:48,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-05 19:24:48,004 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-05 19:24:48,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:48,004 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-05 19:24:48,004 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-05 19:24:48,004 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-05 19:24:48,005 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-05 19:24:48,005 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:48,005 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:48,005 INFO L408 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:48,005 INFO L82 PathProgramCache]: Analyzing trace with hash -1753613222, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:48,011 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:48,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:48,030 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:48,072 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:48,073 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-05 19:24:48,089 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:48,090 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:48,090 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-05 19:24:48,095 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-05 19:24:48,096 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:48,104 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:48,111 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:48,119 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:48,119 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-05 19:24:48,191 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:48,196 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:48,209 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:48,209 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:48,250 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_36| Int)) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_36|))) (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_36| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_36| 0) |c_old(#valid)|))) is different from false [2018-04-05 19:24:48,253 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_35| Int) (|v_main_#t~malloc12.base_36| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_35| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_36| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_35| 0) |v_main_#t~malloc12.base_36| 0) |c_old(#valid)|) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_36|))) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_35|)))))) is different from false [2018-04-05 19:24:48,257 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc10.base_33| Int) (|v_main_#t~malloc11.base_35| Int) (|v_main_#t~malloc12.base_36| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_33| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_35| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_35|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_33|) 0)) (not (= (select .cse1 |v_main_#t~malloc12.base_36|) 0)) (= |c_old(#valid)| (store (store (store (store .cse1 |v_main_#t~malloc12.base_36| 1) |v_main_#t~malloc10.base_33| 0) |v_main_#t~malloc11.base_35| 0) |v_main_#t~malloc12.base_36| 0)))))) is different from false [2018-04-05 19:24:48,275 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:48,297 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:48,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-05 19:24:48,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-05 19:24:48,297 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-05 19:24:48,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-05 19:24:48,298 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-05 19:24:48,315 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc10.base_33| Int) (|v_main_#t~malloc11.base_35| Int) (|v_main_#t~malloc12.base_36| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_33| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_35| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_35|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_33|) 0)) (not (= (select .cse1 |v_main_#t~malloc12.base_36|) 0)) (= |c_old(#valid)| (store (store (store (store .cse1 |v_main_#t~malloc12.base_36| 1) |v_main_#t~malloc10.base_33| 0) |v_main_#t~malloc11.base_35| 0) |v_main_#t~malloc12.base_36| 0)))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-05 19:24:48,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:48,993 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-05 19:24:48,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-05 19:24:48,993 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-05 19:24:48,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:48,995 INFO L225 Difference]: With dead ends: 277 [2018-04-05 19:24:48,995 INFO L226 Difference]: Without dead ends: 266 [2018-04-05 19:24:48,996 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=228, Unknown=9, NotChecked=210, Total=506 [2018-04-05 19:24:48,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-05 19:24:49,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-05 19:24:49,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-05 19:24:49,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-05 19:24:49,026 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-05 19:24:49,027 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:49,027 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-05 19:24:49,027 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-05 19:24:49,027 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-05 19:24:49,028 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-04-05 19:24:49,028 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:49,028 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:49,028 INFO L408 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:49,029 INFO L82 PathProgramCache]: Analyzing trace with hash 740207311, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:49,041 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:49,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:49,061 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:49,097 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:49,098 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-05 19:24:49,114 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:49,115 INFO L700 Elim1Store]: detected not equals via solver [2018-04-05 19:24:49,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-05 19:24:49,117 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-05 19:24:49,118 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:49,125 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:49,130 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:49,136 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-05 19:24:49,137 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-05 19:24:49,205 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:49,210 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-05 19:24:49,223 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:49,223 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:49,264 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_38| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_38| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_38| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_38|))))) is different from false [2018-04-05 19:24:49,268 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_37| Int) (|v_main_#t~malloc12.base_38| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_37| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_37|))) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_38|))) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_38| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_37| 0) |v_main_#t~malloc12.base_38| 0) |c_old(#valid)|)))) is different from false [2018-04-05 19:24:49,272 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc10.base_35| Int) (|v_main_#t~malloc11.base_37| Int) (|v_main_#t~malloc12.base_38| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_35| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_37| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc12.base_38|))) (not (= (select .cse1 |v_main_#t~malloc11.base_37|) 0)) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_38| 1) |v_main_#t~malloc10.base_35| 0) |v_main_#t~malloc11.base_37| 0) |v_main_#t~malloc12.base_38| 0) |c_old(#valid)|) (not (= (select |c_#valid| |v_main_#t~malloc10.base_35|) 0)))))) is different from false [2018-04-05 19:24:49,287 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:49,308 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-05 19:24:49,309 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-05 19:24:49,309 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-05 19:24:49,309 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-05 19:24:49,309 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-05 19:24:49,309 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-05 19:24:49,325 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc10.base_35| Int) (|v_main_#t~malloc11.base_37| Int) (|v_main_#t~malloc12.base_38| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_35| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_37| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc12.base_38|))) (not (= (select .cse1 |v_main_#t~malloc11.base_37|) 0)) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_38| 1) |v_main_#t~malloc10.base_35| 0) |v_main_#t~malloc11.base_37| 0) |v_main_#t~malloc12.base_38| 0) |c_old(#valid)|) (not (= (select |c_#valid| |v_main_#t~malloc10.base_35|) 0))))))) is different from false [2018-04-05 19:24:49,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:49,917 INFO L93 Difference]: Finished difference Result 187 states and 203 transitions. [2018-04-05 19:24:49,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-05 19:24:49,917 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 63 [2018-04-05 19:24:49,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:49,918 INFO L225 Difference]: With dead ends: 187 [2018-04-05 19:24:49,918 INFO L226 Difference]: Without dead ends: 176 [2018-04-05 19:24:49,918 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 111 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=202, Unknown=8, NotChecked=198, Total=462 [2018-04-05 19:24:49,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-04-05 19:24:49,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 94. [2018-04-05 19:24:49,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-04-05 19:24:49,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 102 transitions. [2018-04-05 19:24:49,935 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 102 transitions. Word has length 63 [2018-04-05 19:24:49,936 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:49,936 INFO L459 AbstractCegarLoop]: Abstraction has 94 states and 102 transitions. [2018-04-05 19:24:49,936 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-05 19:24:49,936 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-04-05 19:24:49,936 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-04-05 19:24:49,936 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:49,937 INFO L355 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:49,937 INFO L408 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:49,937 INFO L82 PathProgramCache]: Analyzing trace with hash -452021334, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:49,943 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:49,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:49,967 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:49,970 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:49,970 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:49,973 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:49,973 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-05 19:24:50,211 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:50,211 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:50,540 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-05 19:24:50,561 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:24:50,561 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 27 [2018-04-05 19:24:50,561 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-05 19:24:50,561 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-05 19:24:50,562 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=671, Unknown=0, NotChecked=0, Total=756 [2018-04-05 19:24:50,562 INFO L87 Difference]: Start difference. First operand 94 states and 102 transitions. Second operand 28 states. [2018-04-05 19:24:51,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:51,904 INFO L93 Difference]: Finished difference Result 202 states and 221 transitions. [2018-04-05 19:24:51,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-05 19:24:51,904 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 76 [2018-04-05 19:24:51,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:51,906 INFO L225 Difference]: With dead ends: 202 [2018-04-05 19:24:51,906 INFO L226 Difference]: Without dead ends: 201 [2018-04-05 19:24:51,907 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 389 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=504, Invalid=2148, Unknown=0, NotChecked=0, Total=2652 [2018-04-05 19:24:51,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-04-05 19:24:51,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 149. [2018-04-05 19:24:51,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-05 19:24:51,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 163 transitions. [2018-04-05 19:24:51,941 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 163 transitions. Word has length 76 [2018-04-05 19:24:51,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:51,941 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 163 transitions. [2018-04-05 19:24:51,941 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-05 19:24:51,941 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 163 transitions. [2018-04-05 19:24:51,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-04-05 19:24:51,942 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:51,942 INFO L355 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:51,942 INFO L408 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:51,942 INFO L82 PathProgramCache]: Analyzing trace with hash 888884808, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:51,949 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:51,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:51,974 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:51,980 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:51,980 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:51,985 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:51,985 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-05 19:24:52,234 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-05 19:24:52,234 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:52,632 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-05 19:24:52,652 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:24:52,653 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 31 [2018-04-05 19:24:52,653 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-05 19:24:52,653 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-05 19:24:52,653 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=880, Unknown=0, NotChecked=0, Total=992 [2018-04-05 19:24:52,654 INFO L87 Difference]: Start difference. First operand 149 states and 163 transitions. Second operand 32 states. [2018-04-05 19:24:54,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:24:54,421 INFO L93 Difference]: Finished difference Result 268 states and 293 transitions. [2018-04-05 19:24:54,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-05 19:24:54,455 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 94 [2018-04-05 19:24:54,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:24:54,457 INFO L225 Difference]: With dead ends: 268 [2018-04-05 19:24:54,457 INFO L226 Difference]: Without dead ends: 267 [2018-04-05 19:24:54,458 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 521 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=713, Invalid=2827, Unknown=0, NotChecked=0, Total=3540 [2018-04-05 19:24:54,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-04-05 19:24:54,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 158. [2018-04-05 19:24:54,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-04-05 19:24:54,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 172 transitions. [2018-04-05 19:24:54,495 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 172 transitions. Word has length 94 [2018-04-05 19:24:54,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:24:54,496 INFO L459 AbstractCegarLoop]: Abstraction has 158 states and 172 transitions. [2018-04-05 19:24:54,496 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-05 19:24:54,496 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 172 transitions. [2018-04-05 19:24:54,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-04-05 19:24:54,497 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:24:54,497 INFO L355 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:24:54,497 INFO L408 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:24:54,497 INFO L82 PathProgramCache]: Analyzing trace with hash 1100056318, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:24:54,504 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:24:54,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:24:54,540 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:24:54,543 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:24:54,543 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:24:54,546 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:24:54,546 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-05 19:24:54,990 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-05 19:24:54,991 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:24:55,927 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-05 19:24:55,947 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:24:55,947 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 43 [2018-04-05 19:24:55,948 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-05 19:24:55,948 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-05 19:24:55,949 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1725, Unknown=0, NotChecked=0, Total=1892 [2018-04-05 19:24:55,949 INFO L87 Difference]: Start difference. First operand 158 states and 172 transitions. Second operand 44 states. [2018-04-05 19:24:57,532 WARN L151 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-05 19:25:00,629 WARN L151 SmtUtils]: Spent 438ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-05 19:25:01,070 WARN L151 SmtUtils]: Spent 386ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-05 19:25:01,613 WARN L148 SmtUtils]: Spent 398ms on a formula simplification that was a NOOP. DAG size: 65 [2018-04-05 19:25:02,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:25:02,053 INFO L93 Difference]: Finished difference Result 421 states and 460 transitions. [2018-04-05 19:25:02,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-04-05 19:25:02,053 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 128 [2018-04-05 19:25:02,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:25:02,055 INFO L225 Difference]: With dead ends: 421 [2018-04-05 19:25:02,055 INFO L226 Difference]: Without dead ends: 420 [2018-04-05 19:25:02,057 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 315 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2146 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=1735, Invalid=8771, Unknown=0, NotChecked=0, Total=10506 [2018-04-05 19:25:02,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-04-05 19:25:02,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 277. [2018-04-05 19:25:02,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-04-05 19:25:02,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 303 transitions. [2018-04-05 19:25:02,126 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 303 transitions. Word has length 128 [2018-04-05 19:25:02,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:25:02,126 INFO L459 AbstractCegarLoop]: Abstraction has 277 states and 303 transitions. [2018-04-05 19:25:02,126 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-05 19:25:02,126 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 303 transitions. [2018-04-05 19:25:02,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-04-05 19:25:02,127 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:25:02,128 INFO L355 BasicCegarLoop]: trace histogram [10, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:25:02,128 INFO L408 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:25:02,128 INFO L82 PathProgramCache]: Analyzing trace with hash 746499740, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:25:02,133 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:25:02,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:25:02,178 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:25:02,181 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:25:02,182 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:25:02,186 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:25:02,186 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-05 19:25:02,794 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-05 19:25:02,794 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:25:03,794 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-05 19:25:03,814 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:25:03,814 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 47 [2018-04-05 19:25:03,814 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-04-05 19:25:03,815 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-04-05 19:25:03,815 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=2042, Unknown=0, NotChecked=0, Total=2256 [2018-04-05 19:25:03,815 INFO L87 Difference]: Start difference. First operand 277 states and 303 transitions. Second operand 48 states. [2018-04-05 19:25:05,644 WARN L151 SmtUtils]: Spent 795ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-05 19:25:06,084 WARN L151 SmtUtils]: Spent 389ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-05 19:25:07,920 WARN L151 SmtUtils]: Spent 409ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-05 19:25:08,399 WARN L151 SmtUtils]: Spent 424ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-05 19:25:08,773 WARN L151 SmtUtils]: Spent 329ms on a formula simplification. DAG size of input: 48 DAG size of output 46 [2018-04-05 19:25:09,079 WARN L148 SmtUtils]: Spent 256ms on a formula simplification that was a NOOP. DAG size: 55 [2018-04-05 19:25:10,067 WARN L148 SmtUtils]: Spent 150ms on a formula simplification that was a NOOP. DAG size: 48 [2018-04-05 19:25:10,708 WARN L151 SmtUtils]: Spent 346ms on a formula simplification. DAG size of input: 51 DAG size of output 49 [2018-04-05 19:25:12,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:25:12,237 INFO L93 Difference]: Finished difference Result 554 states and 605 transitions. [2018-04-05 19:25:12,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-04-05 19:25:12,237 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-04-05 19:25:12,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:25:12,239 INFO L225 Difference]: With dead ends: 554 [2018-04-05 19:25:12,240 INFO L226 Difference]: Without dead ends: 553 [2018-04-05 19:25:12,242 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 354 GetRequests, 246 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2514 ImplicationChecksByTransitivity, 8.7s TimeCoverageRelationStatistics Valid=2093, Invalid=9897, Unknown=0, NotChecked=0, Total=11990 [2018-04-05 19:25:12,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2018-04-05 19:25:12,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 286. [2018-04-05 19:25:12,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-04-05 19:25:12,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 312 transitions. [2018-04-05 19:25:12,326 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 312 transitions. Word has length 146 [2018-04-05 19:25:12,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:25:12,326 INFO L459 AbstractCegarLoop]: Abstraction has 286 states and 312 transitions. [2018-04-05 19:25:12,327 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-04-05 19:25:12,327 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 312 transitions. [2018-04-05 19:25:12,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-04-05 19:25:12,327 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:25:12,328 INFO L355 BasicCegarLoop]: trace histogram [16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:25:12,328 INFO L408 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:25:12,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1895798874, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:25:12,337 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:25:12,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:25:12,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:25:12,394 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:25:12,394 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:25:12,396 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:25:12,397 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-05 19:25:13,693 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-05 19:25:13,693 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:25:15,962 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-05 19:25:15,983 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:25:15,983 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 75 [2018-04-05 19:25:15,984 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-04-05 19:25:15,984 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-04-05 19:25:15,985 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=5249, Unknown=0, NotChecked=0, Total=5700 [2018-04-05 19:25:15,985 INFO L87 Difference]: Start difference. First operand 286 states and 312 transitions. Second operand 76 states. [2018-04-05 19:25:17,143 WARN L151 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 107 DAG size of output 101 [2018-04-05 19:25:17,622 WARN L151 SmtUtils]: Spent 402ms on a formula simplification. DAG size of input: 88 DAG size of output 74 [2018-04-05 19:25:18,662 WARN L151 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 121 DAG size of output 97 [2018-04-05 19:25:18,919 WARN L151 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-05 19:25:19,639 WARN L148 SmtUtils]: Spent 448ms on a formula simplification that was a NOOP. DAG size: 102 [2018-04-05 19:25:21,676 WARN L151 SmtUtils]: Spent 437ms on a formula simplification. DAG size of input: 106 DAG size of output 88 [2018-04-05 19:25:21,917 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-05 19:25:23,738 WARN L148 SmtUtils]: Spent 111ms on a formula simplification that was a NOOP. DAG size: 83 [2018-04-05 19:25:24,159 WARN L151 SmtUtils]: Spent 287ms on a formula simplification. DAG size of input: 92 DAG size of output 78 [2018-04-05 19:25:24,433 WARN L151 SmtUtils]: Spent 162ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-05 19:25:25,234 WARN L151 SmtUtils]: Spent 709ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-05 19:25:26,017 WARN L148 SmtUtils]: Spent 413ms on a formula simplification that was a NOOP. DAG size: 77 [2018-04-05 19:25:27,969 WARN L151 SmtUtils]: Spent 347ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-05 19:25:29,589 WARN L148 SmtUtils]: Spent 154ms on a formula simplification that was a NOOP. DAG size: 59 [2018-04-05 19:25:30,416 WARN L151 SmtUtils]: Spent 708ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-05 19:25:30,937 WARN L151 SmtUtils]: Spent 425ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-05 19:25:34,434 WARN L151 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 109 DAG size of output 89 [2018-04-05 19:25:35,139 WARN L151 SmtUtils]: Spent 550ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-05 19:25:35,543 WARN L148 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 113 [2018-04-05 19:25:37,292 WARN L151 SmtUtils]: Spent 818ms on a formula simplification. DAG size of input: 120 DAG size of output 98 [2018-04-05 19:25:37,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-05 19:25:37,349 INFO L93 Difference]: Finished difference Result 865 states and 944 transitions. [2018-04-05 19:25:37,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2018-04-05 19:25:37,350 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 232 [2018-04-05 19:25:37,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-05 19:25:37,353 INFO L225 Difference]: With dead ends: 865 [2018-04-05 19:25:37,353 INFO L226 Difference]: Without dead ends: 864 [2018-04-05 19:25:37,359 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 587 GetRequests, 390 SyntacticMatches, 0 SemanticMatches, 197 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9800 ImplicationChecksByTransitivity, 22.0s TimeCoverageRelationStatistics Valid=5709, Invalid=33693, Unknown=0, NotChecked=0, Total=39402 [2018-04-05 19:25:37,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states. [2018-04-05 19:25:37,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 533. [2018-04-05 19:25:37,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 533 states. [2018-04-05 19:25:37,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 533 states and 583 transitions. [2018-04-05 19:25:37,549 INFO L78 Accepts]: Start accepts. Automaton has 533 states and 583 transitions. Word has length 232 [2018-04-05 19:25:37,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-05 19:25:37,549 INFO L459 AbstractCegarLoop]: Abstraction has 533 states and 583 transitions. [2018-04-05 19:25:37,550 INFO L460 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-04-05 19:25:37,550 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 583 transitions. [2018-04-05 19:25:37,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-04-05 19:25:37,551 INFO L347 BasicCegarLoop]: Found error trace [2018-04-05 19:25:37,552 INFO L355 BasicCegarLoop]: trace histogram [18, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-05 19:25:37,552 INFO L408 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-05 19:25:37,552 INFO L82 PathProgramCache]: Analyzing trace with hash 947464516, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-05 19:25:37,564 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-05 19:25:37,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-05 19:25:37,631 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-05 19:25:37,647 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-05 19:25:37,647 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-05 19:25:37,655 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-05 19:25:37,655 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-05 19:25:38,986 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-05 19:25:38,986 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-05 19:25:41,477 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-05 19:25:41,499 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-05 19:25:41,515 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 79 [2018-04-05 19:25:41,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-04-05 19:25:41,516 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-04-05 19:25:41,517 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=566, Invalid=5754, Unknown=0, NotChecked=0, Total=6320 [2018-04-05 19:25:41,517 INFO L87 Difference]: Start difference. First operand 533 states and 583 transitions. Second operand 80 states. [2018-04-05 19:25:42,906 WARN L151 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 103 DAG size of output 89 [2018-04-05 19:25:43,222 WARN L151 SmtUtils]: Spent 180ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-05 19:25:44,079 WARN L151 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 90 DAG size of output 78 [2018-04-05 19:25:44,322 WARN L151 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 87 DAG size of output 75 [2018-04-05 19:25:45,851 WARN L151 SmtUtils]: Spent 409ms on a formula simplification. DAG size of input: 120 DAG size of output 98 [2018-04-05 19:25:46,486 WARN L151 SmtUtils]: Spent 520ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-05 19:25:47,069 WARN L151 SmtUtils]: Spent 491ms on a formula simplification. DAG size of input: 83 DAG size of output 73 [2018-04-05 19:25:47,457 WARN L148 SmtUtils]: Spent 290ms on a formula simplification that was a NOOP. DAG size: 102 [2018-04-05 19:25:47,706 WARN L148 SmtUtils]: Spent 133ms on a formula simplification that was a NOOP. DAG size: 101 [2018-04-05 19:25:48,183 WARN L151 SmtUtils]: Spent 215ms on a formula simplification. DAG size of input: 78 DAG size of output 68 [2018-04-05 19:25:49,409 WARN L148 SmtUtils]: Spent 426ms on a formula simplification that was a NOOP. DAG size: 95 [2018-04-05 19:25:50,292 WARN L151 SmtUtils]: Spent 464ms on a formula simplification. DAG size of input: 106 DAG size of output 88 [2018-04-05 19:25:50,932 WARN L151 SmtUtils]: Spent 517ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-05 19:25:51,248 WARN L151 SmtUtils]: Spent 222ms on a formula simplification. DAG size of input: 74 DAG size of output 66 [2018-04-05 19:25:51,959 WARN L148 SmtUtils]: Spent 434ms on a formula simplification that was a NOOP. DAG size: 89 [2018-04-05 19:25:52,479 WARN L151 SmtUtils]: Spent 260ms on a formula simplification. DAG size of input: 69 DAG size of output 61 [2018-04-05 19:25:54,166 WARN L151 SmtUtils]: Spent 427ms on a formula simplification. DAG size of input: 92 DAG size of output 78 Received shutdown request... [2018-04-05 19:25:54,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-04-05 19:25:54,667 WARN L519 AbstractCegarLoop]: Verification canceled [2018-04-05 19:25:54,670 WARN L197 ceAbstractionStarter]: Timeout [2018-04-05 19:25:54,670 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 05.04 07:25:54 BasicIcfg [2018-04-05 19:25:54,670 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-05 19:25:54,671 INFO L168 Benchmark]: Toolchain (without parser) took 237209.77 ms. Allocated memory was 305.7 MB in the beginning and 552.6 MB in the end (delta: 246.9 MB). Free memory was 243.3 MB in the beginning and 357.5 MB in the end (delta: -114.2 MB). Peak memory consumption was 132.7 MB. Max. memory is 5.3 GB. [2018-04-05 19:25:54,671 INFO L168 Benchmark]: CDTParser took 0.20 ms. Allocated memory is still 305.7 MB. Free memory is still 266.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-05 19:25:54,672 INFO L168 Benchmark]: CACSL2BoogieTranslator took 317.59 ms. Allocated memory is still 305.7 MB. Free memory was 243.3 MB in the beginning and 219.4 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. [2018-04-05 19:25:54,672 INFO L168 Benchmark]: Boogie Preprocessor took 50.61 ms. Allocated memory is still 305.7 MB. Free memory was 219.4 MB in the beginning and 215.4 MB in the end (delta: 4.0 MB). Peak memory consumption was 4.0 MB. Max. memory is 5.3 GB. [2018-04-05 19:25:54,672 INFO L168 Benchmark]: RCFGBuilder took 471.65 ms. Allocated memory was 305.7 MB in the beginning and 467.1 MB in the end (delta: 161.5 MB). Free memory was 215.4 MB in the beginning and 399.5 MB in the end (delta: -184.0 MB). Peak memory consumption was 20.1 MB. Max. memory is 5.3 GB. [2018-04-05 19:25:54,672 INFO L168 Benchmark]: IcfgTransformer took 141598.57 ms. Allocated memory was 467.1 MB in the beginning and 980.9 MB in the end (delta: 513.8 MB). Free memory was 399.5 MB in the beginning and 589.7 MB in the end (delta: -190.2 MB). Peak memory consumption was 323.6 MB. Max. memory is 5.3 GB. [2018-04-05 19:25:54,672 INFO L168 Benchmark]: TraceAbstraction took 94766.64 ms. Allocated memory was 980.9 MB in the beginning and 552.6 MB in the end (delta: -428.3 MB). Free memory was 589.7 MB in the beginning and 357.5 MB in the end (delta: 232.2 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-04-05 19:25:54,674 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20 ms. Allocated memory is still 305.7 MB. Free memory is still 266.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 317.59 ms. Allocated memory is still 305.7 MB. Free memory was 243.3 MB in the beginning and 219.4 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 50.61 ms. Allocated memory is still 305.7 MB. Free memory was 219.4 MB in the beginning and 215.4 MB in the end (delta: 4.0 MB). Peak memory consumption was 4.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 471.65 ms. Allocated memory was 305.7 MB in the beginning and 467.1 MB in the end (delta: 161.5 MB). Free memory was 215.4 MB in the beginning and 399.5 MB in the end (delta: -184.0 MB). Peak memory consumption was 20.1 MB. Max. memory is 5.3 GB. * IcfgTransformer took 141598.57 ms. Allocated memory was 467.1 MB in the beginning and 980.9 MB in the end (delta: 513.8 MB). Free memory was 399.5 MB in the beginning and 589.7 MB in the end (delta: -190.2 MB). Peak memory consumption was 323.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 94766.64 ms. Allocated memory was 980.9 MB in the beginning and 552.6 MB in the end (delta: -428.3 MB). Free memory was 589.7 MB in the beginning and 357.5 MB in the end (delta: 232.2 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 78 LocStat_MAX_WEQGRAPH_SIZE : 2 LocStat_MAX_SIZEOF_WEQEDGELABEL : 3 LocStat_NO_SUPPORTING_EQUALITIES : 1596 LocStat_NO_SUPPORTING_DISEQUALITIES : 433 LocStat_NO_DISJUNCTIONS : -156 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 96 TransStat_MAX_WEQGRAPH_SIZE : 4 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 111 TransStat_NO_SUPPORTING_DISEQUALITIES : 14 TransStat_NO_DISJUNCTIONS : 99 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 19572.52 RENAME_VARIABLES(MILLISECONDS) : 1076.77 UNFREEZE(MILLISECONDS) : 0.00 CONJOIN(MILLISECONDS) : 19644.26 PROJECTAWAY(MILLISECONDS) : 46252.43 ADD_WEAK_EQUALITY(MILLISECONDS) : 6.16 DISJOIN(MILLISECONDS) : 649.40 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 1149.45 ADD_EQUALITY(MILLISECONDS) : 9.27 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.00 ADD_DISEQUALITY(MILLISECONDS) : 0.44 #CONJOIN_DISJUNCTIVE : 2117 #RENAME_VARIABLES : 4463 #UNFREEZE : 0 #CONJOIN : 2494 #PROJECTAWAY : 2318 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 747 #RENAME_VARIABLES_DISJUNCTIVE : 4370 #ADD_EQUALITY : 112 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 11 - StatisticsResult: WeqCcManagerStatistics FREEZE(MILLISECONDS) : 93783.32 ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 19611.92 FILTERREDUNDANT(MILLISECONDS) : 0.00 REPORTWEQ(MILLISECONDS) : 6.00 JOIN(MILLISECONDS) : 614.78 RENAMEVARS(MILLISECONDS) : 1040.38 FLATTENLABELS(MILLISECONDS) : 0.00 COPY(MILLISECONDS) : 0.00 ISSTRONGERTHAN(MILLISECONDS) : 70636.16 ISLABELSTRONGERTHAN(MILLISECONDS) : 10873.63 ISWEQGRAPHSTRONGERTHAN(MILLISECONDS) : 487.78 UNFREEZE(MILLISECONDS) : 431.33 REPORTCONTAINS(MILLISECONDS) : 5.51 PROJECTAWAY(MILLISECONDS) : 45903.85 MEETEDGELABELS(MILLISECONDS) : 2706.43 REPORTEQUALITY(MILLISECONDS) : 4269.57 ADDALLNODES(MILLISECONDS) : 1415.27 REPORTDISEQUALITY(MILLISECONDS) : 18.48 WEQGRAPHJOIN(MILLISECONDS) : 238.35 #FREEZE : 29169 #ADDNODE : 0 #MEET : 1842 #FILTERREDUNDANT : 0 #REPORTWEQ : 14 #JOIN : 747 #RENAMEVARS : 4463 #FLATTENLABELS : 0 #COPY : 0 #ISSTRONGERTHAN : 10431 #ISLABELSTRONGERTHAN : 1165575 #ISWEQGRAPHSTRONGERTHAN : 4840 #UNFREEZE : 12153 #REPORTCONTAINS : 266 #PROJECTAWAY : 5848 #MEETEDGELABELS : 24525 #REPORTEQUALITY : 45657 #ADDALLNODES : 1842 #REPORTDISEQUALITY : 10545 #WEQGRAPHJOIN : 747 - StatisticsResult: CcManagerStatistics ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 42538.00 REPORT_EQUALITY(MILLISECONDS) : 16865.67 FILTERREDUNDANT(MILLISECONDS) : 38451.85 ADD_ALL_ELEMENTS(MILLISECONDS) : 6516.56 JOIN(MILLISECONDS) : 277.50 ALIGN_ELEMENTS(MILLISECONDS) : 7721.57 COPY(MILLISECONDS) : 0.00 REPORT_DISEQUALITY(MILLISECONDS) : 2064.28 UNFREEZE(MILLISECONDS) : 0.00 OVERALL(MILLISECONDS) : 64839.07 REPORTCONTAINS(MILLISECONDS) : 113.74 IS_STRONGER_THAN_NO_CACHING(MILLISECONDS) : 14752.23 REMOVE(MILLISECONDS) : 0.00 IS_STRONGER_THAN_W_CACHING(MILLISECONDS) : 0.00 PROJECT_TO_ELEMENTS(MILLISECONDS) : 6624.18 #ADDNODE : 0 #MEET : 105070 #REPORT_EQUALITY : 2235784 #FILTERREDUNDANT : 2485338 #ADD_ALL_ELEMENTS : 334004 #JOIN : 747 #ALIGN_ELEMENTS : 109881 #COPY : 0 #REPORT_DISEQUALITY : 574119 #UNFREEZE : 0 #OVERALL : 8058899 #REPORTCONTAINS : 9007 #IS_STRONGER_THAN_NO_CACHING : 2107562 #REMOVE : 0 #IS_STRONGER_THAN_W_CACHING : 0 #PROJECT_TO_ELEMENTS : 97387 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - TimeoutResultAtElement [Line: 564]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 564). Cancelled while BasicCegarLoop was constructing difference of abstraction (533states) and interpolant automaton (currently 66 states, 80 states before enhancement), while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 89. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 82 locations, 9 error locations. TIMEOUT Result, 94.7s OverallTime, 21 OverallIterations, 18 TraceHistogramMax, 66.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1960 SDtfs, 12274 SDslu, 21572 SDs, 0 SdLazy, 12840 SolverSat, 900 SolverUnsat, 26 SolverUnknown, 0 SolverNotchecked, 8.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3778 GetRequests, 2826 SyntacticMatches, 26 SemanticMatches, 925 ConstructedPredicates, 24 IntricatePredicates, 0 DeprecatedPredicates, 19734 ImplicationChecksByTransitivity, 78.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=533occurred in iteration=20, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 20 MinimizatonAttempts, 1403 StatesRemovedByMinimization, 17 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 25.8s InterpolantComputationTime, 1664 NumberOfCodeBlocks, 1664 NumberOfCodeBlocksAsserted, 21 NumberOfCheckSat, 3286 ConstructedInterpolants, 1262 QuantifiedInterpolants, 7818977 SizeOfPredicates, 250 NumberOfNonLiveVariables, 4622 ConjunctsInSsa, 503 ConjunctsInUnsatCore, 42 InterpolantComputations, 26 PerfectInterpolantSequences, 272/4604 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-04-05_19-25-54-684.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-04-05_19-25-54-684.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-04-05_19-25-54-684.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-1-2018-04-05_19-25-54-684.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-2-2018-04-05_19-25-54-684.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-04-05_19-25-54-684.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-05_19-25-54-684.csv Completed graceful shutdown