java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-35b68b2 [2018-04-06 23:13:09,992 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-06 23:13:09,993 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-06 23:13:10,009 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-06 23:13:10,009 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-06 23:13:10,010 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-06 23:13:10,011 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-06 23:13:10,013 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-06 23:13:10,015 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-06 23:13:10,016 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-06 23:13:10,017 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-06 23:13:10,018 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-06 23:13:10,019 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-06 23:13:10,020 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-06 23:13:10,021 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-06 23:13:10,023 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-06 23:13:10,025 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-06 23:13:10,027 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-06 23:13:10,028 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-06 23:13:10,030 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-06 23:13:10,032 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-06 23:13:10,032 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-06 23:13:10,033 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-06 23:13:10,034 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-06 23:13:10,035 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-06 23:13:10,036 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-06 23:13:10,037 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-06 23:13:10,037 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-06 23:13:10,038 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-06 23:13:10,039 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-06 23:13:10,039 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-06 23:13:10,040 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf [2018-04-06 23:13:10,064 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-06 23:13:10,064 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-06 23:13:10,064 INFO L131 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2018-04-06 23:13:10,064 INFO L133 SettingsManager]: * ultimate.logging.details=de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation=DEBUG; [2018-04-06 23:13:10,065 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-04-06 23:13:10,065 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-04-06 23:13:10,065 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-04-06 23:13:10,065 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-04-06 23:13:10,065 INFO L133 SettingsManager]: * Parallel states before merging=1 [2018-04-06 23:13:10,066 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-04-06 23:13:10,066 INFO L131 SettingsManager]: Preferences of LTL2Aut differ from their defaults: [2018-04-06 23:13:10,066 INFO L133 SettingsManager]: * Property to check=[] a a: x > 42 [2018-04-06 23:13:10,066 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-06 23:13:10,066 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-06 23:13:10,067 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-06 23:13:10,068 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-06 23:13:10,068 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-04-06 23:13:10,068 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-04-06 23:13:10,068 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-06 23:13:10,069 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-06 23:13:10,069 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-06 23:13:10,069 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-06 23:13:10,069 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-06 23:13:10,069 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-04-06 23:13:10,069 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-04-06 23:13:10,069 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:13:10,070 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-04-06 23:13:10,070 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-04-06 23:13:10,071 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-04-06 23:13:10,071 INFO L131 SettingsManager]: Preferences of Boogie Printer differ from their defaults: [2018-04-06 23:13:10,071 INFO L133 SettingsManager]: * Dump path:=C:\Users\alex\AppData\Local\Temp\ [2018-04-06 23:13:10,105 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-06 23:13:10,117 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-06 23:13:10,120 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-06 23:13:10,122 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-06 23:13:10,122 INFO L276 PluginConnector]: CDTParser initialized [2018-04-06 23:13:10,123 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,430 INFO L225 CDTParser]: Created temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGf13bb900f [2018-04-06 23:13:10,610 INFO L287 CDTParser]: IsIndexed: true [2018-04-06 23:13:10,614 INFO L288 CDTParser]: Found 1 translation units. [2018-04-06 23:13:10,615 INFO L168 CDTParser]: Scanning diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,625 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-06 23:13:10,625 INFO L215 ultiparseSymbolTable]: [2018-04-06 23:13:10,625 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-06 23:13:10,626 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff ('diff') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-06 23:13:10,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,626 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____socklen_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__size_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____intptr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsword_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,627 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,628 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uint in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,629 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____useconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_set in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____qaddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,630 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,631 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__register_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,632 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ushort in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,633 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,634 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ulong in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__wchar_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__lldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,635 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__div_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,636 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,637 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,638 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-06 23:13:10,657 INFO L330 CDTParser]: Deleted temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGf13bb900f [2018-04-06 23:13:10,661 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-06 23:13:10,663 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-04-06 23:13:10,665 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-06 23:13:10,665 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-06 23:13:10,670 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-06 23:13:10,670 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.04 11:13:10" (1/1) ... [2018-04-06 23:13:10,673 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@20b0da7f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:10, skipping insertion in model container [2018-04-06 23:13:10,673 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.04 11:13:10" (1/1) ... [2018-04-06 23:13:10,689 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-06 23:13:10,720 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-06 23:13:10,918 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-06 23:13:10,975 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-06 23:13:10,983 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-06 23:13:11,019 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11 WrapperNode [2018-04-06 23:13:11,020 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-06 23:13:11,021 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-06 23:13:11,021 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-06 23:13:11,021 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-06 23:13:11,032 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,032 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,045 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,046 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,058 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,064 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,068 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,073 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-06 23:13:11,074 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-06 23:13:11,074 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-06 23:13:11,074 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-06 23:13:11,075 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-06 23:13:11,210 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-06 23:13:11,210 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-06 23:13:11,210 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-06 23:13:11,210 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-06 23:13:11,210 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-06 23:13:11,211 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-06 23:13:11,211 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-06 23:13:11,212 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-06 23:13:11,213 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-06 23:13:11,214 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-06 23:13:11,215 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-06 23:13:11,216 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-06 23:13:11,217 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-06 23:13:11,218 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-06 23:13:11,219 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-06 23:13:11,220 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-06 23:13:11,221 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-06 23:13:11,222 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-06 23:13:11,223 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-06 23:13:11,686 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-06 23:13:11,687 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.04 11:13:11 BoogieIcfgContainer [2018-04-06 23:13:11,687 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-06 23:13:11,688 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-04-06 23:13:11,688 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-04-06 23:13:11,689 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-04-06 23:13:11,693 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.04 11:13:11" (1/1) ... [2018-04-06 23:13:11,703 INFO L139 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-04-06 23:13:11,703 INFO L140 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-04-06 23:13:11,719 INFO L299 apSepIcfgTransformer]: Heap separator: starting memloc-array-style preprocessing [2018-04-06 23:13:11,740 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-06 23:13:11,755 INFO L332 apSepIcfgTransformer]: finished MemlocArrayUpdater, created 2 location literals (each corresponds to one heap write) [2018-04-06 23:13:11,766 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-06 23:13:11,782 INFO L412 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-04-06 23:13:11,783 DEBUG L416 apSepIcfgTransformer]: storeIndexInfoToLocLiteral: Map: (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) : |mll_L558'_0| (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) : |mll_L558'_1| [2018-04-06 23:13:11,786 DEBUG L418 apSepIcfgTransformer]: edgeToIndexToStoreIndexInfo: NestedMap2: (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 : (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2) : (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) [2018-04-06 23:13:11,859 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=1) [2018-04-06 23:13:51,344 INFO L314 AbstractInterpreter]: Visited 90 different actions 765 times. Merged at 58 different actions 438 times. Widened at 1 different actions 3 times. Found 64 fixpoints after 14 different actions. Largest state had 46 variables. [2018-04-06 23:13:51,347 INFO L424 apSepIcfgTransformer]: finished equality analysis [2018-04-06 23:13:51,356 INFO L195 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 4 [2018-04-06 23:13:51,356 INFO L434 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-04-06 23:13:51,357 INFO L435 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-04-06 23:13:51,357 INFO L437 apSepIcfgTransformer]: select infos: Set: ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-06 23:13:51,379 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_32 [2018-04-06 23:13:51,380 DEBUG L374 HeapPartitionManager]: with contents [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-06 23:13:51,380 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-06 23:13:51,380 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-06 23:13:51,380 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-06 23:13:51,380 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_31 [2018-04-06 23:13:51,381 DEBUG L374 HeapPartitionManager]: with contents [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-06 23:13:51,381 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-06 23:13:51,381 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-06 23:13:51,381 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-06 23:13:51,381 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-06 23:13:51,381 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-06 23:13:51,381 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-06 23:13:51,382 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-06 23:13:51,382 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-06 23:13:51,382 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-06 23:13:51,382 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-06 23:13:51,382 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-06 23:13:51,383 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-06 23:13:51,383 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-06 23:13:51,383 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-06 23:13:51,383 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-06 23:13:51,383 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-06 23:13:51,383 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-06 23:13:51,384 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-06 23:13:51,384 INFO L330 HeapPartitionManager]: partitioning result: [2018-04-06 23:13:51,384 INFO L335 HeapPartitionManager]: location blocks for array group [#memory_int] [2018-04-06 23:13:51,384 INFO L344 HeapPartitionManager]: at dimension 0 [2018-04-06 23:13:51,384 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-06 23:13:51,384 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-06 23:13:51,385 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-06 23:13:51,385 DEBUG L356 HeapPartitionManager]: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-06 23:13:51,385 INFO L344 HeapPartitionManager]: at dimension 1 [2018-04-06 23:13:51,385 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-06 23:13:51,385 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-06 23:13:51,385 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-06 23:13:51,386 DEBUG L356 HeapPartitionManager]: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-06 23:13:51,386 INFO L131 ransitionTransformer]: executing heap partitioning transformation [2018-04-06 23:13:51,389 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,389 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,389 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,390 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,390 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,390 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,390 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,390 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,390 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,390 DEBUG L281 ransitionTransformer]: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] [2018-04-06 23:13:51,390 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,390 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,391 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,391 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,391 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,391 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,391 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,391 DEBUG L281 ransitionTransformer]: Formula: (and (<= 0 (+ |v_main_#t~nondet8_1| 2147483648)) (<= |v_main_#t~nondet8_1| 2147483647)) InVars {main_#t~nondet8=|v_main_#t~nondet8_1|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_1|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,391 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,391 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,392 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,392 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] [2018-04-06 23:13:51,392 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,392 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,392 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,392 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Alen~0_1 |v_main_#t~nondet8_2|) InVars {main_#t~nondet8=|v_main_#t~nondet8_2|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_2|, main_~Alen~0=v_main_~Alen~0_1} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-06 23:13:51,392 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,392 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,392 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,392 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,393 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,393 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,393 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,393 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~nondet8=|v_main_#t~nondet8_3|} AuxVars[] AssignedVars[main_#t~nondet8] [2018-04-06 23:13:51,393 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,393 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,393 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,393 DEBUG L281 ransitionTransformer]: Formula: (and (<= |v_main_#t~nondet9_1| 2147483647) (<= 0 (+ |v_main_#t~nondet9_1| 2147483648))) InVars {main_#t~nondet9=|v_main_#t~nondet9_1|} OutVars{main_#t~nondet9=|v_main_#t~nondet9_1|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,393 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,393 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,394 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,394 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Blen~0_1 |v_main_#t~nondet9_2|) InVars {main_#t~nondet9=|v_main_#t~nondet9_2|} OutVars{main_~Blen~0=v_main_~Blen~0_1, main_#t~nondet9=|v_main_#t~nondet9_2|} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-06 23:13:51,394 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,394 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,394 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,394 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~nondet9=|v_main_#t~nondet9_3|} AuxVars[] AssignedVars[main_#t~nondet9] [2018-04-06 23:13:51,394 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,395 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,395 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,395 DEBUG L281 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Alen~0_2) (< v_main_~Alen~0_2 1)) InVars {main_~Alen~0=v_main_~Alen~0_2} OutVars{main_~Alen~0=v_main_~Alen~0_2} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,395 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,395 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,395 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,396 DEBUG L281 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Alen~0_4)) (not (< v_main_~Alen~0_4 1))) InVars {main_~Alen~0=v_main_~Alen~0_4} OutVars{main_~Alen~0=v_main_~Alen~0_4} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,396 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,396 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,396 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,396 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Alen~0_3 1) InVars {} OutVars{main_~Alen~0=v_main_~Alen~0_3} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-06 23:13:51,396 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,396 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,396 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,396 DEBUG L281 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Blen~0_2) (< v_main_~Blen~0_2 1)) InVars {main_~Blen~0=v_main_~Blen~0_2} OutVars{main_~Blen~0=v_main_~Blen~0_2} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,396 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,397 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,397 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,397 DEBUG L281 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Blen~0_4)) (not (< v_main_~Blen~0_4 1))) InVars {main_~Blen~0=v_main_~Blen~0_4} OutVars{main_~Blen~0=v_main_~Blen~0_4} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,397 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,397 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,397 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,397 DEBUG L281 ransitionTransformer]: Formula: (= v_main_~Blen~0_3 1) InVars {} OutVars{main_~Blen~0=v_main_~Blen~0_3} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-06 23:13:51,397 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,397 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,398 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,398 DEBUG L281 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc10.base_1|)) (= (store |v_#valid_12| |v_main_#t~malloc10.base_1| 1) |v_#valid_11|) (= |v_main_#t~malloc10.offset_1| 0) (= 0 (select |v_#valid_12| |v_main_#t~malloc10.base_1|)) (= |v_#length_9| (store |v_#length_10| |v_main_#t~malloc10.base_1| (* 4 v_main_~Alen~0_5)))) InVars {#length=|v_#length_10|, main_~Alen~0=v_main_~Alen~0_5, #valid=|v_#valid_12|} OutVars{#length=|v_#length_9|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_1|, main_~Alen~0=v_main_~Alen~0_5, main_#t~malloc10.base=|v_main_#t~malloc10.base_1|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc10.offset, main_#t~malloc10.base] [2018-04-06 23:13:51,398 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,398 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,398 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,398 DEBUG L281 ransitionTransformer]: Formula: (and (= v_main_~A~0.offset_1 |v_main_#t~malloc10.offset_2|) (= v_main_~A~0.base_1 |v_main_#t~malloc10.base_2|)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|} OutVars{main_~A~0.offset=v_main_~A~0.offset_1, main_~A~0.base=v_main_~A~0.base_1, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|, main_#t~malloc10.base=|v_main_#t~malloc10.base_2|} AuxVars[] AssignedVars[main_~A~0.offset, main_~A~0.base] [2018-04-06 23:13:51,398 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,398 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,399 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,399 DEBUG L281 ransitionTransformer]: Formula: (and (= |v_main_#t~malloc11.offset_1| 0) (not (= |v_main_#t~malloc11.base_1| 0)) (= (store |v_#valid_14| |v_main_#t~malloc11.base_1| 1) |v_#valid_13|) (= |v_#length_11| (store |v_#length_12| |v_main_#t~malloc11.base_1| (* 4 v_main_~Blen~0_5))) (= 0 (select |v_#valid_14| |v_main_#t~malloc11.base_1|))) InVars {#length=|v_#length_12|, main_~Blen~0=v_main_~Blen~0_5, #valid=|v_#valid_14|} OutVars{#length=|v_#length_11|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_1|, main_~Blen~0=v_main_~Blen~0_5, main_#t~malloc11.base=|v_main_#t~malloc11.base_1|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc11.offset, main_#t~malloc11.base] [2018-04-06 23:13:51,399 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,399 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,399 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,399 DEBUG L281 ransitionTransformer]: Formula: (and (= v_main_~B~0.offset_1 |v_main_#t~malloc11.offset_2|) (= v_main_~B~0.base_1 |v_main_#t~malloc11.base_2|)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_2|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|} OutVars{main_~B~0.offset=v_main_~B~0.offset_1, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|, main_~B~0.base=v_main_~B~0.base_1, main_#t~malloc11.base=|v_main_#t~malloc11.base_2|} AuxVars[] AssignedVars[main_~B~0.offset, main_~B~0.base] [2018-04-06 23:13:51,399 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,399 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,399 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,400 DEBUG L281 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc12.base_1|)) (= |v_#valid_15| (store |v_#valid_16| |v_main_#t~malloc12.base_1| 1)) (= 0 |v_main_#t~malloc12.offset_1|) (= 0 (select |v_#valid_16| |v_main_#t~malloc12.base_1|)) (= |v_#length_13| (store |v_#length_14| |v_main_#t~malloc12.base_1| (* 4 v_main_~Alen~0_6)))) InVars {#length=|v_#length_14|, main_~Alen~0=v_main_~Alen~0_6, #valid=|v_#valid_16|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_1|, #length=|v_#length_13|, main_~Alen~0=v_main_~Alen~0_6, main_#t~malloc12.base=|v_main_#t~malloc12.base_1|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[main_#t~malloc12.offset, #valid, #length, main_#t~malloc12.base] [2018-04-06 23:13:51,400 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,400 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,400 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,400 DEBUG L281 ransitionTransformer]: Formula: (and (= v_main_~D~0.base_1 |v_main_#t~malloc12.base_2|) (= v_main_~D~0.offset_1 |v_main_#t~malloc12.offset_2|)) InVars {main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_~D~0.base=v_main_~D~0.base_1, main_~D~0.offset=v_main_~D~0.offset_1, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} AuxVars[] AssignedVars[main_~D~0.base, main_~D~0.offset] [2018-04-06 23:13:51,400 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,401 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,401 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,401 DEBUG L281 ransitionTransformer]: Formula: (and (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1| v_main_~A~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1| v_main_~B~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1| v_main_~A~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1| v_main_~B~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1| v_main_~Blen~0_7) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1| v_main_~D~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1| v_main_~Alen~0_8) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1| v_main_~D~0.base_3)) InVars {main_~B~0.offset=v_main_~B~0.offset_3, main_~A~0.offset=v_main_~A~0.offset_3, main_~Blen~0=v_main_~Blen~0_7, main_~Alen~0=v_main_~Alen~0_8, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~B~0.base=v_main_~B~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen] [2018-04-06 23:13:51,401 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,402 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,402 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,402 DEBUG L281 ransitionTransformer]: Formula: (= |v_main_#res_1| 0) InVars {} OutVars{main_#res=|v_main_#res_1|} AuxVars[] AssignedVars[main_#res] [2018-04-06 23:13:51,402 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,402 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,402 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,403 DEBUG L281 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base] [2018-04-06 23:13:51,403 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,403 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,403 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,403 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_17| (store |v_#valid_18| |v_main_#t~malloc10.base_3| 0)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_18|} OutVars{main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_17|} AuxVars[] AssignedVars[#valid] [2018-04-06 23:13:51,403 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,404 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,404 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,404 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen] [2018-04-06 23:13:51,404 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,404 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,404 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,405 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~malloc10.base=|v_main_#t~malloc10.base_4|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_4|} AuxVars[] AssignedVars[main_#t~malloc10.offset, main_#t~malloc10.base] [2018-04-06 23:13:51,405 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,405 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,405 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,405 DEBUG L281 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset] [2018-04-06 23:13:51,405 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,406 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,406 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,406 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_19| (store |v_#valid_20| |v_main_#t~malloc11.base_3| 0)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_20|} OutVars{main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_19|} AuxVars[] AssignedVars[#valid] [2018-04-06 23:13:51,406 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,406 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,406 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,407 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen] [2018-04-06 23:13:51,407 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,407 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,407 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,407 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~malloc11.base=|v_main_#t~malloc11.base_4|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_4|} AuxVars[] AssignedVars[main_#t~malloc11.offset, main_#t~malloc11.base] [2018-04-06 23:13:51,407 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,407 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,408 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,408 DEBUG L281 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset] [2018-04-06 23:13:51,408 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,408 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,408 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,409 DEBUG L281 ransitionTransformer]: Formula: (= (store |v_#valid_22| |v_main_#t~malloc12.base_3| 0) |v_#valid_21|) InVars {main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_22|} OutVars{main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_21|} AuxVars[] AssignedVars[#valid] [2018-04-06 23:13:51,409 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,409 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,409 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,409 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-06 23:13:51,409 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,409 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,410 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,410 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_4|, main_#t~malloc12.base=|v_main_#t~malloc12.base_4|} AuxVars[] AssignedVars[main_#t~malloc12.offset, main_#t~malloc12.base] [2018-04-06 23:13:51,410 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,410 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,410 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,411 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-06 23:13:51,411 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,411 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,411 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,411 DEBUG L281 ransitionTransformer]: Formula: (= |v_#valid_23| |old(#valid)|) InVars {#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,411 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,411 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,411 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,411 DEBUG L281 ransitionTransformer]: Formula: (not (= |v_#valid_24| |old(#valid)|)) InVars {#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,411 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,411 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,412 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,412 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0] [2018-04-06 23:13:51,412 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,412 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,412 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,412 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0] [2018-04-06 23:13:51,412 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,412 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,412 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,413 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-06 23:13:51,413 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,413 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,413 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,413 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,413 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,413 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,413 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,413 DEBUG L281 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,413 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,413 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,414 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,414 DEBUG L281 ransitionTransformer]: Formula: (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,414 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,414 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,414 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,414 DEBUG L281 ransitionTransformer]: Formula: (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,414 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,415 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,415 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,415 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,415 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,415 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,415 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,416 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-06 23:13:51,416 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,416 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,416 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,416 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-06 23:13:51,416 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,416 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,417 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,417 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,417 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,417 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,417 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,417 DEBUG L281 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,418 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,418 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,418 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,418 DEBUG L281 ransitionTransformer]: Formula: (or (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3)) (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,418 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,418 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,419 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,419 DEBUG L281 ransitionTransformer]: Formula: (and (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3) (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,419 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,419 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,419 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,419 DEBUG L281 ransitionTransformer]: Formula: (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,419 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,420 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,420 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,420 DEBUG L281 ransitionTransformer]: Formula: (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,420 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,420 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,423 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,423 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-06 23:13:51,423 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-06 23:13:51,423 DEBUG L289 ransitionTransformer]: old formula: [2018-04-06 23:13:51,424 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-06 23:13:51,424 DEBUG L291 ransitionTransformer]: new formula: [2018-04-06 23:13:51,424 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-06 23:13:51,424 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-06 23:13:51,424 DEBUG L297 ransitionTransformer]: old invars: [2018-04-06 23:13:51,425 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|} [2018-04-06 23:13:51,425 DEBUG L299 ransitionTransformer]: new invars: [2018-04-06 23:13:51,425 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} [2018-04-06 23:13:51,425 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-06 23:13:51,425 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-06 23:13:51,425 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-06 23:13:51,425 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-06 23:13:51,426 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-06 23:13:51,426 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,426 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,426 DEBUG L281 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3))) InVars {#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} OutVars{#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,426 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,427 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,427 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,427 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0 4) (select |v_#length_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4))))) InVars {#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} OutVars{#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,427 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,427 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,429 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,429 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5] [2018-04-06 23:13:51,429 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-06 23:13:51,429 DEBUG L289 ransitionTransformer]: old formula: [2018-04-06 23:13:51,429 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-06 23:13:51,430 DEBUG L291 ransitionTransformer]: new formula: [2018-04-06 23:13:51,430 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-06 23:13:51,430 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-06 23:13:51,430 DEBUG L297 ransitionTransformer]: old invars: [2018-04-06 23:13:51,430 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|} [2018-04-06 23:13:51,431 DEBUG L299 ransitionTransformer]: new invars: [2018-04-06 23:13:51,431 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} [2018-04-06 23:13:51,431 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-06 23:13:51,431 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-06 23:13:51,431 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-06 23:13:51,431 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-06 23:13:51,431 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-06 23:13:51,432 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,432 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,432 DEBUG L281 ransitionTransformer]: Formula: (not (= (select |v_#valid_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6) 1)) InVars {#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} OutVars{#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,432 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,432 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,432 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,433 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0 4) (select |v_#length_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7))))) InVars {#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} OutVars{#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,433 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,433 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,433 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,433 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7] [2018-04-06 23:13:51,433 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,434 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,434 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,434 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-06 23:13:51,434 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-06 23:13:51,434 DEBUG L289 ransitionTransformer]: old formula: [2018-04-06 23:13:51,434 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-06 23:13:51,435 DEBUG L291 ransitionTransformer]: new formula: [2018-04-06 23:13:51,435 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-06 23:13:51,435 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-06 23:13:51,435 DEBUG L297 ransitionTransformer]: old invars: [2018-04-06 23:13:51,435 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-06 23:13:51,435 DEBUG L299 ransitionTransformer]: new invars: [2018-04-06 23:13:51,436 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-06 23:13:51,436 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-06 23:13:51,436 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-06 23:13:51,436 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-06 23:13:51,436 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-06 23:13:51,436 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-06 23:13:51,436 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,436 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,437 DEBUG L281 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,437 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,437 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,437 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,437 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5))) (or (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0 4) (select |v_#length_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4))) (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,437 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,437 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,439 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,439 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} AuxVars[] AssignedVars[#memory_int_part_locs_32_locs_31] [2018-04-06 23:13:51,439 DEBUG L288 ransitionTransformer]: formula has changed [2018-04-06 23:13:51,439 DEBUG L289 ransitionTransformer]: old formula: [2018-04-06 23:13:51,439 DEBUG L290 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_4|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-06 23:13:51,439 DEBUG L291 ransitionTransformer]: new formula: [2018-04-06 23:13:51,439 DEBUG L292 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-06 23:13:51,440 DEBUG L296 ransitionTransformer]: invars have changed [2018-04-06 23:13:51,440 DEBUG L297 ransitionTransformer]: old invars: [2018-04-06 23:13:51,440 DEBUG L298 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-06 23:13:51,440 DEBUG L299 ransitionTransformer]: new invars: [2018-04-06 23:13:51,440 DEBUG L300 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-06 23:13:51,440 DEBUG L304 ransitionTransformer]: outvars have changed [2018-04-06 23:13:51,440 DEBUG L305 ransitionTransformer]: old outvars: [2018-04-06 23:13:51,440 DEBUG L306 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-06 23:13:51,440 DEBUG L307 ransitionTransformer]: new outvars: [2018-04-06 23:13:51,440 DEBUG L308 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-06 23:13:51,440 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,441 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,441 DEBUG L281 ransitionTransformer]: Formula: (not (= (select |v_#valid_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3) 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,441 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,441 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,441 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,441 DEBUG L281 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0 4) (select |v_#length_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,441 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,441 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,442 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,442 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-06 23:13:51,442 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,442 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,442 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,442 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,442 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,442 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,443 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,443 DEBUG L281 ransitionTransformer]: Formula: (not (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,443 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,443 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,443 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,443 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5] [2018-04-06 23:13:51,443 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,444 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,444 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,444 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7] [2018-04-06 23:13:51,444 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,444 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,444 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,444 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-06 23:13:51,445 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,445 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,445 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,445 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_5|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-06 23:13:51,445 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,445 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,445 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,445 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6] [2018-04-06 23:13:51,445 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,446 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,446 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,446 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-06 23:13:51,446 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,446 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,446 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,446 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_5|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-06 23:13:51,446 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,446 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,447 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,447 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-06 23:13:51,447 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,447 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,447 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,447 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5 1) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-06 23:13:51,447 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,447 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,447 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,447 DEBUG L281 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4] [2018-04-06 23:13:51,447 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,448 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,448 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,448 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6] [2018-04-06 23:13:51,448 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,448 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,448 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,448 DEBUG L281 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-06 23:13:51,448 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,448 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,449 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,449 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_3|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4] [2018-04-06 23:13:51,449 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,449 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,449 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,449 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,449 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,449 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,449 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,449 DEBUG L281 ransitionTransformer]: Formula: (= |v_ULTIMATE.start_#t~ret13_2| |v_main_#resOutParam_1|) InVars {main_#res=|v_main_#resOutParam_1|} OutVars{ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|} AuxVars[] AssignedVars[ULTIMATE.start_#t~ret13] [2018-04-06 23:13:51,449 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,450 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,450 DEBUG L280 ransitionTransformer]: transformed transition [2018-04-06 23:13:51,450 DEBUG L281 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-06 23:13:51,450 DEBUG L284 ransitionTransformer]: transformula unchanged [2018-04-06 23:13:51,450 DEBUG L310 ransitionTransformer]: [2018-04-06 23:13:51,451 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-06 23:13:51,464 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 06.04 11:13:51 BasicIcfg [2018-04-06 23:13:51,464 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-04-06 23:13:51,465 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-06 23:13:51,465 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-06 23:13:51,467 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-06 23:13:51,467 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 06.04 11:13:10" (1/4) ... [2018-04-06 23:13:51,468 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d0eb189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.04 11:13:51, skipping insertion in model container [2018-04-06 23:13:51,468 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.04 11:13:11" (2/4) ... [2018-04-06 23:13:51,468 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d0eb189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 06.04 11:13:51, skipping insertion in model container [2018-04-06 23:13:51,468 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.04 11:13:11" (3/4) ... [2018-04-06 23:13:51,469 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d0eb189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.04 11:13:51, skipping insertion in model container [2018-04-06 23:13:51,469 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 06.04 11:13:51" (4/4) ... [2018-04-06 23:13:51,470 INFO L107 eAbstractionObserver]: Analyzing ICFG memPartitionedIcfg [2018-04-06 23:13:51,476 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-06 23:13:51,483 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 9 error locations. [2018-04-06 23:13:51,514 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-06 23:13:51,515 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-06 23:13:51,515 INFO L370 AbstractCegarLoop]: Hoare is true [2018-04-06 23:13:51,515 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-06 23:13:51,515 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-06 23:13:51,515 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-06 23:13:51,515 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-06 23:13:51,515 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-06 23:13:51,515 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-06 23:13:51,516 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-06 23:13:51,525 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states. [2018-04-06 23:13:51,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-06 23:13:51,531 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:13:51,531 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:13:51,532 INFO L408 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:13:51,535 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476875, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:13:51,549 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:13:51,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:13:51,610 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:13:51,639 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:13:51,640 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:51,648 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:51,648 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-06 23:13:51,694 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:51,695 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:51,696 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-06 23:13:51,696 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:51,711 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:51,711 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-06 23:13:51,745 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2018-04-06 23:13:51,746 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:51,752 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:51,752 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:21, output treesize:20 [2018-04-06 23:13:51,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:51,832 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:13:51,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:51,968 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:13:51,968 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-06 23:13:51,970 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-06 23:13:51,977 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-06 23:13:51,978 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-06 23:13:51,979 INFO L87 Difference]: Start difference. First operand 82 states. Second operand 11 states. [2018-04-06 23:13:52,290 WARN L151 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 20 DAG size of output 16 [2018-04-06 23:13:52,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:13:52,394 INFO L93 Difference]: Finished difference Result 129 states and 143 transitions. [2018-04-06 23:13:52,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-06 23:13:52,396 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-06 23:13:52,397 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:13:52,407 INFO L225 Difference]: With dead ends: 129 [2018-04-06 23:13:52,407 INFO L226 Difference]: Without dead ends: 77 [2018-04-06 23:13:52,411 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 64 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-06 23:13:52,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-04-06 23:13:52,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-04-06 23:13:52,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-04-06 23:13:52,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-04-06 23:13:52,451 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 38 [2018-04-06 23:13:52,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:13:52,452 INFO L459 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-04-06 23:13:52,452 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-06 23:13:52,452 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-04-06 23:13:52,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-06 23:13:52,453 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:13:52,453 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:13:52,453 INFO L408 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:13:52,454 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476876, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:13:52,463 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:13:52,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:13:52,499 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:13:52,513 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:13:52,513 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,523 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:13:52,523 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,531 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,532 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-06 23:13:52,565 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,567 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-06 23:13:52,567 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,603 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,604 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,605 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-06 23:13:52,605 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,623 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:52,624 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:35 [2018-04-06 23:13:52,645 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,646 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,648 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 34 [2018-04-06 23:13:52,648 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,666 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,667 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,668 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:52,668 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-04-06 23:13:52,668 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:52,684 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:52,684 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:48, output treesize:40 [2018-04-06 23:13:52,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:52,838 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:13:55,049 WARN L148 SmtUtils]: Spent 2028ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-06 23:13:57,121 WARN L148 SmtUtils]: Spent 2032ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-06 23:13:57,136 INFO L682 Elim1Store]: detected equality via solver [2018-04-06 23:13:57,157 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 30 [2018-04-06 23:13:57,181 INFO L682 Elim1Store]: detected equality via solver [2018-04-06 23:13:57,181 INFO L682 Elim1Store]: detected equality via solver [2018-04-06 23:13:57,182 INFO L682 Elim1Store]: detected equality via solver [2018-04-06 23:13:57,183 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 10 [2018-04-06 23:13:57,183 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,190 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 24 [2018-04-06 23:13:57,205 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 30 [2018-04-06 23:13:57,235 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 9 [2018-04-06 23:13:57,235 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,238 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,240 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,245 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,245 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:42, output treesize:5 [2018-04-06 23:13:57,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:57,281 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:13:57,281 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 9] imperfect sequences [] total 16 [2018-04-06 23:13:57,282 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-06 23:13:57,283 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-06 23:13:57,283 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-04-06 23:13:57,283 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 17 states. [2018-04-06 23:13:57,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:13:57,769 INFO L93 Difference]: Finished difference Result 118 states and 131 transitions. [2018-04-06 23:13:57,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-06 23:13:57,770 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 38 [2018-04-06 23:13:57,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:13:57,774 INFO L225 Difference]: With dead ends: 118 [2018-04-06 23:13:57,774 INFO L226 Difference]: Without dead ends: 116 [2018-04-06 23:13:57,775 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 59 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2018-04-06 23:13:57,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-04-06 23:13:57,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 86. [2018-04-06 23:13:57,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-06 23:13:57,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 94 transitions. [2018-04-06 23:13:57,788 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 94 transitions. Word has length 38 [2018-04-06 23:13:57,788 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:13:57,788 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 94 transitions. [2018-04-06 23:13:57,789 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-06 23:13:57,789 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 94 transitions. [2018-04-06 23:13:57,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-06 23:13:57,790 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:13:57,790 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:13:57,790 INFO L408 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:13:57,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273898, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:13:57,810 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:13:57,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:13:57,835 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:13:57,847 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:13:57,847 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,848 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,849 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-06 23:13:57,857 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:57,858 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:57,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-06 23:13:57,858 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:57,869 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:57,869 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-06 23:13:57,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:57,924 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:13:57,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:57,989 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:13:57,989 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-06 23:13:57,989 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-06 23:13:57,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-06 23:13:57,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-06 23:13:57,990 INFO L87 Difference]: Start difference. First operand 86 states and 94 transitions. Second operand 11 states. [2018-04-06 23:13:58,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:13:58,129 INFO L93 Difference]: Finished difference Result 86 states and 94 transitions. [2018-04-06 23:13:58,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-06 23:13:58,129 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 39 [2018-04-06 23:13:58,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:13:58,130 INFO L225 Difference]: With dead ends: 86 [2018-04-06 23:13:58,130 INFO L226 Difference]: Without dead ends: 85 [2018-04-06 23:13:58,130 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-06 23:13:58,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-06 23:13:58,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-06 23:13:58,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-06 23:13:58,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 93 transitions. [2018-04-06 23:13:58,138 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 93 transitions. Word has length 39 [2018-04-06 23:13:58,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:13:58,139 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 93 transitions. [2018-04-06 23:13:58,139 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-06 23:13:58,139 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 93 transitions. [2018-04-06 23:13:58,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-06 23:13:58,139 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:13:58,140 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:13:58,140 INFO L408 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:13:58,140 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273899, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:13:58,145 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:13:58,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:13:58,165 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:13:58,171 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:13:58,171 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:58,177 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:13:58,177 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:58,183 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:58,183 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:19 [2018-04-06 23:13:58,201 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:58,201 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:13:58,202 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-06 23:13:58,202 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:58,210 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-06 23:13:58,210 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:13:58,217 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-06 23:13:58,217 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:32, output treesize:25 [2018-04-06 23:13:58,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:13:58,312 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:00,419 WARN L148 SmtUtils]: Spent 2036ms on a formula simplification that was a NOOP. DAG size: 26 [2018-04-06 23:14:02,481 WARN L148 SmtUtils]: Spent 2037ms on a formula simplification that was a NOOP. DAG size: 26 [2018-04-06 23:14:02,489 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-04-06 23:14:02,512 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:02,517 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-04-06 23:14:02,532 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-04-06 23:14:02,532 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:02,533 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-04-06 23:14:02,533 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:02,535 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:02,538 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:02,538 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:25, output treesize:5 [2018-04-06 23:14:02,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:02,568 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:02,568 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 14 [2018-04-06 23:14:02,568 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-06 23:14:02,568 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-06 23:14:02,568 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2018-04-06 23:14:02,568 INFO L87 Difference]: Start difference. First operand 85 states and 93 transitions. Second operand 15 states. [2018-04-06 23:14:02,952 WARN L151 SmtUtils]: Spent 253ms on a formula simplification. DAG size of input: 37 DAG size of output 33 [2018-04-06 23:14:03,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:03,140 INFO L93 Difference]: Finished difference Result 136 states and 152 transitions. [2018-04-06 23:14:03,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-06 23:14:03,141 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 39 [2018-04-06 23:14:03,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:03,142 INFO L225 Difference]: With dead ends: 136 [2018-04-06 23:14:03,143 INFO L226 Difference]: Without dead ends: 135 [2018-04-06 23:14:03,143 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=91, Invalid=371, Unknown=0, NotChecked=0, Total=462 [2018-04-06 23:14:03,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-04-06 23:14:03,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 89. [2018-04-06 23:14:03,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-06 23:14:03,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 98 transitions. [2018-04-06 23:14:03,156 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 98 transitions. Word has length 39 [2018-04-06 23:14:03,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:03,156 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 98 transitions. [2018-04-06 23:14:03,156 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-06 23:14:03,157 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 98 transitions. [2018-04-06 23:14:03,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-06 23:14:03,158 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:03,158 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:03,158 INFO L408 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:03,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1252082927, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:03,173 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:03,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:03,193 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:03,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:03,271 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:03,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:03,319 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:03,319 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 10 [2018-04-06 23:14:03,320 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-06 23:14:03,320 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-06 23:14:03,320 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-04-06 23:14:03,320 INFO L87 Difference]: Start difference. First operand 89 states and 98 transitions. Second operand 10 states. [2018-04-06 23:14:03,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:03,470 INFO L93 Difference]: Finished difference Result 203 states and 226 transitions. [2018-04-06 23:14:03,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-06 23:14:03,471 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 40 [2018-04-06 23:14:03,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:03,472 INFO L225 Difference]: With dead ends: 203 [2018-04-06 23:14:03,472 INFO L226 Difference]: Without dead ends: 151 [2018-04-06 23:14:03,473 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 67 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=76, Invalid=164, Unknown=0, NotChecked=0, Total=240 [2018-04-06 23:14:03,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-04-06 23:14:03,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 88. [2018-04-06 23:14:03,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-06 23:14:03,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 95 transitions. [2018-04-06 23:14:03,486 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 95 transitions. Word has length 40 [2018-04-06 23:14:03,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:03,486 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 95 transitions. [2018-04-06 23:14:03,486 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-06 23:14:03,486 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 95 transitions. [2018-04-06 23:14:03,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-04-06 23:14:03,487 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:03,487 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:03,487 INFO L408 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:03,487 INFO L82 PathProgramCache]: Analyzing trace with hash -1717465618, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:03,494 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:03,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:03,512 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:03,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:03,549 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:03,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:03,623 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:03,623 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 10 [2018-04-06 23:14:03,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-06 23:14:03,623 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-06 23:14:03,623 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-04-06 23:14:03,623 INFO L87 Difference]: Start difference. First operand 88 states and 95 transitions. Second operand 10 states. [2018-04-06 23:14:03,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:03,712 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-04-06 23:14:03,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-06 23:14:03,712 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-04-06 23:14:03,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:03,714 INFO L225 Difference]: With dead ends: 128 [2018-04-06 23:14:03,714 INFO L226 Difference]: Without dead ends: 117 [2018-04-06 23:14:03,714 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 74 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-04-06 23:14:03,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-06 23:14:03,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 88. [2018-04-06 23:14:03,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-06 23:14:03,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 94 transitions. [2018-04-06 23:14:03,728 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 94 transitions. Word has length 43 [2018-04-06 23:14:03,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:03,729 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 94 transitions. [2018-04-06 23:14:03,729 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-06 23:14:03,729 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 94 transitions. [2018-04-06 23:14:03,730 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-04-06 23:14:03,730 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:03,730 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:03,730 INFO L408 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:03,731 INFO L82 PathProgramCache]: Analyzing trace with hash 29055424, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:03,744 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:03,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:03,777 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:03,787 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:03,787 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:03,802 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:03,836 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:03,836 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [] total 3 [2018-04-06 23:14:03,836 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-06 23:14:03,836 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-06 23:14:03,837 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-06 23:14:03,837 INFO L87 Difference]: Start difference. First operand 88 states and 94 transitions. Second operand 3 states. [2018-04-06 23:14:03,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:03,857 INFO L93 Difference]: Finished difference Result 147 states and 159 transitions. [2018-04-06 23:14:03,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-06 23:14:03,858 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-04-06 23:14:03,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:03,859 INFO L225 Difference]: With dead ends: 147 [2018-04-06 23:14:03,859 INFO L226 Difference]: Without dead ends: 98 [2018-04-06 23:14:03,859 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-06 23:14:03,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-06 23:14:03,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 89. [2018-04-06 23:14:03,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-06 23:14:03,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 94 transitions. [2018-04-06 23:14:03,870 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 94 transitions. Word has length 48 [2018-04-06 23:14:03,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:03,871 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 94 transitions. [2018-04-06 23:14:03,871 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-06 23:14:03,871 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 94 transitions. [2018-04-06 23:14:03,872 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-06 23:14:03,872 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:03,872 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:03,872 INFO L408 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:03,872 INFO L82 PathProgramCache]: Analyzing trace with hash -1793713475, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:03,879 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:03,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:03,899 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:03,903 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:14:03,903 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:03,908 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:03,908 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:03,912 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:03,912 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-06 23:14:03,925 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:03,926 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:03,926 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-06 23:14:03,926 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:03,934 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-06 23:14:03,934 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:03,940 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:03,940 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-06 23:14:04,201 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:04,202 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:06,817 WARN L148 SmtUtils]: Spent 2023ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-06 23:14:06,832 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-06 23:14:06,852 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:06,852 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 23 [2018-04-06 23:14:06,853 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-06 23:14:06,853 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-06 23:14:06,853 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=484, Unknown=0, NotChecked=0, Total=552 [2018-04-06 23:14:06,853 INFO L87 Difference]: Start difference. First operand 89 states and 94 transitions. Second operand 24 states. [2018-04-06 23:14:07,043 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 57 DAG size of output 56 [2018-04-06 23:14:08,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:08,334 INFO L93 Difference]: Finished difference Result 123 states and 131 transitions. [2018-04-06 23:14:08,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-06 23:14:08,368 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 49 [2018-04-06 23:14:08,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:08,369 INFO L225 Difference]: With dead ends: 123 [2018-04-06 23:14:08,370 INFO L226 Difference]: Without dead ends: 122 [2018-04-06 23:14:08,370 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 160 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=270, Invalid=1136, Unknown=0, NotChecked=0, Total=1406 [2018-04-06 23:14:08,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-04-06 23:14:08,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 86. [2018-04-06 23:14:08,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-06 23:14:08,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 91 transitions. [2018-04-06 23:14:08,381 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 91 transitions. Word has length 49 [2018-04-06 23:14:08,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:08,382 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 91 transitions. [2018-04-06 23:14:08,382 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-06 23:14:08,382 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 91 transitions. [2018-04-06 23:14:08,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-06 23:14:08,383 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:08,383 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:08,383 INFO L408 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:08,383 INFO L82 PathProgramCache]: Analyzing trace with hash 229425471, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:08,392 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:08,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:08,414 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:08,437 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:14:08,437 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:08,453 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:08,454 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-06 23:14:08,472 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-06 23:14:08,473 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:08,479 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-06 23:14:08,500 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:08,500 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5, 5] imperfect sequences [] total 5 [2018-04-06 23:14:08,500 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-06 23:14:08,501 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-06 23:14:08,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-06 23:14:08,501 INFO L87 Difference]: Start difference. First operand 86 states and 91 transitions. Second operand 6 states. [2018-04-06 23:14:08,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:08,559 INFO L93 Difference]: Finished difference Result 86 states and 91 transitions. [2018-04-06 23:14:08,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-06 23:14:08,559 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 50 [2018-04-06 23:14:08,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:08,560 INFO L225 Difference]: With dead ends: 86 [2018-04-06 23:14:08,560 INFO L226 Difference]: Without dead ends: 85 [2018-04-06 23:14:08,561 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-04-06 23:14:08,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-06 23:14:08,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-06 23:14:08,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-06 23:14:08,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-04-06 23:14:08,574 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 50 [2018-04-06 23:14:08,574 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:08,574 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-04-06 23:14:08,574 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-06 23:14:08,575 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-04-06 23:14:08,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-06 23:14:08,575 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:08,576 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:08,576 INFO L408 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:08,576 INFO L82 PathProgramCache]: Analyzing trace with hash 229425472, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:08,582 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:08,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:08,609 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:08,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:08,616 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:08,622 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:08,623 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-04-06 23:14:08,693 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-06 23:14:08,694 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:08,790 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-06 23:14:08,811 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:08,811 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 12 [2018-04-06 23:14:08,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-06 23:14:08,812 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-06 23:14:08,812 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-04-06 23:14:08,812 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 13 states. [2018-04-06 23:14:08,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:08,976 INFO L93 Difference]: Finished difference Result 121 states and 130 transitions. [2018-04-06 23:14:08,976 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-06 23:14:08,976 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 50 [2018-04-06 23:14:08,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:08,977 INFO L225 Difference]: With dead ends: 121 [2018-04-06 23:14:08,977 INFO L226 Difference]: Without dead ends: 120 [2018-04-06 23:14:08,977 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 87 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=73, Invalid=269, Unknown=0, NotChecked=0, Total=342 [2018-04-06 23:14:08,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-04-06 23:14:08,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 114. [2018-04-06 23:14:08,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-06 23:14:08,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-04-06 23:14:08,991 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 50 [2018-04-06 23:14:08,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:08,991 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-04-06 23:14:08,992 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-06 23:14:08,992 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-04-06 23:14:08,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-06 23:14:08,992 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:08,992 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:08,992 INFO L408 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:08,992 INFO L82 PathProgramCache]: Analyzing trace with hash -72993622, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:08,998 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:09,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:09,018 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:09,021 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:09,021 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:09,026 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-06 23:14:09,026 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:09,031 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:09,031 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-06 23:14:09,044 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:09,045 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:09,046 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-06 23:14:09,046 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:09,053 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-06 23:14:09,053 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:09,058 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:09,059 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-06 23:14:09,080 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 23 treesize of output 30 [2018-04-06 23:14:09,081 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-04-06 23:14:09,098 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-04-06 23:14:09,098 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:30, output treesize:52 [2018-04-06 23:14:09,313 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-06 23:14:09,313 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:09,918 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-06 23:14:09,939 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:09,939 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 24 [2018-04-06 23:14:09,939 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-06 23:14:09,939 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-06 23:14:09,940 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=531, Unknown=0, NotChecked=0, Total=600 [2018-04-06 23:14:09,940 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 25 states. [2018-04-06 23:14:12,116 WARN L151 SmtUtils]: Spent 2110ms on a formula simplification. DAG size of input: 61 DAG size of output 60 [2018-04-06 23:14:13,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:13,252 INFO L93 Difference]: Finished difference Result 145 states and 159 transitions. [2018-04-06 23:14:13,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-06 23:14:13,252 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 56 [2018-04-06 23:14:13,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:13,253 INFO L225 Difference]: With dead ends: 145 [2018-04-06 23:14:13,253 INFO L226 Difference]: Without dead ends: 144 [2018-04-06 23:14:13,254 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 88 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 169 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=275, Invalid=1207, Unknown=0, NotChecked=0, Total=1482 [2018-04-06 23:14:13,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-04-06 23:14:13,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 107. [2018-04-06 23:14:13,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-04-06 23:14:13,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 116 transitions. [2018-04-06 23:14:13,272 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 116 transitions. Word has length 56 [2018-04-06 23:14:13,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:13,273 INFO L459 AbstractCegarLoop]: Abstraction has 107 states and 116 transitions. [2018-04-06 23:14:13,273 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-06 23:14:13,273 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 116 transitions. [2018-04-06 23:14:13,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-06 23:14:13,274 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:13,274 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:13,274 INFO L408 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:13,274 INFO L82 PathProgramCache]: Analyzing trace with hash 1791438736, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:13,283 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:13,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:13,304 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:13,338 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:13,338 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-06 23:14:13,356 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:13,357 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:13,358 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 42 [2018-04-06 23:14:13,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 34 [2018-04-06 23:14:13,360 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:13,368 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:13,374 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:13,382 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:13,382 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-06 23:14:13,441 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:13,447 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:13,459 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:13,459 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:13,509 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_22| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_22| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_22|))))) is different from false [2018-04-06 23:14:13,512 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_21|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_22| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0)) (not (= (select .cse0 |v_main_#t~malloc12.base_22|) 0))))) is different from false [2018-04-06 23:14:13,517 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc10.base_19| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_19| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_21|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_22| 1) |v_main_#t~malloc10.base_19| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_19|))) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_22|))))))) is different from false [2018-04-06 23:14:13,533 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:13,554 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:13,554 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-06 23:14:13,555 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-06 23:14:13,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-06 23:14:13,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-06 23:14:13,555 INFO L87 Difference]: Start difference. First operand 107 states and 116 transitions. Second operand 16 states. [2018-04-06 23:14:13,575 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc10.base_19| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_19| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_21|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_22| 1) |v_main_#t~malloc10.base_19| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_19|))) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_22|)))))))) is different from false [2018-04-06 23:14:14,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:14,152 INFO L93 Difference]: Finished difference Result 199 states and 216 transitions. [2018-04-06 23:14:14,152 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-06 23:14:14,153 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-04-06 23:14:14,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:14,154 INFO L225 Difference]: With dead ends: 199 [2018-04-06 23:14:14,154 INFO L226 Difference]: Without dead ends: 188 [2018-04-06 23:14:14,154 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 107 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=229, Unknown=8, NotChecked=210, Total=506 [2018-04-06 23:14:14,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-04-06 23:14:14,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 185. [2018-04-06 23:14:14,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-04-06 23:14:14,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 202 transitions. [2018-04-06 23:14:14,182 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 202 transitions. Word has length 61 [2018-04-06 23:14:14,182 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:14,182 INFO L459 AbstractCegarLoop]: Abstraction has 185 states and 202 transitions. [2018-04-06 23:14:14,182 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-06 23:14:14,182 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 202 transitions. [2018-04-06 23:14:14,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-06 23:14:14,183 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:14,183 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:14,183 INFO L408 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:14,183 INFO L82 PathProgramCache]: Analyzing trace with hash -1032331687, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:14,189 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:14,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:14,212 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:14,248 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:14,248 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-06 23:14:14,264 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:14,265 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:14,265 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-06 23:14:14,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-06 23:14:14,267 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:14,274 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:14,279 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:14,285 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:14,285 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-06 23:14:14,359 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:14,365 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:14,385 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:14,385 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:14,440 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_24| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_24| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_24| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_24|))))) is different from false [2018-04-06 23:14:14,449 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_24| Int) (|v_main_#t~malloc11.base_23| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_23| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_24| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_23| 0) |v_main_#t~malloc12.base_24| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_23|))) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_24|)))))) is different from false [2018-04-06 23:14:14,455 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_24| Int) (|v_main_#t~malloc10.base_21| Int) (|v_main_#t~malloc11.base_23| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_21| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_23| 1))) (or (not (= (select .cse0 |v_main_#t~malloc12.base_24|) 0)) (not (= (select .cse1 |v_main_#t~malloc11.base_23|) 0)) (not (= (select |c_#valid| |v_main_#t~malloc10.base_21|) 0)) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_24| 1) |v_main_#t~malloc10.base_21| 0) |v_main_#t~malloc11.base_23| 0) |v_main_#t~malloc12.base_24| 0)))))) is different from false [2018-04-06 23:14:14,485 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:14,517 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:14,517 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-06 23:14:14,518 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-06 23:14:14,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-06 23:14:14,518 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-06 23:14:14,518 INFO L87 Difference]: Start difference. First operand 185 states and 202 transitions. Second operand 16 states. [2018-04-06 23:14:14,551 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc12.base_24| Int) (|v_main_#t~malloc10.base_21| Int) (|v_main_#t~malloc11.base_23| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_21| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_23| 1))) (or (not (= (select .cse0 |v_main_#t~malloc12.base_24|) 0)) (not (= (select .cse1 |v_main_#t~malloc11.base_23|) 0)) (not (= (select |c_#valid| |v_main_#t~malloc10.base_21|) 0)) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_24| 1) |v_main_#t~malloc10.base_21| 0) |v_main_#t~malloc11.base_23| 0) |v_main_#t~malloc12.base_24| 0))))))) is different from false [2018-04-06 23:14:15,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:15,283 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-06 23:14:15,283 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-06 23:14:15,283 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-06 23:14:15,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:15,284 INFO L225 Difference]: With dead ends: 277 [2018-04-06 23:14:15,284 INFO L226 Difference]: Without dead ends: 266 [2018-04-06 23:14:15,285 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=59, Invalid=228, Unknown=9, NotChecked=210, Total=506 [2018-04-06 23:14:15,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-06 23:14:15,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-06 23:14:15,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-06 23:14:15,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-06 23:14:15,316 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-06 23:14:15,316 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:15,316 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-06 23:14:15,316 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-06 23:14:15,316 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-06 23:14:15,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-06 23:14:15,317 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:15,317 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:15,317 INFO L408 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:15,317 INFO L82 PathProgramCache]: Analyzing trace with hash -1753613222, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:15,323 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:15,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:15,343 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:15,378 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:15,379 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-06 23:14:15,393 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:15,394 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:15,395 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-06 23:14:15,397 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-06 23:14:15,397 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:15,405 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:15,410 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:15,417 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:15,417 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-06 23:14:15,463 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:15,467 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:15,479 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:15,480 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:15,517 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_26| Int)) (or (= |c_old(#valid)| (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_26| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_26| 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_26|))))) is different from false [2018-04-06 23:14:15,521 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_25| Int) (|v_main_#t~malloc12.base_26| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_25| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_25|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_26| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_25| 0) |v_main_#t~malloc12.base_26| 0)) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_26|)))))) is different from false [2018-04-06 23:14:15,525 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc10.base_23| Int) (|v_main_#t~malloc11.base_25| Int) (|v_main_#t~malloc12.base_26| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_23| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_25| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_26| 1) |v_main_#t~malloc10.base_23| 0) |v_main_#t~malloc11.base_25| 0) |v_main_#t~malloc12.base_26| 0) |c_old(#valid)|) (not (= (select .cse0 |v_main_#t~malloc12.base_26|) 0)) (not (= (select |c_#valid| |v_main_#t~malloc10.base_23|) 0)) (not (= (select .cse1 |v_main_#t~malloc11.base_25|) 0)))))) is different from false [2018-04-06 23:14:15,538 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:15,559 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:15,560 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-06 23:14:15,560 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-06 23:14:15,560 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-06 23:14:15,560 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-06 23:14:15,560 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-06 23:14:15,575 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc10.base_23| Int) (|v_main_#t~malloc11.base_25| Int) (|v_main_#t~malloc12.base_26| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_23| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_25| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_26| 1) |v_main_#t~malloc10.base_23| 0) |v_main_#t~malloc11.base_25| 0) |v_main_#t~malloc12.base_26| 0) |c_old(#valid)|) (not (= (select .cse0 |v_main_#t~malloc12.base_26|) 0)) (not (= (select |c_#valid| |v_main_#t~malloc10.base_23|) 0)) (not (= (select .cse1 |v_main_#t~malloc11.base_25|) 0)))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-06 23:14:16,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:16,176 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-06 23:14:16,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-06 23:14:16,176 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-06 23:14:16,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:16,177 INFO L225 Difference]: With dead ends: 277 [2018-04-06 23:14:16,177 INFO L226 Difference]: Without dead ends: 266 [2018-04-06 23:14:16,178 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=59, Invalid=229, Unknown=8, NotChecked=210, Total=506 [2018-04-06 23:14:16,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-06 23:14:16,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-06 23:14:16,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-06 23:14:16,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-06 23:14:16,221 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-06 23:14:16,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:16,222 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-06 23:14:16,222 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-06 23:14:16,222 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-06 23:14:16,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-04-06 23:14:16,223 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:16,223 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:16,223 INFO L408 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:16,223 INFO L82 PathProgramCache]: Analyzing trace with hash 740207311, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:16,233 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:16,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:16,253 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:16,285 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:16,286 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-06 23:14:16,302 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:16,302 INFO L700 Elim1Store]: detected not equals via solver [2018-04-06 23:14:16,303 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-06 23:14:16,305 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-06 23:14:16,305 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:16,313 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:16,319 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:16,325 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-06 23:14:16,325 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-06 23:14:16,385 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:16,389 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-06 23:14:16,402 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:16,402 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:16,441 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_28| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_28| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_28| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_28|))))) is different from false [2018-04-06 23:14:16,445 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_27| Int) (|v_main_#t~malloc12.base_28| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_27| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_27|))) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_28|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_28| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_27| 0) |v_main_#t~malloc12.base_28| 0))))) is different from false [2018-04-06 23:14:16,449 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc10.base_25| Int) (|v_main_#t~malloc11.base_27| Int) (|v_main_#t~malloc12.base_28| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_25| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_27| 1))) (or (not (= (select |c_#valid| |v_main_#t~malloc10.base_25|) 0)) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_28|))) (not (= (select .cse1 |v_main_#t~malloc11.base_27|) 0)) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_28| 1) |v_main_#t~malloc10.base_25| 0) |v_main_#t~malloc11.base_27| 0) |v_main_#t~malloc12.base_28| 0) |c_old(#valid)|))))) is different from false [2018-04-06 23:14:16,467 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:16,489 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-06 23:14:16,489 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-06 23:14:16,489 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-06 23:14:16,489 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-06 23:14:16,489 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-06 23:14:16,490 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-06 23:14:16,506 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc10.base_25| Int) (|v_main_#t~malloc11.base_27| Int) (|v_main_#t~malloc12.base_28| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_25| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_27| 1))) (or (not (= (select |c_#valid| |v_main_#t~malloc10.base_25|) 0)) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_28|))) (not (= (select .cse1 |v_main_#t~malloc11.base_27|) 0)) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_28| 1) |v_main_#t~malloc10.base_25| 0) |v_main_#t~malloc11.base_27| 0) |v_main_#t~malloc12.base_28| 0) |c_old(#valid)|)))))) is different from false [2018-04-06 23:14:17,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:17,120 INFO L93 Difference]: Finished difference Result 187 states and 203 transitions. [2018-04-06 23:14:17,120 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-06 23:14:17,121 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 63 [2018-04-06 23:14:17,121 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:17,121 INFO L225 Difference]: With dead ends: 187 [2018-04-06 23:14:17,122 INFO L226 Difference]: Without dead ends: 176 [2018-04-06 23:14:17,122 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 111 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=202, Unknown=8, NotChecked=198, Total=462 [2018-04-06 23:14:17,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-04-06 23:14:17,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 94. [2018-04-06 23:14:17,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-04-06 23:14:17,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 102 transitions. [2018-04-06 23:14:17,138 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 102 transitions. Word has length 63 [2018-04-06 23:14:17,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:17,139 INFO L459 AbstractCegarLoop]: Abstraction has 94 states and 102 transitions. [2018-04-06 23:14:17,139 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-06 23:14:17,139 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-04-06 23:14:17,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-04-06 23:14:17,140 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:17,140 INFO L355 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:17,140 INFO L408 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:17,140 INFO L82 PathProgramCache]: Analyzing trace with hash -452021334, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:17,145 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:17,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:17,168 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:17,171 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:17,171 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:17,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:17,174 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:14:17,475 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:17,475 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:17,804 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-06 23:14:17,825 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:17,826 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 27 [2018-04-06 23:14:17,826 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-06 23:14:17,826 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-06 23:14:17,826 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=671, Unknown=0, NotChecked=0, Total=756 [2018-04-06 23:14:17,826 INFO L87 Difference]: Start difference. First operand 94 states and 102 transitions. Second operand 28 states. [2018-04-06 23:14:19,215 WARN L148 SmtUtils]: Spent 312ms on a formula simplification that was a NOOP. DAG size: 48 [2018-04-06 23:14:19,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:19,521 INFO L93 Difference]: Finished difference Result 202 states and 221 transitions. [2018-04-06 23:14:19,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-06 23:14:19,521 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 76 [2018-04-06 23:14:19,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:19,522 INFO L225 Difference]: With dead ends: 202 [2018-04-06 23:14:19,522 INFO L226 Difference]: Without dead ends: 201 [2018-04-06 23:14:19,523 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 176 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 389 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=504, Invalid=2148, Unknown=0, NotChecked=0, Total=2652 [2018-04-06 23:14:19,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-04-06 23:14:19,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 149. [2018-04-06 23:14:19,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-06 23:14:19,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 163 transitions. [2018-04-06 23:14:19,570 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 163 transitions. Word has length 76 [2018-04-06 23:14:19,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:19,570 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 163 transitions. [2018-04-06 23:14:19,571 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-06 23:14:19,571 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 163 transitions. [2018-04-06 23:14:19,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-04-06 23:14:19,572 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:19,572 INFO L355 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:19,572 INFO L408 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:19,572 INFO L82 PathProgramCache]: Analyzing trace with hash 888884808, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:19,579 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:19,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:19,606 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:19,609 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:19,609 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:19,612 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:19,612 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:14:19,892 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-06 23:14:19,893 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:20,309 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-06 23:14:20,331 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:20,332 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 31 [2018-04-06 23:14:20,332 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-06 23:14:20,332 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-06 23:14:20,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=880, Unknown=0, NotChecked=0, Total=992 [2018-04-06 23:14:20,332 INFO L87 Difference]: Start difference. First operand 149 states and 163 transitions. Second operand 32 states. [2018-04-06 23:14:22,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:22,462 INFO L93 Difference]: Finished difference Result 268 states and 293 transitions. [2018-04-06 23:14:22,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-06 23:14:22,462 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 94 [2018-04-06 23:14:22,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:22,464 INFO L225 Difference]: With dead ends: 268 [2018-04-06 23:14:22,464 INFO L226 Difference]: Without dead ends: 267 [2018-04-06 23:14:22,465 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 216 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 521 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=713, Invalid=2827, Unknown=0, NotChecked=0, Total=3540 [2018-04-06 23:14:22,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-04-06 23:14:22,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 158. [2018-04-06 23:14:22,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-04-06 23:14:22,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 172 transitions. [2018-04-06 23:14:22,521 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 172 transitions. Word has length 94 [2018-04-06 23:14:22,522 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:22,522 INFO L459 AbstractCegarLoop]: Abstraction has 158 states and 172 transitions. [2018-04-06 23:14:22,522 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-06 23:14:22,522 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 172 transitions. [2018-04-06 23:14:22,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-04-06 23:14:22,523 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:22,523 INFO L355 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:22,523 INFO L408 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:22,523 INFO L82 PathProgramCache]: Analyzing trace with hash 1100056318, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:22,533 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:22,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:22,574 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:22,577 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:22,577 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:22,580 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:22,580 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:14:23,217 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-06 23:14:23,217 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:24,293 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-06 23:14:24,315 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:24,315 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 43 [2018-04-06 23:14:24,315 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-06 23:14:24,316 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-06 23:14:24,316 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1725, Unknown=0, NotChecked=0, Total=1892 [2018-04-06 23:14:24,316 INFO L87 Difference]: Start difference. First operand 158 states and 172 transitions. Second operand 44 states. [2018-04-06 23:14:26,298 WARN L151 SmtUtils]: Spent 385ms on a formula simplification. DAG size of input: 66 DAG size of output 58 [2018-04-06 23:14:26,489 WARN L151 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-06 23:14:30,248 WARN L151 SmtUtils]: Spent 377ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-06 23:14:30,966 WARN L151 SmtUtils]: Spent 390ms on a formula simplification. DAG size of input: 55 DAG size of output 51 [2018-04-06 23:14:31,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:31,356 INFO L93 Difference]: Finished difference Result 421 states and 460 transitions. [2018-04-06 23:14:31,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-04-06 23:14:31,391 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 128 [2018-04-06 23:14:31,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:31,393 INFO L225 Difference]: With dead ends: 421 [2018-04-06 23:14:31,393 INFO L226 Difference]: Without dead ends: 420 [2018-04-06 23:14:31,395 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 315 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2146 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=1735, Invalid=8771, Unknown=0, NotChecked=0, Total=10506 [2018-04-06 23:14:31,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-04-06 23:14:31,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 277. [2018-04-06 23:14:31,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-04-06 23:14:31,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 303 transitions. [2018-04-06 23:14:31,467 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 303 transitions. Word has length 128 [2018-04-06 23:14:31,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:31,467 INFO L459 AbstractCegarLoop]: Abstraction has 277 states and 303 transitions. [2018-04-06 23:14:31,467 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-06 23:14:31,468 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 303 transitions. [2018-04-06 23:14:31,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-04-06 23:14:31,469 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:31,469 INFO L355 BasicCegarLoop]: trace histogram [10, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:31,469 INFO L408 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:31,469 INFO L82 PathProgramCache]: Analyzing trace with hash 746499740, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:31,475 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:31,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:31,509 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:31,513 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:31,513 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:31,530 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:31,530 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:14:32,128 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-06 23:14:32,129 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:33,064 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-06 23:14:33,085 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:33,085 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 47 [2018-04-06 23:14:33,086 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-04-06 23:14:33,086 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-04-06 23:14:33,087 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=2042, Unknown=0, NotChecked=0, Total=2256 [2018-04-06 23:14:33,087 INFO L87 Difference]: Start difference. First operand 277 states and 303 transitions. Second operand 48 states. [2018-04-06 23:14:34,330 WARN L151 SmtUtils]: Spent 222ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-06 23:14:35,055 WARN L151 SmtUtils]: Spent 676ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-06 23:14:37,268 WARN L151 SmtUtils]: Spent 768ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-06 23:14:37,808 WARN L151 SmtUtils]: Spent 480ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-06 23:14:38,216 WARN L151 SmtUtils]: Spent 362ms on a formula simplification. DAG size of input: 48 DAG size of output 46 [2018-04-06 23:14:38,476 WARN L148 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-06 23:14:39,406 WARN L148 SmtUtils]: Spent 137ms on a formula simplification that was a NOOP. DAG size: 48 [2018-04-06 23:14:41,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:14:41,414 INFO L93 Difference]: Finished difference Result 554 states and 605 transitions. [2018-04-06 23:14:41,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-04-06 23:14:41,414 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-04-06 23:14:41,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:14:41,416 INFO L225 Difference]: With dead ends: 554 [2018-04-06 23:14:41,416 INFO L226 Difference]: Without dead ends: 553 [2018-04-06 23:14:41,418 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 354 GetRequests, 246 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2514 ImplicationChecksByTransitivity, 8.5s TimeCoverageRelationStatistics Valid=2093, Invalid=9897, Unknown=0, NotChecked=0, Total=11990 [2018-04-06 23:14:41,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2018-04-06 23:14:41,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 286. [2018-04-06 23:14:41,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-04-06 23:14:41,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 312 transitions. [2018-04-06 23:14:41,498 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 312 transitions. Word has length 146 [2018-04-06 23:14:41,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:14:41,498 INFO L459 AbstractCegarLoop]: Abstraction has 286 states and 312 transitions. [2018-04-06 23:14:41,498 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-04-06 23:14:41,498 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 312 transitions. [2018-04-06 23:14:41,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-04-06 23:14:41,499 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:14:41,499 INFO L355 BasicCegarLoop]: trace histogram [16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:14:41,499 INFO L408 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:14:41,499 INFO L82 PathProgramCache]: Analyzing trace with hash -1895798874, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:14:41,505 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:14:41,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:14:41,560 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:14:41,563 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:14:41,563 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:14:41,566 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:14:41,566 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:14:42,845 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-06 23:14:42,845 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:14:45,156 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-06 23:14:45,178 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:14:45,178 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 75 [2018-04-06 23:14:45,178 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-04-06 23:14:45,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-04-06 23:14:45,180 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=5249, Unknown=0, NotChecked=0, Total=5700 [2018-04-06 23:14:45,180 INFO L87 Difference]: Start difference. First operand 286 states and 312 transitions. Second operand 76 states. [2018-04-06 23:14:46,559 WARN L151 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 107 DAG size of output 101 [2018-04-06 23:14:47,798 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 121 DAG size of output 97 [2018-04-06 23:14:48,762 WARN L151 SmtUtils]: Spent 853ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-06 23:14:51,556 WARN L151 SmtUtils]: Spent 785ms on a formula simplification. DAG size of input: 106 DAG size of output 88 [2018-04-06 23:14:52,554 WARN L151 SmtUtils]: Spent 879ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-06 23:14:54,733 WARN L148 SmtUtils]: Spent 472ms on a formula simplification that was a NOOP. DAG size: 83 [2018-04-06 23:14:55,039 WARN L151 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 92 DAG size of output 78 [2018-04-06 23:14:55,264 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-06 23:14:56,037 WARN L151 SmtUtils]: Spent 669ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-06 23:14:59,100 WARN L151 SmtUtils]: Spent 343ms on a formula simplification. DAG size of input: 55 DAG size of output 51 [2018-04-06 23:14:59,759 WARN L151 SmtUtils]: Spent 214ms on a formula simplification. DAG size of input: 52 DAG size of output 39 [2018-04-06 23:15:01,067 WARN L151 SmtUtils]: Spent 173ms on a formula simplification. DAG size of input: 49 DAG size of output 37 [2018-04-06 23:15:02,281 WARN L151 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-06 23:15:03,065 WARN L151 SmtUtils]: Spent 681ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-06 23:15:04,154 WARN L148 SmtUtils]: Spent 434ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-06 23:15:07,614 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 109 DAG size of output 89 [2018-04-06 23:15:08,367 WARN L151 SmtUtils]: Spent 596ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-06 23:15:08,801 WARN L148 SmtUtils]: Spent 107ms on a formula simplification that was a NOOP. DAG size: 113 [2018-04-06 23:15:09,232 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 90 DAG size of output 78 [2018-04-06 23:15:09,675 WARN L148 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 106 [2018-04-06 23:15:09,994 WARN L151 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 120 DAG size of output 98 [2018-04-06 23:15:10,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:15:10,053 INFO L93 Difference]: Finished difference Result 865 states and 944 transitions. [2018-04-06 23:15:10,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2018-04-06 23:15:10,054 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 232 [2018-04-06 23:15:10,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:15:10,057 INFO L225 Difference]: With dead ends: 865 [2018-04-06 23:15:10,057 INFO L226 Difference]: Without dead ends: 864 [2018-04-06 23:15:10,060 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 587 GetRequests, 390 SyntacticMatches, 0 SemanticMatches, 197 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9800 ImplicationChecksByTransitivity, 24.9s TimeCoverageRelationStatistics Valid=5709, Invalid=33693, Unknown=0, NotChecked=0, Total=39402 [2018-04-06 23:15:10,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states. [2018-04-06 23:15:10,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 533. [2018-04-06 23:15:10,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 533 states. [2018-04-06 23:15:10,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 533 states and 583 transitions. [2018-04-06 23:15:10,256 INFO L78 Accepts]: Start accepts. Automaton has 533 states and 583 transitions. Word has length 232 [2018-04-06 23:15:10,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:15:10,257 INFO L459 AbstractCegarLoop]: Abstraction has 533 states and 583 transitions. [2018-04-06 23:15:10,257 INFO L460 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-04-06 23:15:10,257 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 583 transitions. [2018-04-06 23:15:10,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-04-06 23:15:10,258 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:15:10,258 INFO L355 BasicCegarLoop]: trace histogram [18, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:15:10,258 INFO L408 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:15:10,258 INFO L82 PathProgramCache]: Analyzing trace with hash 947464516, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:15:10,264 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:15:10,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:15:10,336 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:15:10,339 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:15:10,340 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:15:10,344 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:15:10,344 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:15:13,266 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-06 23:15:13,267 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:15:16,006 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-06 23:15:16,027 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:15:16,027 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 79 [2018-04-06 23:15:16,028 INFO L442 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-04-06 23:15:16,028 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-04-06 23:15:16,028 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=566, Invalid=5754, Unknown=0, NotChecked=0, Total=6320 [2018-04-06 23:15:16,028 INFO L87 Difference]: Start difference. First operand 533 states and 583 transitions. Second operand 80 states. [2018-04-06 23:15:17,572 WARN L151 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 103 DAG size of output 89 [2018-04-06 23:15:18,237 WARN L151 SmtUtils]: Spent 525ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-06 23:15:18,738 WARN L151 SmtUtils]: Spent 402ms on a formula simplification. DAG size of input: 91 DAG size of output 79 [2018-04-06 23:15:18,950 WARN L148 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 113 [2018-04-06 23:15:19,813 WARN L151 SmtUtils]: Spent 376ms on a formula simplification. DAG size of input: 87 DAG size of output 75 [2018-04-06 23:15:21,432 WARN L151 SmtUtils]: Spent 493ms on a formula simplification. DAG size of input: 120 DAG size of output 98 [2018-04-06 23:15:21,987 WARN L151 SmtUtils]: Spent 438ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-06 23:15:22,758 WARN L151 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 81 DAG size of output 71 [2018-04-06 23:15:23,160 WARN L151 SmtUtils]: Spent 316ms on a formula simplification. DAG size of input: 78 DAG size of output 68 [2018-04-06 23:15:24,962 WARN L151 SmtUtils]: Spent 490ms on a formula simplification. DAG size of input: 106 DAG size of output 88 [2018-04-06 23:15:25,755 WARN L151 SmtUtils]: Spent 674ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-06 23:15:26,260 WARN L151 SmtUtils]: Spent 412ms on a formula simplification. DAG size of input: 74 DAG size of output 66 [2018-04-06 23:15:26,902 WARN L148 SmtUtils]: Spent 355ms on a formula simplification that was a NOOP. DAG size: 89 [2018-04-06 23:15:27,500 WARN L151 SmtUtils]: Spent 348ms on a formula simplification. DAG size of input: 69 DAG size of output 61 [2018-04-06 23:15:28,915 WARN L151 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 92 DAG size of output 78 [2018-04-06 23:15:29,133 WARN L151 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-06 23:15:29,898 WARN L151 SmtUtils]: Spent 673ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-06 23:15:30,375 WARN L148 SmtUtils]: Spent 384ms on a formula simplification that was a NOOP. DAG size: 78 [2018-04-06 23:15:32,422 WARN L151 SmtUtils]: Spent 295ms on a formula simplification. DAG size of input: 78 DAG size of output 68 [2018-04-06 23:15:32,996 WARN L151 SmtUtils]: Spent 467ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-06 23:15:33,653 WARN L151 SmtUtils]: Spent 567ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-06 23:15:34,262 WARN L148 SmtUtils]: Spent 369ms on a formula simplification that was a NOOP. DAG size: 65 [2018-04-06 23:15:35,886 WARN L151 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-06 23:15:36,782 WARN L148 SmtUtils]: Spent 369ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-06 23:15:37,190 WARN L151 SmtUtils]: Spent 193ms on a formula simplification. DAG size of input: 43 DAG size of output 41 [2018-04-06 23:15:40,612 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 111 DAG size of output 90 [2018-04-06 23:15:40,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:15:40,798 INFO L93 Difference]: Finished difference Result 1126 states and 1229 transitions. [2018-04-06 23:15:40,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 134 states. [2018-04-06 23:15:40,799 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 250 [2018-04-06 23:15:40,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:15:40,802 INFO L225 Difference]: With dead ends: 1126 [2018-04-06 23:15:40,802 INFO L226 Difference]: Without dead ends: 1125 [2018-04-06 23:15:40,804 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 630 GetRequests, 422 SyntacticMatches, 0 SemanticMatches, 208 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11292 ImplicationChecksByTransitivity, 26.0s TimeCoverageRelationStatistics Valid=6811, Invalid=37079, Unknown=0, NotChecked=0, Total=43890 [2018-04-06 23:15:40,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1125 states. [2018-04-06 23:15:40,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1125 to 542. [2018-04-06 23:15:40,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 542 states. [2018-04-06 23:15:40,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 542 states to 542 states and 592 transitions. [2018-04-06 23:15:40,979 INFO L78 Accepts]: Start accepts. Automaton has 542 states and 592 transitions. Word has length 250 [2018-04-06 23:15:40,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-06 23:15:40,980 INFO L459 AbstractCegarLoop]: Abstraction has 542 states and 592 transitions. [2018-04-06 23:15:40,980 INFO L460 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-04-06 23:15:40,980 INFO L276 IsEmpty]: Start isEmpty. Operand 542 states and 592 transitions. [2018-04-06 23:15:40,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 441 [2018-04-06 23:15:40,982 INFO L347 BasicCegarLoop]: Found error trace [2018-04-06 23:15:40,982 INFO L355 BasicCegarLoop]: trace histogram [32, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-06 23:15:40,982 INFO L408 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-06 23:15:40,982 INFO L82 PathProgramCache]: Analyzing trace with hash -760278794, now seen corresponding path program 4 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-06 23:15:41,008 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-06 23:15:41,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-06 23:15:41,120 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-06 23:15:41,123 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-06 23:15:41,123 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-06 23:15:41,129 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-06 23:15:41,129 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-06 23:15:45,132 INFO L134 CoverageAnalysis]: Checked inductivity of 3527 backedges. 0 proven. 3495 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-06 23:15:45,133 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-06 23:15:52,752 INFO L134 CoverageAnalysis]: Checked inductivity of 3527 backedges. 0 proven. 3495 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-06 23:15:52,773 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-06 23:15:52,773 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 139 [2018-04-06 23:15:52,774 INFO L442 AbstractCegarLoop]: Interpolant automaton has 140 states [2018-04-06 23:15:52,774 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 140 interpolants. [2018-04-06 23:15:52,775 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1499, Invalid=17961, Unknown=0, NotChecked=0, Total=19460 [2018-04-06 23:15:52,775 INFO L87 Difference]: Start difference. First operand 542 states and 592 transitions. Second operand 140 states. [2018-04-06 23:15:54,417 WARN L151 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 162 DAG size of output 132 [2018-04-06 23:15:55,094 WARN L151 SmtUtils]: Spent 431ms on a formula simplification. DAG size of input: 201 DAG size of output 185 [2018-04-06 23:15:55,466 WARN L151 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 158 DAG size of output 128 [2018-04-06 23:15:57,248 WARN L151 SmtUtils]: Spent 411ms on a formula simplification. DAG size of input: 231 DAG size of output 175 [2018-04-06 23:15:57,950 WARN L151 SmtUtils]: Spent 413ms on a formula simplification. DAG size of input: 227 DAG size of output 175 [2018-04-06 23:15:58,335 WARN L151 SmtUtils]: Spent 155ms on a formula simplification. DAG size of input: 153 DAG size of output 127 [2018-04-06 23:15:59,246 WARN L148 SmtUtils]: Spent 663ms on a formula simplification that was a NOOP. DAG size: 196 [2018-04-06 23:15:59,848 WARN L148 SmtUtils]: Spent 225ms on a formula simplification that was a NOOP. DAG size: 195 [2018-04-06 23:16:00,233 WARN L151 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 151 DAG size of output 125 [2018-04-06 23:16:00,661 WARN L151 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 148 DAG size of output 122 [2018-04-06 23:16:02,367 WARN L151 SmtUtils]: Spent 402ms on a formula simplification. DAG size of input: 189 DAG size of output 181 [2018-04-06 23:16:03,044 WARN L151 SmtUtils]: Spent 386ms on a formula simplification. DAG size of input: 216 DAG size of output 166 [2018-04-06 23:16:03,688 WARN L151 SmtUtils]: Spent 360ms on a formula simplification. DAG size of input: 213 DAG size of output 165 [2018-04-06 23:16:04,064 WARN L151 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 144 DAG size of output 120 [2018-04-06 23:16:04,515 WARN L148 SmtUtils]: Spent 208ms on a formula simplification that was a NOOP. DAG size: 184 [2018-04-06 23:16:05,133 WARN L148 SmtUtils]: Spent 223ms on a formula simplification that was a NOOP. DAG size: 183 [2018-04-06 23:16:05,508 WARN L151 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 142 DAG size of output 118 [2018-04-06 23:16:05,913 WARN L151 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 139 DAG size of output 115 [2018-04-06 23:16:07,928 WARN L151 SmtUtils]: Spent 705ms on a formula simplification. DAG size of input: 177 DAG size of output 169 [2018-04-06 23:16:08,543 WARN L151 SmtUtils]: Spent 331ms on a formula simplification. DAG size of input: 202 DAG size of output 156 [2018-04-06 23:16:09,150 WARN L151 SmtUtils]: Spent 330ms on a formula simplification. DAG size of input: 199 DAG size of output 155 [2018-04-06 23:16:09,519 WARN L151 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 135 DAG size of output 113 [2018-04-06 23:16:09,943 WARN L148 SmtUtils]: Spent 184ms on a formula simplification that was a NOOP. DAG size: 172 [2018-04-06 23:16:10,518 WARN L148 SmtUtils]: Spent 183ms on a formula simplification that was a NOOP. DAG size: 171 [2018-04-06 23:16:10,880 WARN L151 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 133 DAG size of output 111 [2018-04-06 23:16:11,271 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 130 DAG size of output 108 [2018-04-06 23:16:12,905 WARN L151 SmtUtils]: Spent 328ms on a formula simplification. DAG size of input: 165 DAG size of output 159 [2018-04-06 23:16:13,494 WARN L151 SmtUtils]: Spent 309ms on a formula simplification. DAG size of input: 188 DAG size of output 146 [2018-04-06 23:16:14,059 WARN L151 SmtUtils]: Spent 290ms on a formula simplification. DAG size of input: 185 DAG size of output 145 [2018-04-06 23:16:14,409 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 126 DAG size of output 106 [2018-04-06 23:16:14,869 WARN L148 SmtUtils]: Spent 227ms on a formula simplification that was a NOOP. DAG size: 160 [2018-04-06 23:16:15,431 WARN L148 SmtUtils]: Spent 171ms on a formula simplification that was a NOOP. DAG size: 159 [2018-04-06 23:16:15,780 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 125 DAG size of output 105 [2018-04-06 23:16:16,163 WARN L151 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 122 DAG size of output 102 [2018-04-06 23:16:18,190 WARN L151 SmtUtils]: Spent 714ms on a formula simplification. DAG size of input: 153 DAG size of output 149 [2018-04-06 23:16:18,752 WARN L151 SmtUtils]: Spent 278ms on a formula simplification. DAG size of input: 175 DAG size of output 137 [2018-04-06 23:16:19,287 WARN L151 SmtUtils]: Spent 260ms on a formula simplification. DAG size of input: 172 DAG size of output 136 [2018-04-06 23:16:19,631 WARN L151 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 118 DAG size of output 100 [2018-04-06 23:16:20,017 WARN L148 SmtUtils]: Spent 156ms on a formula simplification that was a NOOP. DAG size: 149 [2018-04-06 23:16:20,554 WARN L148 SmtUtils]: Spent 147ms on a formula simplification that was a NOOP. DAG size: 148 [2018-04-06 23:16:20,897 WARN L151 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 116 DAG size of output 98 [2018-04-06 23:16:21,275 WARN L151 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 113 DAG size of output 95 [2018-04-06 23:16:23,492 WARN L151 SmtUtils]: Spent 911ms on a formula simplification. DAG size of input: 142 DAG size of output 138 [2018-04-06 23:16:24,023 WARN L151 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 161 DAG size of output 127 [2018-04-06 23:16:24,528 WARN L151 SmtUtils]: Spent 237ms on a formula simplification. DAG size of input: 158 DAG size of output 126 [2018-04-06 23:16:24,846 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 109 DAG size of output 93 [2018-04-06 23:16:25,205 WARN L148 SmtUtils]: Spent 139ms on a formula simplification that was a NOOP. DAG size: 137 [2018-04-06 23:16:25,729 WARN L148 SmtUtils]: Spent 132ms on a formula simplification that was a NOOP. DAG size: 136 [2018-04-06 23:16:26,055 WARN L151 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 107 DAG size of output 91 [2018-04-06 23:16:28,216 WARN L148 SmtUtils]: Spent 511ms on a formula simplification that was a NOOP. DAG size: 130 [2018-04-06 23:16:28,705 WARN L151 SmtUtils]: Spent 215ms on a formula simplification. DAG size of input: 147 DAG size of output 117 [2018-04-06 23:16:29,186 WARN L151 SmtUtils]: Spent 211ms on a formula simplification. DAG size of input: 144 DAG size of output 116 [2018-04-06 23:16:29,811 WARN L148 SmtUtils]: Spent 114ms on a formula simplification that was a NOOP. DAG size: 125 [2018-04-06 23:16:30,302 WARN L148 SmtUtils]: Spent 118ms on a formula simplification that was a NOOP. DAG size: 124 [2018-04-06 23:16:32,381 WARN L148 SmtUtils]: Spent 112ms on a formula simplification that was a NOOP. DAG size: 118 [2018-04-06 23:16:32,842 WARN L151 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 133 DAG size of output 107 [2018-04-06 23:16:33,286 WARN L151 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-06 23:16:34,177 WARN L151 SmtUtils]: Spent 680ms on a formula simplification. DAG size of input: 91 DAG size of output 79 [2018-04-06 23:16:37,346 WARN L148 SmtUtils]: Spent 453ms on a formula simplification that was a NOOP. DAG size: 106 [2018-04-06 23:16:37,781 WARN L151 SmtUtils]: Spent 160ms on a formula simplification. DAG size of input: 120 DAG size of output 98 [2018-04-06 23:16:38,192 WARN L151 SmtUtils]: Spent 164ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-06 23:16:41,581 WARN L151 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 106 DAG size of output 88 [2018-04-06 23:16:41,953 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-06 23:16:45,215 WARN L151 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 92 DAG size of output 78 [2018-04-06 23:16:45,560 WARN L151 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-06 23:16:45,890 WARN L151 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 65 DAG size of output 59 [2018-04-06 23:16:49,401 WARN L151 SmtUtils]: Spent 426ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-06 23:16:50,040 WARN L151 SmtUtils]: Spent 444ms on a formula simplification. DAG size of input: 56 DAG size of output 52 [2018-04-06 23:16:54,119 WARN L148 SmtUtils]: Spent 315ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-06 23:16:56,357 WARN L151 SmtUtils]: Spent 211ms on a formula simplification. DAG size of input: 51 DAG size of output 49 [2018-04-06 23:16:59,602 WARN L151 SmtUtils]: Spent 205ms on a formula simplification. DAG size of input: 179 DAG size of output 143 [2018-04-06 23:17:00,458 WARN L151 SmtUtils]: Spent 444ms on a formula simplification. DAG size of input: 240 DAG size of output 184 [2018-04-06 23:17:00,932 WARN L151 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 161 DAG size of output 133 [2018-04-06 23:17:01,491 WARN L148 SmtUtils]: Spent 248ms on a formula simplification that was a NOOP. DAG size: 207 [2018-04-06 23:17:02,025 WARN L148 SmtUtils]: Spent 251ms on a formula simplification that was a NOOP. DAG size: 206 [2018-04-06 23:17:02,472 WARN L151 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 160 DAG size of output 132 [2018-04-06 23:17:02,881 WARN L151 SmtUtils]: Spent 168ms on a formula simplification. DAG size of input: 157 DAG size of output 129 [2018-04-06 23:17:03,670 WARN L151 SmtUtils]: Spent 455ms on a formula simplification. DAG size of input: 200 DAG size of output 192 [2018-04-06 23:17:04,373 WARN L151 SmtUtils]: Spent 404ms on a formula simplification. DAG size of input: 230 DAG size of output 176 [2018-04-06 23:17:04,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-06 23:17:04,530 INFO L93 Difference]: Finished difference Result 1753 states and 1912 transitions. [2018-04-06 23:17:04,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 255 states. [2018-04-06 23:17:04,531 INFO L78 Accepts]: Start accepts. Automaton has 140 states. Word has length 440 [2018-04-06 23:17:04,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-06 23:17:04,538 INFO L225 Difference]: With dead ends: 1753 [2018-04-06 23:17:04,538 INFO L226 Difference]: Without dead ends: 1752 [2018-04-06 23:17:04,547 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1131 GetRequests, 742 SyntacticMatches, 0 SemanticMatches, 389 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42052 ImplicationChecksByTransitivity, 73.7s TimeCoverageRelationStatistics Valid=20329, Invalid=132161, Unknown=0, NotChecked=0, Total=152490 [2018-04-06 23:17:04,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1752 states. Received shutdown request... [2018-04-06 23:17:04,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1752 to 1045. [2018-04-06 23:17:04,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1045 states. [2018-04-06 23:17:04,982 WARN L519 AbstractCegarLoop]: Verification canceled [2018-04-06 23:17:04,986 WARN L197 ceAbstractionStarter]: Timeout [2018-04-06 23:17:04,986 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 06.04 11:17:04 BasicIcfg [2018-04-06 23:17:04,986 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-06 23:17:04,987 INFO L168 Benchmark]: Toolchain (without parser) took 234325.07 ms. Allocated memory was 301.5 MB in the beginning and 519.0 MB in the end (delta: 217.6 MB). Free memory was 237.0 MB in the beginning and 318.4 MB in the end (delta: -81.4 MB). Peak memory consumption was 226.3 MB. Max. memory is 5.3 GB. [2018-04-06 23:17:04,987 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 301.5 MB. Free memory is still 263.5 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-06 23:17:04,987 INFO L168 Benchmark]: CACSL2BoogieTranslator took 355.62 ms. Allocated memory is still 301.5 MB. Free memory was 237.0 MB in the beginning and 212.8 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 5.3 GB. [2018-04-06 23:17:04,988 INFO L168 Benchmark]: Boogie Preprocessor took 52.58 ms. Allocated memory is still 301.5 MB. Free memory was 212.8 MB in the beginning and 209.8 MB in the end (delta: 3.1 MB). Peak memory consumption was 3.1 MB. Max. memory is 5.3 GB. [2018-04-06 23:17:04,988 INFO L168 Benchmark]: RCFGBuilder took 613.84 ms. Allocated memory was 301.5 MB in the beginning and 460.3 MB in the end (delta: 158.9 MB). Free memory was 209.8 MB in the beginning and 392.8 MB in the end (delta: -183.1 MB). Peak memory consumption was 21.4 MB. Max. memory is 5.3 GB. [2018-04-06 23:17:04,988 INFO L168 Benchmark]: IcfgTransformer took 39776.61 ms. Allocated memory was 460.3 MB in the beginning and 1.0 GB in the end (delta: 553.6 MB). Free memory was 392.8 MB in the beginning and 673.3 MB in the end (delta: -280.5 MB). Peak memory consumption was 273.1 MB. Max. memory is 5.3 GB. [2018-04-06 23:17:04,988 INFO L168 Benchmark]: TraceAbstraction took 193521.37 ms. Allocated memory was 1.0 GB in the beginning and 519.0 MB in the end (delta: -494.9 MB). Free memory was 673.3 MB in the beginning and 318.4 MB in the end (delta: 354.9 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-04-06 23:17:04,990 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 301.5 MB. Free memory is still 263.5 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 355.62 ms. Allocated memory is still 301.5 MB. Free memory was 237.0 MB in the beginning and 212.8 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 52.58 ms. Allocated memory is still 301.5 MB. Free memory was 212.8 MB in the beginning and 209.8 MB in the end (delta: 3.1 MB). Peak memory consumption was 3.1 MB. Max. memory is 5.3 GB. * RCFGBuilder took 613.84 ms. Allocated memory was 301.5 MB in the beginning and 460.3 MB in the end (delta: 158.9 MB). Free memory was 209.8 MB in the beginning and 392.8 MB in the end (delta: -183.1 MB). Peak memory consumption was 21.4 MB. Max. memory is 5.3 GB. * IcfgTransformer took 39776.61 ms. Allocated memory was 460.3 MB in the beginning and 1.0 GB in the end (delta: 553.6 MB). Free memory was 392.8 MB in the beginning and 673.3 MB in the end (delta: -280.5 MB). Peak memory consumption was 273.1 MB. Max. memory is 5.3 GB. * TraceAbstraction took 193521.37 ms. Allocated memory was 1.0 GB in the beginning and 519.0 MB in the end (delta: -494.9 MB). Free memory was 673.3 MB in the beginning and 318.4 MB in the end (delta: 354.9 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 78 LocStat_MAX_WEQGRAPH_SIZE : 2 LocStat_MAX_SIZEOF_WEQEDGELABEL : 3 LocStat_NO_SUPPORTING_EQUALITIES : 1610 LocStat_NO_SUPPORTING_DISEQUALITIES : 431 LocStat_NO_DISJUNCTIONS : -156 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 96 TransStat_MAX_WEQGRAPH_SIZE : 4 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 111 TransStat_NO_SUPPORTING_DISEQUALITIES : 14 TransStat_NO_DISJUNCTIONS : 99 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 8394.76 RENAME_VARIABLES(MILLISECONDS) : 517.68 UNFREEZE(MILLISECONDS) : 0.00 CONJOIN(MILLISECONDS) : 8401.65 PROJECTAWAY(MILLISECONDS) : 16360.41 ADD_WEAK_EQUALITY(MILLISECONDS) : 7.19 DISJOIN(MILLISECONDS) : 390.55 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 554.16 ADD_EQUALITY(MILLISECONDS) : 10.42 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.00 ADD_DISEQUALITY(MILLISECONDS) : 0.43 #CONJOIN_DISJUNCTIVE : 792 #RENAME_VARIABLES : 1636 #UNFREEZE : 0 #CONJOIN : 952 #PROJECTAWAY : 916 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 400 #RENAME_VARIABLES_DISJUNCTIVE : 1594 #ADD_EQUALITY : 112 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 11 - StatisticsResult: WeqCcManagerStatistics FREEZE(MILLISECONDS) : 21179.67 ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 8385.06 FILTERREDUNDANT(MILLISECONDS) : 0.00 REPORTWEQ(MILLISECONDS) : 6.97 JOIN(MILLISECONDS) : 365.97 RENAMEVARS(MILLISECONDS) : 499.96 FLATTENLABELS(MILLISECONDS) : 0.00 COPY(MILLISECONDS) : 0.00 ISSTRONGERTHAN(MILLISECONDS) : 12126.48 ISLABELSTRONGERTHAN(MILLISECONDS) : 2397.36 ISWEQGRAPHSTRONGERTHAN(MILLISECONDS) : 106.27 UNFREEZE(MILLISECONDS) : 181.09 REPORTCONTAINS(MILLISECONDS) : 2.59 PROJECTAWAY(MILLISECONDS) : 16143.21 MEETEDGELABELS(MILLISECONDS) : 1187.83 REPORTEQUALITY(MILLISECONDS) : 2143.28 ADDALLNODES(MILLISECONDS) : 718.23 REPORTDISEQUALITY(MILLISECONDS) : 10.74 WEQGRAPHJOIN(MILLISECONDS) : 126.35 #FREEZE : 6718 #ADDNODE : 0 #MEET : 709 #FILTERREDUNDANT : 0 #REPORTWEQ : 14 #JOIN : 400 #RENAMEVARS : 1636 #FLATTENLABELS : 0 #COPY : 0 #ISSTRONGERTHAN : 1879 #ISLABELSTRONGERTHAN : 187713 #ISWEQGRAPHSTRONGERTHAN : 851 #UNFREEZE : 4189 #REPORTCONTAINS : 99 #PROJECTAWAY : 1844 #MEETEDGELABELS : 8542 #REPORTEQUALITY : 16918 #ADDALLNODES : 709 #REPORTDISEQUALITY : 3839 #WEQGRAPHJOIN : 400 - StatisticsResult: CcManagerStatistics ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 12693.12 REPORT_EQUALITY(MILLISECONDS) : 4933.11 FILTERREDUNDANT(MILLISECONDS) : 10338.17 ADD_ALL_ELEMENTS(MILLISECONDS) : 2165.35 JOIN(MILLISECONDS) : 177.56 ALIGN_ELEMENTS(MILLISECONDS) : 2999.45 COPY(MILLISECONDS) : 0.00 REPORT_DISEQUALITY(MILLISECONDS) : 637.17 UNFREEZE(MILLISECONDS) : 0.00 OVERALL(MILLISECONDS) : 18008.90 REPORTCONTAINS(MILLISECONDS) : 26.51 IS_STRONGER_THAN_NO_CACHING(MILLISECONDS) : 4850.11 REMOVE(MILLISECONDS) : 0.00 IS_STRONGER_THAN_W_CACHING(MILLISECONDS) : 0.00 PROJECT_TO_ELEMENTS(MILLISECONDS) : 1960.84 #ADDNODE : 0 #MEET : 27803 #REPORT_EQUALITY : 532890 #FILTERREDUNDANT : 423820 #ADD_ALL_ELEMENTS : 94430 #JOIN : 400 #ALIGN_ELEMENTS : 32360 #COPY : 0 #REPORT_DISEQUALITY : 132419 #UNFREEZE : 0 #OVERALL : 1643291 #REPORTCONTAINS : 1563 #IS_STRONGER_THAN_NO_CACHING : 371775 #REMOVE : 0 #IS_STRONGER_THAN_W_CACHING : 0 #PROJECT_TO_ELEMENTS : 25831 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - TimeoutResultAtElement [Line: 564]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 564). Cancelled while ReachableStatesComputation was computing reachable states (1 states constructedinput type DoubleDeckerAutomaton). - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 82 locations, 9 error locations. TIMEOUT Result, 193.4s OverallTime, 22 OverallIterations, 32 TraceHistogramMax, 150.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2470 SDtfs, 21795 SDslu, 45039 SDs, 0 SdLazy, 26628 SolverSat, 1747 SolverUnsat, 29 SolverUnknown, 0 SolverNotchecked, 15.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 4976 GetRequests, 3568 SyntacticMatches, 26 SemanticMatches, 1382 ConstructedPredicates, 24 IntricatePredicates, 0 DeprecatedPredicates, 69357 ImplicationChecksByTransitivity, 163.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=542occurred in iteration=21, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 22 MinimizatonAttempts, 1986 StatesRemovedByMinimization, 18 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 40.3s InterpolantComputationTime, 2104 NumberOfCodeBlocks, 2104 NumberOfCodeBlocksAsserted, 22 NumberOfCheckSat, 4164 ConstructedInterpolants, 1681 QuantifiedInterpolants, 16385623 SizeOfPredicates, 320 NumberOfNonLiveVariables, 5624 ConjunctsInSsa, 616 ConjunctsInUnsatCore, 44 InterpolantComputations, 26 PerfectInterpolantSequences, 336/11658 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-04-06_23-17-05-001.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-04-06_23-17-05-001.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-04-06_23-17-05-001.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-1-2018-04-06_23-17-05-001.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-2-2018-04-06_23-17-05-001.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-04-06_23-17-05-001.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-06_23-17-05-001.csv Completed graceful shutdown