java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf -i ../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-453dfda-m [2018-04-09 23:59:54,966 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-09 23:59:54,968 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-09 23:59:54,983 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-04-09 23:59:55,010 INFO L98 SettingsManager]: Beginning loading settings from /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/eq-bench/svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf [2018-04-09 23:59:55,033 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-09 23:59:55,033 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-09 23:59:55,034 INFO L131 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2018-04-09 23:59:55,034 INFO L133 SettingsManager]: * ultimate.logging.details=de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation=DEBUG; [2018-04-09 23:59:55,034 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-04-09 23:59:55,035 INFO L133 SettingsManager]: * to procedures, called more than once=true [2018-04-09 23:59:55,035 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-04-09 23:59:55,035 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=VPDomain [2018-04-09 23:59:55,035 INFO L133 SettingsManager]: * Parallel states before merging=1 [2018-04-09 23:59:55,035 INFO L133 SettingsManager]: * Use the RCFG-of-the-future interface=true [2018-04-09 23:59:55,036 INFO L131 SettingsManager]: Preferences of LTL2Aut differ from their defaults: [2018-04-09 23:59:55,036 INFO L133 SettingsManager]: * Property to check=[] a a: x > 42 [2018-04-09 23:59:55,036 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-09 23:59:55,036 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-09 23:59:55,037 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-09 23:59:55,037 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-09 23:59:55,037 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-09 23:59:55,037 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-09 23:59:55,037 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-09 23:59:55,037 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-04-09 23:59:55,038 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-09 23:59:55,038 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-09 23:59:55,038 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-09 23:59:55,038 INFO L133 SettingsManager]: * Size of a code block=SingleStatement [2018-04-09 23:59:55,038 INFO L133 SettingsManager]: * Add additional assume for each assert=false [2018-04-09 23:59:55,039 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-09 23:59:55,039 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-09 23:59:55,039 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-09 23:59:55,039 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-09 23:59:55,039 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-09 23:59:55,040 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-04-09 23:59:55,040 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-04-09 23:59:55,040 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-09 23:59:55,040 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-04-09 23:59:55,041 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-04-09 23:59:55,041 INFO L133 SettingsManager]: * TransformationType=HEAP_SEPARATOR [2018-04-09 23:59:55,041 INFO L131 SettingsManager]: Preferences of Boogie Printer differ from their defaults: [2018-04-09 23:59:55,042 INFO L133 SettingsManager]: * Dump path:=C:\Users\alex\AppData\Local\Temp\ [2018-04-09 23:59:55,074 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-09 23:59:55,083 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-09 23:59:55,086 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-09 23:59:55,088 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-09 23:59:55,088 INFO L276 PluginConnector]: CDTParser initialized [2018-04-09 23:59:55,089 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,398 INFO L225 CDTParser]: Created temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGff1ada946 [2018-04-09 23:59:55,568 INFO L287 CDTParser]: IsIndexed: true [2018-04-09 23:59:55,568 INFO L288 CDTParser]: Found 1 translation units. [2018-04-09 23:59:55,569 INFO L168 CDTParser]: Scanning diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,580 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-09 23:59:55,580 INFO L215 ultiparseSymbolTable]: [2018-04-09 23:59:55,580 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-09 23:59:55,580 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff ('diff') in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-09 23:59:55,581 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,581 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____socklen_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__size_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,582 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____intptr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsword_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__timer_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__mode_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,583 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_short in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__nlink_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ssize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,584 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uint in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____useconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_set in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____qaddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,585 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__dev_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,586 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__register_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,587 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____time_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ushort in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____key_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,588 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__daddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____gid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____loff_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,589 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__sigset_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_long in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____ino64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____caddr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__ulong in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____uint32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,590 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int8_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__wchar_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__lldiv_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__uid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__div_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__blksize_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__clockid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fd_mask in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,591 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____id_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int16_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____int32_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____rlim_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pid_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,592 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__u_int in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_char in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____off64_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____suseconds_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,593 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____u_quad_t in diff-alloca_true-valid-memsafety_true-termination.i [2018-04-09 23:59:55,612 INFO L330 CDTParser]: Deleted temporary CDT project at /storage/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGff1ada946 [2018-04-09 23:59:55,615 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-09 23:59:55,616 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-04-09 23:59:55,617 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-09 23:59:55,618 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-09 23:59:55,622 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-09 23:59:55,623 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,625 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e3855a6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55, skipping insertion in model container [2018-04-09 23:59:55,625 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,639 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-09 23:59:55,668 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-09 23:59:55,829 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-09 23:59:55,882 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-09 23:59:55,889 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-09 23:59:55,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55 WrapperNode [2018-04-09 23:59:55,925 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-09 23:59:55,926 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-09 23:59:55,926 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-09 23:59:55,926 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-09 23:59:55,936 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,936 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,951 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,951 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,962 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,968 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,971 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... [2018-04-09 23:59:55,976 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-09 23:59:55,977 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-09 23:59:55,977 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-09 23:59:55,977 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-09 23:59:55,978 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (1/1) ... No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-09 23:59:56,112 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-09 23:59:56,112 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-09 23:59:56,112 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-09 23:59:56,112 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-09 23:59:56,112 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-09 23:59:56,112 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-09 23:59:56,112 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-09 23:59:56,113 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-09 23:59:56,114 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-09 23:59:56,114 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-09 23:59:56,114 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-09 23:59:56,114 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-09 23:59:56,114 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-09 23:59:56,114 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-09 23:59:56,115 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-09 23:59:56,115 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-09 23:59:56,115 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-09 23:59:56,115 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-09 23:59:56,115 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-09 23:59:56,115 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-09 23:59:56,116 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-09 23:59:56,117 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-09 23:59:56,118 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-09 23:59:56,119 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-09 23:59:56,120 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-09 23:59:56,121 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-09 23:59:56,122 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-09 23:59:56,123 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-09 23:59:56,124 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-09 23:59:56,125 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-09 23:59:56,126 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-09 23:59:56,127 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-09 23:59:56,516 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-09 23:59:56,516 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.04 11:59:56 BoogieIcfgContainer [2018-04-09 23:59:56,517 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-09 23:59:56,517 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2018-04-09 23:59:56,517 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2018-04-09 23:59:56,518 INFO L276 PluginConnector]: IcfgTransformer initialized [2018-04-09 23:59:56,520 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.04 11:59:56" (1/1) ... [2018-04-09 23:59:56,526 INFO L139 apSepIcfgTransformer]: HeapSepIcfgTransformer: Starting heap partitioning [2018-04-09 23:59:56,526 INFO L140 apSepIcfgTransformer]: To be partitioned heap arrays found [#memory_int] [2018-04-09 23:59:56,544 INFO L299 apSepIcfgTransformer]: Heap separator: starting memloc-array-style preprocessing [2018-04-09 23:59:56,564 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-09 23:59:56,579 INFO L332 apSepIcfgTransformer]: finished MemlocArrayUpdater, created 2 location literals (each corresponds to one heap write) [2018-04-09 23:59:56,588 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-09 23:59:56,605 INFO L412 apSepIcfgTransformer]: finished preprocessing for the equality analysis [2018-04-09 23:59:56,606 DEBUG L416 apSepIcfgTransformer]: storeIndexInfoToLocLiteral: Map: (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) : |mll_L558'_0| (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) : |mll_L558'_1| [2018-04-09 23:59:56,608 DEBUG L418 apSepIcfgTransformer]: edgeToIndexToStoreIndexInfo: NestedMap2: (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 : (Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') : (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2) : (Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2)) [2018-04-09 23:59:56,668 INFO L101 FixpointEngine]: Starting fixpoint engine with domain VPDomain (maxUnwinding=3, maxParallelStates=1) [2018-04-10 00:00:36,530 INFO L314 AbstractInterpreter]: Visited 90 different actions 765 times. Merged at 58 different actions 438 times. Widened at 1 different actions 3 times. Found 64 fixpoints after 14 different actions. Largest state had 46 variables. [2018-04-10 00:00:36,532 INFO L424 apSepIcfgTransformer]: finished equality analysis [2018-04-10 00:00:36,540 INFO L195 HeapSepPreAnalysis]: Number of read from array group [#memory_int] : 4 [2018-04-10 00:00:36,541 INFO L434 apSepIcfgTransformer]: Finished pre analysis before partitioning [2018-04-10 00:00:36,541 INFO L435 apSepIcfgTransformer]: array groups: Set: [#memory_int] [2018-04-10 00:00:36,542 INFO L437 apSepIcfgTransformer]: select infos: Set: ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-10 00:00:36,564 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_32 [2018-04-10 00:00:36,564 DEBUG L374 HeapPartitionManager]: with contents [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-10 00:00:36,565 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-10 00:00:36,565 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-10 00:00:36,565 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-10 00:00:36,565 DEBUG L373 HeapPartitionManager]: creating LocationBlock locs_31 [2018-04-10 00:00:36,565 DEBUG L374 HeapPartitionManager]: with contents [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-10 00:00:36,565 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-10 00:00:36,566 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))), at (SUMMARY for call #t~mem5 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L558)) [2018-04-10 00:00:36,566 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-10 00:00:36,566 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-10 00:00:36,566 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-10 00:00:36,566 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-10 00:00:36,566 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-10 00:00:36,567 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))), at (SUMMARY for call #t~mem3 := read~int(~B.base, ~B.offset + ~j~0 * 4, 4); srcloc: L551')) [2018-04-10 00:00:36,567 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-10 00:00:36,567 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-10 00:00:36,567 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-10 00:00:36,567 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-10 00:00:36,568 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_31 [2018-04-10 00:00:36,568 DEBUG L324 HeapPartitionManager]: at dimension 1 for ((select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))), at (SUMMARY for call #t~mem2 := read~int(~A.base, ~A.offset + ~i~0 * 4, 4); srcloc: L551)) [2018-04-10 00:00:36,568 DEBUG L325 HeapPartitionManager]: write locations: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-10 00:00:36,568 DEBUG L323 HeapPartitionManager]: adding LocationBlock locs_32 [2018-04-10 00:00:36,568 DEBUG L324 HeapPartitionManager]: at dimension 0 for ((select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2), at (SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558')) [2018-04-10 00:00:36,568 DEBUG L325 HeapPartitionManager]: write locations: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-10 00:00:36,568 INFO L330 HeapPartitionManager]: partitioning result: [2018-04-10 00:00:36,569 INFO L335 HeapPartitionManager]: location blocks for array group [#memory_int] [2018-04-10 00:00:36,569 INFO L344 HeapPartitionManager]: at dimension 0 [2018-04-10 00:00:36,569 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-10 00:00:36,569 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-10 00:00:36,569 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-10 00:00:36,569 DEBUG L356 HeapPartitionManager]: [(Store [1] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)] [2018-04-10 00:00:36,570 INFO L344 HeapPartitionManager]: at dimension 1 [2018-04-10 00:00:36,570 INFO L345 HeapPartitionManager]: # array writes (possibly including 1 dummy write/NoStoreIndexInfo) : 1 [2018-04-10 00:00:36,570 INFO L346 HeapPartitionManager]: # location blocks :1 [2018-04-10 00:00:36,570 DEBUG L353 HeapPartitionManager]: location block contents: [2018-04-10 00:00:36,570 DEBUG L356 HeapPartitionManager]: [(Store [0] at(SUMMARY for call write~int(#t~mem5, ~D.base, ~D.offset + ~k~0 * 4, 4); srcloc: L558') with (+ (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2) v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))] [2018-04-10 00:00:36,571 INFO L134 ransitionTransformer]: executing heap partitioning transformation [2018-04-10 00:00:36,574 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,575 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,575 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,575 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,575 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,575 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,575 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,575 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,576 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,576 DEBUG L331 ransitionTransformer]: Formula: (and (= |v_#NULL.offset_1| 0) (= |v_#NULL.base_1| 0)) InVars {} OutVars{#NULL.offset=|v_#NULL.offset_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] [2018-04-10 00:00:36,576 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,576 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,576 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,576 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,576 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,576 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,576 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,577 DEBUG L331 ransitionTransformer]: Formula: (and (<= 0 (+ |v_main_#t~nondet8_1| 2147483648)) (<= |v_main_#t~nondet8_1| 2147483647)) InVars {main_#t~nondet8=|v_main_#t~nondet8_1|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_1|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,577 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,577 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,577 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,577 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_9| (store |v_#valid_10| 0 0)) InVars {#valid=|v_#valid_10|} OutVars{#valid=|v_#valid_9|} AuxVars[] AssignedVars[#valid] [2018-04-10 00:00:36,577 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,577 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,577 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,577 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Alen~0_1 |v_main_#t~nondet8_2|) InVars {main_#t~nondet8=|v_main_#t~nondet8_2|} OutVars{main_#t~nondet8=|v_main_#t~nondet8_2|, main_~Alen~0=v_main_~Alen~0_1} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-10 00:00:36,577 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,578 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,578 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,578 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,578 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,578 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,578 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,578 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,578 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,578 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,578 DEBUG L356 ransitionTransformer]: {main_#t~nondet8=|v_main_#t~nondet8_3|} [2018-04-10 00:00:36,578 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,579 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,579 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,579 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,579 DEBUG L331 ransitionTransformer]: Formula: (and (<= |v_main_#t~nondet9_1| 2147483647) (<= 0 (+ |v_main_#t~nondet9_1| 2147483648))) InVars {main_#t~nondet9=|v_main_#t~nondet9_1|} OutVars{main_#t~nondet9=|v_main_#t~nondet9_1|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,579 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,579 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,579 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,579 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Blen~0_1 |v_main_#t~nondet9_2|) InVars {main_#t~nondet9=|v_main_#t~nondet9_2|} OutVars{main_~Blen~0=v_main_~Blen~0_1, main_#t~nondet9=|v_main_#t~nondet9_2|} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-10 00:00:36,579 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,579 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,580 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,580 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,580 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,580 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,580 DEBUG L356 ransitionTransformer]: {main_#t~nondet9=|v_main_#t~nondet9_3|} [2018-04-10 00:00:36,580 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,580 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,580 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,580 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,580 DEBUG L331 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Alen~0_2) (< v_main_~Alen~0_2 1)) InVars {main_~Alen~0=v_main_~Alen~0_2} OutVars{main_~Alen~0=v_main_~Alen~0_2} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,581 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,581 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,581 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,581 DEBUG L331 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Alen~0_4)) (not (< v_main_~Alen~0_4 1))) InVars {main_~Alen~0=v_main_~Alen~0_4} OutVars{main_~Alen~0=v_main_~Alen~0_4} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,581 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,581 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,581 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,581 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Alen~0_3 1) InVars {} OutVars{main_~Alen~0=v_main_~Alen~0_3} AuxVars[] AssignedVars[main_~Alen~0] [2018-04-10 00:00:36,581 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,582 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,582 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,582 DEBUG L331 ransitionTransformer]: Formula: (or (<= 536870911 v_main_~Blen~0_2) (< v_main_~Blen~0_2 1)) InVars {main_~Blen~0=v_main_~Blen~0_2} OutVars{main_~Blen~0=v_main_~Blen~0_2} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,582 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,582 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,582 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,583 DEBUG L331 ransitionTransformer]: Formula: (and (not (<= 536870911 v_main_~Blen~0_4)) (not (< v_main_~Blen~0_4 1))) InVars {main_~Blen~0=v_main_~Blen~0_4} OutVars{main_~Blen~0=v_main_~Blen~0_4} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,583 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,583 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,583 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,583 DEBUG L331 ransitionTransformer]: Formula: (= v_main_~Blen~0_3 1) InVars {} OutVars{main_~Blen~0=v_main_~Blen~0_3} AuxVars[] AssignedVars[main_~Blen~0] [2018-04-10 00:00:36,583 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,583 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,584 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,584 DEBUG L331 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc10.base_1|)) (= (store |v_#valid_12| |v_main_#t~malloc10.base_1| 1) |v_#valid_11|) (= |v_main_#t~malloc10.offset_1| 0) (= 0 (select |v_#valid_12| |v_main_#t~malloc10.base_1|)) (= |v_#length_9| (store |v_#length_10| |v_main_#t~malloc10.base_1| (* 4 v_main_~Alen~0_5)))) InVars {#length=|v_#length_10|, main_~Alen~0=v_main_~Alen~0_5, #valid=|v_#valid_12|} OutVars{#length=|v_#length_9|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_1|, main_~Alen~0=v_main_~Alen~0_5, main_#t~malloc10.base=|v_main_#t~malloc10.base_1|, #valid=|v_#valid_11|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc10.offset, main_#t~malloc10.base] [2018-04-10 00:00:36,584 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,584 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,584 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,584 DEBUG L331 ransitionTransformer]: Formula: (and (= v_main_~A~0.offset_1 |v_main_#t~malloc10.offset_2|) (= v_main_~A~0.base_1 |v_main_#t~malloc10.base_2|)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_2|, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|} OutVars{main_~A~0.offset=v_main_~A~0.offset_1, main_~A~0.base=v_main_~A~0.base_1, main_#t~malloc10.offset=|v_main_#t~malloc10.offset_2|, main_#t~malloc10.base=|v_main_#t~malloc10.base_2|} AuxVars[] AssignedVars[main_~A~0.offset, main_~A~0.base] [2018-04-10 00:00:36,584 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,584 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,585 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,585 DEBUG L331 ransitionTransformer]: Formula: (and (= |v_main_#t~malloc11.offset_1| 0) (not (= |v_main_#t~malloc11.base_1| 0)) (= (store |v_#valid_14| |v_main_#t~malloc11.base_1| 1) |v_#valid_13|) (= |v_#length_11| (store |v_#length_12| |v_main_#t~malloc11.base_1| (* 4 v_main_~Blen~0_5))) (= 0 (select |v_#valid_14| |v_main_#t~malloc11.base_1|))) InVars {#length=|v_#length_12|, main_~Blen~0=v_main_~Blen~0_5, #valid=|v_#valid_14|} OutVars{#length=|v_#length_11|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_1|, main_~Blen~0=v_main_~Blen~0_5, main_#t~malloc11.base=|v_main_#t~malloc11.base_1|, #valid=|v_#valid_13|} AuxVars[] AssignedVars[#valid, #length, main_#t~malloc11.offset, main_#t~malloc11.base] [2018-04-10 00:00:36,585 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,585 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,585 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,585 DEBUG L331 ransitionTransformer]: Formula: (and (= v_main_~B~0.offset_1 |v_main_#t~malloc11.offset_2|) (= v_main_~B~0.base_1 |v_main_#t~malloc11.base_2|)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_2|, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|} OutVars{main_~B~0.offset=v_main_~B~0.offset_1, main_#t~malloc11.offset=|v_main_#t~malloc11.offset_2|, main_~B~0.base=v_main_~B~0.base_1, main_#t~malloc11.base=|v_main_#t~malloc11.base_2|} AuxVars[] AssignedVars[main_~B~0.offset, main_~B~0.base] [2018-04-10 00:00:36,585 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,586 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,586 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,586 DEBUG L331 ransitionTransformer]: Formula: (and (not (= 0 |v_main_#t~malloc12.base_1|)) (= |v_#valid_15| (store |v_#valid_16| |v_main_#t~malloc12.base_1| 1)) (= 0 |v_main_#t~malloc12.offset_1|) (= 0 (select |v_#valid_16| |v_main_#t~malloc12.base_1|)) (= |v_#length_13| (store |v_#length_14| |v_main_#t~malloc12.base_1| (* 4 v_main_~Alen~0_6)))) InVars {#length=|v_#length_14|, main_~Alen~0=v_main_~Alen~0_6, #valid=|v_#valid_16|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_1|, #length=|v_#length_13|, main_~Alen~0=v_main_~Alen~0_6, main_#t~malloc12.base=|v_main_#t~malloc12.base_1|, #valid=|v_#valid_15|} AuxVars[] AssignedVars[main_#t~malloc12.offset, #valid, #length, main_#t~malloc12.base] [2018-04-10 00:00:36,586 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,587 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,587 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,587 DEBUG L331 ransitionTransformer]: Formula: (and (= v_main_~D~0.base_1 |v_main_#t~malloc12.base_2|) (= v_main_~D~0.offset_1 |v_main_#t~malloc12.offset_2|)) InVars {main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} OutVars{main_#t~malloc12.offset=|v_main_#t~malloc12.offset_2|, main_~D~0.base=v_main_~D~0.base_1, main_~D~0.offset=v_main_~D~0.offset_1, main_#t~malloc12.base=|v_main_#t~malloc12.base_2|} AuxVars[] AssignedVars[main_~D~0.base, main_~D~0.offset] [2018-04-10 00:00:36,587 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,587 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,588 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,588 DEBUG L331 ransitionTransformer]: Formula: (and (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1| v_main_~A~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1| v_main_~B~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1| v_main_~A~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1| v_main_~B~0.base_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1| v_main_~Blen~0_7) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1| v_main_~D~0.offset_3) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1| v_main_~Alen~0_8) (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1| v_main_~D~0.base_3)) InVars {main_~B~0.offset=v_main_~B~0.offset_3, main_~A~0.offset=v_main_~A~0.offset_3, main_~Blen~0=v_main_~Blen~0_7, main_~Alen~0=v_main_~Alen~0_8, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~B~0.base=v_main_~B~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, main_~B~0.offset=v_main_~B~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, main_~B~0.base=v_main_~B~0.base_3, main_~A~0.offset=v_main_~A~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, main_~Blen~0=v_main_~Blen~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, main_~Alen~0=v_main_~Alen~0_8, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen] [2018-04-10 00:00:36,588 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,588 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,588 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} [2018-04-10 00:00:36,589 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,589 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.baseInParam_1|, main_~B~0.offset=v_main_~B~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.baseInParam_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offsetInParam_1|, main_~B~0.base=v_main_~B~0.base_3, main_~A~0.offset=v_main_~A~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~BlenInParam_1|, main_~Blen~0=v_main_~Blen~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offsetInParam_1|, main_~Alen~0=v_main_~Alen~0_8, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offsetInParam_1|, main_~D~0.base=v_main_~D~0.base_3, main_~A~0.base=v_main_~A~0.base_3, main_~D~0.offset=v_main_~D~0.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~AlenInParam_1|} [2018-04-10 00:00:36,589 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,589 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,589 DEBUG L331 ransitionTransformer]: Formula: (= |v_main_#res_1| 0) InVars {} OutVars{main_#res=|v_main_#res_1|} AuxVars[] AssignedVars[main_#res] [2018-04-10 00:00:36,589 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,590 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,590 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,590 DEBUG L331 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~A.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base] [2018-04-10 00:00:36,590 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,590 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,591 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,591 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_17| (store |v_#valid_18| |v_main_#t~malloc10.base_3| 0)) InVars {main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_18|} OutVars{main_#t~malloc10.base=|v_main_#t~malloc10.base_3|, #valid=|v_#valid_17|} AuxVars[] AssignedVars[#valid] [2018-04-10 00:00:36,591 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,591 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,591 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,591 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Alen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen] [2018-04-10 00:00:36,592 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,592 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,592 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,592 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,592 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,592 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,592 DEBUG L356 ransitionTransformer]: {main_#t~malloc10.offset=|v_main_#t~malloc10.offset_4|, main_#t~malloc10.base=|v_main_#t~malloc10.base_4|} [2018-04-10 00:00:36,593 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,593 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,593 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,593 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,593 DEBUG L331 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~B.base_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset] [2018-04-10 00:00:36,593 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,594 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,594 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,594 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_19| (store |v_#valid_20| |v_main_#t~malloc11.base_3| 0)) InVars {main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_20|} OutVars{main_#t~malloc11.base=|v_main_#t~malloc11.base_3|, #valid=|v_#valid_19|} AuxVars[] AssignedVars[#valid] [2018-04-10 00:00:36,594 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,594 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,595 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,595 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~Blen_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen] [2018-04-10 00:00:36,595 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,595 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,595 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,595 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,596 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,596 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,596 DEBUG L356 ransitionTransformer]: {main_#t~malloc11.offset=|v_main_#t~malloc11.offset_4|, main_#t~malloc11.base=|v_main_#t~malloc11.base_4|} [2018-04-10 00:00:36,596 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,596 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,596 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,596 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,596 DEBUG L331 ransitionTransformer]: Formula: (and (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|) (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.base_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#in~D.offset_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset] [2018-04-10 00:00:36,596 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,597 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,597 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,597 DEBUG L331 ransitionTransformer]: Formula: (= (store |v_#valid_22| |v_main_#t~malloc12.base_3| 0) |v_#valid_21|) InVars {main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_22|} OutVars{main_#t~malloc12.base=|v_main_#t~malloc12.base_3|, #valid=|v_#valid_21|} AuxVars[] AssignedVars[#valid] [2018-04-10 00:00:36,597 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,597 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,597 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,597 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-10 00:00:36,597 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,597 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,597 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,598 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,598 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,598 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,598 DEBUG L356 ransitionTransformer]: {main_#t~malloc12.offset=|v_main_#t~malloc12.offset_4|, main_#t~malloc12.base=|v_main_#t~malloc12.base_4|} [2018-04-10 00:00:36,598 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,598 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,598 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,598 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,598 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-10 00:00:36,598 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,599 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,599 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,599 DEBUG L331 ransitionTransformer]: Formula: (= |v_#valid_23| |old(#valid)|) InVars {#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_23|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,599 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,599 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,599 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,599 DEBUG L331 ransitionTransformer]: Formula: (not (= |v_#valid_24| |old(#valid)|)) InVars {#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} OutVars{#valid=|v_#valid_24|, old(#valid)=|old(#valid)|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,599 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,599 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,599 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,600 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_1, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Alen_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0] [2018-04-10 00:00:36,600 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,600 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,600 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,600 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~Blen_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0] [2018-04-10 00:00:36,600 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,600 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,600 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,600 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,600 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,601 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,601 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_1} [2018-04-10 00:00:36,601 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,601 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,601 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,601 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,601 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,601 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,601 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,601 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,602 DEBUG L331 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,602 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,602 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,602 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,602 DEBUG L331 ransitionTransformer]: Formula: (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_2} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,602 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,602 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,602 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,603 DEBUG L331 ransitionTransformer]: Formula: (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l1~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_3} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,603 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,603 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,603 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,603 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,603 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,603 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,604 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,604 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_1} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-10 00:00:36,604 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,604 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,604 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,604 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2 0) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_2} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-10 00:00:36,605 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,605 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,605 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,605 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,605 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,605 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,606 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,606 DEBUG L331 ransitionTransformer]: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,606 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,606 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,606 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,606 DEBUG L331 ransitionTransformer]: Formula: (or (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3)) (not (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_2} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,606 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,607 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,607 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,607 DEBUG L331 ransitionTransformer]: Formula: (and (< v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3) (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~l2~0_3} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,607 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,607 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,608 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,608 DEBUG L331 ransitionTransformer]: Formula: (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_6} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,608 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,608 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,608 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,608 DEBUG L331 ransitionTransformer]: Formula: (not (= 0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_7} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,608 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,608 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,611 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,611 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2] [2018-04-10 00:00:36,612 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-10 00:00:36,612 DEBUG L339 ransitionTransformer]: old formula: [2018-04-10 00:00:36,612 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-10 00:00:36,612 DEBUG L341 ransitionTransformer]: new formula: [2018-04-10 00:00:36,612 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2 .cse0 4) (select |v_#length_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (<= 0 .cse1) (= 1 (select |v_#valid_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2)) (= (select (select |v_#memory_int_part_locs_32_locs_31_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|)))) [2018-04-10 00:00:36,612 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-10 00:00:36,613 DEBUG L347 ransitionTransformer]: old invars: [2018-04-10 00:00:36,613 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|} [2018-04-10 00:00:36,613 DEBUG L349 ransitionTransformer]: new invars: [2018-04-10 00:00:36,613 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|} [2018-04-10 00:00:36,613 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,613 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,613 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-10 00:00:36,614 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,614 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_2, #valid=|v_#valid_1|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_1|, #length=|v_#length_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_1|} [2018-04-10 00:00:36,614 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,614 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,614 DEBUG L331 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3))) InVars {#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} OutVars{#valid=|v_#valid_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_3} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,614 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,615 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,615 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,615 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3 .cse0 4) (select |v_#length_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4))))) InVars {#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} OutVars{#length=|v_#length_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_4} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,615 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,615 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,617 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,617 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5] [2018-04-10 00:00:36,617 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-10 00:00:36,617 DEBUG L339 ransitionTransformer]: old formula: [2018-04-10 00:00:36,617 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-10 00:00:36,618 DEBUG L341 ransitionTransformer]: new formula: [2018-04-10 00:00:36,618 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4 .cse0 4) (select |v_#length_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (= (select (select |v_#memory_int_part_locs_32_locs_31_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|) (= 1 (select |v_#valid_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5)) (<= 0 .cse1)))) [2018-04-10 00:00:36,618 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-10 00:00:36,618 DEBUG L347 ransitionTransformer]: old invars: [2018-04-10 00:00:36,618 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|} [2018-04-10 00:00:36,618 DEBUG L349 ransitionTransformer]: new invars: [2018-04-10 00:00:36,618 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|} [2018-04-10 00:00:36,619 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,619 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,619 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_3|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-10 00:00:36,619 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,619 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_6, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_4, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_5, #valid=|v_#valid_5|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_2|, #length=|v_#length_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_1|} [2018-04-10 00:00:36,619 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,620 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,620 DEBUG L331 ransitionTransformer]: Formula: (not (= (select |v_#valid_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6) 1)) InVars {#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} OutVars{#valid=|v_#valid_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_6} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,620 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,620 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,620 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,620 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5 .cse0 4) (select |v_#length_6| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7))))) InVars {#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} OutVars{#length=|v_#length_6|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_7, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.offset_5, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~A.base_7} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,621 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,621 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,621 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,621 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_8} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7] [2018-04-10 00:00:36,621 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,621 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,622 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,622 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3] [2018-04-10 00:00:36,622 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-10 00:00:36,622 DEBUG L339 ransitionTransformer]: old formula: [2018-04-10 00:00:36,622 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_2| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-10 00:00:36,622 DEBUG L341 ransitionTransformer]: new formula: [2018-04-10 00:00:36,622 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4))) (let ((.cse1 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0))) (and (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2 .cse0 4) (select |v_#length_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (= 1 (select |v_#valid_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2)) (<= 0 .cse1) (= (select (select |v_#memory_int_part_locs_32_locs_31_3| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2) .cse1) |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|)))) [2018-04-10 00:00:36,623 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-10 00:00:36,623 DEBUG L347 ransitionTransformer]: old invars: [2018-04-10 00:00:36,623 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-10 00:00:36,623 DEBUG L349 ransitionTransformer]: new invars: [2018-04-10 00:00:36,623 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2} [2018-04-10 00:00:36,623 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,623 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,623 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int=|v_#memory_int_2|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-10 00:00:36,623 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,623 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_4, #valid=|v_#valid_3|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_3|, #length=|v_#length_3|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_1|} [2018-04-10 00:00:36,624 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,624 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,624 DEBUG L331 ransitionTransformer]: Formula: (not (= 1 (select |v_#valid_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_3, #valid=|v_#valid_4|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,624 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,624 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,624 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,624 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5))) (or (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0 4) (select |v_#length_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4))) (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3 .cse0))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.base_4, #length=|v_#length_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~B.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_5} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,625 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,625 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,626 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,627 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} AuxVars[] AssignedVars[#memory_int_part_locs_32_locs_31] [2018-04-10 00:00:36,627 DEBUG L338 ransitionTransformer]: formula has changed [2018-04-10 00:00:36,627 DEBUG L339 ransitionTransformer]: old formula: [2018-04-10 00:00:36,627 DEBUG L340 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_5| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_4|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-10 00:00:36,627 DEBUG L341 ransitionTransformer]: new formula: [2018-04-10 00:00:36,627 DEBUG L342 ransitionTransformer]: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2))) (let ((.cse1 (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2))) (and (<= (+ .cse0 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2 4) (select |v_#length_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2)) (= (store |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2 (store (select |v_#memory_int_part_locs_32_locs_31_4| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) .cse1 |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|)) |v_#memory_int_part_locs_32_locs_31_5|) (= (select |v_#valid_7| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2) 1) (<= 0 .cse1)))) [2018-04-10 00:00:36,627 DEBUG L346 ransitionTransformer]: invars have changed [2018-04-10 00:00:36,627 DEBUG L347 ransitionTransformer]: old invars: [2018-04-10 00:00:36,627 DEBUG L348 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-10 00:00:36,627 DEBUG L349 ransitionTransformer]: new invars: [2018-04-10 00:00:36,627 DEBUG L350 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-10 00:00:36,628 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,628 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,628 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int=|v_#memory_int_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-10 00:00:36,628 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,628 DEBUG L358 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_2, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_2, #valid=|v_#valid_7|, #memory_int_part_locs_32_locs_31=|v_#memory_int_part_locs_32_locs_31_5|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_2, #length=|v_#length_7|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_2|} [2018-04-10 00:00:36,628 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,628 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,628 DEBUG L331 ransitionTransformer]: Formula: (not (= (select |v_#valid_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3) 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_3, #valid=|v_#valid_8|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,628 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,628 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,629 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,629 DEBUG L331 ransitionTransformer]: Formula: (let ((.cse0 (* 4 v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3))) (or (not (<= 0 (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0))) (not (<= (+ v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3 .cse0 4) (select |v_#length_8| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4))))) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_3, #length=|v_#length_8|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.offset_3, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~D.base_4} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,629 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,629 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,629 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,629 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0_9, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_2|} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~i~0] [2018-04-10 00:00:36,629 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,629 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,629 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,630 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_2|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,630 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,630 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,630 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,630 DEBUG L331 ransitionTransformer]: Formula: (not (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4| |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_4|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_4|} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,630 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,630 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,631 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,631 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,631 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,631 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,631 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem5_3|} [2018-04-10 00:00:36,631 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,631 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,631 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,632 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,632 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,632 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,632 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,632 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post7_3|} [2018-04-10 00:00:36,632 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,632 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,632 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,632 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,632 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,632 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,632 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,633 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_3|} [2018-04-10 00:00:36,633 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,633 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,633 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,633 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,633 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,633 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,633 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,633 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem2_5|} [2018-04-10 00:00:36,633 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,633 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,633 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,634 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,634 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_4} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6] [2018-04-10 00:00:36,634 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,634 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,634 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,634 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,634 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,635 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,635 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_3|} [2018-04-10 00:00:36,635 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,635 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,635 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,635 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,635 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,635 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,635 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,635 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~mem3_5|} [2018-04-10 00:00:36,636 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,636 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,636 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,636 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,636 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~k~0] [2018-04-10 00:00:36,636 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,636 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,636 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,636 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5 1) InVars {} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0_5} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~found~0] [2018-04-10 00:00:36,636 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,636 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,637 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,637 DEBUG L331 ransitionTransformer]: Formula: (= |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1| v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_1|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_6} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4] [2018-04-10 00:00:36,637 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,637 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,637 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,637 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,637 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,637 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,637 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post6_3|} [2018-04-10 00:00:36,637 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,637 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,638 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,638 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,638 DEBUG L331 ransitionTransformer]: Formula: (= v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7 (+ |v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2| 1)) InVars {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|} OutVars{__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_2|, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0=v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0_7} AuxVars[] AssignedVars[__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_~j~0] [2018-04-10 00:00:36,638 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,638 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,638 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,638 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,639 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,639 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,639 DEBUG L356 ransitionTransformer]: {__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4=|v___U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diff_#t~post4_3|} [2018-04-10 00:00:36,639 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,639 DEBUG L358 ransitionTransformer]: {} [2018-04-10 00:00:36,639 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,639 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,639 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,639 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,640 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,640 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,640 DEBUG L331 ransitionTransformer]: Formula: (= |v_ULTIMATE.start_#t~ret13_2| |v_main_#resOutParam_1|) InVars {main_#res=|v_main_#resOutParam_1|} OutVars{ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|, main_#res=|v_main_#resOutParam_1|} AuxVars[] AssignedVars[ULTIMATE.start_#t~ret13] [2018-04-10 00:00:36,640 DEBUG L354 ransitionTransformer]: outvars have changed [2018-04-10 00:00:36,640 DEBUG L355 ransitionTransformer]: old outvars: [2018-04-10 00:00:36,640 DEBUG L356 ransitionTransformer]: {ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|} [2018-04-10 00:00:36,640 DEBUG L357 ransitionTransformer]: new outvars: [2018-04-10 00:00:36,640 DEBUG L358 ransitionTransformer]: {ULTIMATE.start_#t~ret13=|v_ULTIMATE.start_#t~ret13_2|, main_#res=|v_main_#resOutParam_1|} [2018-04-10 00:00:36,640 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,640 DEBUG L330 ransitionTransformer]: transformed transition [2018-04-10 00:00:36,641 DEBUG L331 ransitionTransformer]: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] [2018-04-10 00:00:36,641 DEBUG L334 ransitionTransformer]: transformula unchanged [2018-04-10 00:00:36,641 DEBUG L360 ransitionTransformer]: [2018-04-10 00:00:36,641 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-10 00:00:36,661 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 10.04 12:00:36 BasicIcfg [2018-04-10 00:00:36,661 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2018-04-10 00:00:36,661 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-10 00:00:36,661 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-10 00:00:36,664 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-10 00:00:36,664 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 09.04 11:59:55" (1/4) ... [2018-04-10 00:00:36,664 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e4b3d9f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.04 12:00:36, skipping insertion in model container [2018-04-10 00:00:36,665 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.04 11:59:55" (2/4) ... [2018-04-10 00:00:36,665 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e4b3d9f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 10.04 12:00:36, skipping insertion in model container [2018-04-10 00:00:36,665 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.04 11:59:56" (3/4) ... [2018-04-10 00:00:36,665 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e4b3d9f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.04 12:00:36, skipping insertion in model container [2018-04-10 00:00:36,665 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 10.04 12:00:36" (4/4) ... [2018-04-10 00:00:36,666 INFO L107 eAbstractionObserver]: Analyzing ICFG memPartitionedIcfg [2018-04-10 00:00:36,673 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-10 00:00:36,680 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 9 error locations. [2018-04-10 00:00:36,710 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-10 00:00:36,711 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-10 00:00:36,711 INFO L370 AbstractCegarLoop]: Hoare is true [2018-04-10 00:00:36,711 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-10 00:00:36,711 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-10 00:00:36,711 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-10 00:00:36,711 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-10 00:00:36,711 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-10 00:00:36,711 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-10 00:00:36,712 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-10 00:00:36,721 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states. [2018-04-10 00:00:36,726 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-10 00:00:36,726 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:36,727 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:36,727 INFO L408 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:36,730 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476875, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:36,743 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:36,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:36,792 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:36,824 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:36,825 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:36,830 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:36,831 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-10 00:00:36,854 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:36,856 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:36,857 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-10 00:00:36,858 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:36,870 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:36,870 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-10 00:00:36,911 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 20 [2018-04-10 00:00:36,912 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:36,922 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:36,922 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:21, output treesize:20 [2018-04-10 00:00:36,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:36,988 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:37,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:37,145 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:37,145 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-10 00:00:37,147 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-10 00:00:37,158 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-10 00:00:37,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-10 00:00:37,161 INFO L87 Difference]: Start difference. First operand 82 states. Second operand 11 states. [2018-04-10 00:00:37,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:37,415 INFO L93 Difference]: Finished difference Result 129 states and 143 transitions. [2018-04-10 00:00:37,421 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-10 00:00:37,422 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-10 00:00:37,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:37,433 INFO L225 Difference]: With dead ends: 129 [2018-04-10 00:00:37,433 INFO L226 Difference]: Without dead ends: 77 [2018-04-10 00:00:37,437 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 64 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-10 00:00:37,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-04-10 00:00:37,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-04-10 00:00:37,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-04-10 00:00:37,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 82 transitions. [2018-04-10 00:00:37,480 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 82 transitions. Word has length 38 [2018-04-10 00:00:37,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:37,481 INFO L459 AbstractCegarLoop]: Abstraction has 77 states and 82 transitions. [2018-04-10 00:00:37,481 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-10 00:00:37,481 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 82 transitions. [2018-04-10 00:00:37,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-10 00:00:37,482 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:37,483 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:37,483 INFO L408 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:37,483 INFO L82 PathProgramCache]: Analyzing trace with hash 2139476876, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:37,491 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:37,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:37,518 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:37,526 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:37,526 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,563 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:37,563 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,571 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,572 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-10 00:00:37,608 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,610 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-10 00:00:37,610 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,626 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,627 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,628 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-10 00:00:37,628 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,645 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:37,645 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:35 [2018-04-10 00:00:37,666 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,667 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,669 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 34 [2018-04-10 00:00:37,669 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,687 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,688 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,689 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:37,689 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-04-10 00:00:37,689 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:37,701 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:37,702 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:48, output treesize:40 [2018-04-10 00:00:37,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:37,847 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:40,148 WARN L148 SmtUtils]: Spent 2036ms on a formula simplification that was a NOOP. DAG size: 41 [2018-04-10 00:00:40,163 INFO L682 Elim1Store]: detected equality via solver [2018-04-10 00:00:40,164 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 30 [2018-04-10 00:00:40,259 INFO L682 Elim1Store]: detected equality via solver [2018-04-10 00:00:40,260 INFO L682 Elim1Store]: detected equality via solver [2018-04-10 00:00:40,260 INFO L682 Elim1Store]: detected equality via solver [2018-04-10 00:00:40,260 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 10 [2018-04-10 00:00:40,261 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,265 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,283 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 24 [2018-04-10 00:00:40,286 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 30 [2018-04-10 00:00:40,308 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 9 [2018-04-10 00:00:40,308 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,312 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,313 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,318 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,319 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 6 variables, input treesize:42, output treesize:5 [2018-04-10 00:00:40,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:40,365 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:40,365 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 9] imperfect sequences [] total 16 [2018-04-10 00:00:40,367 INFO L442 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-04-10 00:00:40,367 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-04-10 00:00:40,367 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=224, Unknown=0, NotChecked=0, Total=272 [2018-04-10 00:00:40,367 INFO L87 Difference]: Start difference. First operand 77 states and 82 transitions. Second operand 17 states. [2018-04-10 00:00:40,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:40,871 INFO L93 Difference]: Finished difference Result 118 states and 131 transitions. [2018-04-10 00:00:40,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-10 00:00:40,871 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 38 [2018-04-10 00:00:40,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:40,875 INFO L225 Difference]: With dead ends: 118 [2018-04-10 00:00:40,875 INFO L226 Difference]: Without dead ends: 116 [2018-04-10 00:00:40,875 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 59 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=112, Invalid=440, Unknown=0, NotChecked=0, Total=552 [2018-04-10 00:00:40,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-04-10 00:00:40,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 86. [2018-04-10 00:00:40,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-10 00:00:40,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 94 transitions. [2018-04-10 00:00:40,886 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 94 transitions. Word has length 38 [2018-04-10 00:00:40,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:40,886 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 94 transitions. [2018-04-10 00:00:40,886 INFO L460 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-04-10 00:00:40,886 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 94 transitions. [2018-04-10 00:00:40,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-10 00:00:40,888 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:40,888 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:40,888 INFO L408 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:40,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273898, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:40,900 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:40,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:40,926 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:40,935 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:40,936 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,937 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,937 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-10 00:00:40,944 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:40,944 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:40,945 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-10 00:00:40,945 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:40,951 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:40,951 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-10 00:00:41,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:41,000 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:41,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:41,066 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:41,067 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6, 6] imperfect sequences [] total 10 [2018-04-10 00:00:41,067 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-10 00:00:41,067 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-10 00:00:41,067 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-10 00:00:41,067 INFO L87 Difference]: Start difference. First operand 86 states and 94 transitions. Second operand 11 states. [2018-04-10 00:00:41,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:41,157 INFO L93 Difference]: Finished difference Result 86 states and 94 transitions. [2018-04-10 00:00:41,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-10 00:00:41,157 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 39 [2018-04-10 00:00:41,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:41,158 INFO L225 Difference]: With dead ends: 86 [2018-04-10 00:00:41,158 INFO L226 Difference]: Without dead ends: 85 [2018-04-10 00:00:41,159 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2018-04-10 00:00:41,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-10 00:00:41,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-10 00:00:41,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-10 00:00:41,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 93 transitions. [2018-04-10 00:00:41,170 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 93 transitions. Word has length 39 [2018-04-10 00:00:41,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:41,170 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 93 transitions. [2018-04-10 00:00:41,170 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-10 00:00:41,170 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 93 transitions. [2018-04-10 00:00:41,171 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-10 00:00:41,171 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:41,171 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:41,171 INFO L408 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:41,171 INFO L82 PathProgramCache]: Analyzing trace with hash 1899273899, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:41,183 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:41,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:41,205 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:41,214 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:41,215 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:41,221 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:41,221 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:41,226 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:41,226 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:19 [2018-04-10 00:00:41,245 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:41,245 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:41,246 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-10 00:00:41,246 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:41,254 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-10 00:00:41,254 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:41,261 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:41,261 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:32, output treesize:25 [2018-04-10 00:00:41,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:41,350 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:43,703 WARN L148 SmtUtils]: Spent 2282ms on a formula simplification that was a NOOP. DAG size: 26 [2018-04-10 00:00:43,746 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 3 [2018-04-10 00:00:43,746 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:43,757 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 19 [2018-04-10 00:00:43,771 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 5 [2018-04-10 00:00:43,771 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:43,771 WARN L307 Elim1Store]: Array PQE input equivalent to true [2018-04-10 00:00:43,772 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:43,775 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:43,777 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:43,778 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:25, output treesize:5 [2018-04-10 00:00:43,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:43,805 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:43,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 14 [2018-04-10 00:00:43,805 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-10 00:00:43,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-10 00:00:43,806 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=174, Unknown=0, NotChecked=0, Total=210 [2018-04-10 00:00:43,806 INFO L87 Difference]: Start difference. First operand 85 states and 93 transitions. Second operand 15 states. [2018-04-10 00:00:44,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:44,181 INFO L93 Difference]: Finished difference Result 136 states and 152 transitions. [2018-04-10 00:00:44,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-10 00:00:44,181 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 39 [2018-04-10 00:00:44,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:44,183 INFO L225 Difference]: With dead ends: 136 [2018-04-10 00:00:44,183 INFO L226 Difference]: Without dead ends: 135 [2018-04-10 00:00:44,183 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 63 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=91, Invalid=371, Unknown=0, NotChecked=0, Total=462 [2018-04-10 00:00:44,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-04-10 00:00:44,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 89. [2018-04-10 00:00:44,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-10 00:00:44,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 98 transitions. [2018-04-10 00:00:44,192 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 98 transitions. Word has length 39 [2018-04-10 00:00:44,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:44,192 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 98 transitions. [2018-04-10 00:00:44,192 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-10 00:00:44,192 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 98 transitions. [2018-04-10 00:00:44,193 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-04-10 00:00:44,193 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:44,193 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:44,193 INFO L408 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:44,193 INFO L82 PathProgramCache]: Analyzing trace with hash -1252082927, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:44,200 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:44,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:44,218 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:44,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:44,244 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:44,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:44,290 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:44,290 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8, 8] imperfect sequences [] total 10 [2018-04-10 00:00:44,291 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-10 00:00:44,291 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-10 00:00:44,291 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-04-10 00:00:44,291 INFO L87 Difference]: Start difference. First operand 89 states and 98 transitions. Second operand 10 states. [2018-04-10 00:00:44,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:44,428 INFO L93 Difference]: Finished difference Result 203 states and 226 transitions. [2018-04-10 00:00:44,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-10 00:00:44,428 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 40 [2018-04-10 00:00:44,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:44,430 INFO L225 Difference]: With dead ends: 203 [2018-04-10 00:00:44,430 INFO L226 Difference]: Without dead ends: 151 [2018-04-10 00:00:44,430 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 67 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=76, Invalid=164, Unknown=0, NotChecked=0, Total=240 [2018-04-10 00:00:44,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-04-10 00:00:44,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 88. [2018-04-10 00:00:44,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-10 00:00:44,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 95 transitions. [2018-04-10 00:00:44,440 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 95 transitions. Word has length 40 [2018-04-10 00:00:44,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:44,440 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 95 transitions. [2018-04-10 00:00:44,440 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-10 00:00:44,440 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 95 transitions. [2018-04-10 00:00:44,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-04-10 00:00:44,441 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:44,441 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:44,441 INFO L408 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:44,441 INFO L82 PathProgramCache]: Analyzing trace with hash -1717465618, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:44,447 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:44,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:44,469 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:44,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:44,502 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:44,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:44,580 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:44,580 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 10 [2018-04-10 00:00:44,580 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-10 00:00:44,580 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-10 00:00:44,580 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=65, Unknown=0, NotChecked=0, Total=90 [2018-04-10 00:00:44,581 INFO L87 Difference]: Start difference. First operand 88 states and 95 transitions. Second operand 10 states. [2018-04-10 00:00:44,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:44,734 INFO L93 Difference]: Finished difference Result 128 states and 138 transitions. [2018-04-10 00:00:44,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-10 00:00:44,734 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 43 [2018-04-10 00:00:44,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:44,736 INFO L225 Difference]: With dead ends: 128 [2018-04-10 00:00:44,736 INFO L226 Difference]: Without dead ends: 117 [2018-04-10 00:00:44,736 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 74 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=50, Invalid=106, Unknown=0, NotChecked=0, Total=156 [2018-04-10 00:00:44,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-10 00:00:44,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 88. [2018-04-10 00:00:44,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-10 00:00:44,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 94 transitions. [2018-04-10 00:00:44,750 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 94 transitions. Word has length 43 [2018-04-10 00:00:44,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:44,750 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 94 transitions. [2018-04-10 00:00:44,750 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-10 00:00:44,750 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 94 transitions. [2018-04-10 00:00:44,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-04-10 00:00:44,752 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:44,752 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:44,752 INFO L408 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:44,752 INFO L82 PathProgramCache]: Analyzing trace with hash 29055424, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:44,767 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:44,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:44,792 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:44,846 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:44,847 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:44,863 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:44,884 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:44,885 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [] total 3 [2018-04-10 00:00:44,885 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-10 00:00:44,885 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-10 00:00:44,885 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-10 00:00:44,885 INFO L87 Difference]: Start difference. First operand 88 states and 94 transitions. Second operand 3 states. [2018-04-10 00:00:44,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:44,901 INFO L93 Difference]: Finished difference Result 147 states and 159 transitions. [2018-04-10 00:00:44,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-10 00:00:44,902 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 48 [2018-04-10 00:00:44,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:44,903 INFO L225 Difference]: With dead ends: 147 [2018-04-10 00:00:44,903 INFO L226 Difference]: Without dead ends: 98 [2018-04-10 00:00:44,904 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 93 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-10 00:00:44,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-10 00:00:44,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 89. [2018-04-10 00:00:44,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-04-10 00:00:44,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 94 transitions. [2018-04-10 00:00:44,931 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 94 transitions. Word has length 48 [2018-04-10 00:00:44,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:44,931 INFO L459 AbstractCegarLoop]: Abstraction has 89 states and 94 transitions. [2018-04-10 00:00:44,931 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-10 00:00:44,931 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 94 transitions. [2018-04-10 00:00:44,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-04-10 00:00:44,932 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:44,932 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:44,932 INFO L408 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:44,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1793713475, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:44,938 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:44,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:44,960 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:44,965 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:44,965 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:44,971 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:44,971 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:44,975 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:44,975 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-10 00:00:44,989 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:44,989 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:44,990 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-10 00:00:44,990 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:44,997 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-10 00:00:44,997 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:45,002 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:45,002 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-10 00:00:45,263 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:45,263 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:45,810 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-10 00:00:45,832 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:00:45,832 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 23 [2018-04-10 00:00:45,832 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-10 00:00:45,833 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-10 00:00:45,833 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=484, Unknown=0, NotChecked=0, Total=552 [2018-04-10 00:00:45,833 INFO L87 Difference]: Start difference. First operand 89 states and 94 transitions. Second operand 24 states. [2018-04-10 00:00:47,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:47,252 INFO L93 Difference]: Finished difference Result 147 states and 157 transitions. [2018-04-10 00:00:47,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-10 00:00:47,252 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 49 [2018-04-10 00:00:47,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:47,253 INFO L225 Difference]: With dead ends: 147 [2018-04-10 00:00:47,253 INFO L226 Difference]: Without dead ends: 146 [2018-04-10 00:00:47,254 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=249, Invalid=1083, Unknown=0, NotChecked=0, Total=1332 [2018-04-10 00:00:47,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-04-10 00:00:47,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 86. [2018-04-10 00:00:47,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-10 00:00:47,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 91 transitions. [2018-04-10 00:00:47,267 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 91 transitions. Word has length 49 [2018-04-10 00:00:47,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:47,267 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 91 transitions. [2018-04-10 00:00:47,267 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-10 00:00:47,268 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 91 transitions. [2018-04-10 00:00:47,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-10 00:00:47,269 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:47,269 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:47,269 INFO L408 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:47,269 INFO L82 PathProgramCache]: Analyzing trace with hash 229425471, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:47,279 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:47,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:47,300 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:47,313 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:47,314 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,315 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,315 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-10 00:00:47,351 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-10 00:00:47,351 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:47,357 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-10 00:00:47,379 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:47,379 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5, 5] imperfect sequences [] total 5 [2018-04-10 00:00:47,379 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-10 00:00:47,379 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-10 00:00:47,380 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-10 00:00:47,380 INFO L87 Difference]: Start difference. First operand 86 states and 91 transitions. Second operand 6 states. [2018-04-10 00:00:47,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:47,454 INFO L93 Difference]: Finished difference Result 86 states and 91 transitions. [2018-04-10 00:00:47,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-10 00:00:47,455 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 50 [2018-04-10 00:00:47,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:47,455 INFO L225 Difference]: With dead ends: 86 [2018-04-10 00:00:47,455 INFO L226 Difference]: Without dead ends: 85 [2018-04-10 00:00:47,456 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 101 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-04-10 00:00:47,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-10 00:00:47,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-10 00:00:47,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-10 00:00:47,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 90 transitions. [2018-04-10 00:00:47,465 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 90 transitions. Word has length 50 [2018-04-10 00:00:47,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:47,465 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 90 transitions. [2018-04-10 00:00:47,465 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-10 00:00:47,465 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 90 transitions. [2018-04-10 00:00:47,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-04-10 00:00:47,466 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:47,466 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:47,466 INFO L408 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:47,466 INFO L82 PathProgramCache]: Analyzing trace with hash 229425472, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:47,478 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:47,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:47,504 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:47,518 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:47,519 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,525 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:47,525 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:15, output treesize:14 [2018-04-10 00:00:47,612 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-10 00:00:47,612 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:47,688 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-10 00:00:47,710 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:47,710 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7, 7] imperfect sequences [] total 12 [2018-04-10 00:00:47,710 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-10 00:00:47,710 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-10 00:00:47,710 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-04-10 00:00:47,711 INFO L87 Difference]: Start difference. First operand 85 states and 90 transitions. Second operand 13 states. [2018-04-10 00:00:47,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:47,866 INFO L93 Difference]: Finished difference Result 121 states and 130 transitions. [2018-04-10 00:00:47,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-10 00:00:47,866 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 50 [2018-04-10 00:00:47,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:47,867 INFO L225 Difference]: With dead ends: 121 [2018-04-10 00:00:47,867 INFO L226 Difference]: Without dead ends: 120 [2018-04-10 00:00:47,867 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 87 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=239, Unknown=0, NotChecked=0, Total=306 [2018-04-10 00:00:47,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-04-10 00:00:47,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 114. [2018-04-10 00:00:47,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-10 00:00:47,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-04-10 00:00:47,880 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 50 [2018-04-10 00:00:47,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:47,880 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-04-10 00:00:47,880 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-10 00:00:47,880 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-04-10 00:00:47,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-04-10 00:00:47,881 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:47,881 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:47,881 INFO L408 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:47,881 INFO L82 PathProgramCache]: Analyzing trace with hash -72993622, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:47,886 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:47,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:47,906 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:47,909 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:47,909 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,914 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-10 00:00:47,914 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,918 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,918 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-10 00:00:47,932 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:47,932 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:47,933 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-10 00:00:47,933 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,940 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-10 00:00:47,940 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:47,946 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:47,946 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:29, output treesize:22 [2018-04-10 00:00:47,971 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 23 treesize of output 30 [2018-04-10 00:00:47,971 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 2 xjuncts. [2018-04-10 00:00:47,991 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-04-10 00:00:47,991 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 4 variables, input treesize:30, output treesize:52 [2018-04-10 00:00:48,227 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-10 00:00:48,227 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:49,276 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-10 00:00:49,297 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:00:49,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13] total 24 [2018-04-10 00:00:49,297 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-10 00:00:49,298 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-10 00:00:49,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=531, Unknown=1, NotChecked=0, Total=600 [2018-04-10 00:00:49,298 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 25 states. [2018-04-10 00:00:50,723 WARN L151 SmtUtils]: Spent 1350ms on a formula simplification. DAG size of input: 65 DAG size of output 60 [2018-04-10 00:00:51,463 WARN L151 SmtUtils]: Spent 445ms on a formula simplification. DAG size of input: 60 DAG size of output 50 [2018-04-10 00:00:52,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:52,306 INFO L93 Difference]: Finished difference Result 145 states and 159 transitions. [2018-04-10 00:00:52,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-10 00:00:52,306 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 56 [2018-04-10 00:00:52,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:52,307 INFO L225 Difference]: With dead ends: 145 [2018-04-10 00:00:52,307 INFO L226 Difference]: Without dead ends: 144 [2018-04-10 00:00:52,307 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 124 GetRequests, 88 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 143 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=231, Invalid=1100, Unknown=1, NotChecked=0, Total=1332 [2018-04-10 00:00:52,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-04-10 00:00:52,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 107. [2018-04-10 00:00:52,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-04-10 00:00:52,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 116 transitions. [2018-04-10 00:00:52,321 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 116 transitions. Word has length 56 [2018-04-10 00:00:52,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:52,321 INFO L459 AbstractCegarLoop]: Abstraction has 107 states and 116 transitions. [2018-04-10 00:00:52,321 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-10 00:00:52,321 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 116 transitions. [2018-04-10 00:00:52,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-10 00:00:52,322 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:52,322 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:52,322 INFO L408 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:52,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1791438736, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:52,334 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:52,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:52,352 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:52,388 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:52,389 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-10 00:00:52,409 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:52,409 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:52,410 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 42 [2018-04-10 00:00:52,412 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 34 [2018-04-10 00:00:52,413 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:52,421 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:52,428 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:52,436 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:52,436 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-10 00:00:52,511 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:52,516 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:52,528 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:52,528 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:52,583 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_20| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_20| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_20|))))) is different from false [2018-04-10 00:00:52,587 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_20| Int) (|v_main_#t~malloc11.base_19| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_19| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_19|))) (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_20| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_19| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= 0 (select .cse0 |v_main_#t~malloc12.base_20|)))))) is different from false [2018-04-10 00:00:52,591 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_20| Int) (|v_main_#t~malloc10.base_17| Int) (|v_main_#t~malloc11.base_19| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_17| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_19| 1))) (or (not (= (select |c_#valid| |v_main_#t~malloc10.base_17|) 0)) (not (= (select .cse0 |v_main_#t~malloc11.base_19|) 0)) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_20| 1) |v_main_#t~malloc10.base_17| 0) |v_main_#t~malloc11.base_19| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= (select .cse1 |v_main_#t~malloc12.base_20|) 0)))))) is different from false [2018-04-10 00:00:52,607 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:52,629 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:52,629 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-10 00:00:52,629 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-10 00:00:52,629 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-10 00:00:52,630 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-10 00:00:52,630 INFO L87 Difference]: Start difference. First operand 107 states and 116 transitions. Second operand 16 states. [2018-04-10 00:00:52,649 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc12.base_20| Int) (|v_main_#t~malloc10.base_17| Int) (|v_main_#t~malloc11.base_19| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_17| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_19| 1))) (or (not (= (select |c_#valid| |v_main_#t~malloc10.base_17|) 0)) (not (= (select .cse0 |v_main_#t~malloc11.base_19|) 0)) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_20| 1) |v_main_#t~malloc10.base_17| 0) |v_main_#t~malloc11.base_19| 0) |v_main_#t~malloc12.base_20| 0) |c_old(#valid)|) (not (= (select .cse1 |v_main_#t~malloc12.base_20|) 0))))))) is different from false [2018-04-10 00:00:53,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:53,170 INFO L93 Difference]: Finished difference Result 199 states and 216 transitions. [2018-04-10 00:00:53,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-10 00:00:53,170 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-04-10 00:00:53,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:53,171 INFO L225 Difference]: With dead ends: 199 [2018-04-10 00:00:53,171 INFO L226 Difference]: Without dead ends: 188 [2018-04-10 00:00:53,172 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 129 GetRequests, 107 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=171, Unknown=9, NotChecked=186, Total=420 [2018-04-10 00:00:53,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-04-10 00:00:53,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 185. [2018-04-10 00:00:53,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-04-10 00:00:53,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 202 transitions. [2018-04-10 00:00:53,200 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 202 transitions. Word has length 61 [2018-04-10 00:00:53,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:53,200 INFO L459 AbstractCegarLoop]: Abstraction has 185 states and 202 transitions. [2018-04-10 00:00:53,200 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-10 00:00:53,201 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 202 transitions. [2018-04-10 00:00:53,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-10 00:00:53,201 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:53,201 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:53,201 INFO L408 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:53,201 INFO L82 PathProgramCache]: Analyzing trace with hash -1032331687, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:53,209 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:53,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:53,230 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:53,262 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:53,263 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-10 00:00:53,278 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:53,279 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:53,279 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-10 00:00:53,281 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-10 00:00:53,282 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:53,288 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:53,293 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:53,299 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:53,300 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-10 00:00:53,363 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:53,367 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:53,387 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:53,387 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:53,429 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_21| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_21| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_21| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_21|))))) is different from false [2018-04-10 00:00:53,437 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_20| Int) (|v_main_#t~malloc12.base_21| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_20| 1))) (or (not (= (select .cse0 |v_main_#t~malloc12.base_21|) 0)) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_21| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_20| 0) |v_main_#t~malloc12.base_21| 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_20|)))))) is different from false [2018-04-10 00:00:53,441 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_20| Int) (|v_main_#t~malloc10.base_18| Int) (|v_main_#t~malloc12.base_21| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_18| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_20| 1))) (or (not (= (select .cse0 |v_main_#t~malloc11.base_20|) 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_18|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_21| 1) |v_main_#t~malloc10.base_18| 0) |v_main_#t~malloc11.base_20| 0) |v_main_#t~malloc12.base_21| 0) |c_old(#valid)|) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_21|))))))) is different from false [2018-04-10 00:00:53,463 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:53,484 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:53,484 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-10 00:00:53,485 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-10 00:00:53,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-10 00:00:53,485 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-10 00:00:53,485 INFO L87 Difference]: Start difference. First operand 185 states and 202 transitions. Second operand 16 states. [2018-04-10 00:00:53,512 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc11.base_20| Int) (|v_main_#t~malloc10.base_18| Int) (|v_main_#t~malloc12.base_21| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_18| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_20| 1))) (or (not (= (select .cse0 |v_main_#t~malloc11.base_20|) 0)) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_18|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_21| 1) |v_main_#t~malloc10.base_18| 0) |v_main_#t~malloc11.base_20| 0) |v_main_#t~malloc12.base_21| 0) |c_old(#valid)|) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_21|))))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-10 00:00:56,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:56,169 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-10 00:00:56,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-10 00:00:56,170 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-10 00:00:56,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:56,171 INFO L225 Difference]: With dead ends: 277 [2018-04-10 00:00:56,171 INFO L226 Difference]: Without dead ends: 266 [2018-04-10 00:00:56,172 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=171, Unknown=9, NotChecked=186, Total=420 [2018-04-10 00:00:56,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-10 00:00:56,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-10 00:00:56,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-10 00:00:56,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-10 00:00:56,202 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-10 00:00:56,202 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:56,203 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-10 00:00:56,203 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-10 00:00:56,203 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-10 00:00:56,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-04-10 00:00:56,203 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:56,203 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:56,203 INFO L408 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:56,204 INFO L82 PathProgramCache]: Analyzing trace with hash -1753613222, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:56,210 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:56,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:56,227 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:56,262 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:56,263 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 32 [2018-04-10 00:00:56,282 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:56,282 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:56,283 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-10 00:00:56,285 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-10 00:00:56,286 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:56,293 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:56,298 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:56,318 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:56,319 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-10 00:00:56,364 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:56,367 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:56,379 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:56,380 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:56,412 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_22| Int)) (or (= (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_22| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_22|))))) is different from false [2018-04-10 00:00:56,416 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_21|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_22| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0)) (not (= (select .cse0 |v_main_#t~malloc12.base_22|) 0))))) is different from false [2018-04-10 00:00:56,419 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc10.base_19| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_19| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_21|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_22| 1) |v_main_#t~malloc10.base_19| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_19|))) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_22|))))))) is different from false [2018-04-10 00:00:56,433 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:56,453 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:56,454 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-10 00:00:56,454 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-10 00:00:56,454 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-10 00:00:56,454 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-10 00:00:56,454 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-10 00:00:56,468 WARN L1011 $PredicateComparison]: unable to prove that (and (= |c_#valid| |c_old(#valid)|) (forall ((|v_main_#t~malloc11.base_21| Int) (|v_main_#t~malloc10.base_19| Int) (|v_main_#t~malloc12.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc10.base_19| 1))) (let ((.cse1 (store .cse0 |v_main_#t~malloc11.base_21| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc11.base_21|))) (= (store (store (store (store .cse1 |v_main_#t~malloc12.base_22| 1) |v_main_#t~malloc10.base_19| 0) |v_main_#t~malloc11.base_21| 0) |v_main_#t~malloc12.base_22| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc10.base_19|))) (not (= 0 (select .cse1 |v_main_#t~malloc12.base_22|)))))))) is different from false [2018-04-10 00:00:57,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:57,127 INFO L93 Difference]: Finished difference Result 277 states and 301 transitions. [2018-04-10 00:00:57,127 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-10 00:00:57,127 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-04-10 00:00:57,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:57,129 INFO L225 Difference]: With dead ends: 277 [2018-04-10 00:00:57,129 INFO L226 Difference]: Without dead ends: 266 [2018-04-10 00:00:57,129 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 109 SyntacticMatches, 3 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=54, Invalid=169, Unknown=11, NotChecked=186, Total=420 [2018-04-10 00:00:57,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-04-10 00:00:57,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 186. [2018-04-10 00:00:57,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-04-10 00:00:57,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 203 transitions. [2018-04-10 00:00:57,160 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 203 transitions. Word has length 62 [2018-04-10 00:00:57,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:57,160 INFO L459 AbstractCegarLoop]: Abstraction has 186 states and 203 transitions. [2018-04-10 00:00:57,160 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-10 00:00:57,160 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 203 transitions. [2018-04-10 00:00:57,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-04-10 00:00:57,161 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:57,161 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:57,161 INFO L408 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:57,162 INFO L82 PathProgramCache]: Analyzing trace with hash 740207311, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:57,170 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:57,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:57,191 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:57,225 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:57,226 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-10 00:00:57,243 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:57,244 INFO L700 Elim1Store]: detected not equals via solver [2018-04-10 00:00:57,245 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 40 [2018-04-10 00:00:57,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 34 [2018-04-10 00:00:57,247 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:57,256 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:57,262 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:57,270 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-10 00:00:57,270 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:37, output treesize:28 [2018-04-10 00:00:57,378 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (store (store (store .cse0 |c_main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |c_#valid|) (= (select .cse0 |c_main_#t~malloc12.base|) 0) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:57,383 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|main_#t~malloc11.base| Int) (|main_#t~malloc10.base| Int) (|main_#t~malloc12.base| Int)) (let ((.cse1 (store |c_old(#valid)| |main_#t~malloc10.base| 1))) (let ((.cse0 (store .cse1 |main_#t~malloc11.base| 1))) (and (= 0 (select |c_old(#valid)| |main_#t~malloc10.base|)) (= (select .cse0 |main_#t~malloc12.base|) 0) (= |c_#valid| (store (store (store (store .cse0 |main_#t~malloc12.base| 1) |main_#t~malloc10.base| 0) |main_#t~malloc11.base| 0) |main_#t~malloc12.base| 0)) (= (select .cse1 |main_#t~malloc11.base|) 0))))) is different from true [2018-04-10 00:00:57,404 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:57,404 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:57,466 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_23| Int)) (or (not (= 0 (select |c_#valid| |v_main_#t~malloc12.base_23|))) (= |c_old(#valid)| (store (store (store (store |c_#valid| |v_main_#t~malloc12.base_23| 1) |c_main_#t~malloc10.base| 0) |c_main_#t~malloc11.base| 0) |v_main_#t~malloc12.base_23| 0)))) is different from false [2018-04-10 00:00:57,470 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_23| Int) (|v_main_#t~malloc11.base_22| Int)) (let ((.cse0 (store |c_#valid| |v_main_#t~malloc11.base_22| 1))) (or (= (store (store (store (store .cse0 |v_main_#t~malloc12.base_23| 1) |c_main_#t~malloc10.base| 0) |v_main_#t~malloc11.base_22| 0) |v_main_#t~malloc12.base_23| 0) |c_old(#valid)|) (not (= 0 (select |c_#valid| |v_main_#t~malloc11.base_22|))) (not (= (select .cse0 |v_main_#t~malloc12.base_23|) 0))))) is different from false [2018-04-10 00:00:57,475 WARN L1011 $PredicateComparison]: unable to prove that (forall ((|v_main_#t~malloc12.base_23| Int) (|v_main_#t~malloc10.base_20| Int) (|v_main_#t~malloc11.base_22| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_20| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_22| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc12.base_23|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_23| 1) |v_main_#t~malloc10.base_20| 0) |v_main_#t~malloc11.base_22| 0) |v_main_#t~malloc12.base_23| 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_22|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_20|) 0)))))) is different from false [2018-04-10 00:00:57,504 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:57,537 INFO L320 seRefinementStrategy]: Constructing automaton from 2 perfect and 0 imperfect interpolant sequences. [2018-04-10 00:00:57,537 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9, 8] imperfect sequences [] total 15 [2018-04-10 00:00:57,538 INFO L442 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-04-10 00:00:57,538 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-04-10 00:00:57,538 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=92, Unknown=6, NotChecked=110, Total=240 [2018-04-10 00:00:57,538 INFO L87 Difference]: Start difference. First operand 186 states and 203 transitions. Second operand 16 states. [2018-04-10 00:00:57,555 WARN L1011 $PredicateComparison]: unable to prove that (and (forall ((|v_main_#t~malloc12.base_23| Int) (|v_main_#t~malloc10.base_20| Int) (|v_main_#t~malloc11.base_22| Int)) (let ((.cse1 (store |c_#valid| |v_main_#t~malloc10.base_20| 1))) (let ((.cse0 (store .cse1 |v_main_#t~malloc11.base_22| 1))) (or (not (= 0 (select .cse0 |v_main_#t~malloc12.base_23|))) (= |c_old(#valid)| (store (store (store (store .cse0 |v_main_#t~malloc12.base_23| 1) |v_main_#t~malloc10.base_20| 0) |v_main_#t~malloc11.base_22| 0) |v_main_#t~malloc12.base_23| 0)) (not (= 0 (select .cse1 |v_main_#t~malloc11.base_22|))) (not (= (select |c_#valid| |v_main_#t~malloc10.base_20|) 0)))))) (= |c_#valid| |c_old(#valid)|)) is different from false [2018-04-10 00:00:58,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:58,140 INFO L93 Difference]: Finished difference Result 187 states and 203 transitions. [2018-04-10 00:00:58,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-10 00:00:58,140 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 63 [2018-04-10 00:00:58,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:58,141 INFO L225 Difference]: With dead ends: 187 [2018-04-10 00:00:58,141 INFO L226 Difference]: Without dead ends: 176 [2018-04-10 00:00:58,142 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 111 SyntacticMatches, 4 SemanticMatches, 19 ConstructedPredicates, 6 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=170, Unknown=10, NotChecked=186, Total=420 [2018-04-10 00:00:58,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-04-10 00:00:58,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 94. [2018-04-10 00:00:58,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-04-10 00:00:58,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 102 transitions. [2018-04-10 00:00:58,160 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 102 transitions. Word has length 63 [2018-04-10 00:00:58,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:58,160 INFO L459 AbstractCegarLoop]: Abstraction has 94 states and 102 transitions. [2018-04-10 00:00:58,160 INFO L460 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-04-10 00:00:58,160 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 102 transitions. [2018-04-10 00:00:58,160 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-04-10 00:00:58,161 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:58,161 INFO L355 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:58,161 INFO L408 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:58,161 INFO L82 PathProgramCache]: Analyzing trace with hash -452021334, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:58,166 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:58,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:58,189 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:58,192 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:58,192 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:58,195 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:58,195 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:00:58,436 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:58,437 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:00:58,744 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-10 00:00:58,765 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:00:58,765 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 27 [2018-04-10 00:00:58,766 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-10 00:00:58,766 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-10 00:00:58,766 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=671, Unknown=0, NotChecked=0, Total=756 [2018-04-10 00:00:58,766 INFO L87 Difference]: Start difference. First operand 94 states and 102 transitions. Second operand 28 states. [2018-04-10 00:00:59,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:00:59,870 INFO L93 Difference]: Finished difference Result 202 states and 221 transitions. [2018-04-10 00:00:59,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-10 00:00:59,870 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 76 [2018-04-10 00:00:59,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:00:59,872 INFO L225 Difference]: With dead ends: 202 [2018-04-10 00:00:59,872 INFO L226 Difference]: Without dead ends: 201 [2018-04-10 00:00:59,873 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 126 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 284 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=402, Invalid=1760, Unknown=0, NotChecked=0, Total=2162 [2018-04-10 00:00:59,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-04-10 00:00:59,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 149. [2018-04-10 00:00:59,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-04-10 00:00:59,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 163 transitions. [2018-04-10 00:00:59,921 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 163 transitions. Word has length 76 [2018-04-10 00:00:59,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:00:59,921 INFO L459 AbstractCegarLoop]: Abstraction has 149 states and 163 transitions. [2018-04-10 00:00:59,921 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-10 00:00:59,922 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 163 transitions. [2018-04-10 00:00:59,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-04-10 00:00:59,923 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:00:59,923 INFO L355 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:00:59,923 INFO L408 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:00:59,923 INFO L82 PathProgramCache]: Analyzing trace with hash 888884808, now seen corresponding path program 1 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:00:59,935 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:00:59,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:00:59,962 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:00:59,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:00:59,964 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:00:59,967 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:00:59,967 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:01:00,219 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-10 00:01:00,219 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:01:00,620 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 16 proven. 42 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-04-10 00:01:00,640 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:01:00,647 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 31 [2018-04-10 00:01:00,647 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-10 00:01:00,647 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-10 00:01:00,647 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=880, Unknown=0, NotChecked=0, Total=992 [2018-04-10 00:01:00,648 INFO L87 Difference]: Start difference. First operand 149 states and 163 transitions. Second operand 32 states. [2018-04-10 00:01:02,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:01:02,145 INFO L93 Difference]: Finished difference Result 268 states and 293 transitions. [2018-04-10 00:01:02,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-10 00:01:02,145 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 94 [2018-04-10 00:01:02,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:01:02,146 INFO L225 Difference]: With dead ends: 268 [2018-04-10 00:01:02,146 INFO L226 Difference]: Without dead ends: 267 [2018-04-10 00:01:02,147 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 158 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 360 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=532, Invalid=2224, Unknown=0, NotChecked=0, Total=2756 [2018-04-10 00:01:02,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-04-10 00:01:02,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 158. [2018-04-10 00:01:02,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-04-10 00:01:02,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 172 transitions. [2018-04-10 00:01:02,185 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 172 transitions. Word has length 94 [2018-04-10 00:01:02,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:01:02,185 INFO L459 AbstractCegarLoop]: Abstraction has 158 states and 172 transitions. [2018-04-10 00:01:02,185 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-10 00:01:02,186 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 172 transitions. [2018-04-10 00:01:02,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-04-10 00:01:02,186 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:01:02,187 INFO L355 BasicCegarLoop]: trace histogram [8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:01:02,187 INFO L408 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:01:02,187 INFO L82 PathProgramCache]: Analyzing trace with hash 1100056318, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:01:02,195 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:01:02,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:01:02,229 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:01:02,232 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:01:02,232 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:01:02,262 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:01:02,262 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:01:02,719 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-10 00:01:02,719 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:01:03,662 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 159 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-10 00:01:03,695 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:01:03,695 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 43 [2018-04-10 00:01:03,696 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-10 00:01:03,696 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-10 00:01:03,697 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1725, Unknown=0, NotChecked=0, Total=1892 [2018-04-10 00:01:03,697 INFO L87 Difference]: Start difference. First operand 158 states and 172 transitions. Second operand 44 states. [2018-04-10 00:01:04,666 WARN L151 SmtUtils]: Spent 344ms on a formula simplification. DAG size of input: 60 DAG size of output 58 [2018-04-10 00:01:05,725 WARN L148 SmtUtils]: Spent 109ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-10 00:01:06,569 WARN L148 SmtUtils]: Spent 231ms on a formula simplification that was a NOOP. DAG size: 56 [2018-04-10 00:01:07,979 WARN L151 SmtUtils]: Spent 465ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-10 00:01:08,521 WARN L151 SmtUtils]: Spent 480ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-10 00:01:08,809 WARN L148 SmtUtils]: Spent 232ms on a formula simplification that was a NOOP. DAG size: 65 [2018-04-10 00:01:09,186 WARN L148 SmtUtils]: Spent 325ms on a formula simplification that was a NOOP. DAG size: 59 [2018-04-10 00:01:10,030 WARN L151 SmtUtils]: Spent 753ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-10 00:01:10,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:01:10,052 INFO L93 Difference]: Finished difference Result 421 states and 460 transitions. [2018-04-10 00:01:10,053 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-10 00:01:10,053 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 128 [2018-04-10 00:01:10,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:01:10,054 INFO L225 Difference]: With dead ends: 421 [2018-04-10 00:01:10,054 INFO L226 Difference]: Without dead ends: 420 [2018-04-10 00:01:10,056 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 297 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1207 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=1221, Invalid=5919, Unknown=0, NotChecked=0, Total=7140 [2018-04-10 00:01:10,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 420 states. [2018-04-10 00:01:10,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 420 to 277. [2018-04-10 00:01:10,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-04-10 00:01:10,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 303 transitions. [2018-04-10 00:01:10,135 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 303 transitions. Word has length 128 [2018-04-10 00:01:10,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:01:10,136 INFO L459 AbstractCegarLoop]: Abstraction has 277 states and 303 transitions. [2018-04-10 00:01:10,136 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-10 00:01:10,136 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 303 transitions. [2018-04-10 00:01:10,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-04-10 00:01:10,137 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:01:10,137 INFO L355 BasicCegarLoop]: trace histogram [10, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:01:10,137 INFO L408 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:01:10,137 INFO L82 PathProgramCache]: Analyzing trace with hash 746499740, now seen corresponding path program 2 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:01:10,145 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:01:10,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:01:10,188 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:01:10,191 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:01:10,191 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:01:10,194 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:01:10,194 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:01:10,769 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-10 00:01:10,770 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:01:11,683 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 16 proven. 216 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-10 00:01:11,705 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:01:11,705 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 47 [2018-04-10 00:01:11,706 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-04-10 00:01:11,706 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-04-10 00:01:11,706 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=2042, Unknown=0, NotChecked=0, Total=2256 [2018-04-10 00:01:11,707 INFO L87 Difference]: Start difference. First operand 277 states and 303 transitions. Second operand 48 states. [2018-04-10 00:01:12,826 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-10 00:01:13,211 WARN L148 SmtUtils]: Spent 225ms on a formula simplification that was a NOOP. DAG size: 59 [2018-04-10 00:01:13,497 WARN L151 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 79 DAG size of output 65 [2018-04-10 00:01:14,616 WARN L151 SmtUtils]: Spent 775ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-10 00:01:15,269 WARN L151 SmtUtils]: Spent 587ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-10 00:01:15,941 WARN L151 SmtUtils]: Spent 140ms on a formula simplification. DAG size of input: 77 DAG size of output 65 [2018-04-10 00:01:16,757 WARN L148 SmtUtils]: Spent 413ms on a formula simplification that was a NOOP. DAG size: 56 [2018-04-10 00:01:17,361 WARN L151 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 76 DAG size of output 64 [2018-04-10 00:01:17,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:01:17,905 INFO L93 Difference]: Finished difference Result 554 states and 605 transitions. [2018-04-10 00:01:17,905 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-10 00:01:17,905 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-04-10 00:01:17,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:01:17,907 INFO L225 Difference]: With dead ends: 554 [2018-04-10 00:01:17,907 INFO L226 Difference]: Without dead ends: 553 [2018-04-10 00:01:17,909 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 333 GetRequests, 246 SyntacticMatches, 0 SemanticMatches, 87 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1353 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=1402, Invalid=6430, Unknown=0, NotChecked=0, Total=7832 [2018-04-10 00:01:17,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2018-04-10 00:01:17,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 286. [2018-04-10 00:01:17,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 286 states. [2018-04-10 00:01:17,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 286 states to 286 states and 312 transitions. [2018-04-10 00:01:17,997 INFO L78 Accepts]: Start accepts. Automaton has 286 states and 312 transitions. Word has length 146 [2018-04-10 00:01:17,998 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:01:17,998 INFO L459 AbstractCegarLoop]: Abstraction has 286 states and 312 transitions. [2018-04-10 00:01:17,998 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-04-10 00:01:17,998 INFO L276 IsEmpty]: Start isEmpty. Operand 286 states and 312 transitions. [2018-04-10 00:01:17,999 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-04-10 00:01:17,999 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:01:17,999 INFO L355 BasicCegarLoop]: trace histogram [16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:01:17,999 INFO L408 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:01:17,999 INFO L82 PathProgramCache]: Analyzing trace with hash -1895798874, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:01:18,005 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:01:18,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:01:18,058 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:01:18,060 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:01:18,061 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:01:18,063 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:01:18,063 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:01:19,339 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-10 00:01:19,339 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:01:21,610 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 791 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-04-10 00:01:21,631 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:01:21,631 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 75 [2018-04-10 00:01:21,631 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-04-10 00:01:21,632 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-04-10 00:01:21,633 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=451, Invalid=5249, Unknown=0, NotChecked=0, Total=5700 [2018-04-10 00:01:21,633 INFO L87 Difference]: Start difference. First operand 286 states and 312 transitions. Second operand 76 states. [2018-04-10 00:01:22,896 WARN L151 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 107 DAG size of output 101 [2018-04-10 00:01:23,930 WARN L151 SmtUtils]: Spent 280ms on a formula simplification. DAG size of input: 140 DAG size of output 124 [2018-04-10 00:01:24,833 WARN L151 SmtUtils]: Spent 764ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-10 00:01:25,896 WARN L151 SmtUtils]: Spent 952ms on a formula simplification. DAG size of input: 136 DAG size of output 126 [2018-04-10 00:01:27,706 WARN L151 SmtUtils]: Spent 741ms on a formula simplification. DAG size of input: 123 DAG size of output 115 [2018-04-10 00:01:27,942 WARN L151 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-10 00:01:28,281 WARN L151 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 119 DAG size of output 111 [2018-04-10 00:01:29,875 WARN L151 SmtUtils]: Spent 534ms on a formula simplification. DAG size of input: 106 DAG size of output 100 [2018-04-10 00:01:30,116 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-10 00:01:30,484 WARN L151 SmtUtils]: Spent 259ms on a formula simplification. DAG size of input: 102 DAG size of output 96 [2018-04-10 00:01:31,613 WARN L151 SmtUtils]: Spent 140ms on a formula simplification. DAG size of input: 89 DAG size of output 85 [2018-04-10 00:01:32,522 WARN L151 SmtUtils]: Spent 805ms on a formula simplification. DAG size of input: 75 DAG size of output 67 [2018-04-10 00:01:33,159 WARN L151 SmtUtils]: Spent 531ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-10 00:01:33,777 WARN L148 SmtUtils]: Spent 345ms on a formula simplification that was a NOOP. DAG size: 59 [2018-04-10 00:01:35,143 WARN L151 SmtUtils]: Spent 707ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-10 00:01:35,535 WARN L151 SmtUtils]: Spent 277ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-10 00:01:36,081 WARN L148 SmtUtils]: Spent 260ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-10 00:01:37,289 WARN L148 SmtUtils]: Spent 413ms on a formula simplification that was a NOOP. DAG size: 56 [2018-04-10 00:01:38,611 WARN L151 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-10 00:01:39,047 WARN L151 SmtUtils]: Spent 277ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-10 00:01:39,809 WARN L151 SmtUtils]: Spent 622ms on a formula simplification. DAG size of input: 152 DAG size of output 140 [2018-04-10 00:01:40,676 WARN L151 SmtUtils]: Spent 266ms on a formula simplification. DAG size of input: 139 DAG size of output 127 [2018-04-10 00:01:40,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:01:40,738 INFO L93 Difference]: Finished difference Result 865 states and 944 transitions. [2018-04-10 00:01:40,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-10 00:01:40,738 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 232 [2018-04-10 00:01:40,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:01:40,742 INFO L225 Difference]: With dead ends: 865 [2018-04-10 00:01:40,742 INFO L226 Difference]: Without dead ends: 864 [2018-04-10 00:01:40,748 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 545 GetRequests, 390 SyntacticMatches, 0 SemanticMatches, 155 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4999 ImplicationChecksByTransitivity, 19.5s TimeCoverageRelationStatistics Valid=3993, Invalid=20499, Unknown=0, NotChecked=0, Total=24492 [2018-04-10 00:01:40,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 864 states. [2018-04-10 00:01:40,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 864 to 533. [2018-04-10 00:01:40,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 533 states. [2018-04-10 00:01:40,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 533 states to 533 states and 583 transitions. [2018-04-10 00:01:40,944 INFO L78 Accepts]: Start accepts. Automaton has 533 states and 583 transitions. Word has length 232 [2018-04-10 00:01:40,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:01:40,944 INFO L459 AbstractCegarLoop]: Abstraction has 533 states and 583 transitions. [2018-04-10 00:01:40,944 INFO L460 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-04-10 00:01:40,944 INFO L276 IsEmpty]: Start isEmpty. Operand 533 states and 583 transitions. [2018-04-10 00:01:40,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 251 [2018-04-10 00:01:40,946 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:01:40,946 INFO L355 BasicCegarLoop]: trace histogram [18, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:01:40,947 INFO L408 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:01:40,947 INFO L82 PathProgramCache]: Analyzing trace with hash 947464516, now seen corresponding path program 3 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:01:40,962 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:01:41,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:01:41,026 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:01:41,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:01:41,029 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:01:41,044 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:01:41,044 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:01:42,380 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-10 00:01:42,380 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:01:44,862 INFO L134 CoverageAnalysis]: Checked inductivity of 958 backedges. 16 proven. 924 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-10 00:01:44,883 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:01:44,883 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 79 [2018-04-10 00:01:44,883 INFO L442 AbstractCegarLoop]: Interpolant automaton has 80 states [2018-04-10 00:01:44,884 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2018-04-10 00:01:44,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=566, Invalid=5754, Unknown=0, NotChecked=0, Total=6320 [2018-04-10 00:01:44,884 INFO L87 Difference]: Start difference. First operand 533 states and 583 transitions. Second operand 80 states. [2018-04-10 00:01:46,086 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 103 DAG size of output 89 [2018-04-10 00:01:46,767 WARN L151 SmtUtils]: Spent 537ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-10 00:01:47,205 WARN L151 SmtUtils]: Spent 316ms on a formula simplification. DAG size of input: 152 DAG size of output 140 [2018-04-10 00:01:48,048 WARN L151 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 114 DAG size of output 92 [2018-04-10 00:01:48,774 WARN L151 SmtUtils]: Spent 266ms on a formula simplification. DAG size of input: 139 DAG size of output 127 [2018-04-10 00:01:49,085 WARN L151 SmtUtils]: Spent 182ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-10 00:01:49,472 WARN L151 SmtUtils]: Spent 274ms on a formula simplification. DAG size of input: 136 DAG size of output 126 [2018-04-10 00:01:50,251 WARN L151 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 112 DAG size of output 92 [2018-04-10 00:01:50,924 WARN L151 SmtUtils]: Spent 222ms on a formula simplification. DAG size of input: 123 DAG size of output 115 [2018-04-10 00:01:51,174 WARN L151 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-10 00:01:51,871 WARN L151 SmtUtils]: Spent 583ms on a formula simplification. DAG size of input: 119 DAG size of output 111 [2018-04-10 00:01:52,687 WARN L151 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-10 00:01:53,499 WARN L151 SmtUtils]: Spent 370ms on a formula simplification. DAG size of input: 106 DAG size of output 100 [2018-04-10 00:01:53,719 WARN L151 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-10 00:01:54,228 WARN L151 SmtUtils]: Spent 397ms on a formula simplification. DAG size of input: 102 DAG size of output 96 [2018-04-10 00:01:54,952 WARN L151 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-10 00:01:55,785 WARN L151 SmtUtils]: Spent 399ms on a formula simplification. DAG size of input: 89 DAG size of output 85 [2018-04-10 00:01:56,909 WARN L151 SmtUtils]: Spent 819ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-10 00:01:57,665 WARN L151 SmtUtils]: Spent 173ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-10 00:01:58,459 WARN L151 SmtUtils]: Spent 364ms on a formula simplification. DAG size of input: 72 DAG size of output 70 [2018-04-10 00:01:59,423 WARN L148 SmtUtils]: Spent 297ms on a formula simplification that was a NOOP. DAG size: 48 [2018-04-10 00:01:59,843 WARN L151 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-10 00:02:01,252 WARN L151 SmtUtils]: Spent 173ms on a formula simplification. DAG size of input: 111 DAG size of output 91 [2018-04-10 00:02:01,917 WARN L151 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 113 DAG size of output 92 [2018-04-10 00:02:02,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:02:02,118 INFO L93 Difference]: Finished difference Result 1126 states and 1229 transitions. [2018-04-10 00:02:02,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2018-04-10 00:02:02,118 INFO L78 Accepts]: Start accepts. Automaton has 80 states. Word has length 250 [2018-04-10 00:02:02,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:02:02,122 INFO L225 Difference]: With dead ends: 1126 [2018-04-10 00:02:02,122 INFO L226 Difference]: Without dead ends: 1125 [2018-04-10 00:02:02,124 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 581 GetRequests, 422 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5391 ImplicationChecksByTransitivity, 17.7s TimeCoverageRelationStatistics Valid=4538, Invalid=21222, Unknown=0, NotChecked=0, Total=25760 [2018-04-10 00:02:02,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1125 states. [2018-04-10 00:02:02,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1125 to 542. [2018-04-10 00:02:02,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 542 states. [2018-04-10 00:02:02,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 542 states to 542 states and 592 transitions. [2018-04-10 00:02:02,341 INFO L78 Accepts]: Start accepts. Automaton has 542 states and 592 transitions. Word has length 250 [2018-04-10 00:02:02,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:02:02,342 INFO L459 AbstractCegarLoop]: Abstraction has 542 states and 592 transitions. [2018-04-10 00:02:02,342 INFO L460 AbstractCegarLoop]: Interpolant automaton has 80 states. [2018-04-10 00:02:02,342 INFO L276 IsEmpty]: Start isEmpty. Operand 542 states and 592 transitions. [2018-04-10 00:02:02,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 441 [2018-04-10 00:02:02,345 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:02:02,346 INFO L355 BasicCegarLoop]: trace histogram [32, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:02:02,346 INFO L408 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:02:02,346 INFO L82 PathProgramCache]: Analyzing trace with hash -760278794, now seen corresponding path program 4 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:02:02,355 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:02:02,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:02:02,472 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:02:02,487 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:02:02,487 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:02:02,499 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:02:02,500 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:02:06,493 INFO L134 CoverageAnalysis]: Checked inductivity of 3527 backedges. 0 proven. 3495 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-10 00:02:06,493 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:02:14,145 INFO L134 CoverageAnalysis]: Checked inductivity of 3527 backedges. 0 proven. 3495 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-10 00:02:14,166 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:02:14,167 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 139 [2018-04-10 00:02:14,167 INFO L442 AbstractCegarLoop]: Interpolant automaton has 140 states [2018-04-10 00:02:14,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 140 interpolants. [2018-04-10 00:02:14,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1499, Invalid=17961, Unknown=0, NotChecked=0, Total=19460 [2018-04-10 00:02:14,168 INFO L87 Difference]: Start difference. First operand 542 states and 592 transitions. Second operand 140 states. [2018-04-10 00:02:15,813 WARN L151 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 162 DAG size of output 132 [2018-04-10 00:02:16,508 WARN L151 SmtUtils]: Spent 445ms on a formula simplification. DAG size of input: 201 DAG size of output 185 [2018-04-10 00:02:18,562 WARN L151 SmtUtils]: Spent 823ms on a formula simplification. DAG size of input: 274 DAG size of output 246 [2018-04-10 00:02:19,410 WARN L151 SmtUtils]: Spent 514ms on a formula simplification. DAG size of input: 227 DAG size of output 175 [2018-04-10 00:02:20,469 WARN L151 SmtUtils]: Spent 778ms on a formula simplification. DAG size of input: 270 DAG size of output 244 [2018-04-10 00:02:20,959 WARN L148 SmtUtils]: Spent 226ms on a formula simplification that was a NOOP. DAG size: 195 [2018-04-10 00:02:21,718 WARN L151 SmtUtils]: Spent 462ms on a formula simplification. DAG size of input: 189 DAG size of output 181 [2018-04-10 00:02:23,518 WARN L151 SmtUtils]: Spent 699ms on a formula simplification. DAG size of input: 257 DAG size of output 225 [2018-04-10 00:02:24,158 WARN L151 SmtUtils]: Spent 357ms on a formula simplification. DAG size of input: 213 DAG size of output 165 [2018-04-10 00:02:25,148 WARN L151 SmtUtils]: Spent 706ms on a formula simplification. DAG size of input: 253 DAG size of output 229 [2018-04-10 00:02:25,600 WARN L148 SmtUtils]: Spent 201ms on a formula simplification that was a NOOP. DAG size: 183 [2018-04-10 00:02:26,672 WARN L151 SmtUtils]: Spent 778ms on a formula simplification. DAG size of input: 177 DAG size of output 169 [2018-04-10 00:02:28,977 WARN L151 SmtUtils]: Spent 1211ms on a formula simplification. DAG size of input: 240 DAG size of output 210 [2018-04-10 00:02:29,635 WARN L151 SmtUtils]: Spent 379ms on a formula simplification. DAG size of input: 199 DAG size of output 155 [2018-04-10 00:02:30,545 WARN L151 SmtUtils]: Spent 626ms on a formula simplification. DAG size of input: 236 DAG size of output 214 [2018-04-10 00:02:30,976 WARN L148 SmtUtils]: Spent 183ms on a formula simplification that was a NOOP. DAG size: 171 [2018-04-10 00:02:31,968 WARN L151 SmtUtils]: Spent 695ms on a formula simplification. DAG size of input: 165 DAG size of output 159 [2018-04-10 00:02:33,722 WARN L151 SmtUtils]: Spent 659ms on a formula simplification. DAG size of input: 223 DAG size of output 197 [2018-04-10 00:02:34,304 WARN L151 SmtUtils]: Spent 297ms on a formula simplification. DAG size of input: 185 DAG size of output 145 [2018-04-10 00:02:35,187 WARN L151 SmtUtils]: Spent 591ms on a formula simplification. DAG size of input: 219 DAG size of output 199 [2018-04-10 00:02:35,613 WARN L148 SmtUtils]: Spent 176ms on a formula simplification that was a NOOP. DAG size: 159 [2018-04-10 00:02:36,584 WARN L151 SmtUtils]: Spent 680ms on a formula simplification. DAG size of input: 153 DAG size of output 149 [2018-04-10 00:02:38,210 WARN L151 SmtUtils]: Spent 512ms on a formula simplification. DAG size of input: 206 DAG size of output 184 [2018-04-10 00:02:38,757 WARN L151 SmtUtils]: Spent 265ms on a formula simplification. DAG size of input: 172 DAG size of output 136 [2018-04-10 00:02:39,933 WARN L151 SmtUtils]: Spent 885ms on a formula simplification. DAG size of input: 203 DAG size of output 185 [2018-04-10 00:02:40,336 WARN L148 SmtUtils]: Spent 156ms on a formula simplification that was a NOOP. DAG size: 148 [2018-04-10 00:02:40,886 WARN L151 SmtUtils]: Spent 264ms on a formula simplification. DAG size of input: 142 DAG size of output 138 [2018-04-10 00:02:42,535 WARN L151 SmtUtils]: Spent 553ms on a formula simplification. DAG size of input: 190 DAG size of output 170 [2018-04-10 00:02:43,048 WARN L151 SmtUtils]: Spent 240ms on a formula simplification. DAG size of input: 158 DAG size of output 126 [2018-04-10 00:02:44,182 WARN L151 SmtUtils]: Spent 845ms on a formula simplification. DAG size of input: 186 DAG size of output 170 [2018-04-10 00:02:44,561 WARN L148 SmtUtils]: Spent 139ms on a formula simplification that was a NOOP. DAG size: 136 [2018-04-10 00:02:45,311 WARN L148 SmtUtils]: Spent 468ms on a formula simplification that was a NOOP. DAG size: 130 [2018-04-10 00:02:47,102 WARN L151 SmtUtils]: Spent 720ms on a formula simplification. DAG size of input: 173 DAG size of output 155 [2018-04-10 00:02:47,587 WARN L151 SmtUtils]: Spent 213ms on a formula simplification. DAG size of input: 144 DAG size of output 116 [2018-04-10 00:02:48,245 WARN L151 SmtUtils]: Spent 372ms on a formula simplification. DAG size of input: 169 DAG size of output 155 [2018-04-10 00:02:48,597 WARN L148 SmtUtils]: Spent 122ms on a formula simplification that was a NOOP. DAG size: 124 [2018-04-10 00:02:49,285 WARN L148 SmtUtils]: Spent 402ms on a formula simplification that was a NOOP. DAG size: 118 [2018-04-10 00:02:51,079 WARN L151 SmtUtils]: Spent 697ms on a formula simplification. DAG size of input: 156 DAG size of output 140 [2018-04-10 00:02:51,540 WARN L151 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 130 DAG size of output 106 [2018-04-10 00:02:52,151 WARN L151 SmtUtils]: Spent 332ms on a formula simplification. DAG size of input: 152 DAG size of output 140 [2018-04-10 00:02:54,952 WARN L151 SmtUtils]: Spent 1008ms on a formula simplification. DAG size of input: 139 DAG size of output 127 [2018-04-10 00:02:55,369 WARN L151 SmtUtils]: Spent 162ms on a formula simplification. DAG size of input: 117 DAG size of output 97 [2018-04-10 00:02:55,924 WARN L151 SmtUtils]: Spent 281ms on a formula simplification. DAG size of input: 136 DAG size of output 126 [2018-04-10 00:02:58,015 WARN L151 SmtUtils]: Spent 352ms on a formula simplification. DAG size of input: 123 DAG size of output 115 [2018-04-10 00:02:58,396 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 103 DAG size of output 87 [2018-04-10 00:02:58,896 WARN L151 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 119 DAG size of output 111 [2018-04-10 00:03:01,354 WARN L151 SmtUtils]: Spent 759ms on a formula simplification. DAG size of input: 106 DAG size of output 100 [2018-04-10 00:03:01,709 WARN L151 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 89 DAG size of output 77 [2018-04-10 00:03:02,146 WARN L151 SmtUtils]: Spent 183ms on a formula simplification. DAG size of input: 102 DAG size of output 96 [2018-04-10 00:03:03,910 WARN L151 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 89 DAG size of output 85 [2018-04-10 00:03:04,589 WARN L151 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 85 DAG size of output 81 [2018-04-10 00:03:07,128 WARN L151 SmtUtils]: Spent 668ms on a formula simplification. DAG size of input: 62 DAG size of output 58 [2018-04-10 00:03:07,839 WARN L151 SmtUtils]: Spent 489ms on a formula simplification. DAG size of input: 69 DAG size of output 67 [2018-04-10 00:03:08,261 WARN L148 SmtUtils]: Spent 227ms on a formula simplification that was a NOOP. DAG size: 54 [2018-04-10 00:03:11,846 WARN L151 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 181 DAG size of output 145 [2018-04-10 00:03:12,701 WARN L151 SmtUtils]: Spent 439ms on a formula simplification. DAG size of input: 240 DAG size of output 184 [2018-04-10 00:03:13,993 WARN L151 SmtUtils]: Spent 881ms on a formula simplification. DAG size of input: 286 DAG size of output 258 [2018-04-10 00:03:14,575 WARN L148 SmtUtils]: Spent 252ms on a formula simplification that was a NOOP. DAG size: 206 [2018-04-10 00:03:15,332 WARN L151 SmtUtils]: Spent 438ms on a formula simplification. DAG size of input: 200 DAG size of output 192 [2018-04-10 00:03:17,323 WARN L151 SmtUtils]: Spent 1521ms on a formula simplification. DAG size of input: 273 DAG size of output 247 [2018-04-10 00:03:17,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-10 00:03:17,500 INFO L93 Difference]: Finished difference Result 1753 states and 1912 transitions. [2018-04-10 00:03:17,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 165 states. [2018-04-10 00:03:17,500 INFO L78 Accepts]: Start accepts. Automaton has 140 states. Word has length 440 [2018-04-10 00:03:17,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-10 00:03:17,507 INFO L225 Difference]: With dead ends: 1753 [2018-04-10 00:03:17,507 INFO L226 Difference]: Without dead ends: 1752 [2018-04-10 00:03:17,510 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1041 GetRequests, 742 SyntacticMatches, 0 SemanticMatches, 299 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20551 ImplicationChecksByTransitivity, 65.4s TimeCoverageRelationStatistics Valid=14433, Invalid=75867, Unknown=0, NotChecked=0, Total=90300 [2018-04-10 00:03:17,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1752 states. [2018-04-10 00:03:17,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1752 to 1045. [2018-04-10 00:03:17,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1045 states. [2018-04-10 00:03:17,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1045 states to 1045 states and 1143 transitions. [2018-04-10 00:03:17,923 INFO L78 Accepts]: Start accepts. Automaton has 1045 states and 1143 transitions. Word has length 440 [2018-04-10 00:03:17,923 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-10 00:03:17,923 INFO L459 AbstractCegarLoop]: Abstraction has 1045 states and 1143 transitions. [2018-04-10 00:03:17,923 INFO L460 AbstractCegarLoop]: Interpolant automaton has 140 states. [2018-04-10 00:03:17,923 INFO L276 IsEmpty]: Start isEmpty. Operand 1045 states and 1143 transitions. [2018-04-10 00:03:17,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 459 [2018-04-10 00:03:17,926 INFO L347 BasicCegarLoop]: Found error trace [2018-04-10 00:03:17,926 INFO L355 BasicCegarLoop]: trace histogram [34, 17, 17, 17, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-10 00:03:17,927 INFO L408 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr4RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr5RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr3RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr0RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr2RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr6RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr1RequiresViolation, __U_MULTI_fdiff_alloca_true_valid_memsafety_true_termination_i__diffErr7RequiresViolation, mainErr0EnsuresViolationMEMORY_LEAK]=== [2018-04-10 00:03:17,927 INFO L82 PathProgramCache]: Analyzing trace with hash 778634900, now seen corresponding path program 4 times No working directory specified, using /storage/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-04-10 00:03:17,933 INFO L68 tionRefinementEngine]: Using refinement strategy FixedRefinementStrategy [2018-04-10 00:03:18,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-10 00:03:18,046 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-10 00:03:18,050 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-10 00:03:18,051 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-10 00:03:18,069 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-10 00:03:18,069 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-10 00:03:22,208 INFO L134 CoverageAnalysis]: Checked inductivity of 3830 backedges. 16 proven. 3780 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-04-10 00:03:22,208 INFO L314 TraceCheckSpWp]: Computing backward predicates... [2018-04-10 00:03:30,215 INFO L134 CoverageAnalysis]: Checked inductivity of 3830 backedges. 16 proven. 3780 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-04-10 00:03:30,236 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-10 00:03:30,237 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 72] total 143 [2018-04-10 00:03:30,237 INFO L442 AbstractCegarLoop]: Interpolant automaton has 144 states [2018-04-10 00:03:30,238 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 144 interpolants. [2018-04-10 00:03:30,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1846, Invalid=18746, Unknown=0, NotChecked=0, Total=20592 [2018-04-10 00:03:30,238 INFO L87 Difference]: Start difference. First operand 1045 states and 1143 transitions. Second operand 144 states. [2018-04-10 00:03:32,289 WARN L151 SmtUtils]: Spent 198ms on a formula simplification. DAG size of input: 173 DAG size of output 143 [2018-04-10 00:03:33,062 WARN L151 SmtUtils]: Spent 446ms on a formula simplification. DAG size of input: 240 DAG size of output 184 [2018-04-10 00:03:34,246 WARN L151 SmtUtils]: Spent 863ms on a formula simplification. DAG size of input: 286 DAG size of output 258 [2018-04-10 00:03:34,778 WARN L148 SmtUtils]: Spent 248ms on a formula simplification that was a NOOP. DAG size: 206 [2018-04-10 00:03:35,465 WARN L151 SmtUtils]: Spent 444ms on a formula simplification. DAG size of input: 200 DAG size of output 192 [2018-04-10 00:03:36,212 WARN L151 SmtUtils]: Spent 295ms on a formula simplification. DAG size of input: 184 DAG size of output 146 [2018-04-10 00:03:38,172 WARN L151 SmtUtils]: Spent 1194ms on a formula simplification. DAG size of input: 273 DAG size of output 247 [2018-04-10 00:03:38,938 WARN L151 SmtUtils]: Spent 450ms on a formula simplification. DAG size of input: 227 DAG size of output 175 [2018-04-10 00:03:40,019 WARN L151 SmtUtils]: Spent 798ms on a formula simplification. DAG size of input: 270 DAG size of output 244 [2018-04-10 00:03:40,504 WARN L148 SmtUtils]: Spent 232ms on a formula simplification that was a NOOP. DAG size: 195 [2018-04-10 00:03:41,149 WARN L151 SmtUtils]: Spent 405ms on a formula simplification. DAG size of input: 189 DAG size of output 181 [2018-04-10 00:03:41,934 WARN L151 SmtUtils]: Spent 302ms on a formula simplification. DAG size of input: 182 DAG size of output 146 Received shutdown request... [2018-04-10 00:03:42,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-10 00:03:42,042 WARN L519 AbstractCegarLoop]: Verification canceled [2018-04-10 00:03:42,044 WARN L197 ceAbstractionStarter]: Timeout [2018-04-10 00:03:42,045 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 10.04 12:03:42 BasicIcfg [2018-04-10 00:03:42,045 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-10 00:03:42,045 INFO L168 Benchmark]: Toolchain (without parser) took 226430.31 ms. Allocated memory was 302.5 MB in the beginning and 667.9 MB in the end (delta: 365.4 MB). Free memory was 239.5 MB in the beginning and 297.6 MB in the end (delta: -58.0 MB). Peak memory consumption was 307.4 MB. Max. memory is 5.3 GB. [2018-04-10 00:03:42,046 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 302.5 MB. Free memory is still 264.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-10 00:03:42,046 INFO L168 Benchmark]: CACSL2BoogieTranslator took 308.01 ms. Allocated memory is still 302.5 MB. Free memory was 239.5 MB in the beginning and 215.6 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. [2018-04-10 00:03:42,046 INFO L168 Benchmark]: Boogie Preprocessor took 50.40 ms. Allocated memory is still 302.5 MB. Free memory was 215.6 MB in the beginning and 212.6 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 5.3 GB. [2018-04-10 00:03:42,046 INFO L168 Benchmark]: RCFGBuilder took 539.95 ms. Allocated memory was 302.5 MB in the beginning and 465.6 MB in the end (delta: 163.1 MB). Free memory was 212.6 MB in the beginning and 398.9 MB in the end (delta: -186.3 MB). Peak memory consumption was 21.0 MB. Max. memory is 5.3 GB. [2018-04-10 00:03:42,047 INFO L168 Benchmark]: IcfgTransformer took 40143.93 ms. Allocated memory was 465.6 MB in the beginning and 1.0 GB in the end (delta: 535.3 MB). Free memory was 398.9 MB in the beginning and 429.5 MB in the end (delta: -30.6 MB). Peak memory consumption was 504.7 MB. Max. memory is 5.3 GB. [2018-04-10 00:03:42,047 INFO L168 Benchmark]: TraceAbstraction took 185383.46 ms. Allocated memory was 1.0 GB in the beginning and 667.9 MB in the end (delta: -332.9 MB). Free memory was 429.5 MB in the beginning and 297.6 MB in the end (delta: 132.0 MB). There was no memory consumed. Max. memory is 5.3 GB. [2018-04-10 00:03:42,049 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 302.5 MB. Free memory is still 264.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 308.01 ms. Allocated memory is still 302.5 MB. Free memory was 239.5 MB in the beginning and 215.6 MB in the end (delta: 23.9 MB). Peak memory consumption was 23.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 50.40 ms. Allocated memory is still 302.5 MB. Free memory was 215.6 MB in the beginning and 212.6 MB in the end (delta: 3.0 MB). Peak memory consumption was 3.0 MB. Max. memory is 5.3 GB. * RCFGBuilder took 539.95 ms. Allocated memory was 302.5 MB in the beginning and 465.6 MB in the end (delta: 163.1 MB). Free memory was 212.6 MB in the beginning and 398.9 MB in the end (delta: -186.3 MB). Peak memory consumption was 21.0 MB. Max. memory is 5.3 GB. * IcfgTransformer took 40143.93 ms. Allocated memory was 465.6 MB in the beginning and 1.0 GB in the end (delta: 535.3 MB). Free memory was 398.9 MB in the beginning and 429.5 MB in the end (delta: -30.6 MB). Peak memory consumption was 504.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 185383.46 ms. Allocated memory was 1.0 GB in the beginning and 667.9 MB in the end (delta: -332.9 MB). Free memory was 429.5 MB in the beginning and 297.6 MB in the end (delta: 132.0 MB). There was no memory consumed. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.analysis.abstractinterpretationv2: - StatisticsResult: ArrayEqualityDomainStatistics #Locations : 78 LocStat_MAX_WEQGRAPH_SIZE : 2 LocStat_MAX_SIZEOF_WEQEDGELABEL : 3 LocStat_NO_SUPPORTING_EQUALITIES : 1610 LocStat_NO_SUPPORTING_DISEQUALITIES : 431 LocStat_NO_DISJUNCTIONS : -156 LocStat_MAX_NO_DISJUNCTIONS : -1 #Transitions : 96 TransStat_MAX_WEQGRAPH_SIZE : 4 TransStat_MAX_SIZEOF_WEQEDGELABEL : 1 TransStat_NO_SUPPORTING_EQUALITIES : 111 TransStat_NO_SUPPORTING_DISEQUALITIES : 14 TransStat_NO_DISJUNCTIONS : 99 TransStat_MAX_NO_DISJUNCTIONS : 2 - StatisticsResult: EqConstraintFactoryStatistics CONJOIN_DISJUNCTIVE(MILLISECONDS) : 8244.20 RENAME_VARIABLES(MILLISECONDS) : 508.86 UNFREEZE(MILLISECONDS) : 0.00 CONJOIN(MILLISECONDS) : 8266.49 PROJECTAWAY(MILLISECONDS) : 16593.77 ADD_WEAK_EQUALITY(MILLISECONDS) : 6.95 DISJOIN(MILLISECONDS) : 394.87 RENAME_VARIABLES_DISJUNCTIVE(MILLISECONDS) : 545.84 ADD_EQUALITY(MILLISECONDS) : 10.46 DISJOIN_DISJUNCTIVE(MILLISECONDS) : 0.00 ADD_DISEQUALITY(MILLISECONDS) : 0.88 #CONJOIN_DISJUNCTIVE : 792 #RENAME_VARIABLES : 1636 #UNFREEZE : 0 #CONJOIN : 952 #PROJECTAWAY : 916 #ADD_WEAK_EQUALITY : 14 #DISJOIN : 400 #RENAME_VARIABLES_DISJUNCTIVE : 1594 #ADD_EQUALITY : 112 #DISJOIN_DISJUNCTIVE : 0 #ADD_DISEQUALITY : 11 - StatisticsResult: WeqCcManagerStatistics FREEZE(MILLISECONDS) : 21472.91 ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 8250.05 FILTERREDUNDANT(MILLISECONDS) : 0.00 REPORTWEQ(MILLISECONDS) : 6.74 JOIN(MILLISECONDS) : 370.04 RENAMEVARS(MILLISECONDS) : 490.38 FLATTENLABELS(MILLISECONDS) : 0.00 COPY(MILLISECONDS) : 0.00 ISSTRONGERTHAN(MILLISECONDS) : 12355.38 ISLABELSTRONGERTHAN(MILLISECONDS) : 2473.59 ISWEQGRAPHSTRONGERTHAN(MILLISECONDS) : 103.55 UNFREEZE(MILLISECONDS) : 194.15 REPORTCONTAINS(MILLISECONDS) : 2.81 PROJECTAWAY(MILLISECONDS) : 16402.70 MEETEDGELABELS(MILLISECONDS) : 1189.32 REPORTEQUALITY(MILLISECONDS) : 2124.83 ADDALLNODES(MILLISECONDS) : 717.30 REPORTDISEQUALITY(MILLISECONDS) : 10.20 WEQGRAPHJOIN(MILLISECONDS) : 127.03 #FREEZE : 6718 #ADDNODE : 0 #MEET : 709 #FILTERREDUNDANT : 0 #REPORTWEQ : 14 #JOIN : 400 #RENAMEVARS : 1636 #FLATTENLABELS : 0 #COPY : 0 #ISSTRONGERTHAN : 1879 #ISLABELSTRONGERTHAN : 187713 #ISWEQGRAPHSTRONGERTHAN : 851 #UNFREEZE : 4189 #REPORTCONTAINS : 99 #PROJECTAWAY : 1844 #MEETEDGELABELS : 8542 #REPORTEQUALITY : 16918 #ADDALLNODES : 709 #REPORTDISEQUALITY : 3839 #WEQGRAPHJOIN : 400 - StatisticsResult: CcManagerStatistics ADDNODE(MILLISECONDS) : 0.00 MEET(MILLISECONDS) : 12918.65 REPORT_EQUALITY(MILLISECONDS) : 5159.39 FILTERREDUNDANT(MILLISECONDS) : 10264.44 ADD_ALL_ELEMENTS(MILLISECONDS) : 2171.42 JOIN(MILLISECONDS) : 179.75 ALIGN_ELEMENTS(MILLISECONDS) : 2928.60 COPY(MILLISECONDS) : 0.00 REPORT_DISEQUALITY(MILLISECONDS) : 638.98 UNFREEZE(MILLISECONDS) : 0.00 OVERALL(MILLISECONDS) : 18280.07 REPORTCONTAINS(MILLISECONDS) : 26.88 IS_STRONGER_THAN_NO_CACHING(MILLISECONDS) : 4870.92 REMOVE(MILLISECONDS) : 0.00 IS_STRONGER_THAN_W_CACHING(MILLISECONDS) : 0.00 PROJECT_TO_ELEMENTS(MILLISECONDS) : 1971.61 #ADDNODE : 0 #MEET : 27803 #REPORT_EQUALITY : 533106 #FILTERREDUNDANT : 423820 #ADD_ALL_ELEMENTS : 94410 #JOIN : 400 #ALIGN_ELEMENTS : 32350 #COPY : 0 #REPORT_DISEQUALITY : 132417 #UNFREEZE : 0 #OVERALL : 1643482 #REPORTCONTAINS : 1563 #IS_STRONGER_THAN_NO_CACHING : 371782 #REMOVE : 0 #IS_STRONGER_THAN_W_CACHING : 0 #PROJECT_TO_ELEMENTS : 25831 * Results from de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation: - StatisticsResult: HeapSeparatorStatistics #COUNT_NEW_ARRAY_VARS_[#memory_int] : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_0 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_0 : 1 COUNT_ARRAY_WRITES_for_[#memory_int]_at_dim_1 : 1 COUNT_BLOCKS_for_[#memory_int]_at_dim_1 : 1 COUNT_ARRAY_READS for [#memory_int] : 4 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 551]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 551). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 558]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 558). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - TimeoutResultAtElement [Line: 564]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 564). Cancelled while BasicCegarLoop was constructing difference of abstraction (1045states) and interpolant automaton (currently 31 states, 144 states before enhancement), while PredicateComparison was comparing new predicate (quantified with 0quantifier alternations) to 171 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 82 locations, 9 error locations. TIMEOUT Result, 185.3s OverallTime, 23 OverallIterations, 34 TraceHistogramMax, 137.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2624 SDtfs, 35992 SDslu, 52313 SDs, 0 SdLazy, 28634 SolverSat, 3548 SolverUnsat, 30 SolverUnknown, 0 SolverNotchecked, 18.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 5678 GetRequests, 4342 SyntacticMatches, 27 SemanticMatches, 1308 ConstructedPredicates, 24 IntricatePredicates, 0 DeprecatedPredicates, 39948 ImplicationChecksByTransitivity, 151.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1045occurred in iteration=22, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 22 MinimizatonAttempts, 2717 StatesRemovedByMinimization, 19 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 44.9s InterpolantComputationTime, 2562 NumberOfCodeBlocks, 2562 NumberOfCodeBlocksAsserted, 23 NumberOfCheckSat, 5078 ConstructedInterpolants, 2118 QuantifiedInterpolants, 25690143 SizeOfPredicates, 392 NumberOfNonLiveVariables, 6662 ConjunctsInSsa, 731 ConjunctsInUnsatCore, 46 InterpolantComputations, 26 PerfectInterpolantSequences, 436/19318 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-Benchmark-0-2018-04-10_00-03-42-061.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-VPDomainBenchmark-0-2018-04-10_00-03-42-061.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-0-2018-04-10_00-03-42-061.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-1-2018-04-10_00-03-42-061.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-BenchmarkWithCounters-2-2018-04-10_00-03-42-061.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-HeapSeparatorBenchmark-0-2018-04-10_00-03-42-061.csv Written .csv to /storage/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/diff-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Fixed_noBitfields+AI_EQ_SS.epf_AutomizerCTransformed.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-10_00-03-42-061.csv Completed graceful shutdown