java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_1_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 09:30:55,747 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 09:30:55,748 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 09:30:55,761 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 09:30:55,761 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 09:30:55,762 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 09:30:55,763 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 09:30:55,765 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 09:30:55,766 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 09:30:55,767 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 09:30:55,768 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 09:30:55,768 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 09:30:55,769 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 09:30:55,770 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 09:30:55,771 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 09:30:55,773 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 09:30:55,775 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 09:30:55,776 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 09:30:55,777 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 09:30:55,778 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 09:30:55,780 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-02 09:30:55,780 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-02 09:30:55,781 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-02 09:30:55,782 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-02 09:30:55,782 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-02 09:30:55,783 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-02 09:30:55,784 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-02 09:30:55,784 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-02 09:30:55,784 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-02 09:30:55,785 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-02 09:30:55,785 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-02 09:30:55,785 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-02-02 09:30:55,796 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 09:30:55,797 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 09:30:55,797 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 09:30:55,797 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 09:30:55,798 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 09:30:55,798 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 09:30:55,799 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:30:55,799 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 09:30:55,799 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-02 09:30:55,800 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-02 09:30:55,800 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-02-02 09:30:55,828 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 09:30:55,836 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 09:30:55,839 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 09:30:55,840 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 09:30:55,841 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 09:30:55,841 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_1_true-valid-memsafety_true-termination.i [2018-02-02 09:30:55,973 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 09:30:55,974 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 09:30:55,974 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 09:30:55,974 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 09:30:55,979 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 09:30:55,980 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:30:55" (1/1) ... [2018-02-02 09:30:55,982 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@30ce2b5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:55, skipping insertion in model container [2018-02-02 09:30:55,982 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:30:55" (1/1) ... [2018-02-02 09:30:55,993 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:30:56,028 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:30:56,130 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:30:56,149 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:30:56,158 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56 WrapperNode [2018-02-02 09:30:56,158 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 09:30:56,158 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 09:30:56,159 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 09:30:56,159 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 09:30:56,170 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,170 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,178 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,178 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,183 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,186 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,188 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... [2018-02-02 09:30:56,191 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 09:30:56,192 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 09:30:56,192 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 09:30:56,192 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 09:30:56,193 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:30:56,231 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 09:30:56,231 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 09:30:56,231 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-02-02 09:30:56,232 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-02-02 09:30:56,233 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-02-02 09:30:56,233 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-02 09:30:56,233 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-02-02 09:30:56,233 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-02 09:30:56,233 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-02-02 09:30:56,234 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-02 09:30:56,235 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 09:30:56,236 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 09:30:56,236 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 09:30:56,399 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-02 09:30:56,536 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 09:30:56,537 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:30:56 BoogieIcfgContainer [2018-02-02 09:30:56,537 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 09:30:56,537 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 09:30:56,538 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 09:30:56,539 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 09:30:56,540 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 09:30:55" (1/3) ... [2018-02-02 09:30:56,540 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3b61ecb4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:30:56, skipping insertion in model container [2018-02-02 09:30:56,540 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:30:56" (2/3) ... [2018-02-02 09:30:56,540 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3b61ecb4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:30:56, skipping insertion in model container [2018-02-02 09:30:56,541 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:30:56" (3/3) ... [2018-02-02 09:30:56,542 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test22_1_true-valid-memsafety_true-termination.i [2018-02-02 09:30:56,547 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-02 09:30:56,554 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-02-02 09:30:56,586 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 09:30:56,587 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 09:30:56,587 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-02 09:30:56,587 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-02 09:30:56,587 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 09:30:56,587 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 09:30:56,587 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 09:30:56,587 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 09:30:56,588 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 09:30:56,599 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states. [2018-02-02 09:30:56,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-02-02 09:30:56,606 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:56,607 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:56,607 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:56,610 INFO L82 PathProgramCache]: Analyzing trace with hash -401333144, now seen corresponding path program 1 times [2018-02-02 09:30:56,611 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:56,611 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:56,648 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:56,648 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:56,648 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:56,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:56,692 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:56,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:56,786 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:56,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:30:56,788 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:30:56,856 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:30:56,857 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:30:56,859 INFO L87 Difference]: Start difference. First operand 118 states. Second operand 5 states. [2018-02-02 09:30:56,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:56,917 INFO L93 Difference]: Finished difference Result 124 states and 131 transitions. [2018-02-02 09:30:56,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:30:56,919 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-02-02 09:30:56,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:56,931 INFO L225 Difference]: With dead ends: 124 [2018-02-02 09:30:56,931 INFO L226 Difference]: Without dead ends: 121 [2018-02-02 09:30:56,932 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:30:56,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-02-02 09:30:56,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 119. [2018-02-02 09:30:56,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-02-02 09:30:56,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 126 transitions. [2018-02-02 09:30:56,962 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 126 transitions. Word has length 17 [2018-02-02 09:30:56,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:56,963 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 126 transitions. [2018-02-02 09:30:56,963 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:30:56,963 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 126 transitions. [2018-02-02 09:30:56,963 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-02 09:30:56,963 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:56,963 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:56,963 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:56,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1306365930, now seen corresponding path program 1 times [2018-02-02 09:30:56,964 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:56,964 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:56,965 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:56,965 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:56,965 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:56,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:56,982 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,023 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:57,023 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:30:57,024 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:30:57,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:30:57,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:30:57,025 INFO L87 Difference]: Start difference. First operand 119 states and 126 transitions. Second operand 6 states. [2018-02-02 09:30:57,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:57,129 INFO L93 Difference]: Finished difference Result 120 states and 127 transitions. [2018-02-02 09:30:57,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:30:57,130 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-02-02 09:30:57,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:57,131 INFO L225 Difference]: With dead ends: 120 [2018-02-02 09:30:57,132 INFO L226 Difference]: Without dead ends: 120 [2018-02-02 09:30:57,132 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:30:57,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-02-02 09:30:57,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 118. [2018-02-02 09:30:57,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-02 09:30:57,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 125 transitions. [2018-02-02 09:30:57,141 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 125 transitions. Word has length 19 [2018-02-02 09:30:57,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:57,141 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 125 transitions. [2018-02-02 09:30:57,141 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:30:57,141 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 125 transitions. [2018-02-02 09:30:57,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-02 09:30:57,142 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:57,142 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:57,142 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:57,142 INFO L82 PathProgramCache]: Analyzing trace with hash 1306365931, now seen corresponding path program 1 times [2018-02-02 09:30:57,143 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:57,143 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:57,144 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,144 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:57,144 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:57,160 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,307 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:57,307 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:30:57,307 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:30:57,307 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:30:57,307 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:30:57,308 INFO L87 Difference]: Start difference. First operand 118 states and 125 transitions. Second operand 7 states. [2018-02-02 09:30:57,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:57,482 INFO L93 Difference]: Finished difference Result 119 states and 126 transitions. [2018-02-02 09:30:57,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:30:57,485 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-02-02 09:30:57,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:57,486 INFO L225 Difference]: With dead ends: 119 [2018-02-02 09:30:57,486 INFO L226 Difference]: Without dead ends: 119 [2018-02-02 09:30:57,486 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:30:57,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-02 09:30:57,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 117. [2018-02-02 09:30:57,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-02-02 09:30:57,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 124 transitions. [2018-02-02 09:30:57,497 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 124 transitions. Word has length 19 [2018-02-02 09:30:57,497 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:57,497 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 124 transitions. [2018-02-02 09:30:57,497 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:30:57,497 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 124 transitions. [2018-02-02 09:30:57,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:30:57,498 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:57,498 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:57,498 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:57,500 INFO L82 PathProgramCache]: Analyzing trace with hash -860603530, now seen corresponding path program 1 times [2018-02-02 09:30:57,500 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:57,500 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:57,502 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,502 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:57,502 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:57,530 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,585 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:57,585 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 09:30:57,585 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:30:57,585 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:30:57,585 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:30:57,585 INFO L87 Difference]: Start difference. First operand 117 states and 124 transitions. Second operand 7 states. [2018-02-02 09:30:57,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:57,626 INFO L93 Difference]: Finished difference Result 129 states and 136 transitions. [2018-02-02 09:30:57,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:30:57,627 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-02-02 09:30:57,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:57,628 INFO L225 Difference]: With dead ends: 129 [2018-02-02 09:30:57,628 INFO L226 Difference]: Without dead ends: 129 [2018-02-02 09:30:57,628 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:30:57,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-02-02 09:30:57,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 125. [2018-02-02 09:30:57,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-02 09:30:57,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 132 transitions. [2018-02-02 09:30:57,635 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 132 transitions. Word has length 29 [2018-02-02 09:30:57,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:57,636 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 132 transitions. [2018-02-02 09:30:57,636 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:30:57,636 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 132 transitions. [2018-02-02 09:30:57,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-02 09:30:57,637 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:57,637 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:57,637 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:57,637 INFO L82 PathProgramCache]: Analyzing trace with hash 23284980, now seen corresponding path program 1 times [2018-02-02 09:30:57,637 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:57,637 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:57,638 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,638 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:57,639 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:57,647 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,685 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:57,685 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 09:30:57,685 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 09:30:57,685 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 09:30:57,685 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:30:57,686 INFO L87 Difference]: Start difference. First operand 125 states and 132 transitions. Second operand 3 states. [2018-02-02 09:30:57,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:57,785 INFO L93 Difference]: Finished difference Result 140 states and 147 transitions. [2018-02-02 09:30:57,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 09:30:57,786 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 27 [2018-02-02 09:30:57,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:57,787 INFO L225 Difference]: With dead ends: 140 [2018-02-02 09:30:57,787 INFO L226 Difference]: Without dead ends: 129 [2018-02-02 09:30:57,787 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:30:57,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-02-02 09:30:57,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 121. [2018-02-02 09:30:57,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 121 states. [2018-02-02 09:30:57,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 127 transitions. [2018-02-02 09:30:57,797 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 127 transitions. Word has length 27 [2018-02-02 09:30:57,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:57,797 INFO L432 AbstractCegarLoop]: Abstraction has 121 states and 127 transitions. [2018-02-02 09:30:57,798 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 09:30:57,798 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 127 transitions. [2018-02-02 09:30:57,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:30:57,798 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:57,798 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:57,799 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:57,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1295663626, now seen corresponding path program 1 times [2018-02-02 09:30:57,799 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:57,799 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:57,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,800 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:57,800 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:57,811 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,841 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:57,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:30:57,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:30:57,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:30:57,841 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:30:57,841 INFO L87 Difference]: Start difference. First operand 121 states and 127 transitions. Second operand 6 states. [2018-02-02 09:30:57,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:57,857 INFO L93 Difference]: Finished difference Result 113 states and 118 transitions. [2018-02-02 09:30:57,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:30:57,858 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 29 [2018-02-02 09:30:57,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:57,859 INFO L225 Difference]: With dead ends: 113 [2018-02-02 09:30:57,859 INFO L226 Difference]: Without dead ends: 113 [2018-02-02 09:30:57,859 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:30:57,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-02-02 09:30:57,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-02-02 09:30:57,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-02 09:30:57,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-02-02 09:30:57,864 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 29 [2018-02-02 09:30:57,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:57,865 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-02-02 09:30:57,865 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:30:57,865 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-02-02 09:30:57,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-02 09:30:57,866 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:57,866 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:57,866 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:57,866 INFO L82 PathProgramCache]: Analyzing trace with hash 522747174, now seen corresponding path program 1 times [2018-02-02 09:30:57,866 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:57,867 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:57,868 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,868 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:57,868 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:57,881 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,913 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:30:57,913 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 09:30:57,913 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:30:57,913 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:30:57,913 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:30:57,914 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 4 states. [2018-02-02 09:30:57,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:57,924 INFO L93 Difference]: Finished difference Result 116 states and 121 transitions. [2018-02-02 09:30:57,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:30:57,926 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-02-02 09:30:57,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:57,927 INFO L225 Difference]: With dead ends: 116 [2018-02-02 09:30:57,927 INFO L226 Difference]: Without dead ends: 114 [2018-02-02 09:30:57,927 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:30:57,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-02-02 09:30:57,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-02-02 09:30:57,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:30:57,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 119 transitions. [2018-02-02 09:30:57,932 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 119 transitions. Word has length 34 [2018-02-02 09:30:57,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:57,932 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 119 transitions. [2018-02-02 09:30:57,932 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:30:57,932 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 119 transitions. [2018-02-02 09:30:57,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:30:57,933 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:57,933 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:57,933 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:57,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1305776369, now seen corresponding path program 1 times [2018-02-02 09:30:57,933 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:57,933 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:57,934 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,934 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:57,935 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:57,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:57,946 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:57,969 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:57,969 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:30:57,969 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:30:57,975 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:58,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:58,012 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:30:58,028 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:58,054 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:30:58,054 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-02-02 09:30:58,054 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:30:58,054 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:30:58,055 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:30:58,055 INFO L87 Difference]: Start difference. First operand 114 states and 119 transitions. Second operand 6 states. [2018-02-02 09:30:58,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:30:58,072 INFO L93 Difference]: Finished difference Result 117 states and 122 transitions. [2018-02-02 09:30:58,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:30:58,072 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-02 09:30:58,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:30:58,073 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:30:58,073 INFO L226 Difference]: Without dead ends: 115 [2018-02-02 09:30:58,073 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:30:58,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-02-02 09:30:58,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-02-02 09:30:58,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-02-02 09:30:58,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 120 transitions. [2018-02-02 09:30:58,078 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 120 transitions. Word has length 35 [2018-02-02 09:30:58,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:30:58,078 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 120 transitions. [2018-02-02 09:30:58,078 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:30:58,078 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 120 transitions. [2018-02-02 09:30:58,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 09:30:58,079 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:30:58,079 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:30:58,079 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:30:58,080 INFO L82 PathProgramCache]: Analyzing trace with hash 2139535942, now seen corresponding path program 2 times [2018-02-02 09:30:58,080 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:30:58,080 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:30:58,081 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:58,081 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:30:58,081 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:30:58,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:30:58,095 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:30:58,121 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:30:58,121 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:30:58,121 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:30:58,126 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-02 09:30:58,145 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:30:58,147 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:30:58,150 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:30:58,173 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-02 09:30:58,174 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-02 09:30:58,184 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-02 09:30:58,184 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:30:58,194 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-02 09:30:58,194 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-02 09:31:00,420 WARN L143 SmtUtils]: Spent 2034ms on a formula simplification that was a NOOP. DAG size: 27 [2018-02-02 09:31:00,664 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:31:00,681 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:31:00,681 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14] imperfect sequences [6] total 19 [2018-02-02 09:31:00,682 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 09:31:00,682 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 09:31:00,682 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:31:00,682 INFO L87 Difference]: Start difference. First operand 115 states and 120 transitions. Second operand 19 states. [2018-02-02 09:31:02,811 WARN L143 SmtUtils]: Spent 2018ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-02 09:31:03,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:03,610 INFO L93 Difference]: Finished difference Result 117 states and 122 transitions. [2018-02-02 09:31:03,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 09:31:03,611 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 36 [2018-02-02 09:31:03,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:03,612 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:31:03,612 INFO L226 Difference]: Without dead ends: 115 [2018-02-02 09:31:03,612 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=99, Invalid=603, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:31:03,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-02-02 09:31:03,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-02-02 09:31:03,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-02-02 09:31:03,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 120 transitions. [2018-02-02 09:31:03,619 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 120 transitions. Word has length 36 [2018-02-02 09:31:03,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:03,619 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 120 transitions. [2018-02-02 09:31:03,619 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 09:31:03,620 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 120 transitions. [2018-02-02 09:31:03,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-02-02 09:31:03,620 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:03,621 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:03,621 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:03,621 INFO L82 PathProgramCache]: Analyzing trace with hash 1570035182, now seen corresponding path program 1 times [2018-02-02 09:31:03,621 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:03,622 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:03,623 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:03,623 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:03,623 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:03,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:03,636 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:03,758 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 09:31:03,758 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:03,758 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-02 09:31:03,759 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:31:03,759 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:31:03,759 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:31:03,759 INFO L87 Difference]: Start difference. First operand 115 states and 120 transitions. Second operand 10 states. [2018-02-02 09:31:03,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:03,901 INFO L93 Difference]: Finished difference Result 114 states and 119 transitions. [2018-02-02 09:31:03,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:31:03,901 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 37 [2018-02-02 09:31:03,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:03,902 INFO L225 Difference]: With dead ends: 114 [2018-02-02 09:31:03,902 INFO L226 Difference]: Without dead ends: 114 [2018-02-02 09:31:03,902 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:31:03,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-02-02 09:31:03,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-02-02 09:31:03,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:31:03,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 119 transitions. [2018-02-02 09:31:03,906 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 119 transitions. Word has length 37 [2018-02-02 09:31:03,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:03,906 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 119 transitions. [2018-02-02 09:31:03,906 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:31:03,906 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 119 transitions. [2018-02-02 09:31:03,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 09:31:03,911 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:03,911 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:03,911 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:03,911 INFO L82 PathProgramCache]: Analyzing trace with hash 258949559, now seen corresponding path program 1 times [2018-02-02 09:31:03,911 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:03,912 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:03,912 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:03,913 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:03,913 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:03,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:03,928 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:04,091 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 09:31:04,091 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:04,091 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-02 09:31:04,092 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:31:04,092 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:31:04,092 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:31:04,092 INFO L87 Difference]: Start difference. First operand 114 states and 119 transitions. Second operand 10 states. [2018-02-02 09:31:04,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:04,250 INFO L93 Difference]: Finished difference Result 112 states and 117 transitions. [2018-02-02 09:31:04,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:31:04,251 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-02 09:31:04,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:04,251 INFO L225 Difference]: With dead ends: 112 [2018-02-02 09:31:04,251 INFO L226 Difference]: Without dead ends: 112 [2018-02-02 09:31:04,252 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:31:04,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-02-02 09:31:04,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-02-02 09:31:04,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-02-02 09:31:04,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 117 transitions. [2018-02-02 09:31:04,254 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 117 transitions. Word has length 42 [2018-02-02 09:31:04,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:04,254 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 117 transitions. [2018-02-02 09:31:04,255 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:31:04,255 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 117 transitions. [2018-02-02 09:31:04,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 09:31:04,255 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:04,255 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:04,255 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:04,256 INFO L82 PathProgramCache]: Analyzing trace with hash 258949560, now seen corresponding path program 1 times [2018-02-02 09:31:04,256 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:04,256 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:04,256 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:04,257 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:04,257 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:04,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:04,268 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:04,302 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:04,302 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:04,302 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:04,309 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:04,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:04,339 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:04,348 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:04,371 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:04,371 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-02-02 09:31:04,371 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:31:04,371 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:31:04,371 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:31:04,371 INFO L87 Difference]: Start difference. First operand 112 states and 117 transitions. Second operand 8 states. [2018-02-02 09:31:04,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:04,389 INFO L93 Difference]: Finished difference Result 115 states and 120 transitions. [2018-02-02 09:31:04,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:31:04,390 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-02-02 09:31:04,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:04,390 INFO L225 Difference]: With dead ends: 115 [2018-02-02 09:31:04,390 INFO L226 Difference]: Without dead ends: 113 [2018-02-02 09:31:04,391 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:31:04,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-02-02 09:31:04,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-02-02 09:31:04,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-02 09:31:04,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-02-02 09:31:04,394 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 42 [2018-02-02 09:31:04,394 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:04,395 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-02-02 09:31:04,395 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:31:04,395 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-02-02 09:31:04,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-02-02 09:31:04,395 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:04,395 INFO L351 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:04,396 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:04,396 INFO L82 PathProgramCache]: Analyzing trace with hash -549832031, now seen corresponding path program 2 times [2018-02-02 09:31:04,396 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:04,396 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:04,397 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:04,397 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:04,397 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:04,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:04,410 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:04,451 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:04,451 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:04,451 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:04,464 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-02 09:31:04,487 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:04,489 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:04,501 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:04,508 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-02 09:31:04,508 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:04,524 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-02 09:31:04,524 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:04,539 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-02 09:31:04,540 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-02 09:31:05,011 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 09:31:05,028 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:31:05,028 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [8] total 22 [2018-02-02 09:31:05,028 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:31:05,028 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:31:05,029 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:31:05,029 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 22 states. [2018-02-02 09:31:07,339 WARN L143 SmtUtils]: Spent 2016ms on a formula simplification that was a NOOP. DAG size: 32 [2018-02-02 09:31:07,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:07,749 INFO L93 Difference]: Finished difference Result 114 states and 119 transitions. [2018-02-02 09:31:07,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:31:07,749 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 43 [2018-02-02 09:31:07,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:07,750 INFO L225 Difference]: With dead ends: 114 [2018-02-02 09:31:07,750 INFO L226 Difference]: Without dead ends: 112 [2018-02-02 09:31:07,750 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=147, Invalid=845, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:31:07,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-02-02 09:31:07,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-02-02 09:31:07,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-02-02 09:31:07,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 117 transitions. [2018-02-02 09:31:07,752 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 117 transitions. Word has length 43 [2018-02-02 09:31:07,752 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:07,752 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 117 transitions. [2018-02-02 09:31:07,752 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:31:07,752 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 117 transitions. [2018-02-02 09:31:07,753 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-02-02 09:31:07,753 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:07,753 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:07,753 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:07,753 INFO L82 PathProgramCache]: Analyzing trace with hash -2038388811, now seen corresponding path program 1 times [2018-02-02 09:31:07,753 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:07,753 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:07,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:07,754 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:07,754 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:07,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:07,762 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:07,814 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-02 09:31:07,814 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:07,814 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 09:31:07,815 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:31:07,815 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:31:07,815 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:31:07,815 INFO L87 Difference]: Start difference. First operand 112 states and 117 transitions. Second operand 8 states. [2018-02-02 09:31:07,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:07,854 INFO L93 Difference]: Finished difference Result 114 states and 118 transitions. [2018-02-02 09:31:07,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:31:07,854 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 49 [2018-02-02 09:31:07,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:07,855 INFO L225 Difference]: With dead ends: 114 [2018-02-02 09:31:07,855 INFO L226 Difference]: Without dead ends: 112 [2018-02-02 09:31:07,855 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:31:07,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-02-02 09:31:07,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-02-02 09:31:07,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-02-02 09:31:07,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-02-02 09:31:07,858 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 49 [2018-02-02 09:31:07,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:07,858 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-02-02 09:31:07,858 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:31:07,858 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-02-02 09:31:07,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-02 09:31:07,859 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:07,859 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:07,859 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:07,859 INFO L82 PathProgramCache]: Analyzing trace with hash 2077653417, now seen corresponding path program 1 times [2018-02-02 09:31:07,860 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:07,860 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:07,860 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:07,861 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:07,861 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:07,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:07,869 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:07,926 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-02 09:31:07,926 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:07,926 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-02 09:31:07,926 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:31:07,926 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:31:07,926 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:31:07,927 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 10 states. [2018-02-02 09:31:07,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:07,964 INFO L93 Difference]: Finished difference Result 116 states and 119 transitions. [2018-02-02 09:31:07,964 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:31:07,964 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 54 [2018-02-02 09:31:07,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:07,965 INFO L225 Difference]: With dead ends: 116 [2018-02-02 09:31:07,965 INFO L226 Difference]: Without dead ends: 112 [2018-02-02 09:31:07,965 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:31:07,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-02-02 09:31:07,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-02-02 09:31:07,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-02-02 09:31:07,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 115 transitions. [2018-02-02 09:31:07,967 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 115 transitions. Word has length 54 [2018-02-02 09:31:07,967 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:07,967 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 115 transitions. [2018-02-02 09:31:07,967 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:31:07,967 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 115 transitions. [2018-02-02 09:31:07,967 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-02 09:31:07,967 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:07,967 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:07,967 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:07,967 INFO L82 PathProgramCache]: Analyzing trace with hash -154764032, now seen corresponding path program 1 times [2018-02-02 09:31:07,968 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:07,968 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:07,968 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:07,968 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:07,968 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:07,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:07,977 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:08,114 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-02 09:31:08,114 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:08,114 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-02-02 09:31:08,114 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 09:31:08,114 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 09:31:08,115 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=379, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:31:08,115 INFO L87 Difference]: Start difference. First operand 112 states and 115 transitions. Second operand 21 states. [2018-02-02 09:31:08,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:08,402 INFO L93 Difference]: Finished difference Result 119 states and 122 transitions. [2018-02-02 09:31:08,402 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-02 09:31:08,402 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-02-02 09:31:08,402 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:08,403 INFO L225 Difference]: With dead ends: 119 [2018-02-02 09:31:08,403 INFO L226 Difference]: Without dead ends: 119 [2018-02-02 09:31:08,403 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=69, Invalid=687, Unknown=0, NotChecked=0, Total=756 [2018-02-02 09:31:08,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-02 09:31:08,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 110. [2018-02-02 09:31:08,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-02-02 09:31:08,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2018-02-02 09:31:08,406 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 113 transitions. Word has length 65 [2018-02-02 09:31:08,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:08,406 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 113 transitions. [2018-02-02 09:31:08,406 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 09:31:08,406 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 113 transitions. [2018-02-02 09:31:08,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-02 09:31:08,407 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:08,407 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:08,407 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:08,407 INFO L82 PathProgramCache]: Analyzing trace with hash -154764031, now seen corresponding path program 1 times [2018-02-02 09:31:08,407 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:08,408 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:08,408 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:08,408 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:08,409 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:08,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:08,423 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:08,467 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:08,467 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:08,467 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:08,472 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:08,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:08,501 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:08,511 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:08,528 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:08,528 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-02-02 09:31:08,528 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:31:08,528 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:31:08,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:31:08,529 INFO L87 Difference]: Start difference. First operand 110 states and 113 transitions. Second operand 10 states. [2018-02-02 09:31:08,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:08,542 INFO L93 Difference]: Finished difference Result 113 states and 116 transitions. [2018-02-02 09:31:08,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:31:08,542 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-02-02 09:31:08,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:08,543 INFO L225 Difference]: With dead ends: 113 [2018-02-02 09:31:08,543 INFO L226 Difference]: Without dead ends: 111 [2018-02-02 09:31:08,543 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:31:08,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-02-02 09:31:08,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-02-02 09:31:08,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-02-02 09:31:08,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 114 transitions. [2018-02-02 09:31:08,545 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 114 transitions. Word has length 65 [2018-02-02 09:31:08,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:08,545 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 114 transitions. [2018-02-02 09:31:08,545 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:31:08,545 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 114 transitions. [2018-02-02 09:31:08,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-02 09:31:08,545 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:08,546 INFO L351 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:08,546 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:08,546 INFO L82 PathProgramCache]: Analyzing trace with hash -477131272, now seen corresponding path program 2 times [2018-02-02 09:31:08,546 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:08,546 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:08,546 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:08,547 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:08,547 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:08,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:08,555 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:08,616 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:08,616 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:08,616 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:08,624 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-02 09:31:08,655 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:08,660 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:08,665 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:08,677 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-02 09:31:08,678 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:08,692 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-02 09:31:08,692 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:08,713 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-02 09:31:08,713 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-02 09:31:10,829 WARN L1033 $PredicateComparison]: unable to prove that (or (exists ((v_prenex_13 Int) (v_ldv_kobject_create_~kobj~1.base_BEFORE_CALL_5 Int)) (let ((.cse0 (mod v_prenex_13 4294967296))) (and (< 2147483647 .cse0) (= (+ (select |c_#length| v_ldv_kobject_create_~kobj~1.base_BEFORE_CALL_5) 4294967296) .cse0)))) (exists ((v_prenex_14 Int) (ldv_malloc_~size Int)) (let ((.cse1 (mod ldv_malloc_~size 4294967296))) (and (<= .cse1 2147483647) (= (select |c_#length| v_prenex_14) .cse1))))) is different from true [2018-02-02 09:31:11,287 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-02 09:31:11,303 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:31:11,303 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [10] total 29 [2018-02-02 09:31:11,303 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-02 09:31:11,303 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-02 09:31:11,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=670, Unknown=1, NotChecked=52, Total=812 [2018-02-02 09:31:11,304 INFO L87 Difference]: Start difference. First operand 111 states and 114 transitions. Second operand 29 states. [2018-02-02 09:31:13,512 WARN L143 SmtUtils]: Spent 2017ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-02 09:31:17,012 WARN L143 SmtUtils]: Spent 3454ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-02 09:31:19,052 WARN L143 SmtUtils]: Spent 2024ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-02 09:31:19,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:19,658 INFO L93 Difference]: Finished difference Result 112 states and 115 transitions. [2018-02-02 09:31:19,658 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 09:31:19,658 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 66 [2018-02-02 09:31:19,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:19,659 INFO L225 Difference]: With dead ends: 112 [2018-02-02 09:31:19,659 INFO L226 Difference]: Without dead ends: 110 [2018-02-02 09:31:19,660 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 346 ImplicationChecksByTransitivity, 10.3s TimeCoverageRelationStatistics Valid=195, Invalid=1530, Unknown=1, NotChecked=80, Total=1806 [2018-02-02 09:31:19,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-02-02 09:31:19,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-02-02 09:31:19,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-02-02 09:31:19,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2018-02-02 09:31:19,662 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 113 transitions. Word has length 66 [2018-02-02 09:31:19,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:19,662 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 113 transitions. [2018-02-02 09:31:19,662 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-02 09:31:19,662 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 113 transitions. [2018-02-02 09:31:19,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-02 09:31:19,662 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:19,662 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:19,663 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:19,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1613283294, now seen corresponding path program 1 times [2018-02-02 09:31:19,663 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:19,663 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:19,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:19,664 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:19,664 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:19,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:19,672 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:19,719 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-02 09:31:19,720 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:19,720 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-02-02 09:31:19,720 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 09:31:19,720 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 09:31:19,720 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:31:19,721 INFO L87 Difference]: Start difference. First operand 110 states and 113 transitions. Second operand 11 states. [2018-02-02 09:31:19,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:19,754 INFO L93 Difference]: Finished difference Result 112 states and 114 transitions. [2018-02-02 09:31:19,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 09:31:19,754 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 65 [2018-02-02 09:31:19,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:19,754 INFO L225 Difference]: With dead ends: 112 [2018-02-02 09:31:19,755 INFO L226 Difference]: Without dead ends: 110 [2018-02-02 09:31:19,755 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:31:19,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-02-02 09:31:19,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-02-02 09:31:19,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-02-02 09:31:19,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-02-02 09:31:19,757 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 65 [2018-02-02 09:31:19,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:19,757 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-02-02 09:31:19,757 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 09:31:19,757 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-02-02 09:31:19,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-02 09:31:19,757 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:19,757 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:19,758 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:19,758 INFO L82 PathProgramCache]: Analyzing trace with hash -1474253813, now seen corresponding path program 1 times [2018-02-02 09:31:19,758 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:19,758 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:19,758 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:19,759 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:19,759 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:19,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:19,769 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:20,009 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-02 09:31:20,009 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:31:20,009 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [23] imperfect sequences [] total 23 [2018-02-02 09:31:20,010 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:31:20,010 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:31:20,010 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=507, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:31:20,010 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 24 states. [2018-02-02 09:31:20,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:20,435 INFO L93 Difference]: Finished difference Result 113 states and 115 transitions. [2018-02-02 09:31:20,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:31:20,435 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 81 [2018-02-02 09:31:20,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:20,436 INFO L225 Difference]: With dead ends: 113 [2018-02-02 09:31:20,436 INFO L226 Difference]: Without dead ends: 113 [2018-02-02 09:31:20,436 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=85, Invalid=1037, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:31:20,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-02-02 09:31:20,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 108. [2018-02-02 09:31:20,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-02-02 09:31:20,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 110 transitions. [2018-02-02 09:31:20,438 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 110 transitions. Word has length 81 [2018-02-02 09:31:20,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:20,438 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 110 transitions. [2018-02-02 09:31:20,438 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:31:20,438 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 110 transitions. [2018-02-02 09:31:20,439 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-02 09:31:20,439 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:20,439 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:20,439 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:20,439 INFO L82 PathProgramCache]: Analyzing trace with hash -1474253812, now seen corresponding path program 1 times [2018-02-02 09:31:20,439 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:20,439 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:20,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:20,440 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:20,440 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:20,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:20,455 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:20,533 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:20,533 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:20,533 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:20,540 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:20,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:20,594 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:20,603 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:20,620 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:20,620 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-02-02 09:31:20,620 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 09:31:20,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 09:31:20,621 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:31:20,621 INFO L87 Difference]: Start difference. First operand 108 states and 110 transitions. Second operand 12 states. [2018-02-02 09:31:20,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:20,638 INFO L93 Difference]: Finished difference Result 111 states and 113 transitions. [2018-02-02 09:31:20,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 09:31:20,639 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 81 [2018-02-02 09:31:20,640 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:20,640 INFO L225 Difference]: With dead ends: 111 [2018-02-02 09:31:20,640 INFO L226 Difference]: Without dead ends: 109 [2018-02-02 09:31:20,640 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:31:20,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-02-02 09:31:20,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-02-02 09:31:20,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-02 09:31:20,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 111 transitions. [2018-02-02 09:31:20,642 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 111 transitions. Word has length 81 [2018-02-02 09:31:20,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:20,642 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 111 transitions. [2018-02-02 09:31:20,642 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 09:31:20,642 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 111 transitions. [2018-02-02 09:31:20,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-02-02 09:31:20,642 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:20,642 INFO L351 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:20,642 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:20,643 INFO L82 PathProgramCache]: Analyzing trace with hash 1420750595, now seen corresponding path program 2 times [2018-02-02 09:31:20,643 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:20,643 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:20,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:20,643 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:20,643 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:20,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:20,657 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:20,734 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:20,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:20,734 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:20,742 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-02 09:31:20,782 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:20,789 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:20,794 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:20,799 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-02 09:31:20,800 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:20,811 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-02 09:31:20,811 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:20,821 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-02 09:31:20,821 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-02 09:31:21,793 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 09:31:21,809 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:31:21,810 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [24] imperfect sequences [12] total 35 [2018-02-02 09:31:21,810 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-02-02 09:31:21,810 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-02-02 09:31:21,810 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=1048, Unknown=0, NotChecked=0, Total=1190 [2018-02-02 09:31:21,810 INFO L87 Difference]: Start difference. First operand 109 states and 111 transitions. Second operand 35 states. [2018-02-02 09:31:23,831 WARN L143 SmtUtils]: Spent 1990ms on a formula simplification that was a NOOP. DAG size: 39 [2018-02-02 09:31:26,062 WARN L143 SmtUtils]: Spent 2017ms on a formula simplification that was a NOOP. DAG size: 35 [2018-02-02 09:31:27,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:27,014 INFO L93 Difference]: Finished difference Result 110 states and 112 transitions. [2018-02-02 09:31:27,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-02 09:31:27,015 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 82 [2018-02-02 09:31:27,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:27,015 INFO L225 Difference]: With dead ends: 110 [2018-02-02 09:31:27,015 INFO L226 Difference]: Without dead ends: 108 [2018-02-02 09:31:27,016 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 57 SyntacticMatches, 3 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 617 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=314, Invalid=2442, Unknown=0, NotChecked=0, Total=2756 [2018-02-02 09:31:27,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-02-02 09:31:27,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2018-02-02 09:31:27,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-02-02 09:31:27,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 110 transitions. [2018-02-02 09:31:27,017 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 110 transitions. Word has length 82 [2018-02-02 09:31:27,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:27,018 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 110 transitions. [2018-02-02 09:31:27,018 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-02-02 09:31:27,018 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 110 transitions. [2018-02-02 09:31:27,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-02 09:31:27,018 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:27,018 INFO L351 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:27,018 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:27,018 INFO L82 PathProgramCache]: Analyzing trace with hash -1218395795, now seen corresponding path program 1 times [2018-02-02 09:31:27,019 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:27,019 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:27,019 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:27,020 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:27,020 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:27,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:27,030 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:27,134 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:27,135 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:27,135 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:27,144 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:27,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:27,185 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:27,193 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:27,210 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:27,210 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-02-02 09:31:27,210 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 09:31:27,215 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 09:31:27,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:31:27,215 INFO L87 Difference]: Start difference. First operand 108 states and 110 transitions. Second operand 14 states. [2018-02-02 09:31:27,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:27,236 INFO L93 Difference]: Finished difference Result 111 states and 113 transitions. [2018-02-02 09:31:27,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-02 09:31:27,236 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 87 [2018-02-02 09:31:27,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:27,237 INFO L225 Difference]: With dead ends: 111 [2018-02-02 09:31:27,237 INFO L226 Difference]: Without dead ends: 109 [2018-02-02 09:31:27,237 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:31:27,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-02-02 09:31:27,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-02-02 09:31:27,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-02 09:31:27,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 111 transitions. [2018-02-02 09:31:27,240 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 111 transitions. Word has length 87 [2018-02-02 09:31:27,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:27,240 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 111 transitions. [2018-02-02 09:31:27,240 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 09:31:27,240 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 111 transitions. [2018-02-02 09:31:27,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-02-02 09:31:27,241 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:27,241 INFO L351 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:27,241 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:27,241 INFO L82 PathProgramCache]: Analyzing trace with hash -1495748828, now seen corresponding path program 2 times [2018-02-02 09:31:27,241 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:27,241 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:27,242 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:27,242 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:27,242 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:27,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:27,254 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:27,321 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:27,321 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:27,322 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:27,326 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-02 09:31:27,359 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:27,371 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:27,373 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:27,376 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:27,394 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:27,412 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:27,412 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2018-02-02 09:31:27,412 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 09:31:27,412 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 09:31:27,412 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:31:27,413 INFO L87 Difference]: Start difference. First operand 109 states and 111 transitions. Second operand 15 states. [2018-02-02 09:31:27,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:27,432 INFO L93 Difference]: Finished difference Result 112 states and 114 transitions. [2018-02-02 09:31:27,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-02 09:31:27,433 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 88 [2018-02-02 09:31:27,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:27,433 INFO L225 Difference]: With dead ends: 112 [2018-02-02 09:31:27,433 INFO L226 Difference]: Without dead ends: 110 [2018-02-02 09:31:27,433 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=97, Invalid=143, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:31:27,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-02-02 09:31:27,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2018-02-02 09:31:27,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 110 states. [2018-02-02 09:31:27,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 112 transitions. [2018-02-02 09:31:27,436 INFO L78 Accepts]: Start accepts. Automaton has 110 states and 112 transitions. Word has length 88 [2018-02-02 09:31:27,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:27,436 INFO L432 AbstractCegarLoop]: Abstraction has 110 states and 112 transitions. [2018-02-02 09:31:27,436 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 09:31:27,436 INFO L276 IsEmpty]: Start isEmpty. Operand 110 states and 112 transitions. [2018-02-02 09:31:27,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-02 09:31:27,436 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:27,437 INFO L351 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:27,437 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:27,437 INFO L82 PathProgramCache]: Analyzing trace with hash -1503758259, now seen corresponding path program 3 times [2018-02-02 09:31:27,437 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:27,437 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:27,438 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:27,438 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:27,438 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:27,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:27,454 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:27,555 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:27,555 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:27,555 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:27,562 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-02 09:31:27,603 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:27,617 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:27,645 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:27,855 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:28,327 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:28,700 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:29,732 INFO L254 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued a check-sat command [2018-02-02 09:31:29,736 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:29,743 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:29,879 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:29,897 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:29,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 20] total 33 [2018-02-02 09:31:29,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-02 09:31:29,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-02 09:31:29,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=770, Unknown=0, NotChecked=0, Total=1056 [2018-02-02 09:31:29,898 INFO L87 Difference]: Start difference. First operand 110 states and 112 transitions. Second operand 33 states. [2018-02-02 09:31:30,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:30,003 INFO L93 Difference]: Finished difference Result 113 states and 115 transitions. [2018-02-02 09:31:30,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 09:31:30,003 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 89 [2018-02-02 09:31:30,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:30,004 INFO L225 Difference]: With dead ends: 113 [2018-02-02 09:31:30,004 INFO L226 Difference]: Without dead ends: 111 [2018-02-02 09:31:30,004 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 72 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 390 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=324, Invalid=936, Unknown=0, NotChecked=0, Total=1260 [2018-02-02 09:31:30,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-02-02 09:31:30,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-02-02 09:31:30,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-02-02 09:31:30,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 113 transitions. [2018-02-02 09:31:30,006 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 113 transitions. Word has length 89 [2018-02-02 09:31:30,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:30,006 INFO L432 AbstractCegarLoop]: Abstraction has 111 states and 113 transitions. [2018-02-02 09:31:30,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-02 09:31:30,006 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 113 transitions. [2018-02-02 09:31:30,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-02 09:31:30,006 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:30,006 INFO L351 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:30,006 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:30,007 INFO L82 PathProgramCache]: Analyzing trace with hash -1752050620, now seen corresponding path program 4 times [2018-02-02 09:31:30,007 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:30,007 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:30,007 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:30,007 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:30,008 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:30,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:30,020 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:30,133 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:30,134 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:30,134 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:30,141 INFO L101 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-02-02 09:31:30,198 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:30,200 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:30,211 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:30,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:30,233 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2018-02-02 09:31:30,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:31:30,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:31:30,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:31:30,234 INFO L87 Difference]: Start difference. First operand 111 states and 113 transitions. Second operand 17 states. [2018-02-02 09:31:30,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:30,269 INFO L93 Difference]: Finished difference Result 114 states and 116 transitions. [2018-02-02 09:31:30,269 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 09:31:30,269 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 90 [2018-02-02 09:31:30,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:30,270 INFO L225 Difference]: With dead ends: 114 [2018-02-02 09:31:30,270 INFO L226 Difference]: Without dead ends: 112 [2018-02-02 09:31:30,270 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=126, Invalid=180, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:31:30,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-02-02 09:31:30,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2018-02-02 09:31:30,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-02-02 09:31:30,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 114 transitions. [2018-02-02 09:31:30,273 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 114 transitions. Word has length 90 [2018-02-02 09:31:30,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:30,273 INFO L432 AbstractCegarLoop]: Abstraction has 112 states and 114 transitions. [2018-02-02 09:31:30,273 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:31:30,273 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 114 transitions. [2018-02-02 09:31:30,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-02-02 09:31:30,274 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:30,274 INFO L351 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:30,274 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:30,274 INFO L82 PathProgramCache]: Analyzing trace with hash -859179219, now seen corresponding path program 5 times [2018-02-02 09:31:30,274 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:30,274 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:30,275 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:30,275 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:30,275 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:30,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:30,290 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:30,407 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:30,408 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:30,408 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:30,414 INFO L101 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-02-02 09:31:30,431 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,433 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,437 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,453 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,471 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,531 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,560 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,753 INFO L278 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:30,757 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:30,761 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:30,769 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:30,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:30,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-02-02 09:31:30,787 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 09:31:30,787 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 09:31:30,787 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=168, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:31:30,787 INFO L87 Difference]: Start difference. First operand 112 states and 114 transitions. Second operand 18 states. [2018-02-02 09:31:30,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:30,824 INFO L93 Difference]: Finished difference Result 115 states and 117 transitions. [2018-02-02 09:31:30,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:31:30,824 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 91 [2018-02-02 09:31:30,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:30,824 INFO L225 Difference]: With dead ends: 115 [2018-02-02 09:31:30,825 INFO L226 Difference]: Without dead ends: 113 [2018-02-02 09:31:30,825 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=142, Invalid=200, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:31:30,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-02-02 09:31:30,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-02-02 09:31:30,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-02 09:31:30,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 115 transitions. [2018-02-02 09:31:30,827 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 115 transitions. Word has length 91 [2018-02-02 09:31:30,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:30,828 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 115 transitions. [2018-02-02 09:31:30,828 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 09:31:30,828 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 115 transitions. [2018-02-02 09:31:30,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-02 09:31:30,828 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:30,828 INFO L351 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:30,829 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:30,829 INFO L82 PathProgramCache]: Analyzing trace with hash 1050030436, now seen corresponding path program 6 times [2018-02-02 09:31:30,829 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:30,829 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:30,830 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:30,830 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:30,830 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:30,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:30,846 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:30,961 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:30,961 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:30,961 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:30,965 INFO L101 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-02-02 09:31:30,987 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:30,996 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:31,008 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:31,126 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:31,252 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:32,009 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:32,684 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:34,446 INFO L310 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued a check-sat command [2018-02-02 09:31:34,448 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:34,453 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:34,471 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:34,490 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:34,491 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-02-02 09:31:34,491 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 09:31:34,491 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 09:31:34,491 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:31:34,492 INFO L87 Difference]: Start difference. First operand 113 states and 115 transitions. Second operand 19 states. [2018-02-02 09:31:34,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:34,514 INFO L93 Difference]: Finished difference Result 116 states and 118 transitions. [2018-02-02 09:31:34,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:31:34,514 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 92 [2018-02-02 09:31:34,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:34,514 INFO L225 Difference]: With dead ends: 116 [2018-02-02 09:31:34,514 INFO L226 Difference]: Without dead ends: 114 [2018-02-02 09:31:34,515 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=159, Invalid=221, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:31:34,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-02-02 09:31:34,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-02-02 09:31:34,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:31:34,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 116 transitions. [2018-02-02 09:31:34,517 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 116 transitions. Word has length 92 [2018-02-02 09:31:34,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:34,517 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 116 transitions. [2018-02-02 09:31:34,517 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 09:31:34,517 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 116 transitions. [2018-02-02 09:31:34,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-02 09:31:34,518 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:34,518 INFO L351 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:34,518 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:34,518 INFO L82 PathProgramCache]: Analyzing trace with hash 105987597, now seen corresponding path program 7 times [2018-02-02 09:31:34,518 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:34,518 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:34,519 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:34,519 INFO L99 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-02 09:31:34,519 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:34,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:34,535 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:34,687 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:34,687 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:34,687 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:34,692 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:34,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:34,731 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:34,743 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:34,771 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-02 09:31:34,771 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2018-02-02 09:31:34,772 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:31:34,772 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:31:34,772 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=207, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:31:34,772 INFO L87 Difference]: Start difference. First operand 114 states and 116 transitions. Second operand 20 states. [2018-02-02 09:31:34,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:31:34,816 INFO L93 Difference]: Finished difference Result 117 states and 119 transitions. [2018-02-02 09:31:34,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 09:31:34,816 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 93 [2018-02-02 09:31:34,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:31:34,817 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:31:34,817 INFO L226 Difference]: Without dead ends: 115 [2018-02-02 09:31:34,817 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=177, Invalid=243, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:31:34,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-02-02 09:31:34,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-02-02 09:31:34,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-02-02 09:31:34,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 117 transitions. [2018-02-02 09:31:34,820 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 117 transitions. Word has length 93 [2018-02-02 09:31:34,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:31:34,820 INFO L432 AbstractCegarLoop]: Abstraction has 115 states and 117 transitions. [2018-02-02 09:31:34,820 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:31:34,820 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 117 transitions. [2018-02-02 09:31:34,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-02-02 09:31:34,820 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:31:34,821 INFO L351 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:31:34,821 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-02 09:31:34,821 INFO L82 PathProgramCache]: Analyzing trace with hash 905430660, now seen corresponding path program 8 times [2018-02-02 09:31:34,821 INFO L209 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-02 09:31:34,821 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-02 09:31:34,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:34,822 INFO L101 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-02 09:31:34,822 INFO L117 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-02 09:31:34,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:31:34,884 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:31:37,584 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:31:37,584 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-02 09:31:37,584 INFO L209 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-02 09:31:37,589 INFO L101 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-02 09:31:37,613 INFO L201 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:37,626 INFO L214 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued a check-sat command [2018-02-02 09:31:37,629 INFO L239 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-02 09:31:37,634 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-02 09:31:37,801 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-02 09:31:37,802 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-02 09:31:37,802 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,804 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,808 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,808 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-02-02 09:31:37,849 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-02-02 09:31:37,851 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,853 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-02-02 09:31:37,853 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,857 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,862 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,862 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-02-02 09:31:37,909 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-02-02 09:31:37,910 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,911 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,911 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,912 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 52 [2018-02-02 09:31:37,912 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,917 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,923 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,923 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:38 [2018-02-02 09:31:37,979 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-02-02 09:31:37,984 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,984 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,985 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,987 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:37,988 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 85 [2018-02-02 09:31:37,988 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:37,998 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,005 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,005 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:53, output treesize:49 [2018-02-02 09:31:38,074 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 47 [2018-02-02 09:31:38,077 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,084 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 126 [2018-02-02 09:31:38,085 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,099 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,108 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,108 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:64, output treesize:60 [2018-02-02 09:31:38,176 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-02-02 09:31:38,179 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,179 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,180 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,180 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,181 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,182 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,182 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,183 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,183 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,184 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,185 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,185 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,187 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,187 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,188 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,188 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 175 [2018-02-02 09:31:38,189 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,208 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,217 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,217 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:75, output treesize:71 [2018-02-02 09:31:38,278 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 65 [2018-02-02 09:31:38,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,281 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,282 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,282 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,283 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,283 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,284 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,284 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,285 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,286 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,286 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,287 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,287 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,289 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,289 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,291 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,292 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 232 [2018-02-02 09:31:38,292 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,320 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,330 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,330 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:86, output treesize:82 [2018-02-02 09:31:38,398 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 74 [2018-02-02 09:31:38,400 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,401 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,402 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,402 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,403 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,404 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,404 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,405 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,406 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,406 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,407 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,407 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,408 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,409 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,409 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,410 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,410 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,411 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,412 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,412 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,413 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,413 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,414 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,415 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,415 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,416 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,417 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,417 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,418 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 297 [2018-02-02 09:31:38,419 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,461 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,473 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,473 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:97, output treesize:93 [2018-02-02 09:31:38,550 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 83 [2018-02-02 09:31:38,552 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,553 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,553 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,554 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,554 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,555 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,555 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,556 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,556 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,557 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,557 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,557 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,558 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,558 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,559 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,559 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,560 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,560 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,560 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,561 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,561 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,562 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,562 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,563 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,563 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,564 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,564 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,565 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,565 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,565 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,566 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,566 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,567 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,567 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,567 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,568 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,569 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 36 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 370 [2018-02-02 09:31:38,569 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,634 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,647 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,648 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:108, output treesize:104 [2018-02-02 09:31:38,737 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 92 [2018-02-02 09:31:38,745 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,746 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,748 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,749 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,750 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,751 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,753 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,754 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,756 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,757 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,766 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,767 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,768 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,770 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,771 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,772 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,773 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,774 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,776 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,777 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,778 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,779 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,779 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,780 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,781 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,782 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,783 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,784 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,784 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,785 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,786 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,787 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,788 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,788 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,789 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:38,790 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 45 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 451 [2018-02-02 09:31:38,791 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,887 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:38,908 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:38,908 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:124, output treesize:120 [2018-02-02 09:31:39,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 101 [2018-02-02 09:31:39,040 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,041 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,043 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,046 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,048 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,050 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,052 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,055 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,060 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,061 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,063 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,064 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,065 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,066 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,067 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,068 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,069 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,071 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,071 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,072 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,075 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,077 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,084 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,088 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,091 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,093 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 55 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 540 [2018-02-02 09:31:39,094 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:39,187 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:39,205 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:39,206 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:135, output treesize:131 [2018-02-02 09:31:39,312 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 110 [2018-02-02 09:31:39,316 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,317 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,319 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,320 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,321 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,322 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,323 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,325 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,325 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,326 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,328 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,329 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,331 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,332 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,333 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,334 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,335 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,335 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,338 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,338 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,339 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,340 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,342 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,343 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,344 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,346 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,347 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,348 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,349 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,350 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,351 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,352 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,354 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,354 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,355 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,356 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,357 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,358 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,361 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,362 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,363 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,364 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,365 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,367 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,368 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,369 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,370 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,372 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,373 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,374 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,376 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,377 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,379 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,383 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 55 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 551 [2018-02-02 09:31:39,384 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:39,490 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:39,516 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:39,517 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:151, output treesize:147 [2018-02-02 09:31:39,653 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 119 [2018-02-02 09:31:39,658 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,659 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,660 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,662 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,664 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,666 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,667 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,670 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,670 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,671 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,671 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,673 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,674 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,675 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,675 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,676 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,676 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,677 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,677 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,685 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,686 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,686 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,687 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,687 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,688 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,688 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,689 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,690 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,691 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,691 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,692 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,692 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,693 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,694 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,694 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,695 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,695 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,696 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,697 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,697 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,698 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,699 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,700 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,700 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,701 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,702 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,703 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:39,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 12 select indices, 12 select index equivalence classes, 55 disjoint index pairs (out of 66 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 562 [2018-02-02 09:31:39,706 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:39,819 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:39,848 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:39,848 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:167, output treesize:163 [2018-02-02 09:31:40,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 128 [2018-02-02 09:31:40,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,019 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,020 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,021 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,023 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,024 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,026 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,033 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,034 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,034 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,038 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,039 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,041 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,042 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,052 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,060 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,063 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,068 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,069 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,075 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,096 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,101 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,106 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,119 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,127 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,128 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,129 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,149 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,150 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,156 INFO L303 Elim1Store]: Index analysis took 153 ms [2018-02-02 09:31:40,157 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 13 select indices, 13 select index equivalence classes, 55 disjoint index pairs (out of 78 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 573 [2018-02-02 09:31:40,158 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:40,298 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:40,340 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 5 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:40,340 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:183, output treesize:179 [2018-02-02 09:31:40,496 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 168 treesize of output 137 [2018-02-02 09:31:40,503 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,504 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,507 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,508 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,509 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,510 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,512 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,516 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,519 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,527 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,530 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,531 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,533 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,534 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,536 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,537 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,540 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,544 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,548 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,552 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,553 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,555 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,556 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,558 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,562 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,566 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,569 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,572 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,574 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,575 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,577 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,581 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,585 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,589 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,617 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,627 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,631 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,641 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,644 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,647 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,666 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,681 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:40,690 INFO L303 Elim1Store]: Index analysis took 192 ms [2018-02-02 09:31:40,691 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 55 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 584 [2018-02-02 09:31:40,692 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:40,817 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:40,857 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:40,857 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 7 variables, input treesize:199, output treesize:195 [2018-02-02 09:31:41,055 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 179 treesize of output 146 [2018-02-02 09:31:41,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,088 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,126 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,128 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,138 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,140 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,141 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,154 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,159 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,163 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,166 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,167 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,169 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,176 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,178 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,182 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,185 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,186 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,188 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,197 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,198 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,202 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,206 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,207 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,217 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,219 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,222 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,228 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,235 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,236 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,240 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,252 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,253 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,257 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,308 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,313 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,319 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:41,328 INFO L303 Elim1Store]: Index analysis took 270 ms [2018-02-02 09:31:41,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 55 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 595 [2018-02-02 09:31:41,330 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:41,478 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-02 09:31:41,522 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-2 vars, End of recursive call: 7 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:41,522 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 8 variables, input treesize:215, output treesize:211 [2018-02-02 09:31:43,345 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:43,348 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:43,354 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-02 09:31:43,354 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:47, output treesize:35 [2018-02-02 09:31:43,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,596 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 162 treesize of output 142 [2018-02-02 09:31:43,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,617 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,628 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,633 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,644 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,648 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,652 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,655 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,658 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,662 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,670 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,673 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,674 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,680 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,685 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,689 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,697 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,703 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,708 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,714 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,718 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,721 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,725 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,730 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,733 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,759 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,761 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,765 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,770 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,774 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,777 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,781 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,785 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,789 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,794 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,797 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,800 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,802 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,804 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,809 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,813 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,816 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,820 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,832 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,836 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,872 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,879 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,880 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,895 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,898 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,903 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,907 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,912 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,917 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,922 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,927 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,930 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,936 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,940 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,945 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,950 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,952 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:43,957 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,002 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,009 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,013 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,026 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,029 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,042 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,050 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,066 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,075 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,095 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,156 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,184 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,200 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,223 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,236 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,241 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,260 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,274 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,277 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,293 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,294 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,296 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,305 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,310 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,314 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,319 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,323 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,327 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,337 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,344 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:44,591 INFO L303 Elim1Store]: Index analysis took 992 ms [2018-02-02 09:31:44,924 INFO L477 Elim1Store]: Elim1 applied some preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 117 disjoint index pairs (out of 136 index pairs), introduced 3 new quantified variables, introduced 25 case distinctions, treesize of input 142 treesize of output 1126 [2018-02-02 09:31:44,925 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-02-02 09:31:45,921 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,924 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,927 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,929 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,932 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,935 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,938 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,940 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,943 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,946 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,949 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,951 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,954 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,957 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,959 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,965 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,968 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,971 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,973 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,976 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,978 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,981 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,983 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,989 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,991 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,993 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,995 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,997 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:45,998 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,000 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,002 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,003 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,004 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,006 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,007 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,009 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,010 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,012 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,013 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,019 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,021 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,022 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,023 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,025 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,026 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,028 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,029 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,030 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,032 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,034 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,035 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,043 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,048 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,049 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,052 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,055 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,061 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,061 INFO L682 Elim1Store]: detected equality via solver [2018-02-02 09:31:46,067 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,072 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,092 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,098 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:46,144 INFO L303 Elim1Store]: Index analysis took 233 ms [2018-02-02 09:31:46,167 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 109 disjoint index pairs (out of 105 index pairs), introduced 1 new quantified variables, introduced 5 case distinctions, treesize of input 1004 treesize of output 1144 [2018-02-02 09:31:47,901 WARN L146 SmtUtils]: Spent 1729ms on a formula simplification. DAG size of input: 335 DAG size of output 202 [2018-02-02 09:31:47,912 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,914 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,915 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,916 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,918 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,919 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,920 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,922 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,923 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,924 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,925 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,926 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,928 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,928 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,929 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,930 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,931 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,932 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,933 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,933 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,934 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,935 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,936 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,937 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,938 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,939 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,942 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,945 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,946 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,947 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,948 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,949 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,949 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,950 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,951 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,952 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,953 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,953 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,954 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,955 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,956 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,957 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,958 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,958 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,959 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,961 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,965 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,968 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,969 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,970 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,971 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,975 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,976 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,977 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,978 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,979 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,980 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,981 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,982 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,984 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,985 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,987 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,988 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,989 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,990 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,991 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:47,992 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,009 INFO L303 Elim1Store]: Index analysis took 105 ms [2018-02-02 09:31:48,017 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 83 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 3 case distinctions, treesize of input 309 treesize of output 1049 [2018-02-02 09:31:48,019 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:48,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,666 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,667 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,670 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,671 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,672 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,673 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,675 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,676 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,677 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,677 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,679 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,680 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,681 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,682 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,683 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,684 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,685 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,686 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,687 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,688 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,689 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,690 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,690 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,692 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,693 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,694 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,695 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,699 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,702 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,703 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,704 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,705 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,706 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,707 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,708 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,709 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,710 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,711 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,713 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,713 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,714 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,715 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,716 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,717 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,718 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,719 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,720 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,721 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,722 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,723 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,724 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,725 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,726 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,728 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,729 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,730 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,731 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,732 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,733 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,733 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,734 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,735 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,736 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,739 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,744 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,745 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,746 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,749 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,762 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,764 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,765 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,767 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,768 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,770 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,771 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,772 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,774 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,776 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,777 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,778 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,779 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,780 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,781 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,782 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,783 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,784 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,785 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,785 INFO L682 Elim1Store]: detected equality via solver [2018-02-02 09:31:48,787 INFO L700 Elim1Store]: detected not equals via solver [2018-02-02 09:31:48,805 INFO L303 Elim1Store]: Index analysis took 143 ms [2018-02-02 09:31:48,813 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 83 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 3 case distinctions, treesize of input 126 treesize of output 911 [2018-02-02 09:31:48,814 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-02 09:31:49,128 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 2 xjuncts. Received shutdown request... [2018-02-02 09:31:59,832 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-02-02 09:31:59,832 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 09:31:59,835 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 09:31:59,835 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 09:31:59 BoogieIcfgContainer [2018-02-02 09:31:59,835 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 09:31:59,836 INFO L168 Benchmark]: Toolchain (without parser) took 63862.85 ms. Allocated memory was 395.8 MB in the beginning and 1.2 GB in the end (delta: 778.0 MB). Free memory was 352.7 MB in the beginning and 790.7 MB in the end (delta: -438.0 MB). Peak memory consumption was 748.7 MB. Max. memory is 5.3 GB. [2018-02-02 09:31:59,837 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 395.8 MB. Free memory is still 359.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 09:31:59,837 INFO L168 Benchmark]: CACSL2BoogieTranslator took 183.84 ms. Allocated memory is still 395.8 MB. Free memory was 352.7 MB in the beginning and 338.2 MB in the end (delta: 14.5 MB). Peak memory consumption was 14.5 MB. Max. memory is 5.3 GB. [2018-02-02 09:31:59,837 INFO L168 Benchmark]: Boogie Preprocessor took 32.85 ms. Allocated memory is still 395.8 MB. Free memory was 338.2 MB in the beginning and 336.9 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-02 09:31:59,837 INFO L168 Benchmark]: RCFGBuilder took 345.43 ms. Allocated memory is still 395.8 MB. Free memory was 336.9 MB in the beginning and 304.3 MB in the end (delta: 32.6 MB). Peak memory consumption was 32.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:31:59,838 INFO L168 Benchmark]: TraceAbstraction took 63298.04 ms. Allocated memory was 395.8 MB in the beginning and 1.2 GB in the end (delta: 778.0 MB). Free memory was 304.3 MB in the beginning and 790.7 MB in the end (delta: -486.5 MB). Peak memory consumption was 700.3 MB. Max. memory is 5.3 GB. [2018-02-02 09:31:59,838 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 395.8 MB. Free memory is still 359.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 183.84 ms. Allocated memory is still 395.8 MB. Free memory was 352.7 MB in the beginning and 338.2 MB in the end (delta: 14.5 MB). Peak memory consumption was 14.5 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 32.85 ms. Allocated memory is still 395.8 MB. Free memory was 338.2 MB in the beginning and 336.9 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 345.43 ms. Allocated memory is still 395.8 MB. Free memory was 336.9 MB in the beginning and 304.3 MB in the end (delta: 32.6 MB). Peak memory consumption was 32.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 63298.04 ms. Allocated memory was 395.8 MB in the beginning and 1.2 GB in the end (delta: 778.0 MB). Free memory was 304.3 MB in the beginning and 790.7 MB in the end (delta: -486.5 MB). Peak memory consumption was 700.3 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1441]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1441). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 95 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while SimplifyDDAWithTimeout was simplifying term of DAG size 19753. - StatisticsResult: Ultimate Automizer benchmark data CFG has 18 procedures, 118 locations, 19 error locations. TIMEOUT Result, 63.2s OverallTime, 30 OverallIterations, 16 TraceHistogramMax, 21.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 2910 SDtfs, 648 SDslu, 24461 SDs, 0 SdLazy, 6671 SolverSat, 180 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 3.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1479 GetRequests, 1023 SyntacticMatches, 5 SemanticMatches, 451 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 1957 ImplicationChecksByTransitivity, 25.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=125occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 29 MinimizatonAttempts, 32 StatesRemovedByMinimization, 7 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 6.5s SatisfiabilityAnalysisTime, 9.3s InterpolantComputationTime, 2727 NumberOfCodeBlocks, 2707 NumberOfCodeBlocksAsserted, 66 NumberOfCheckSat, 2683 ConstructedInterpolants, 175 QuantifiedInterpolants, 586303 SizeOfPredicates, 67 NumberOfNonLiveVariables, 5369 ConjunctsInSsa, 395 ConjunctsInUnsatCore, 44 InterpolantComputations, 18 PerfectInterpolantSequences, 183/1473 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_1_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_09-31-59-843.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_1_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_09-31-59-843.csv Completed graceful shutdown