java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/cstrcat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 09:46:52,561 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 09:46:52,563 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 09:46:52,573 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 09:46:52,573 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 09:46:52,574 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 09:46:52,575 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 09:46:52,576 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 09:46:52,578 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 09:46:52,578 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 09:46:52,579 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 09:46:52,579 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 09:46:52,580 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 09:46:52,581 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 09:46:52,582 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 09:46:52,583 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 09:46:52,585 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 09:46:52,587 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 09:46:52,588 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 09:46:52,588 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 09:46:52,590 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-02-02 09:46:52,594 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-02 09:46:52,595 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-02 09:46:52,595 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 09:46:52,605 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 09:46:52,605 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 09:46:52,606 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 09:46:52,606 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 09:46:52,606 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 09:46:52,606 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 09:46:52,607 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 09:46:52,607 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 09:46:52,607 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 09:46:52,607 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 09:46:52,607 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 09:46:52,607 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 09:46:52,608 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 09:46:52,608 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 09:46:52,608 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 09:46:52,608 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 09:46:52,608 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 09:46:52,608 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 09:46:52,609 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 09:46:52,609 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 09:46:52,609 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:46:52,609 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 09:46:52,609 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 09:46:52,638 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 09:46:52,651 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 09:46:52,657 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 09:46:52,659 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 09:46:52,659 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 09:46:52,660 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:46:52,814 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 09:46:52,816 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 09:46:52,816 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 09:46:52,816 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 09:46:52,822 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 09:46:52,823 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,825 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1482aa0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52, skipping insertion in model container [2018-02-02 09:46:52,825 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,835 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:46:52,861 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:46:52,946 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:46:52,958 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:46:52,962 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52 WrapperNode [2018-02-02 09:46:52,962 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 09:46:52,962 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 09:46:52,962 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 09:46:52,963 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 09:46:52,971 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,972 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,980 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,980 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,982 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,984 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,985 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... [2018-02-02 09:46:52,987 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 09:46:52,987 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 09:46:52,988 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 09:46:52,988 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 09:46:52,989 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:46:53,024 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 09:46:53,024 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 09:46:53,024 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrcat [2018-02-02 09:46:53,024 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 09:46:53,024 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 09:46:53,024 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 09:46:53,024 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 09:46:53,024 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 09:46:53,025 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 09:46:53,025 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 09:46:53,025 INFO L128 BoogieDeclarations]: Found specification of procedure cstrcat [2018-02-02 09:46:53,025 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 09:46:53,025 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 09:46:53,025 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 09:46:53,176 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 09:46:53,176 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:46:53 BoogieIcfgContainer [2018-02-02 09:46:53,176 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 09:46:53,177 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 09:46:53,177 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 09:46:53,179 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 09:46:53,179 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 09:46:52" (1/3) ... [2018-02-02 09:46:53,179 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43567440 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:46:53, skipping insertion in model container [2018-02-02 09:46:53,179 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:46:52" (2/3) ... [2018-02-02 09:46:53,179 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@43567440 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:46:53, skipping insertion in model container [2018-02-02 09:46:53,180 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:46:53" (3/3) ... [2018-02-02 09:46:53,181 INFO L107 eAbstractionObserver]: Analyzing ICFG cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:46:53,186 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 09:46:53,191 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 11 error locations. [2018-02-02 09:46:53,224 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 09:46:53,224 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 09:46:53,224 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 09:46:53,224 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 09:46:53,224 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 09:46:53,224 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 09:46:53,224 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 09:46:53,225 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 09:46:53,225 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 09:46:53,236 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states. [2018-02-02 09:46:53,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-02-02 09:46:53,244 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:53,245 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:53,245 INFO L371 AbstractCegarLoop]: === Iteration 1 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:53,249 INFO L82 PathProgramCache]: Analyzing trace with hash 104454547, now seen corresponding path program 1 times [2018-02-02 09:46:53,287 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:53,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:53,322 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:53,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,355 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:53,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 09:46:53,356 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:53,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,356 INFO L182 omatonBuilderFactory]: Interpolants [52#true, 53#false, 54#(= |#valid| |old(#valid)|)] [2018-02-02 09:46:53,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,357 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 09:46:53,365 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 09:46:53,366 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:46:53,367 INFO L87 Difference]: Start difference. First operand 49 states. Second operand 3 states. [2018-02-02 09:46:53,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:53,458 INFO L93 Difference]: Finished difference Result 50 states and 55 transitions. [2018-02-02 09:46:53,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 09:46:53,460 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-02-02 09:46:53,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:53,468 INFO L225 Difference]: With dead ends: 50 [2018-02-02 09:46:53,468 INFO L226 Difference]: Without dead ends: 46 [2018-02-02 09:46:53,525 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:46:53,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-02-02 09:46:53,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2018-02-02 09:46:53,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-02-02 09:46:53,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-02-02 09:46:53,551 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 11 [2018-02-02 09:46:53,551 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:53,552 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-02-02 09:46:53,552 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 09:46:53,552 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-02-02 09:46:53,552 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:46:53,552 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:53,552 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:53,552 INFO L371 AbstractCegarLoop]: === Iteration 2 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:53,552 INFO L82 PathProgramCache]: Analyzing trace with hash 1017224676, now seen corresponding path program 1 times [2018-02-02 09:46:53,553 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:53,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:53,568 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:53,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,625 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:53,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:46:53,626 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:53,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,626 INFO L182 omatonBuilderFactory]: Interpolants [151#true, 152#false, 153#(= 1 (select |#valid| |main_#t~malloc9.base|)), 154#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-02-02 09:46:53,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:46:53,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:46:53,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:46:53,627 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 4 states. [2018-02-02 09:46:53,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:53,675 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2018-02-02 09:46:53,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:46:53,676 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-02-02 09:46:53,676 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:53,677 INFO L225 Difference]: With dead ends: 45 [2018-02-02 09:46:53,677 INFO L226 Difference]: Without dead ends: 45 [2018-02-02 09:46:53,678 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:46:53,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-02-02 09:46:53,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-02-02 09:46:53,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-02-02 09:46:53,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2018-02-02 09:46:53,682 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 15 [2018-02-02 09:46:53,682 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:53,683 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2018-02-02 09:46:53,683 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:46:53,683 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2018-02-02 09:46:53,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:46:53,683 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:53,683 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:53,684 INFO L371 AbstractCegarLoop]: === Iteration 3 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:53,684 INFO L82 PathProgramCache]: Analyzing trace with hash 1017224677, now seen corresponding path program 1 times [2018-02-02 09:46:53,685 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:53,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:53,700 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:53,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,769 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:53,770 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:46:53,770 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:53,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,770 INFO L182 omatonBuilderFactory]: Interpolants [247#true, 248#false, 249#(<= 1 main_~length1~0), 250#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 251#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 252#(and (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:46:53,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,770 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:46:53,770 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:46:53,771 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:46:53,771 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 6 states. [2018-02-02 09:46:53,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:53,826 INFO L93 Difference]: Finished difference Result 44 states and 48 transitions. [2018-02-02 09:46:53,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:46:53,827 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-02-02 09:46:53,827 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:53,828 INFO L225 Difference]: With dead ends: 44 [2018-02-02 09:46:53,828 INFO L226 Difference]: Without dead ends: 44 [2018-02-02 09:46:53,828 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:46:53,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-02-02 09:46:53,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-02-02 09:46:53,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-02 09:46:53,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-02-02 09:46:53,832 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 15 [2018-02-02 09:46:53,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:53,832 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-02-02 09:46:53,832 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:46:53,832 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-02-02 09:46:53,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:46:53,833 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:53,833 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:53,833 INFO L371 AbstractCegarLoop]: === Iteration 4 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:53,833 INFO L82 PathProgramCache]: Analyzing trace with hash 1469193927, now seen corresponding path program 1 times [2018-02-02 09:46:53,834 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:53,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:53,845 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:53,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,868 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:53,868 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:46:53,868 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:53,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,868 INFO L182 omatonBuilderFactory]: Interpolants [343#true, 344#false, 345#(= 1 (select |#valid| |main_#t~malloc10.base|)), 346#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-02-02 09:46:53,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,869 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:46:53,869 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:46:53,869 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:46:53,869 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 4 states. [2018-02-02 09:46:53,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:53,911 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-02-02 09:46:53,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:46:53,911 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-02-02 09:46:53,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:53,912 INFO L225 Difference]: With dead ends: 43 [2018-02-02 09:46:53,912 INFO L226 Difference]: Without dead ends: 43 [2018-02-02 09:46:53,913 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:46:53,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-02-02 09:46:53,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-02-02 09:46:53,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-02-02 09:46:53,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-02-02 09:46:53,916 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 16 [2018-02-02 09:46:53,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:53,916 INFO L432 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-02-02 09:46:53,916 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:46:53,916 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-02-02 09:46:53,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:46:53,917 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:53,917 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:53,917 INFO L371 AbstractCegarLoop]: === Iteration 5 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:53,917 INFO L82 PathProgramCache]: Analyzing trace with hash 1469193928, now seen corresponding path program 1 times [2018-02-02 09:46:53,918 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:53,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:53,928 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:53,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,975 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:53,975 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:46:53,975 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:53,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,976 INFO L182 omatonBuilderFactory]: Interpolants [435#true, 436#false, 437#(<= 2 main_~length2~0), 438#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 439#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 440#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-02-02 09:46:53,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:53,976 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:46:53,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:46:53,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:46:53,976 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 6 states. [2018-02-02 09:46:54,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,065 INFO L93 Difference]: Finished difference Result 58 states and 62 transitions. [2018-02-02 09:46:54,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:46:54,065 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-02-02 09:46:54,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,067 INFO L225 Difference]: With dead ends: 58 [2018-02-02 09:46:54,067 INFO L226 Difference]: Without dead ends: 58 [2018-02-02 09:46:54,068 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:46:54,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-02-02 09:46:54,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 50. [2018-02-02 09:46:54,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-02-02 09:46:54,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-02-02 09:46:54,076 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 16 [2018-02-02 09:46:54,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,076 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-02-02 09:46:54,076 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:46:54,076 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-02-02 09:46:54,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:46:54,077 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,077 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,077 INFO L371 AbstractCegarLoop]: === Iteration 6 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,077 INFO L82 PathProgramCache]: Analyzing trace with hash 659847302, now seen corresponding path program 1 times [2018-02-02 09:46:54,078 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,087 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,133 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:54,133 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:46:54,134 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,134 INFO L182 omatonBuilderFactory]: Interpolants [560#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 561#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)), 555#true, 556#false, 557#(<= 1 main_~length1~0), 558#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 559#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0))] [2018-02-02 09:46:54,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,134 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:46:54,135 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:46:54,135 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:46:54,135 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 7 states. [2018-02-02 09:46:54,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,222 INFO L93 Difference]: Finished difference Result 49 states and 53 transitions. [2018-02-02 09:46:54,222 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:46:54,222 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 16 [2018-02-02 09:46:54,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,223 INFO L225 Difference]: With dead ends: 49 [2018-02-02 09:46:54,223 INFO L226 Difference]: Without dead ends: 49 [2018-02-02 09:46:54,223 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:46:54,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-02-02 09:46:54,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 42. [2018-02-02 09:46:54,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-02-02 09:46:54,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 46 transitions. [2018-02-02 09:46:54,226 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 46 transitions. Word has length 16 [2018-02-02 09:46:54,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,227 INFO L432 AbstractCegarLoop]: Abstraction has 42 states and 46 transitions. [2018-02-02 09:46:54,227 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:46:54,227 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-02-02 09:46:54,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-02 09:46:54,227 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,227 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,228 INFO L371 AbstractCegarLoop]: === Iteration 7 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,228 INFO L82 PathProgramCache]: Analyzing trace with hash -262056781, now seen corresponding path program 1 times [2018-02-02 09:46:54,228 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,237 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,265 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:54,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 09:46:54,265 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,266 INFO L182 omatonBuilderFactory]: Interpolants [661#true, 662#false, 663#(= 1 (select |#valid| main_~nondetString2~0.base)), 664#(= 1 (select |#valid| |cstrcat_#in~s1.base|)), 665#(= 1 (select |#valid| cstrcat_~s~0.base))] [2018-02-02 09:46:54,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,266 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:46:54,267 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:46:54,267 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:46:54,267 INFO L87 Difference]: Start difference. First operand 42 states and 46 transitions. Second operand 5 states. [2018-02-02 09:46:54,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,317 INFO L93 Difference]: Finished difference Result 41 states and 45 transitions. [2018-02-02 09:46:54,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:46:54,318 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-02-02 09:46:54,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,318 INFO L225 Difference]: With dead ends: 41 [2018-02-02 09:46:54,318 INFO L226 Difference]: Without dead ends: 41 [2018-02-02 09:46:54,319 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:46:54,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2018-02-02 09:46:54,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2018-02-02 09:46:54,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41 states. [2018-02-02 09:46:54,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 45 transitions. [2018-02-02 09:46:54,320 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 45 transitions. Word has length 20 [2018-02-02 09:46:54,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,321 INFO L432 AbstractCegarLoop]: Abstraction has 41 states and 45 transitions. [2018-02-02 09:46:54,321 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:46:54,321 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 45 transitions. [2018-02-02 09:46:54,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-02 09:46:54,321 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,321 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,321 INFO L371 AbstractCegarLoop]: === Iteration 8 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,321 INFO L82 PathProgramCache]: Analyzing trace with hash -262056780, now seen corresponding path program 1 times [2018-02-02 09:46:54,322 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,332 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,396 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:54,396 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:46:54,396 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,397 INFO L182 omatonBuilderFactory]: Interpolants [752#(<= 2 main_~length2~0), 753#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 754#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 755#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 756#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 750#true, 751#false] [2018-02-02 09:46:54,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,397 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:46:54,397 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:46:54,397 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:46:54,397 INFO L87 Difference]: Start difference. First operand 41 states and 45 transitions. Second operand 7 states. [2018-02-02 09:46:54,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,489 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2018-02-02 09:46:54,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:46:54,489 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 20 [2018-02-02 09:46:54,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,490 INFO L225 Difference]: With dead ends: 46 [2018-02-02 09:46:54,490 INFO L226 Difference]: Without dead ends: 46 [2018-02-02 09:46:54,491 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:46:54,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-02-02 09:46:54,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 43. [2018-02-02 09:46:54,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-02-02 09:46:54,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-02-02 09:46:54,493 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 20 [2018-02-02 09:46:54,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,494 INFO L432 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-02-02 09:46:54,494 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:46:54,494 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-02-02 09:46:54,494 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-02-02 09:46:54,494 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,494 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,495 INFO L371 AbstractCegarLoop]: === Iteration 9 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,495 INFO L82 PathProgramCache]: Analyzing trace with hash 1316966177, now seen corresponding path program 1 times [2018-02-02 09:46:54,495 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,504 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,576 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,576 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:54,576 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 09:46:54,577 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,577 INFO L182 omatonBuilderFactory]: Interpolants [854#true, 855#false, 856#(<= 2 main_~length2~0), 857#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 858#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 859#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 860#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 861#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-02-02 09:46:54,577 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,577 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:46:54,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:46:54,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:46:54,577 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 8 states. [2018-02-02 09:46:54,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,689 INFO L93 Difference]: Finished difference Result 61 states and 68 transitions. [2018-02-02 09:46:54,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:46:54,690 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 23 [2018-02-02 09:46:54,690 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,692 INFO L225 Difference]: With dead ends: 61 [2018-02-02 09:46:54,692 INFO L226 Difference]: Without dead ends: 61 [2018-02-02 09:46:54,692 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:46:54,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-02-02 09:46:54,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 46. [2018-02-02 09:46:54,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-02-02 09:46:54,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 51 transitions. [2018-02-02 09:46:54,695 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 51 transitions. Word has length 23 [2018-02-02 09:46:54,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,696 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 51 transitions. [2018-02-02 09:46:54,696 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:46:54,696 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 51 transitions. [2018-02-02 09:46:54,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:46:54,697 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,697 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,697 INFO L371 AbstractCegarLoop]: === Iteration 10 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,697 INFO L82 PathProgramCache]: Analyzing trace with hash -2123766212, now seen corresponding path program 1 times [2018-02-02 09:46:54,698 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,706 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,738 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:54,738 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:46:54,738 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,738 INFO L182 omatonBuilderFactory]: Interpolants [979#true, 980#false, 981#(= 1 (select |#valid| main_~nondetString1~0.base)), 982#(= 1 (select |#valid| |cstrcat_#in~s2.base|)), 983#(= 1 (select |#valid| cstrcat_~s2.base)), 984#(= 1 (select |#valid| |cstrcat_#t~post3.base|))] [2018-02-02 09:46:54,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,739 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:46:54,739 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:46:54,739 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:46:54,739 INFO L87 Difference]: Start difference. First operand 46 states and 51 transitions. Second operand 6 states. [2018-02-02 09:46:54,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,783 INFO L93 Difference]: Finished difference Result 45 states and 50 transitions. [2018-02-02 09:46:54,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:46:54,783 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 24 [2018-02-02 09:46:54,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,784 INFO L225 Difference]: With dead ends: 45 [2018-02-02 09:46:54,784 INFO L226 Difference]: Without dead ends: 45 [2018-02-02 09:46:54,784 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:46:54,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-02-02 09:46:54,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-02-02 09:46:54,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-02-02 09:46:54,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 50 transitions. [2018-02-02 09:46:54,786 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 50 transitions. Word has length 24 [2018-02-02 09:46:54,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,786 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 50 transitions. [2018-02-02 09:46:54,786 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:46:54,786 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 50 transitions. [2018-02-02 09:46:54,786 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:46:54,786 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,786 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,786 INFO L371 AbstractCegarLoop]: === Iteration 11 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,787 INFO L82 PathProgramCache]: Analyzing trace with hash -2123766211, now seen corresponding path program 1 times [2018-02-02 09:46:54,787 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,792 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,866 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:54,866 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 09:46:54,866 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,866 INFO L182 omatonBuilderFactory]: Interpolants [1079#true, 1080#false, 1081#(<= 1 main_~length1~0), 1082#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0)), 1083#(and (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 1084#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 1085#(and (= 0 |cstrcat_#in~s2.offset|) (<= 1 (select |#length| |cstrcat_#in~s2.base|))), 1086#(and (= 0 cstrcat_~s2.offset) (<= 1 (select |#length| cstrcat_~s2.base))), 1087#(and (= |cstrcat_#t~post3.offset| 0) (<= 1 (select |#length| |cstrcat_#t~post3.base|)))] [2018-02-02 09:46:54,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,867 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:46:54,867 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:46:54,867 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:46:54,867 INFO L87 Difference]: Start difference. First operand 45 states and 50 transitions. Second operand 9 states. [2018-02-02 09:46:54,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:54,941 INFO L93 Difference]: Finished difference Result 52 states and 58 transitions. [2018-02-02 09:46:54,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:46:54,941 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-02-02 09:46:54,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:54,942 INFO L225 Difference]: With dead ends: 52 [2018-02-02 09:46:54,942 INFO L226 Difference]: Without dead ends: 52 [2018-02-02 09:46:54,943 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:46:54,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-02-02 09:46:54,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 48. [2018-02-02 09:46:54,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-02-02 09:46:54,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 53 transitions. [2018-02-02 09:46:54,945 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 53 transitions. Word has length 24 [2018-02-02 09:46:54,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:54,945 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 53 transitions. [2018-02-02 09:46:54,945 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:46:54,946 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 53 transitions. [2018-02-02 09:46:54,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-02 09:46:54,946 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:54,946 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:54,946 INFO L371 AbstractCegarLoop]: === Iteration 12 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:54,946 INFO L82 PathProgramCache]: Analyzing trace with hash -1412243135, now seen corresponding path program 1 times [2018-02-02 09:46:54,947 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:54,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:54,954 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:54,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,977 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:54,977 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:46:54,977 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:54,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,979 INFO L182 omatonBuilderFactory]: Interpolants [1200#(= 1 (select |#valid| main_~nondetString2~0.base)), 1201#(= 1 (select |#valid| |cstrcat_#in~s1.base|)), 1202#(= 1 (select |#valid| cstrcat_~s~0.base)), 1203#(= 1 (select |#valid| |cstrcat_#t~post2.base|)), 1198#true, 1199#false] [2018-02-02 09:46:54,979 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:54,979 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:46:54,979 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:46:54,979 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:46:54,979 INFO L87 Difference]: Start difference. First operand 48 states and 53 transitions. Second operand 6 states. [2018-02-02 09:46:55,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:55,019 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-02-02 09:46:55,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:46:55,019 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-02-02 09:46:55,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:55,019 INFO L225 Difference]: With dead ends: 47 [2018-02-02 09:46:55,019 INFO L226 Difference]: Without dead ends: 47 [2018-02-02 09:46:55,020 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:46:55,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-02 09:46:55,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-02-02 09:46:55,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-02-02 09:46:55,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-02-02 09:46:55,021 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 25 [2018-02-02 09:46:55,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:55,021 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-02-02 09:46:55,021 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:46:55,021 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-02-02 09:46:55,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-02 09:46:55,022 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:55,022 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:55,022 INFO L371 AbstractCegarLoop]: === Iteration 13 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:55,022 INFO L82 PathProgramCache]: Analyzing trace with hash -1412243134, now seen corresponding path program 1 times [2018-02-02 09:46:55,023 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:55,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:55,031 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:55,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,085 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:55,085 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 09:46:55,085 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:55,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,085 INFO L182 omatonBuilderFactory]: Interpolants [1302#true, 1303#false, 1304#(<= 2 main_~length2~0), 1305#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 1306#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 1307#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 1308#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 1309#(and (<= 0 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 2) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:46:55,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,086 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:46:55,086 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:46:55,086 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:46:55,086 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 8 states. [2018-02-02 09:46:55,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:55,169 INFO L93 Difference]: Finished difference Result 52 states and 58 transitions. [2018-02-02 09:46:55,169 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:46:55,169 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 25 [2018-02-02 09:46:55,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:55,169 INFO L225 Difference]: With dead ends: 52 [2018-02-02 09:46:55,169 INFO L226 Difference]: Without dead ends: 52 [2018-02-02 09:46:55,170 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:46:55,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-02-02 09:46:55,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-02-02 09:46:55,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-02 09:46:55,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 56 transitions. [2018-02-02 09:46:55,171 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 56 transitions. Word has length 25 [2018-02-02 09:46:55,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:55,172 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 56 transitions. [2018-02-02 09:46:55,172 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:46:55,172 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 56 transitions. [2018-02-02 09:46:55,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 09:46:55,172 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:55,172 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:55,172 INFO L371 AbstractCegarLoop]: === Iteration 14 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:55,172 INFO L82 PathProgramCache]: Analyzing trace with hash -786914924, now seen corresponding path program 2 times [2018-02-02 09:46:55,173 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:55,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:55,179 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:55,249 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:46:55,249 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:55,249 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-02 09:46:55,249 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:55,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,249 INFO L182 omatonBuilderFactory]: Interpolants [1424#false, 1425#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1426#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1427#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1428#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 1429#(= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)), 1430#(= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)), 1431#(= |cstrcat_#t~mem0| 0), 1423#true] [2018-02-02 09:46:55,249 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:46:55,250 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:46:55,250 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:46:55,250 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:46:55,250 INFO L87 Difference]: Start difference. First operand 51 states and 56 transitions. Second operand 9 states. [2018-02-02 09:46:55,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:55,308 INFO L93 Difference]: Finished difference Result 74 states and 79 transitions. [2018-02-02 09:46:55,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:46:55,308 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 26 [2018-02-02 09:46:55,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:55,308 INFO L225 Difference]: With dead ends: 74 [2018-02-02 09:46:55,308 INFO L226 Difference]: Without dead ends: 74 [2018-02-02 09:46:55,309 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:46:55,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-02-02 09:46:55,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 63. [2018-02-02 09:46:55,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-02-02 09:46:55,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 69 transitions. [2018-02-02 09:46:55,317 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 69 transitions. Word has length 26 [2018-02-02 09:46:55,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:55,317 INFO L432 AbstractCegarLoop]: Abstraction has 63 states and 69 transitions. [2018-02-02 09:46:55,318 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:46:55,318 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 69 transitions. [2018-02-02 09:46:55,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 09:46:55,318 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:55,318 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:55,318 INFO L371 AbstractCegarLoop]: === Iteration 15 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:55,318 INFO L82 PathProgramCache]: Analyzing trace with hash 1513907666, now seen corresponding path program 1 times [2018-02-02 09:46:55,319 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:55,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:55,329 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:55,454 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:46:55,455 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:55,455 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-02-02 09:46:55,455 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:55,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,455 INFO L182 omatonBuilderFactory]: Interpolants [1584#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1585#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 1586#(= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)), 1587#(= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)), 1588#(= |cstrcat_#t~mem0| 0), 1577#true, 1578#false, 1579#(<= 1 main_~length1~0), 1580#(<= main_~length2~0 (+ main_~length1~0 1)), 1581#(and (<= main_~length2~0 (+ main_~length1~0 1)) (<= 1 main_~length3~0)), 1582#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1583#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= main_~length3~0 1))] [2018-02-02 09:46:55,456 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:46:55,456 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 09:46:55,456 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 09:46:55,456 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:46:55,456 INFO L87 Difference]: Start difference. First operand 63 states and 69 transitions. Second operand 12 states. [2018-02-02 09:46:55,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:55,674 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-02-02 09:46:55,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:46:55,674 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 26 [2018-02-02 09:46:55,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:55,675 INFO L225 Difference]: With dead ends: 102 [2018-02-02 09:46:55,675 INFO L226 Difference]: Without dead ends: 102 [2018-02-02 09:46:55,676 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=150, Invalid=500, Unknown=0, NotChecked=0, Total=650 [2018-02-02 09:46:55,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-02-02 09:46:55,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 64. [2018-02-02 09:46:55,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-02-02 09:46:55,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 71 transitions. [2018-02-02 09:46:55,680 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 71 transitions. Word has length 26 [2018-02-02 09:46:55,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:55,681 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 71 transitions. [2018-02-02 09:46:55,681 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 09:46:55,681 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 71 transitions. [2018-02-02 09:46:55,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 09:46:55,681 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:55,682 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:55,682 INFO L371 AbstractCegarLoop]: === Iteration 16 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:55,682 INFO L82 PathProgramCache]: Analyzing trace with hash -175036076, now seen corresponding path program 1 times [2018-02-02 09:46:55,682 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:55,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:55,690 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:55,815 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,815 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:55,815 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 09:46:55,815 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:55,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,816 INFO L182 omatonBuilderFactory]: Interpolants [1792#(and (or (<= 3 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 1793#(and (= cstrcat_~s~0.offset 0) (or (<= 3 (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0))), 1794#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 1795#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 1783#true, 1784#false, 1785#(<= 1 main_~length1~0), 1786#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 1787#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 1788#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 1789#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))), 1790#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 1791#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= 3 (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s1.offset|))] [2018-02-02 09:46:55,816 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:55,816 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 09:46:55,816 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 09:46:55,816 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:46:55,816 INFO L87 Difference]: Start difference. First operand 64 states and 71 transitions. Second operand 13 states. [2018-02-02 09:46:56,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:56,031 INFO L93 Difference]: Finished difference Result 83 states and 93 transitions. [2018-02-02 09:46:56,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 09:46:56,032 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 26 [2018-02-02 09:46:56,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:56,032 INFO L225 Difference]: With dead ends: 83 [2018-02-02 09:46:56,032 INFO L226 Difference]: Without dead ends: 83 [2018-02-02 09:46:56,033 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=83, Invalid=379, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:46:56,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-02-02 09:46:56,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 75. [2018-02-02 09:46:56,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-02-02 09:46:56,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 85 transitions. [2018-02-02 09:46:56,035 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 85 transitions. Word has length 26 [2018-02-02 09:46:56,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:56,036 INFO L432 AbstractCegarLoop]: Abstraction has 75 states and 85 transitions. [2018-02-02 09:46:56,036 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 09:46:56,036 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 85 transitions. [2018-02-02 09:46:56,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 09:46:56,037 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:56,037 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:56,037 INFO L371 AbstractCegarLoop]: === Iteration 17 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:56,037 INFO L82 PathProgramCache]: Analyzing trace with hash -707331403, now seen corresponding path program 1 times [2018-02-02 09:46:56,038 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:56,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:56,045 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:56,139 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:56,139 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:56,139 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 09:46:56,140 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:56,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:56,140 INFO L182 omatonBuilderFactory]: Interpolants [1972#true, 1973#false, 1974#(<= 2 main_~length2~0), 1975#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 1976#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 1977#(and (<= 2 (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s1.offset|)), 1978#(and (<= 2 (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 1979#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 1980#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:46:56,140 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:56,140 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:46:56,140 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:46:56,140 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:46:56,140 INFO L87 Difference]: Start difference. First operand 75 states and 85 transitions. Second operand 9 states. [2018-02-02 09:46:56,277 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:56,277 INFO L93 Difference]: Finished difference Result 85 states and 97 transitions. [2018-02-02 09:46:56,277 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:46:56,277 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-02-02 09:46:56,277 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:56,278 INFO L225 Difference]: With dead ends: 85 [2018-02-02 09:46:56,278 INFO L226 Difference]: Without dead ends: 85 [2018-02-02 09:46:56,278 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:46:56,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-02-02 09:46:56,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 80. [2018-02-02 09:46:56,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-02-02 09:46:56,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 91 transitions. [2018-02-02 09:46:56,281 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 91 transitions. Word has length 28 [2018-02-02 09:46:56,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:56,281 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 91 transitions. [2018-02-02 09:46:56,281 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:46:56,281 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 91 transitions. [2018-02-02 09:46:56,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:46:56,282 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:56,282 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:56,282 INFO L371 AbstractCegarLoop]: === Iteration 18 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:56,282 INFO L82 PathProgramCache]: Analyzing trace with hash -653260906, now seen corresponding path program 1 times [2018-02-02 09:46:56,283 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:56,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:56,292 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:56,494 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:56,494 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:46:56,494 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-02-02 09:46:56,494 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:56,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:56,495 INFO L182 omatonBuilderFactory]: Interpolants [2158#true, 2159#false, 2160#(<= 1 main_~length1~0), 2161#(and (<= 1 main_~length1~0) (<= main_~length2~0 2)), 2162#(and (<= main_~length2~0 (+ main_~length3~0 1)) (<= 1 main_~length1~0)), 2163#(and (<= 1 main_~length1~0) (<= main_~length1~0 1)), 2164#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1) (<= main_~length1~0 1)), 2165#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2166#(and (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2167#(and (<= 1 main_~length1~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2168#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2169#(= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) |cstrcat_#in~s2.offset|)), 2170#(= 0 (select (select |#memory_int| cstrcat_~s2.base) cstrcat_~s2.offset)), 2171#(= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 2172#(= |cstrcat_#t~mem5| 0)] [2018-02-02 09:46:56,495 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:56,495 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 09:46:56,496 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 09:46:56,496 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:46:56,496 INFO L87 Difference]: Start difference. First operand 80 states and 91 transitions. Second operand 15 states. [2018-02-02 09:46:56,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:56,926 INFO L93 Difference]: Finished difference Result 161 states and 178 transitions. [2018-02-02 09:46:56,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:46:56,926 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 29 [2018-02-02 09:46:56,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:56,927 INFO L225 Difference]: With dead ends: 161 [2018-02-02 09:46:56,927 INFO L226 Difference]: Without dead ends: 161 [2018-02-02 09:46:56,927 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 197 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=233, Invalid=889, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:46:56,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-02-02 09:46:56,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 134. [2018-02-02 09:46:56,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-02-02 09:46:56,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 153 transitions. [2018-02-02 09:46:56,932 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 153 transitions. Word has length 29 [2018-02-02 09:46:56,932 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:56,932 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 153 transitions. [2018-02-02 09:46:56,932 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 09:46:56,932 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 153 transitions. [2018-02-02 09:46:56,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:46:56,933 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:56,933 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:56,933 INFO L371 AbstractCegarLoop]: === Iteration 19 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:56,933 INFO L82 PathProgramCache]: Analyzing trace with hash -434406188, now seen corresponding path program 1 times [2018-02-02 09:46:56,934 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:56,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:56,944 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:57,123 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:57,123 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:57,123 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 09:46:57,123 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:57,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:57,123 INFO L182 omatonBuilderFactory]: Interpolants [2506#true, 2507#false, 2508#(<= 1 main_~length1~0), 2509#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 2510#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (= (select |#valid| main_~nondetString1~0.base) 1)) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2511#(and (<= 1 main_~length1~0) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base |main_#t~malloc10.base|))) (= main_~nondetString1~0.offset 0)), 2512#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2513#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 2 (select |#length| main_~nondetString1~0.base)))), 2514#(and (= 0 |cstrcat_#in~s2.offset|) (or (<= 2 (select |#length| |cstrcat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) |cstrcat_#in~s2.offset|)))), 2515#(and (or (<= 2 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) cstrcat_~s2.offset))) (= 0 cstrcat_~s2.offset)), 2516#(and (or (and (<= (+ cstrcat_~s2.offset 1) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))) (= |cstrcat_#t~post3.offset| 0) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 2517#(or (= |cstrcat_#t~mem5| 0) (and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset))), 2518#(and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset)), 2519#(and (<= 1 |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)))] [2018-02-02 09:46:57,123 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:57,124 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 09:46:57,124 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 09:46:57,124 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=152, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:46:57,124 INFO L87 Difference]: Start difference. First operand 134 states and 153 transitions. Second operand 14 states. [2018-02-02 09:46:57,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:57,382 INFO L93 Difference]: Finished difference Result 143 states and 163 transitions. [2018-02-02 09:46:57,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:46:57,382 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-02-02 09:46:57,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:57,383 INFO L225 Difference]: With dead ends: 143 [2018-02-02 09:46:57,383 INFO L226 Difference]: Without dead ends: 143 [2018-02-02 09:46:57,383 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=418, Unknown=0, NotChecked=0, Total=506 [2018-02-02 09:46:57,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-02-02 09:46:57,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 139. [2018-02-02 09:46:57,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-02 09:46:57,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 159 transitions. [2018-02-02 09:46:57,388 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 159 transitions. Word has length 29 [2018-02-02 09:46:57,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:57,388 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 159 transitions. [2018-02-02 09:46:57,388 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 09:46:57,389 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 159 transitions. [2018-02-02 09:46:57,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:46:57,389 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:57,389 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:57,389 INFO L371 AbstractCegarLoop]: === Iteration 20 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:57,390 INFO L82 PathProgramCache]: Analyzing trace with hash -409487743, now seen corresponding path program 2 times [2018-02-02 09:46:57,390 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:57,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:57,404 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:57,879 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:57,879 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:57,879 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 09:46:57,879 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:57,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:57,879 INFO L182 omatonBuilderFactory]: Interpolants [2820#true, 2821#false, 2822#(<= 1 main_~length1~0), 2823#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 2824#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 2825#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 2826#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2827#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 2828#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (or (not (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (= main_~nondetString1~0.offset 0)), 2829#(and (or (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (or (not (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))) (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) (* 2 main_~nondetString1~0.offset)))) (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 2830#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (or (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))) (= main_~nondetString1~0.offset 0)), 2831#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (and (<= 3 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)))) (= 0 |cstrcat_#in~s1.offset|)), 2832#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (<= 4 (select |#length| cstrcat_~s~0.base))) (or (<= 4 (select |#length| cstrcat_~s~0.base)) (= 3 (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 2833#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (<= 4 (select |#length| cstrcat_~s~0.base))) (or (<= 4 (select |#length| cstrcat_~s~0.base)) (= 3 (select |#length| cstrcat_~s~0.base)))) (= |cstrcat_#t~mem0| 0)) (= cstrcat_~s~0.offset 0)), 2834#(or (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 2835#(or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 2836#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 2837#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 2838#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-02-02 09:46:57,879 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:57,880 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 09:46:57,880 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 09:46:57,880 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=292, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:46:57,880 INFO L87 Difference]: Start difference. First operand 139 states and 159 transitions. Second operand 19 states. [2018-02-02 09:46:58,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:58,323 INFO L93 Difference]: Finished difference Result 171 states and 196 transitions. [2018-02-02 09:46:58,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 09:46:58,323 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 29 [2018-02-02 09:46:58,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:58,324 INFO L225 Difference]: With dead ends: 171 [2018-02-02 09:46:58,324 INFO L226 Difference]: Without dead ends: 171 [2018-02-02 09:46:58,325 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=155, Invalid=775, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:46:58,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-02-02 09:46:58,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 153. [2018-02-02 09:46:58,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-02-02 09:46:58,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 177 transitions. [2018-02-02 09:46:58,328 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 177 transitions. Word has length 29 [2018-02-02 09:46:58,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:58,329 INFO L432 AbstractCegarLoop]: Abstraction has 153 states and 177 transitions. [2018-02-02 09:46:58,329 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 09:46:58,329 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 177 transitions. [2018-02-02 09:46:58,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-02-02 09:46:58,329 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:58,329 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:58,329 INFO L371 AbstractCegarLoop]: === Iteration 21 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:58,329 INFO L82 PathProgramCache]: Analyzing trace with hash 1617883298, now seen corresponding path program 2 times [2018-02-02 09:46:58,330 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:58,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:58,335 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:58,395 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:58,395 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:58,395 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 09:46:58,395 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:58,395 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:58,395 INFO L182 omatonBuilderFactory]: Interpolants [3187#true, 3188#false, 3189#(= 0 |main_#t~malloc10.offset|), 3190#(= 0 main_~nondetString2~0.offset), 3191#(= 0 |cstrcat_#in~s1.offset|), 3192#(= cstrcat_~s~0.offset 0), 3193#(<= 1 cstrcat_~s~0.offset), 3194#(<= 2 cstrcat_~s~0.offset), 3195#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 3196#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:46:58,395 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:58,395 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:46:58,396 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:46:58,396 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:46:58,396 INFO L87 Difference]: Start difference. First operand 153 states and 177 transitions. Second operand 10 states. [2018-02-02 09:46:58,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:58,466 INFO L93 Difference]: Finished difference Result 162 states and 184 transitions. [2018-02-02 09:46:58,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 09:46:58,467 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 31 [2018-02-02 09:46:58,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:58,468 INFO L225 Difference]: With dead ends: 162 [2018-02-02 09:46:58,469 INFO L226 Difference]: Without dead ends: 162 [2018-02-02 09:46:58,469 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=186, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:46:58,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-02 09:46:58,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 141. [2018-02-02 09:46:58,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-02-02 09:46:58,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 161 transitions. [2018-02-02 09:46:58,473 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 161 transitions. Word has length 31 [2018-02-02 09:46:58,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:58,473 INFO L432 AbstractCegarLoop]: Abstraction has 141 states and 161 transitions. [2018-02-02 09:46:58,473 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:46:58,473 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 161 transitions. [2018-02-02 09:46:58,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-02 09:46:58,474 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:58,474 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:58,474 INFO L371 AbstractCegarLoop]: === Iteration 22 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:58,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1342276044, now seen corresponding path program 3 times [2018-02-02 09:46:58,475 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:58,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:58,487 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:58,868 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:58,869 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:58,869 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 09:46:58,869 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:58,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:58,869 INFO L182 omatonBuilderFactory]: Interpolants [3520#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 3521#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 3522#(and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= 0 main_~nondetString2~0.offset) (= main_~nondetString1~0.offset 0)), 3523#(and (or (and (or (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1))))) (<= 4 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 3524#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 3525#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 3526#(and (= cstrcat_~s~0.offset 1) (or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 3527#(and (or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0)) (= cstrcat_~s~0.offset 1)), 3528#(and (<= 2 cstrcat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 3529#(and (<= 2 cstrcat_~s~0.offset) (or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 3530#(and (<= 3 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 3531#(and (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 3512#true, 3513#false, 3514#(<= 1 main_~length1~0), 3515#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3516#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3517#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3518#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 3519#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:46:58,869 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:58,869 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:46:58,870 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:46:58,870 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=331, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:46:58,870 INFO L87 Difference]: Start difference. First operand 141 states and 161 transitions. Second operand 20 states. [2018-02-02 09:46:59,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:46:59,555 INFO L93 Difference]: Finished difference Result 177 states and 202 transitions. [2018-02-02 09:46:59,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:46:59,555 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 32 [2018-02-02 09:46:59,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:46:59,556 INFO L225 Difference]: With dead ends: 177 [2018-02-02 09:46:59,556 INFO L226 Difference]: Without dead ends: 177 [2018-02-02 09:46:59,556 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=151, Invalid=971, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:46:59,557 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-02 09:46:59,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 147. [2018-02-02 09:46:59,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-02-02 09:46:59,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 169 transitions. [2018-02-02 09:46:59,560 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 169 transitions. Word has length 32 [2018-02-02 09:46:59,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:46:59,560 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 169 transitions. [2018-02-02 09:46:59,560 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:46:59,560 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 169 transitions. [2018-02-02 09:46:59,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-02 09:46:59,561 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:46:59,561 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:46:59,561 INFO L371 AbstractCegarLoop]: === Iteration 23 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:46:59,561 INFO L82 PathProgramCache]: Analyzing trace with hash 785498486, now seen corresponding path program 1 times [2018-02-02 09:46:59,561 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:46:59,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:46:59,568 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:46:59,740 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:59,740 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:46:59,740 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:46:59,740 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:46:59,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:59,741 INFO L182 omatonBuilderFactory]: Interpolants [3884#true, 3885#false, 3886#(<= 1 main_~length3~0), 3887#(<= (+ main_~length1~0 1) main_~length2~0), 3888#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 3889#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 3890#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc10.base|))), 3891#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 3892#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 3893#(and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 3894#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 1) (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 3895#(and (= 0 cstrcat_~s2.offset) (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 3896#(and (<= 2 cstrcat_~s~0.offset) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 3897#(and (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 3898#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 2 |cstrcat_#t~post2.offset|)), 3899#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:46:59,741 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:46:59,741 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:46:59,741 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:46:59,741 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:46:59,741 INFO L87 Difference]: Start difference. First operand 147 states and 169 transitions. Second operand 16 states. [2018-02-02 09:47:00,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:00,079 INFO L93 Difference]: Finished difference Result 175 states and 199 transitions. [2018-02-02 09:47:00,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:47:00,079 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 33 [2018-02-02 09:47:00,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:00,080 INFO L225 Difference]: With dead ends: 175 [2018-02-02 09:47:00,080 INFO L226 Difference]: Without dead ends: 175 [2018-02-02 09:47:00,080 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=124, Invalid=688, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:47:00,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-02-02 09:47:00,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 160. [2018-02-02 09:47:00,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-02-02 09:47:00,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 185 transitions. [2018-02-02 09:47:00,082 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 185 transitions. Word has length 33 [2018-02-02 09:47:00,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:00,083 INFO L432 AbstractCegarLoop]: Abstraction has 160 states and 185 transitions. [2018-02-02 09:47:00,083 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:47:00,083 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 185 transitions. [2018-02-02 09:47:00,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-02 09:47:00,083 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:00,083 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:00,083 INFO L371 AbstractCegarLoop]: === Iteration 24 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:00,083 INFO L82 PathProgramCache]: Analyzing trace with hash -1281886369, now seen corresponding path program 2 times [2018-02-02 09:47:00,084 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:00,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:00,090 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:00,332 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:00,333 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:00,333 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:47:00,333 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:00,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:00,333 INFO L182 omatonBuilderFactory]: Interpolants [4261#true, 4262#false, 4263#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4264#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 4265#(and (or (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (not (= (+ main_~nondetString1~0.offset main_~length1~0) 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 4266#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 4267#(and (or (<= 3 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) 1)))) (= main_~nondetString1~0.offset 0)), 4268#(and (or (and (not (= |cstrcat_#in~s2.base| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) 1))) (<= (select |#length| |cstrcat_#in~s2.base|) 1) (<= 3 (select |#length| |cstrcat_#in~s2.base|))) (= 0 |cstrcat_#in~s2.offset|)), 4269#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 1) (and (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1)) (not (= cstrcat_~s2.base cstrcat_~s~0.base))) (<= 3 (select |#length| cstrcat_~s2.base)))), 4270#(and (or (and (not (= |cstrcat_#t~post2.base| cstrcat_~s2.base)) (<= cstrcat_~s2.offset (+ |cstrcat_#t~post3.offset| 1)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1))) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~s2.offset) (<= (+ cstrcat_~s2.offset 2) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))) (= |cstrcat_#t~post3.offset| 0) (= |cstrcat_#t~post3.base| cstrcat_~s2.base) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~s2.offset)), 4271#(and (or (and (= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~s2.base) 1)) (<= cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s2.offset 2) (select |#length| cstrcat_~s2.base)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= 1 cstrcat_~s2.offset)), 4272#(and (or (<= (+ cstrcat_~s2.offset 2) (select |#length| cstrcat_~s2.base)) (and (<= cstrcat_~s2.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s2.base) 1))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)) (<= 1 cstrcat_~s2.offset)), 4273#(and (<= 2 cstrcat_~s2.offset) (or (and (= 1 |cstrcat_#t~post3.offset|) (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))) (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))), 4274#(and (or (= |cstrcat_#t~mem5| 0) (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base))) (<= 2 cstrcat_~s2.offset)), 4275#(and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 2 cstrcat_~s2.offset)), 4276#(and (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)) (<= 2 |cstrcat_#t~post3.offset|))] [2018-02-02 09:47:00,333 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:00,333 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:47:00,333 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:47:00,334 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:47:00,334 INFO L87 Difference]: Start difference. First operand 160 states and 185 transitions. Second operand 16 states. [2018-02-02 09:47:00,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:00,643 INFO L93 Difference]: Finished difference Result 182 states and 212 transitions. [2018-02-02 09:47:00,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:47:00,644 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-02-02 09:47:00,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:00,644 INFO L225 Difference]: With dead ends: 182 [2018-02-02 09:47:00,644 INFO L226 Difference]: Without dead ends: 182 [2018-02-02 09:47:00,644 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=82, Invalid=470, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:47:00,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-02-02 09:47:00,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 170. [2018-02-02 09:47:00,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-02-02 09:47:00,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 198 transitions. [2018-02-02 09:47:00,648 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 198 transitions. Word has length 34 [2018-02-02 09:47:00,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:00,648 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 198 transitions. [2018-02-02 09:47:00,648 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:47:00,648 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 198 transitions. [2018-02-02 09:47:00,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:47:00,649 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:00,649 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:00,649 INFO L371 AbstractCegarLoop]: === Iteration 25 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:00,649 INFO L82 PathProgramCache]: Analyzing trace with hash 304009148, now seen corresponding path program 1 times [2018-02-02 09:47:00,649 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:00,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:00,655 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:00,713 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:00,713 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:00,713 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:47:00,714 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:00,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:00,714 INFO L182 omatonBuilderFactory]: Interpolants [4645#true, 4646#false, 4647#(= |#valid| |old(#valid)|), 4648#(and (= (store |#valid| |main_#t~malloc9.base| 0) |old(#valid)|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4649#(and (= (store (store |#valid| |main_#t~malloc9.base| 0) |main_#t~malloc10.base| 0) |old(#valid)|) (not (= |main_#t~malloc9.base| |main_#t~malloc10.base|))), 4650#(= |old(#valid)| (store |#valid| |main_#t~malloc10.base| 0))] [2018-02-02 09:47:00,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:00,714 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:47:00,714 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:47:00,714 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:47:00,714 INFO L87 Difference]: Start difference. First operand 170 states and 198 transitions. Second operand 6 states. [2018-02-02 09:47:00,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:00,799 INFO L93 Difference]: Finished difference Result 169 states and 197 transitions. [2018-02-02 09:47:00,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:47:00,799 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-02 09:47:00,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:00,800 INFO L225 Difference]: With dead ends: 169 [2018-02-02 09:47:00,800 INFO L226 Difference]: Without dead ends: 128 [2018-02-02 09:47:00,800 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:47:00,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-02-02 09:47:00,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 123. [2018-02-02 09:47:00,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-02-02 09:47:00,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 133 transitions. [2018-02-02 09:47:00,802 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 133 transitions. Word has length 35 [2018-02-02 09:47:00,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:00,802 INFO L432 AbstractCegarLoop]: Abstraction has 123 states and 133 transitions. [2018-02-02 09:47:00,802 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:47:00,802 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 133 transitions. [2018-02-02 09:47:00,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:47:00,802 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:00,802 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:00,802 INFO L371 AbstractCegarLoop]: === Iteration 26 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:00,803 INFO L82 PathProgramCache]: Analyzing trace with hash -1083771808, now seen corresponding path program 1 times [2018-02-02 09:47:00,803 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:00,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:00,810 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:01,024 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:01,025 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:01,025 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:47:01,025 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:01,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:01,025 INFO L182 omatonBuilderFactory]: Interpolants [4960#(and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 4961#(and (<= 2 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 4962#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset| 1) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 2 |cstrcat_#t~post2.offset|)), 4963#(and (<= (+ |cstrcat_#t~post2.offset| 2) (select |#length| |cstrcat_#t~post2.base|)) (<= 2 |cstrcat_#t~post2.offset|)), 4947#true, 4948#false, 4949#(<= 1 main_~length3~0), 4950#(<= (+ main_~length1~0 1) main_~length2~0), 4951#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4952#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 4953#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc10.base|))), 4954#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 4955#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 4956#(and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 4957#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) 1) (select |#length| cstrcat_~s~0.base)) (= cstrcat_~s~0.offset 0)), 4958#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| cstrcat_~s~0.offset 1) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post3.offset| 0) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 4959#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))))] [2018-02-02 09:47:01,025 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:01,026 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:47:01,026 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:47:01,026 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:47:01,026 INFO L87 Difference]: Start difference. First operand 123 states and 133 transitions. Second operand 17 states. [2018-02-02 09:47:01,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:01,393 INFO L93 Difference]: Finished difference Result 133 states and 143 transitions. [2018-02-02 09:47:01,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 09:47:01,393 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 35 [2018-02-02 09:47:01,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:01,394 INFO L225 Difference]: With dead ends: 133 [2018-02-02 09:47:01,394 INFO L226 Difference]: Without dead ends: 133 [2018-02-02 09:47:01,394 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=128, Invalid=684, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:47:01,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-02-02 09:47:01,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 114. [2018-02-02 09:47:01,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:47:01,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 124 transitions. [2018-02-02 09:47:01,397 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 124 transitions. Word has length 35 [2018-02-02 09:47:01,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:01,397 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 124 transitions. [2018-02-02 09:47:01,397 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:47:01,397 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 124 transitions. [2018-02-02 09:47:01,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:47:01,398 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:01,398 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:01,398 INFO L371 AbstractCegarLoop]: === Iteration 27 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:01,398 INFO L82 PathProgramCache]: Analyzing trace with hash -1600146015, now seen corresponding path program 4 times [2018-02-02 09:47:01,399 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:01,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:01,416 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:01,859 WARN L146 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 45 DAG size of output 35 [2018-02-02 09:47:02,003 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:02,004 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:02,004 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-02 09:47:02,004 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:02,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:02,004 INFO L182 omatonBuilderFactory]: Interpolants [5248#(and (or (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (or (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 5249#(and (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 5250#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))))), 5251#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 5252#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0)), 5253#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 5254#(or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 5255#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 5256#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 5257#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 5235#true, 5236#false, 5237#(<= 1 main_~length1~0), 5238#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5239#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5240#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5241#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 5242#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 5243#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 5244#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 5245#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 5246#(and (or (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 5247#(and (or (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 5 (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0))] [2018-02-02 09:47:02,004 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:02,005 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-02 09:47:02,005 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-02 09:47:02,005 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=444, Unknown=0, NotChecked=0, Total=506 [2018-02-02 09:47:02,005 INFO L87 Difference]: Start difference. First operand 114 states and 124 transitions. Second operand 23 states. [2018-02-02 09:47:02,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:02,961 INFO L93 Difference]: Finished difference Result 137 states and 149 transitions. [2018-02-02 09:47:02,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:47:02,961 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 35 [2018-02-02 09:47:02,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:02,961 INFO L225 Difference]: With dead ends: 137 [2018-02-02 09:47:02,961 INFO L226 Difference]: Without dead ends: 137 [2018-02-02 09:47:02,962 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 269 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=199, Invalid=1207, Unknown=0, NotChecked=0, Total=1406 [2018-02-02 09:47:02,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-02-02 09:47:02,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 120. [2018-02-02 09:47:02,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-02-02 09:47:02,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 131 transitions. [2018-02-02 09:47:02,964 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 131 transitions. Word has length 35 [2018-02-02 09:47:02,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:02,964 INFO L432 AbstractCegarLoop]: Abstraction has 120 states and 131 transitions. [2018-02-02 09:47:02,964 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-02 09:47:02,964 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 131 transitions. [2018-02-02 09:47:02,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 09:47:02,965 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:02,965 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:02,965 INFO L371 AbstractCegarLoop]: === Iteration 28 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:02,965 INFO L82 PathProgramCache]: Analyzing trace with hash 1381463977, now seen corresponding path program 2 times [2018-02-02 09:47:02,966 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:02,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:02,974 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:03,294 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:03,295 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:03,295 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 09:47:03,295 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:03,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:03,296 INFO L182 omatonBuilderFactory]: Interpolants [5545#true, 5546#false, 5547#(<= 1 main_~length3~0), 5548#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 5549#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 5550#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 5551#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 5552#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))), 5553#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)), 5554#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 5555#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 2) (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 5556#(and (or (<= (+ (select |#length| cstrcat_~s2.base) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0)), 5557#(and (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0) (or (<= (+ (select |#length| cstrcat_~s2.base) 2) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0))), 5558#(and (= 0 cstrcat_~s2.offset) (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 5559#(and (<= 2 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 5560#(and (<= 3 cstrcat_~s~0.offset) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 5561#(and (<= 3 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 5562#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 3 |cstrcat_#t~post2.offset|)), 5563#(and (<= 3 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:47:03,296 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:03,296 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 09:47:03,296 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 09:47:03,296 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=297, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:47:03,296 INFO L87 Difference]: Start difference. First operand 120 states and 131 transitions. Second operand 19 states. [2018-02-02 09:47:03,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:03,974 INFO L93 Difference]: Finished difference Result 141 states and 152 transitions. [2018-02-02 09:47:03,974 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 09:47:03,974 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 36 [2018-02-02 09:47:03,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:03,975 INFO L225 Difference]: With dead ends: 141 [2018-02-02 09:47:03,975 INFO L226 Difference]: Without dead ends: 141 [2018-02-02 09:47:03,975 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=116, Invalid=754, Unknown=0, NotChecked=0, Total=870 [2018-02-02 09:47:03,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-02-02 09:47:03,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 120. [2018-02-02 09:47:03,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-02-02 09:47:03,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 131 transitions. [2018-02-02 09:47:03,978 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 131 transitions. Word has length 36 [2018-02-02 09:47:03,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:03,978 INFO L432 AbstractCegarLoop]: Abstraction has 120 states and 131 transitions. [2018-02-02 09:47:03,978 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 09:47:03,978 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 131 transitions. [2018-02-02 09:47:03,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 09:47:03,979 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:03,979 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:03,979 INFO L371 AbstractCegarLoop]: === Iteration 29 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:03,979 INFO L82 PathProgramCache]: Analyzing trace with hash -107959532, now seen corresponding path program 5 times [2018-02-02 09:47:03,980 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:03,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:03,992 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:04,685 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:04,685 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:04,685 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:47:04,685 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:04,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:04,686 INFO L182 omatonBuilderFactory]: Interpolants [5856#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 5857#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (- 1))))) (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 2))) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 5858#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 2)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s1.offset|)), 5859#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (or (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= cstrcat_~s~0.offset 0)), 5860#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (or (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= cstrcat_~s~0.offset 0)), 5861#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= cstrcat_~s~0.offset 1)), 5862#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))) (= cstrcat_~s~0.offset 1)), 5863#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 5864#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 5865#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 5866#(or (= |cstrcat_#t~mem0| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 5867#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 5868#(and (or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= 0 cstrcat_~s~0.offset)), 5869#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 5870#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 5847#true, 5848#false, 5849#(<= 1 main_~length1~0), 5850#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5851#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5852#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5853#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 5854#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 5855#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:47:04,686 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:04,686 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:47:04,686 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:47:04,686 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=485, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:47:04,686 INFO L87 Difference]: Start difference. First operand 120 states and 131 transitions. Second operand 24 states. [2018-02-02 09:47:05,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:05,644 INFO L93 Difference]: Finished difference Result 150 states and 163 transitions. [2018-02-02 09:47:05,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 09:47:05,644 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 38 [2018-02-02 09:47:05,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:05,645 INFO L225 Difference]: With dead ends: 150 [2018-02-02 09:47:05,645 INFO L226 Difference]: Without dead ends: 150 [2018-02-02 09:47:05,645 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 291 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=220, Invalid=1340, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 09:47:05,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-02-02 09:47:05,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 126. [2018-02-02 09:47:05,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-02 09:47:05,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 138 transitions. [2018-02-02 09:47:05,648 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 138 transitions. Word has length 38 [2018-02-02 09:47:05,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:05,648 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 138 transitions. [2018-02-02 09:47:05,648 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:47:05,648 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 138 transitions. [2018-02-02 09:47:05,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 09:47:05,649 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:05,649 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:05,649 INFO L371 AbstractCegarLoop]: === Iteration 30 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:05,649 INFO L82 PathProgramCache]: Analyzing trace with hash 269048756, now seen corresponding path program 3 times [2018-02-02 09:47:05,650 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:05,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:05,655 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:05,913 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:47:05,913 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:05,913 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 09:47:05,913 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:05,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:05,914 INFO L182 omatonBuilderFactory]: Interpolants [6179#true, 6180#false, 6181#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 6182#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 6183#(and (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 6184#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6185#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6186#(and (not (= |cstrcat_#in~s2.base| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s2.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))), 6187#(and (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6188#(and (not (= |cstrcat_#t~post2.base| cstrcat_~s2.base)) (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| |cstrcat_#t~post3.base|) (- 1)))) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 6189#(and (not (= cstrcat_~s2.base cstrcat_~s~0.base)) (= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6190#(and (not (= |cstrcat_#t~post2.base| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))), 6191#(= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))), 6192#(= 0 (select (select |#memory_int| cstrcat_~s2.base) (+ (select |#length| cstrcat_~s2.base) (- 1)))), 6193#(or (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (or (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~s2.offset))), 6194#(or (= |cstrcat_#t~mem5| 0) (and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset))), 6195#(and (<= (+ cstrcat_~s2.offset 1) (select |#length| cstrcat_~s2.base)) (<= 1 cstrcat_~s2.offset)), 6196#(and (<= 1 |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)))] [2018-02-02 09:47:05,914 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:47:05,914 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 09:47:05,914 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 09:47:05,915 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:47:05,915 INFO L87 Difference]: Start difference. First operand 126 states and 138 transitions. Second operand 18 states. [2018-02-02 09:47:06,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:06,284 INFO L93 Difference]: Finished difference Result 125 states and 136 transitions. [2018-02-02 09:47:06,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 09:47:06,284 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-02-02 09:47:06,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:06,284 INFO L225 Difference]: With dead ends: 125 [2018-02-02 09:47:06,284 INFO L226 Difference]: Without dead ends: 95 [2018-02-02 09:47:06,285 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=140, Invalid=672, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:47:06,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-02-02 09:47:06,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 86. [2018-02-02 09:47:06,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-02-02 09:47:06,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 92 transitions. [2018-02-02 09:47:06,288 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 92 transitions. Word has length 39 [2018-02-02 09:47:06,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:06,288 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 92 transitions. [2018-02-02 09:47:06,288 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 09:47:06,288 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 92 transitions. [2018-02-02 09:47:06,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 09:47:06,289 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:06,289 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:06,289 INFO L371 AbstractCegarLoop]: === Iteration 31 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:06,289 INFO L82 PathProgramCache]: Analyzing trace with hash 394604694, now seen corresponding path program 3 times [2018-02-02 09:47:06,289 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:06,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:06,298 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:06,782 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:06,783 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:06,783 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 09:47:06,783 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:06,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:06,783 INFO L182 omatonBuilderFactory]: Interpolants [6432#(<= 1 main_~length3~0), 6433#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 6434#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 6435#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 6436#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 6437#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 6438#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 6439#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 6440#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 6441#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 6442#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem0| 0) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 6443#(and (or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 6444#(and (= cstrcat_~s~0.offset 1) (or (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))))), 6445#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6446#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 6447#(or (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~s2.offset) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)) (and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 6448#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 6449#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 6450#(or (and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 6451#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 6430#true, 6431#false] [2018-02-02 09:47:06,783 INFO L134 CoverageAnalysis]: Checked inductivity of 22 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:06,783 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:47:06,784 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:47:06,784 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=409, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:47:06,784 INFO L87 Difference]: Start difference. First operand 86 states and 92 transitions. Second operand 22 states. [2018-02-02 09:47:07,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:07,348 INFO L93 Difference]: Finished difference Result 96 states and 102 transitions. [2018-02-02 09:47:07,348 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-02 09:47:07,348 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 39 [2018-02-02 09:47:07,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:07,349 INFO L225 Difference]: With dead ends: 96 [2018-02-02 09:47:07,349 INFO L226 Difference]: Without dead ends: 96 [2018-02-02 09:47:07,349 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 223 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=133, Invalid=989, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:47:07,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-02-02 09:47:07,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 91. [2018-02-02 09:47:07,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-02-02 09:47:07,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 97 transitions. [2018-02-02 09:47:07,351 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 97 transitions. Word has length 39 [2018-02-02 09:47:07,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:07,351 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 97 transitions. [2018-02-02 09:47:07,351 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:47:07,351 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 97 transitions. [2018-02-02 09:47:07,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-02 09:47:07,351 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:07,351 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:07,351 INFO L371 AbstractCegarLoop]: === Iteration 32 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:07,351 INFO L82 PathProgramCache]: Analyzing trace with hash 708041921, now seen corresponding path program 6 times [2018-02-02 09:47:07,352 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:07,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:07,367 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:08,380 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:08,380 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:08,380 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:47:08,380 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:08,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:08,381 INFO L182 omatonBuilderFactory]: Interpolants [6663#true, 6664#false, 6665#(<= 1 main_~length1~0), 6666#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6667#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6668#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6669#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 6670#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 6671#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 6672#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 6673#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 6674#(and (or (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (<= 7 (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))))) (= 0 |cstrcat_#in~s1.offset|)), 6675#(and (or (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (<= 7 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 6676#(and (or (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (<= 7 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 6677#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))), 6678#(and (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))) (= cstrcat_~s~0.offset 1)), 6679#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6680#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0)), 6681#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6682#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))), 6683#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6684#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0)), 6685#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6686#(or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6687#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 6688#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 6689#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-02-02 09:47:08,381 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:08,381 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:47:08,381 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:47:08,381 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=618, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:47:08,381 INFO L87 Difference]: Start difference. First operand 91 states and 97 transitions. Second operand 27 states. [2018-02-02 09:47:09,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:09,701 INFO L93 Difference]: Finished difference Result 116 states and 124 transitions. [2018-02-02 09:47:09,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:47:09,701 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 41 [2018-02-02 09:47:09,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:09,701 INFO L225 Difference]: With dead ends: 116 [2018-02-02 09:47:09,702 INFO L226 Difference]: Without dead ends: 116 [2018-02-02 09:47:09,702 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 384 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=287, Invalid=1693, Unknown=0, NotChecked=0, Total=1980 [2018-02-02 09:47:09,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-02-02 09:47:09,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 97. [2018-02-02 09:47:09,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-02 09:47:09,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 104 transitions. [2018-02-02 09:47:09,703 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 104 transitions. Word has length 41 [2018-02-02 09:47:09,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:09,703 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 104 transitions. [2018-02-02 09:47:09,703 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:47:09,703 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 104 transitions. [2018-02-02 09:47:09,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 09:47:09,704 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:09,704 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:09,704 INFO L371 AbstractCegarLoop]: === Iteration 33 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:09,704 INFO L82 PathProgramCache]: Analyzing trace with hash -79154039, now seen corresponding path program 4 times [2018-02-02 09:47:09,704 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:09,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:09,714 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:10,523 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:10,523 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:10,523 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:47:10,523 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:10,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:10,524 INFO L182 omatonBuilderFactory]: Interpolants [6944#(and (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= main_~length3~0 (div (+ main_~length2~0 (+ main_~nondetString1~0.offset (- 2))) 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 6945#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (<= main_~length3~0 (div (+ (select |#length| |main_#t~malloc10.base|) (+ main_~nondetString1~0.offset (- 2))) 2))) (= main_~nondetString1~0.offset 0)), 6946#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (= (+ main_~length1~0 1) (+ main_~nondetString2~0.offset main_~length3~0)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString1~0.offset (* 2 main_~length1~0)) (select |#length| main_~nondetString2~0.base))) (<= main_~length3~0 (div (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 2))) 2)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~length3~0 1))) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~length3~0 1))))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 6947#(and (= 0 main_~nondetString2~0.offset) (or (and (or (and (<= (select |#length| main_~nondetString1~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (or (= (+ main_~nondetString2~0.offset main_~length3~0) (+ (select |#length| main_~nondetString1~0.base) 1)) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset main_~length3~0) (select |#length| main_~nondetString1~0.base)))) (<= (+ (* 2 main_~length3~0) 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 6948#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (select |#length| main_~nondetString1~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (<= 6 (+ (* 2 main_~nondetString2~0.offset) (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= main_~nondetString1~0.offset 0)), 6949#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (and (<= (select |#length| |cstrcat_#in~s2.base|) (div (select |#length| |cstrcat_#in~s1.base|) 2)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 1) (div (select |#length| |cstrcat_#in~s1.base|) 2))))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 6950#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (<= 2 (div (+ (select |#length| cstrcat_~s~0.base) (- 2)) 2)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) (div (select |#length| cstrcat_~s~0.base) 2)))))) (= cstrcat_~s~0.offset 0)), 6951#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (or (<= 2 (div (+ (select |#length| cstrcat_~s~0.base) (- 2)) 2)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) (div (select |#length| cstrcat_~s~0.base) 2)))))) (= cstrcat_~s~0.offset 0)), 6952#(or (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 6953#(or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (div (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))), 6954#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 6955#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 6956#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 6957#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 6958#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (or (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~s2.offset) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 6959#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 6960#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 6961#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 6962#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 6939#true, 6940#false, 6941#(<= 1 main_~length3~0), 6942#(and (<= 1 main_~length3~0) (or (= main_~length2~0 (+ main_~length3~0 main_~length1~0)) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0) 1) (* 2 main_~length2~0)))), 6943#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length3~0) (or (= main_~length2~0 (+ main_~length3~0 main_~length1~0)) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0) 1) (* 2 main_~length2~0))) (= (select |#valid| |main_#t~malloc9.base|) 1))] [2018-02-02 09:47:10,524 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:10,524 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:47:10,524 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:47:10,524 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:47:10,524 INFO L87 Difference]: Start difference. First operand 97 states and 104 transitions. Second operand 24 states. [2018-02-02 09:47:11,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:11,463 INFO L93 Difference]: Finished difference Result 111 states and 118 transitions. [2018-02-02 09:47:11,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:47:11,463 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 42 [2018-02-02 09:47:11,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:11,464 INFO L225 Difference]: With dead ends: 111 [2018-02-02 09:47:11,464 INFO L226 Difference]: Without dead ends: 111 [2018-02-02 09:47:11,464 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 274 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=148, Invalid=1258, Unknown=0, NotChecked=0, Total=1406 [2018-02-02 09:47:11,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-02-02 09:47:11,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 97. [2018-02-02 09:47:11,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-02 09:47:11,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 104 transitions. [2018-02-02 09:47:11,466 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 104 transitions. Word has length 42 [2018-02-02 09:47:11,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:11,467 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 104 transitions. [2018-02-02 09:47:11,467 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:47:11,467 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 104 transitions. [2018-02-02 09:47:11,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 09:47:11,467 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:11,467 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:11,467 INFO L371 AbstractCegarLoop]: === Iteration 34 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:11,468 INFO L82 PathProgramCache]: Analyzing trace with hash -1162932171, now seen corresponding path program 5 times [2018-02-02 09:47:11,468 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:11,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:11,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:11,951 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:11,951 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:11,951 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 09:47:11,951 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:11,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:11,951 INFO L182 omatonBuilderFactory]: Interpolants [7200#false, 7201#(<= 1 main_~length3~0), 7202#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7203#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7204#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 7205#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 7206#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 7207#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 7208#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7209#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 7210#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 7211#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem0| 0) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 7212#(and (or (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 1)), 7213#(and (= cstrcat_~s~0.offset 1) (or (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))))), 7214#(and (<= 2 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 7215#(and (<= 3 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 7216#(and (= |cstrcat_#t~post3.offset| 0) (<= 4 cstrcat_~s~0.offset) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 7217#(and (<= 4 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 7218#(and (<= 5 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))), 7219#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 5 |cstrcat_#t~post2.offset|)), 7220#(and (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)) (<= 5 |cstrcat_#t~post2.offset|)), 7199#true] [2018-02-02 09:47:11,952 INFO L134 CoverageAnalysis]: Checked inductivity of 31 backedges. 4 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:11,952 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:47:11,952 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:47:11,952 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:47:11,952 INFO L87 Difference]: Start difference. First operand 97 states and 104 transitions. Second operand 22 states. [2018-02-02 09:47:12,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:12,430 INFO L93 Difference]: Finished difference Result 116 states and 123 transitions. [2018-02-02 09:47:12,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:47:12,430 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 44 [2018-02-02 09:47:12,430 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:12,431 INFO L225 Difference]: With dead ends: 116 [2018-02-02 09:47:12,431 INFO L226 Difference]: Without dead ends: 101 [2018-02-02 09:47:12,431 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 235 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=135, Invalid=1055, Unknown=0, NotChecked=0, Total=1190 [2018-02-02 09:47:12,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-02-02 09:47:12,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 97. [2018-02-02 09:47:12,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-02 09:47:12,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 103 transitions. [2018-02-02 09:47:12,432 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 103 transitions. Word has length 44 [2018-02-02 09:47:12,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:12,433 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 103 transitions. [2018-02-02 09:47:12,433 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:47:12,433 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 103 transitions. [2018-02-02 09:47:12,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 09:47:12,433 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:12,433 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:12,434 INFO L371 AbstractCegarLoop]: === Iteration 35 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:12,434 INFO L82 PathProgramCache]: Analyzing trace with hash 692432884, now seen corresponding path program 7 times [2018-02-02 09:47:12,434 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:12,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:12,449 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:13,940 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:13,940 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:13,940 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-02 09:47:13,940 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:13,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:13,941 INFO L182 omatonBuilderFactory]: Interpolants [7460#true, 7461#false, 7462#(<= 1 main_~length1~0), 7463#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7464#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7465#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7466#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 7467#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7468#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 7469#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 7470#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 7471#(and (or (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))))) (= 0 |cstrcat_#in~s1.offset|)), 7472#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (or (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 7473#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (or (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 7474#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))), 7475#(and (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))) (= cstrcat_~s~0.offset 1)), 7476#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 2 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))))))), 7477#(or (= |cstrcat_#t~mem0| 0) (and (<= 2 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))))))), 7478#(or (and (<= 3 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 7479#(or (= |cstrcat_#t~mem0| 0) (and (<= 3 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 7480#(or (and (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (<= 4 cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 7481#(or (= |cstrcat_#t~mem0| 0) (and (or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))) (<= 4 cstrcat_~s~0.offset))), 7482#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 5 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 7483#(or (= |cstrcat_#t~mem0| 0) (and (<= 5 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 7484#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= 6 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 7485#(and (<= 6 cstrcat_~s~0.offset) (or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 7486#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 7 cstrcat_~s~0.offset)), 7487#(and (<= 8 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))] [2018-02-02 09:47:13,941 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:13,941 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-02 09:47:13,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-02 09:47:13,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=691, Unknown=0, NotChecked=0, Total=756 [2018-02-02 09:47:13,941 INFO L87 Difference]: Start difference. First operand 97 states and 103 transitions. Second operand 28 states. [2018-02-02 09:47:15,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:15,409 INFO L93 Difference]: Finished difference Result 122 states and 130 transitions. [2018-02-02 09:47:15,410 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:47:15,410 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 44 [2018-02-02 09:47:15,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:15,411 INFO L225 Difference]: With dead ends: 122 [2018-02-02 09:47:15,411 INFO L226 Difference]: Without dead ends: 122 [2018-02-02 09:47:15,411 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=185, Invalid=2071, Unknown=0, NotChecked=0, Total=2256 [2018-02-02 09:47:15,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-02-02 09:47:15,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 103. [2018-02-02 09:47:15,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-02-02 09:47:15,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 110 transitions. [2018-02-02 09:47:15,414 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 110 transitions. Word has length 44 [2018-02-02 09:47:15,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:15,414 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 110 transitions. [2018-02-02 09:47:15,414 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-02 09:47:15,414 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 110 transitions. [2018-02-02 09:47:15,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-02-02 09:47:15,414 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:15,415 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:15,415 INFO L371 AbstractCegarLoop]: === Iteration 36 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:15,415 INFO L82 PathProgramCache]: Analyzing trace with hash -563034186, now seen corresponding path program 6 times [2018-02-02 09:47:15,416 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:15,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:15,435 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:15,930 WARN L146 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 88 DAG size of output 37 [2018-02-02 09:47:16,727 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:16,727 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:16,727 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-02 09:47:16,727 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:16,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:16,728 INFO L182 omatonBuilderFactory]: Interpolants [7753#true, 7754#false, 7755#(<= 1 main_~length3~0), 7756#(and (<= 1 main_~length3~0) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0)) (* 2 main_~length2~0))), 7757#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length3~0) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0)) (* 2 main_~length2~0)) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7758#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 7759#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7760#(and (or (and (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= 0 main_~nondetString2~0.offset)), 7761#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (<= 1 main_~length3~0) (or (<= (+ (select |#length| main_~nondetString1~0.base) 1) (div (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) (- 1)))) 2)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ (* 2 main_~length3~0) 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))))) (= main_~nondetString1~0.offset 0)))), 7762#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 7 (+ (* 2 main_~nondetString2~0.offset) (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (select |#length| main_~nondetString2~0.base)) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base))) (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base)))) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1))))))) (or (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= 3 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base)))))) (= main_~nondetString1~0.offset 0)))), 7763#(and (or (and (= 0 |cstrcat_#in~s2.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|)))) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= 3 (select |#length| |cstrcat_#in~s2.base|))) (<= (* 2 (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|))) (<= 7 (select |#length| |cstrcat_#in~s1.base|)) (and (<= (select |#length| |cstrcat_#in~s2.base|) (div (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) 2)) (or (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 7764#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))) (<= 3 (select |#length| cstrcat_~s2.base))) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base)))) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (* 2 (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base))))) (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 7765#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))) (<= 3 (select |#length| cstrcat_~s2.base))) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base)))) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (* 2 (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base))))) (<= 7 (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0)))) (= cstrcat_~s~0.offset 0)), 7766#(or (and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))) (<= 3 (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) 1)) (- 1))))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (<= 1 cstrcat_~s~0.offset)) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 7767#(or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))))) (<= 3 (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (+ (- (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) 1)) (- 1))))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (<= 1 cstrcat_~s~0.offset))), 7768#(or (and (<= 2 cstrcat_~s~0.offset) (or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 7769#(or (and (<= 2 cstrcat_~s~0.offset) (or (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 7770#(or (and (<= 3 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 7771#(or (and (<= 3 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 7772#(or (and (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 7773#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (and (<= 5 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 7774#(or (and (<= 6 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~s2.offset) (= |cstrcat_#t~post3.base| cstrcat_~s2.base))), 7775#(or (and (<= 6 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 7776#(or (and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 7777#(and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:47:16,728 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:16,728 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-02 09:47:16,729 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-02 09:47:16,729 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=542, Unknown=0, NotChecked=0, Total=600 [2018-02-02 09:47:16,729 INFO L87 Difference]: Start difference. First operand 103 states and 110 transitions. Second operand 25 states. [2018-02-02 09:47:17,195 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 101 DAG size of output 100 [2018-02-02 09:47:17,397 WARN L146 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 117 DAG size of output 116 [2018-02-02 09:47:17,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:17,975 INFO L93 Difference]: Finished difference Result 117 states and 124 transitions. [2018-02-02 09:47:17,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:47:17,976 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 45 [2018-02-02 09:47:17,976 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:17,976 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:47:17,976 INFO L226 Difference]: Without dead ends: 117 [2018-02-02 09:47:17,976 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 296 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=149, Invalid=1411, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 09:47:17,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-02-02 09:47:17,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 103. [2018-02-02 09:47:17,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-02-02 09:47:17,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 110 transitions. [2018-02-02 09:47:17,978 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 110 transitions. Word has length 45 [2018-02-02 09:47:17,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:17,978 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 110 transitions. [2018-02-02 09:47:17,978 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-02 09:47:17,978 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 110 transitions. [2018-02-02 09:47:17,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 09:47:17,979 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:17,979 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:17,979 INFO L371 AbstractCegarLoop]: === Iteration 37 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:17,979 INFO L82 PathProgramCache]: Analyzing trace with hash 1979681826, now seen corresponding path program 7 times [2018-02-02 09:47:17,980 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:17,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:17,988 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:18,829 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:18,829 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:18,829 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:47:18,829 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:18,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:18,830 INFO L182 omatonBuilderFactory]: Interpolants [8032#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 8033#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 8034#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 8035#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))), 8036#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)), 8037#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 8038#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (<= 4 (select |#length| |cstrcat_#in~s2.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 8039#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 8040#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 8041#(and (= 0 cstrcat_~s2.offset) (or (and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))))), 8042#(and (= 0 cstrcat_~s2.offset) (or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (<= 1 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))))), 8043#(and (<= 2 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8044#(and (<= 2 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (or (<= 4 (select |#length| cstrcat_~s2.base)) (= |cstrcat_#t~mem0| 0) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 8045#(and (<= 3 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 8046#(and (= 0 cstrcat_~s2.offset) (<= 4 cstrcat_~s~0.offset) (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))), 8047#(and (<= 5 cstrcat_~s~0.offset) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base) 1)) (or (<= (+ cstrcat_~s2.offset 3) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ (* 2 (select |#length| |cstrcat_#t~post3.base|)) (* 2 |cstrcat_#t~post3.offset|) cstrcat_~s~0.offset) (+ (* 2 cstrcat_~s2.offset) (select |#length| cstrcat_~s~0.base) 2))) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)), 8048#(and (<= 5 cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s2.offset 3) (select |#length| cstrcat_~s2.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base) 1))), 8049#(and (<= 6 cstrcat_~s~0.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base) 1)) (or (<= (+ cstrcat_~s2.offset 2) (select |#length| cstrcat_~s2.base)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (+ cstrcat_~s2.offset (select |#length| cstrcat_~s~0.base))))), 8050#(and (<= 6 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 8051#(and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 8028#true, 8029#false, 8030#(<= 1 main_~length3~0), 8031#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0))] [2018-02-02 09:47:18,830 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 43 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:18,830 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:47:18,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:47:18,830 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:47:18,831 INFO L87 Difference]: Start difference. First operand 103 states and 110 transitions. Second operand 24 states. [2018-02-02 09:47:19,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:19,681 INFO L93 Difference]: Finished difference Result 122 states and 129 transitions. [2018-02-02 09:47:19,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 09:47:19,681 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 47 [2018-02-02 09:47:19,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:19,682 INFO L225 Difference]: With dead ends: 122 [2018-02-02 09:47:19,682 INFO L226 Difference]: Without dead ends: 122 [2018-02-02 09:47:19,682 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 250 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=137, Invalid=1195, Unknown=0, NotChecked=0, Total=1332 [2018-02-02 09:47:19,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-02-02 09:47:19,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 108. [2018-02-02 09:47:19,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-02-02 09:47:19,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 115 transitions. [2018-02-02 09:47:19,684 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 115 transitions. Word has length 47 [2018-02-02 09:47:19,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:19,686 INFO L432 AbstractCegarLoop]: Abstraction has 108 states and 115 transitions. [2018-02-02 09:47:19,686 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:47:19,686 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 115 transitions. [2018-02-02 09:47:19,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 09:47:19,686 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:19,686 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:19,686 INFO L371 AbstractCegarLoop]: === Iteration 38 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:19,686 INFO L82 PathProgramCache]: Analyzing trace with hash -459920415, now seen corresponding path program 8 times [2018-02-02 09:47:19,687 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:19,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:19,704 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:20,204 WARN L146 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 171 DAG size of output 69 [2018-02-02 09:47:20,360 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 133 DAG size of output 59 [2018-02-02 09:47:20,501 WARN L146 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 133 DAG size of output 59 [2018-02-02 09:47:20,656 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 135 DAG size of output 59 [2018-02-02 09:47:20,824 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 149 DAG size of output 65 [2018-02-02 09:47:20,994 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 151 DAG size of output 65 [2018-02-02 09:47:21,128 WARN L146 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 100 DAG size of output 56 [2018-02-02 09:47:21,733 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:21,733 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:21,733 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-02-02 09:47:21,733 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:21,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:21,734 INFO L182 omatonBuilderFactory]: Interpolants [8320#(and (or (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 8321#(and (or (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 8322#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))) (= cstrcat_~s~0.offset 1)), 8323#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))) (= cstrcat_~s~0.offset 1)), 8324#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8325#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8326#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))))), 8327#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1))))))), 8328#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8329#(or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 8330#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 8331#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))))), 8332#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8333#(or (= |cstrcat_#t~mem0| 0) (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))), 8334#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 8335#(or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 8336#(<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)), 8337#(and (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 8338#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 8308#true, 8309#false, 8310#(<= 1 main_~length1~0), 8311#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8312#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8313#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8314#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 8315#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 8316#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8317#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8318#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1))))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 8319#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| |cstrcat_#in~s1.base|))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))))) (= 0 |cstrcat_#in~s1.offset|))] [2018-02-02 09:47:21,734 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:21,734 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-02 09:47:21,734 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-02 09:47:21,734 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=114, Invalid=816, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:47:21,735 INFO L87 Difference]: Start difference. First operand 108 states and 115 transitions. Second operand 31 states. [2018-02-02 09:47:22,406 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 117 DAG size of output 116 [2018-02-02 09:47:23,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:23,802 INFO L93 Difference]: Finished difference Result 140 states and 149 transitions. [2018-02-02 09:47:23,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-02 09:47:23,803 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 47 [2018-02-02 09:47:23,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:23,803 INFO L225 Difference]: With dead ends: 140 [2018-02-02 09:47:23,803 INFO L226 Difference]: Without dead ends: 140 [2018-02-02 09:47:23,804 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 546 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=417, Invalid=2339, Unknown=0, NotChecked=0, Total=2756 [2018-02-02 09:47:23,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-02-02 09:47:23,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 114. [2018-02-02 09:47:23,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:47:23,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 122 transitions. [2018-02-02 09:47:23,805 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 122 transitions. Word has length 47 [2018-02-02 09:47:23,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:23,805 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 122 transitions. [2018-02-02 09:47:23,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-02 09:47:23,805 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 122 transitions. [2018-02-02 09:47:23,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 09:47:23,806 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:23,806 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:23,806 INFO L371 AbstractCegarLoop]: === Iteration 39 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:23,806 INFO L82 PathProgramCache]: Analyzing trace with hash -1926248087, now seen corresponding path program 8 times [2018-02-02 09:47:23,806 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:23,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:23,817 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:24,644 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 0 proven. 67 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:24,644 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:24,644 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:47:24,644 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:24,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:24,645 INFO L182 omatonBuilderFactory]: Interpolants [8640#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8641#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 8642#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 8643#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 8644#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)), 8645#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))), 8646#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 4) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 3) (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 8647#(and (or (and (= 0 |cstrcat_#in~s2.offset|) (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 6) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 4 1) (- 1))))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 8648#(and (or (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= cstrcat_~s~0.offset 0)), 8649#(and (or (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0)) (= cstrcat_~s~0.offset 0)), 8650#(or (and (= 0 cstrcat_~s2.offset) (<= 1 cstrcat_~s~0.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8651#(or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (= 0 cstrcat_~s2.offset) (<= 1 cstrcat_~s~0.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))))), 8652#(or (and (<= 2 cstrcat_~s~0.offset) (or (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 8653#(or (= |cstrcat_#t~mem0| 0) (and (<= 2 cstrcat_~s~0.offset) (or (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 8654#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 3 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)))), 8655#(or (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (and (<= 3 cstrcat_~s~0.offset) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)))), 8656#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 8657#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0)) (<= 4 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 8658#(or (and (<= 5 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 8659#(or (and (<= 6 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 8660#(or (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~s2.offset) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)) (and (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (<= 7 cstrcat_~s~0.offset))), 8661#(or (and (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (<= 7 cstrcat_~s~0.offset)) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 8662#(or (and (<= 7 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 8663#(and (<= 7 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 8637#true, 8638#false, 8639#(<= 1 main_~length3~0)] [2018-02-02 09:47:24,645 INFO L134 CoverageAnalysis]: Checked inductivity of 67 backedges. 0 proven. 67 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:24,645 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:47:24,645 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:47:24,645 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=640, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:47:24,645 INFO L87 Difference]: Start difference. First operand 114 states and 122 transitions. Second operand 27 states. [2018-02-02 09:47:25,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:25,861 INFO L93 Difference]: Finished difference Result 132 states and 140 transitions. [2018-02-02 09:47:25,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-02 09:47:25,861 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 48 [2018-02-02 09:47:25,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:25,862 INFO L225 Difference]: With dead ends: 132 [2018-02-02 09:47:25,862 INFO L226 Difference]: Without dead ends: 132 [2018-02-02 09:47:25,862 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 354 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=163, Invalid=1729, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 09:47:25,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-02-02 09:47:25,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 114. [2018-02-02 09:47:25,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:47:25,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 122 transitions. [2018-02-02 09:47:25,864 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 122 transitions. Word has length 48 [2018-02-02 09:47:25,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:25,864 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 122 transitions. [2018-02-02 09:47:25,864 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:47:25,864 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 122 transitions. [2018-02-02 09:47:25,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 09:47:25,864 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:25,865 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:25,865 INFO L371 AbstractCegarLoop]: === Iteration 40 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:25,865 INFO L82 PathProgramCache]: Analyzing trace with hash 1896148245, now seen corresponding path program 9 times [2018-02-02 09:47:25,865 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:25,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:25,872 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:26,943 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:26,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:26,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:47:26,943 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:26,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:26,943 INFO L182 omatonBuilderFactory]: Interpolants [8960#(or (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (and (= 2 cstrcat_~s~0.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 4) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= 4 (select |#length| cstrcat_~s2.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))))), 8961#(or (and (or (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= cstrcat_~s~0.offset (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 5) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8962#(or (= |cstrcat_#t~mem0| 0) (and (or (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (= 0 cstrcat_~s2.offset)) (and (= cstrcat_~s~0.offset (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 5) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8963#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))), 8964#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 8965#(or (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~s2.offset 1)) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 8966#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 8967#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 8968#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 8969#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 8970#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 8944#true, 8945#false, 8946#(<= 1 main_~length3~0), 8947#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8948#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1) (= (select |#length| |main_#t~malloc9.base|) main_~length1~0)), 8949#(and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= (select |#length| main_~nondetString1~0.base) main_~length1~0)), 8950#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 8951#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))))), 8952#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (or (= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base)))) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2))), 8953#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))) (= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (or (<= 4 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString2~0.offset)) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))))), 8954#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (select |#length| |cstrcat_#in~s2.base|))) (<= 4 (select |#length| |cstrcat_#in~s2.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (select |#length| |cstrcat_#in~s2.base|) (- 1))))) (= 0 |cstrcat_#in~s2.offset|) (or (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 8955#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))) (= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 8956#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (select |#length| cstrcat_~s2.base))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (- 1))))) (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))) (= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))))) (= cstrcat_~s~0.offset 0)), 8957#(or (and (or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1))))) (= 1 cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))))))) (= 0 cstrcat_~s2.offset)) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 8958#(or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (and (or (<= 4 (select |#length| cstrcat_~s2.base)) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1))) (- 1))))) (= 1 cstrcat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))))))) (= 0 cstrcat_~s2.offset))), 8959#(or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 cstrcat_~s2.offset) (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (or (and (= 2 cstrcat_~s~0.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 4) (+ (select |#length| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= 4 (select |#length| cstrcat_~s2.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 2))))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)))))] [2018-02-02 09:47:26,943 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:26,944 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:47:26,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:47:26,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=635, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:47:26,944 INFO L87 Difference]: Start difference. First operand 114 states and 122 transitions. Second operand 27 states. [2018-02-02 09:47:27,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:27,979 INFO L93 Difference]: Finished difference Result 142 states and 150 transitions. [2018-02-02 09:47:27,979 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:47:27,979 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 50 [2018-02-02 09:47:27,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:27,980 INFO L225 Difference]: With dead ends: 142 [2018-02-02 09:47:27,980 INFO L226 Difference]: Without dead ends: 142 [2018-02-02 09:47:27,980 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 362 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=193, Invalid=1613, Unknown=0, NotChecked=0, Total=1806 [2018-02-02 09:47:27,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-02-02 09:47:27,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 114. [2018-02-02 09:47:27,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:47:27,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 122 transitions. [2018-02-02 09:47:27,982 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 122 transitions. Word has length 50 [2018-02-02 09:47:27,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:27,982 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 122 transitions. [2018-02-02 09:47:27,982 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:47:27,982 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 122 transitions. [2018-02-02 09:47:27,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 09:47:27,982 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:27,982 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:27,982 INFO L371 AbstractCegarLoop]: === Iteration 41 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:27,982 INFO L82 PathProgramCache]: Analyzing trace with hash -543453996, now seen corresponding path program 9 times [2018-02-02 09:47:27,983 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:27,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:27,998 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:28,805 WARN L146 SmtUtils]: Spent 300ms on a formula simplification. DAG size of input: 187 DAG size of output 77 [2018-02-02 09:47:29,105 WARN L146 SmtUtils]: Spent 261ms on a formula simplification. DAG size of input: 161 DAG size of output 67 [2018-02-02 09:47:29,297 WARN L146 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 161 DAG size of output 67 [2018-02-02 09:47:29,499 WARN L146 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 163 DAG size of output 67 [2018-02-02 09:47:29,736 WARN L146 SmtUtils]: Spent 200ms on a formula simplification. DAG size of input: 177 DAG size of output 73 [2018-02-02 09:47:29,964 WARN L146 SmtUtils]: Spent 188ms on a formula simplification. DAG size of input: 179 DAG size of output 73 [2018-02-02 09:47:30,134 WARN L146 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 122 DAG size of output 64 [2018-02-02 09:47:30,310 WARN L146 SmtUtils]: Spent 140ms on a formula simplification. DAG size of input: 124 DAG size of output 64 [2018-02-02 09:47:31,011 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:31,011 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:31,011 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-02 09:47:31,011 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:31,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:31,012 INFO L182 omatonBuilderFactory]: Interpolants [9280#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1)))))), 9281#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9282#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0)), 9283#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9284#(or (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))))), 9285#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9286#(or (and (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0)), 9287#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 9288#(and (or (= |cstrcat_#t~mem0| 0) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (<= 0 cstrcat_~s~0.offset)), 9289#(and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 9290#(and (<= 2 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 9259#true, 9260#false, 9261#(<= 1 main_~length1~0), 9262#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9263#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9264#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9265#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 9266#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 9267#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 9268#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 9269#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 9270#(and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s1.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 5 1) 2) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (and (<= 4 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= 5 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ 5 1) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s1.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- 1)) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s1.base|))) (<= 10 (select |#length| |cstrcat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1)))))) (= 0 |cstrcat_#in~s1.offset|)), 9271#(and (= cstrcat_~s~0.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (or (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 10 (select |#length| cstrcat_~s~0.base))))), 9272#(and (or (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ 5 1) (- 1))))) (and (<= 6 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (<= 4 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1))))) (and (<= 9 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrcat_~s~0.base))) (and (or (<= 11 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= 10 (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 9273#(and (or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) (- 1)))))) (= cstrcat_~s~0.offset 1)), 9274#(and (= cstrcat_~s~0.offset 1) (or (and (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 4) 1) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s~0.offset 10) (select |#length| cstrcat_~s~0.base))) (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 4) 1) 1) (- 1))))))), 9275#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))), 9276#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (or (<= (+ cstrcat_~s~0.offset 9) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)))), 9277#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9278#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1))))))), 9279#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 1)) (- 1)))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))))] [2018-02-02 09:47:31,012 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:31,012 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-02 09:47:31,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-02 09:47:31,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=877, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:47:31,013 INFO L87 Difference]: Start difference. First operand 114 states and 122 transitions. Second operand 32 states. [2018-02-02 09:47:32,009 WARN L146 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 129 DAG size of output 123 [2018-02-02 09:47:32,285 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 122 DAG size of output 116 [2018-02-02 09:47:32,533 WARN L146 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 114 DAG size of output 108 [2018-02-02 09:47:33,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:33,634 INFO L93 Difference]: Finished difference Result 148 states and 158 transitions. [2018-02-02 09:47:33,634 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 09:47:33,635 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 50 [2018-02-02 09:47:33,635 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:33,635 INFO L225 Difference]: With dead ends: 148 [2018-02-02 09:47:33,635 INFO L226 Difference]: Without dead ends: 148 [2018-02-02 09:47:33,636 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 613 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=457, Invalid=2623, Unknown=0, NotChecked=0, Total=3080 [2018-02-02 09:47:33,636 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-02-02 09:47:33,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 120. [2018-02-02 09:47:33,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-02-02 09:47:33,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-02-02 09:47:33,637 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 50 [2018-02-02 09:47:33,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:33,637 INFO L432 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-02-02 09:47:33,637 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-02 09:47:33,637 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-02-02 09:47:33,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-02 09:47:33,638 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:33,638 INFO L351 BasicCegarLoop]: trace histogram [8, 8, 7, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:33,638 INFO L371 AbstractCegarLoop]: === Iteration 42 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:33,638 INFO L82 PathProgramCache]: Analyzing trace with hash -220821802, now seen corresponding path program 10 times [2018-02-02 09:47:33,638 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:33,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:33,654 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:34,813 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 0 proven. 88 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:34,814 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:34,814 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 09:47:34,814 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:34,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:34,814 INFO L182 omatonBuilderFactory]: Interpolants [9607#true, 9608#false, 9609#(<= 1 main_~length3~0), 9610#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 9611#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 9612#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 9613#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 9614#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))), 9615#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))))), 9616#(and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))))) (= 0 main_~nondetString2~0.offset)), 9617#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (or (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 5) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 5 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 6) (select |#length| |cstrcat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s1.base|) (- (select |#length| |cstrcat_#in~s2.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 7) (select |#length| |cstrcat_#in~s1.base|))))) (= 0 |cstrcat_#in~s2.offset|))) (= 0 |cstrcat_#in~s1.offset|)), 9618#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 9619#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- (select |#length| cstrcat_~s2.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) 6) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ 4 (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base)))))) (= cstrcat_~s~0.offset 0)), 9620#(and (= cstrcat_~s~0.offset 1) (or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 9621#(and (= cstrcat_~s~0.offset 1) (or (and (= 0 cstrcat_~s2.offset) (or (and (or (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ cstrcat_~s~0.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 4) (- 1))))) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))))) (= |cstrcat_#t~mem0| 0))), 9622#(or (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))), 9623#(or (= |cstrcat_#t~mem0| 0) (and (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 3) (- 1)))))), 9624#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 9625#(or (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (and (or (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base))) (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset 2) (- 1)))))), 9626#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9627#(or (and (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (or (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 2)) (- 1)))))) (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 9628#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))), 9629#(or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0) (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1))), 9630#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 9631#(or (and (= 0 cstrcat_~s2.offset) (<= (select |#length| cstrcat_~s2.base) 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 9632#(or (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~s2.offset) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)) (and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 9633#(or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 9634#(or (and (<= 1 cstrcat_~s~0.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset)), 9635#(or (and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 9636#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:47:34,815 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 0 proven. 88 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:34,815 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 09:47:34,815 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 09:47:34,815 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=781, Unknown=0, NotChecked=0, Total=870 [2018-02-02 09:47:34,815 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 30 states. [2018-02-02 09:47:35,320 WARN L146 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 103 DAG size of output 102 [2018-02-02 09:47:36,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:36,382 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2018-02-02 09:47:36,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 09:47:36,382 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 51 [2018-02-02 09:47:36,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:36,383 INFO L225 Difference]: With dead ends: 145 [2018-02-02 09:47:36,383 INFO L226 Difference]: Without dead ends: 145 [2018-02-02 09:47:36,384 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 541 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=290, Invalid=2160, Unknown=0, NotChecked=0, Total=2450 [2018-02-02 09:47:36,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-02 09:47:36,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 120. [2018-02-02 09:47:36,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-02-02 09:47:36,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 129 transitions. [2018-02-02 09:47:36,385 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 129 transitions. Word has length 51 [2018-02-02 09:47:36,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:36,386 INFO L432 AbstractCegarLoop]: Abstraction has 120 states and 129 transitions. [2018-02-02 09:47:36,386 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 09:47:36,386 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 129 transitions. [2018-02-02 09:47:36,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-02 09:47:36,386 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:36,386 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:36,386 INFO L371 AbstractCegarLoop]: === Iteration 43 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:36,386 INFO L82 PathProgramCache]: Analyzing trace with hash -1873015767, now seen corresponding path program 11 times [2018-02-02 09:47:36,387 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:36,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:36,395 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:36,902 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:36,902 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:36,902 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-02-02 09:47:36,902 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:36,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:36,902 INFO L182 omatonBuilderFactory]: Interpolants [9942#true, 9943#false, 9944#(<= 1 main_~length3~0), 9945#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 9946#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 9947#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 9948#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 9949#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 9950#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)))), 9951#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 9952#(and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (select |#length| |cstrcat_#in~s2.base|)) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|)))) (= 0 |cstrcat_#in~s2.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1))) (= 0 |cstrcat_#in~s1.offset|)), 9953#(and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (= 0 cstrcat_~s2.offset))) (= cstrcat_~s~0.offset 0)), 9954#(and (= cstrcat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem0| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (select |#length| cstrcat_~s2.base)) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base))))))), 9955#(or (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 9956#(or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (select |#length| cstrcat_~s2.base) (+ cstrcat_~s~0.offset (- 1)))) (+ (select |#length| cstrcat_~s~0.base) (+ cstrcat_~s~0.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 9957#(and (= 0 cstrcat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 9958#(and (= 0 cstrcat_~s2.offset) (or (= |cstrcat_#t~mem0| 0) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)))), 9959#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))), 9960#(and (= 0 cstrcat_~s2.offset) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))), 9961#(or (and (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~s2.offset 2)) (= |cstrcat_#t~post3.base| cstrcat_~s2.base)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 9962#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 2)) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))), 9963#(or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))), 9964#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)))), 9965#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 1 cstrcat_~s~0.offset)), 9966#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 9967#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:47:36,903 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:36,903 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-02-02 09:47:36,903 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-02-02 09:47:36,903 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=585, Unknown=0, NotChecked=0, Total=650 [2018-02-02 09:47:36,903 INFO L87 Difference]: Start difference. First operand 120 states and 129 transitions. Second operand 26 states. [2018-02-02 09:47:37,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:37,768 INFO L93 Difference]: Finished difference Result 148 states and 157 transitions. [2018-02-02 09:47:37,768 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 09:47:37,768 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 52 [2018-02-02 09:47:37,768 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:37,768 INFO L225 Difference]: With dead ends: 148 [2018-02-02 09:47:37,768 INFO L226 Difference]: Without dead ends: 148 [2018-02-02 09:47:37,769 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 434 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=216, Invalid=1854, Unknown=0, NotChecked=0, Total=2070 [2018-02-02 09:47:37,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-02-02 09:47:37,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 125. [2018-02-02 09:47:37,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-02 09:47:37,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 134 transitions. [2018-02-02 09:47:37,770 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 134 transitions. Word has length 52 [2018-02-02 09:47:37,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:37,771 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 134 transitions. [2018-02-02 09:47:37,771 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-02-02 09:47:37,771 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 134 transitions. [2018-02-02 09:47:37,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 09:47:37,771 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:37,771 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:37,771 INFO L371 AbstractCegarLoop]: === Iteration 44 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:37,771 INFO L82 PathProgramCache]: Analyzing trace with hash 133301058, now seen corresponding path program 12 times [2018-02-02 09:47:37,772 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:37,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:37,780 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:38,347 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 202 DAG size of output 87 [2018-02-02 09:47:38,801 WARN L146 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 164 DAG size of output 80 [2018-02-02 09:47:38,965 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 166 DAG size of output 80 [2018-02-02 09:47:39,512 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:39,512 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:39,512 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-02 09:47:39,512 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:39,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:39,513 INFO L182 omatonBuilderFactory]: Interpolants [10304#(and (or (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~post3.offset| 0) (= |cstrcat_#t~post3.base| cstrcat_~s2.base) (<= 7 cstrcat_~s~0.offset)), 10305#(and (or (<= (select |#length| cstrcat_~s2.base) (+ cstrcat_~s2.offset 1)) (<= (+ cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (<= 7 cstrcat_~s~0.offset)), 10306#(and (or (<= (select |#length| cstrcat_~s2.base) cstrcat_~s2.offset) (<= (+ cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base))) (<= 8 cstrcat_~s~0.offset)), 10307#(and (<= 8 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 10308#(and (<= 8 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 10281#true, 10282#false, 10283#(<= 1 main_~length3~0), 10284#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10285#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 10286#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10287#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 10288#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10289#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 10290#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) 1))) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset 1))) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (+ (- main_~nondetString2~0.offset) 3)) (+ (select |#length| main_~nondetString2~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset 2))) (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (+ (- (+ (- main_~nondetString2~0.offset) 3)) (select |#length| main_~nondetString2~0.base))) (select |#length| main_~nondetString2~0.base)) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= main_~nondetString1~0.offset 0)), 10291#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) |cstrcat_#in~s1.offset|)) (and (<= (+ (select |#length| |cstrcat_#in~s2.base|) 4) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- 3) (+ (select |#length| |cstrcat_#in~s1.base|) (- 1))) (- 1))))) (and (<= 7 (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 1) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s2.base|) 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (- (+ (- 3) (select |#length| |cstrcat_#in~s1.base|))) (select |#length| |cstrcat_#in~s1.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~s2.base|) 3) (select |#length| |cstrcat_#in~s1.base|))) (and (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 2) (select |#length| |cstrcat_#in~s1.base|)) (or (<= (+ (* 2 (select |#length| |cstrcat_#in~s2.base|)) 3) (select |#length| |cstrcat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s1.base|) (+ (+ (select |#length| |cstrcat_#in~s2.base|) 2) (- 1)))))) (<= 9 (select |#length| |cstrcat_#in~s1.base|))) (= 0 |cstrcat_#in~s2.offset|) (= 0 |cstrcat_#in~s1.offset|)), 10292#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= 9 (select |#length| cstrcat_~s~0.base)) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s~0.base))) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (= cstrcat_~s~0.offset 0)), 10293#(and (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 4) (select |#length| cstrcat_~s~0.base))) (<= 9 (select |#length| cstrcat_~s~0.base)) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 3) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 2) (select |#length| cstrcat_~s~0.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s2.base) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) 1)) (= |cstrcat_#t~mem0| 0) (and (<= 7 (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s~0.base))) (select |#length| cstrcat_~s~0.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~s2.base) 3) (select |#length| cstrcat_~s~0.base)))) (= cstrcat_~s~0.offset 0)), 10294#(and (or (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s~0.base) (- 1))))) (+ (select |#length| cstrcat_~s~0.base) (- 1)))) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s~0.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (= cstrcat_~s~0.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) 1) (- 1)))) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) 1)) (- 1))))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base)))) (= 0 cstrcat_~s2.offset) (<= 1 cstrcat_~s~0.offset)), 10295#(and (= 0 cstrcat_~s2.offset) (<= 1 cstrcat_~s~0.offset) (or (and (= |cstrcat_#t~mem0| 0) (= cstrcat_~s~0.offset 1)) (and (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (- (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s~0.base) (- 1))))) (+ (select |#length| cstrcat_~s~0.base) (- 1)))) (- 1))))) (and (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ (+ cstrcat_~s~0.offset 2) 1) (- 1)) (- 1))))) (<= (+ cstrcat_~s~0.offset 8) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (- (+ cstrcat_~s~0.offset 2)) (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s~0.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) 1) (- 1)))) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) 1)) (- 1))))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))))), 10296#(and (<= 2 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))))), 10297#(and (<= 2 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 7) (select |#length| cstrcat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (select |#length| cstrcat_~s~0.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (<= (+ (select |#length| cstrcat_~s2.base) cstrcat_~s~0.offset 2) (select |#length| cstrcat_~s~0.base))) (= |cstrcat_#t~mem0| 0) (and (or (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset 1) (select |#length| cstrcat_~s~0.base)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (select |#length| cstrcat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))))), 10298#(and (<= 3 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) 2) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))), 10299#(and (<= 3 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s~0.base) (+ (+ cstrcat_~s~0.offset (+ (select |#length| cstrcat_~s2.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 1))) (<= (+ cstrcat_~s~0.offset 6) (select |#length| cstrcat_~s~0.base)) (= |cstrcat_#t~mem0| 0) (<= (select |#length| cstrcat_~s2.base) 2))), 10300#(and (or (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s~0.base) cstrcat_~s~0.offset)))) (= 0 cstrcat_~s2.offset) (<= 4 cstrcat_~s~0.offset)), 10301#(and (= 0 cstrcat_~s2.offset) (<= 4 cstrcat_~s~0.offset) (or (<= (select |#length| cstrcat_~s2.base) 2) (and (<= (+ (* 2 (select |#length| cstrcat_~s2.base)) cstrcat_~s~0.offset) (+ (select |#length| cstrcat_~s~0.base) 2)) (= |cstrcat_#t~mem0| 0)) (<= (+ cstrcat_~s~0.offset 5) (select |#length| cstrcat_~s~0.base)))), 10302#(and (<= 5 cstrcat_~s~0.offset) (= 0 cstrcat_~s2.offset) (or (<= (+ cstrcat_~s~0.offset 4) (select |#length| cstrcat_~s~0.base)) (<= (select |#length| cstrcat_~s2.base) 2))), 10303#(and (= 0 cstrcat_~s2.offset) (or (<= (select |#length| cstrcat_~s2.base) 2) (<= (+ cstrcat_~s~0.offset 3) (select |#length| cstrcat_~s~0.base))) (<= 6 cstrcat_~s~0.offset))] [2018-02-02 09:47:39,513 INFO L134 CoverageAnalysis]: Checked inductivity of 76 backedges. 0 proven. 76 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:39,513 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-02 09:47:39,513 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-02 09:47:39,513 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=692, Unknown=0, NotChecked=0, Total=756 [2018-02-02 09:47:39,513 INFO L87 Difference]: Start difference. First operand 125 states and 134 transitions. Second operand 28 states. [2018-02-02 09:47:40,172 WARN L146 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 145 DAG size of output 144 [2018-02-02 09:47:40,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:41,000 INFO L93 Difference]: Finished difference Result 152 states and 161 transitions. [2018-02-02 09:47:41,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:47:41,000 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 53 [2018-02-02 09:47:41,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:41,000 INFO L225 Difference]: With dead ends: 152 [2018-02-02 09:47:41,000 INFO L226 Difference]: Without dead ends: 152 [2018-02-02 09:47:41,001 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 362 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=165, Invalid=1815, Unknown=0, NotChecked=0, Total=1980 [2018-02-02 09:47:41,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-02-02 09:47:41,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 125. [2018-02-02 09:47:41,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-02 09:47:41,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 134 transitions. [2018-02-02 09:47:41,002 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 134 transitions. Word has length 53 [2018-02-02 09:47:41,002 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:41,002 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 134 transitions. [2018-02-02 09:47:41,002 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-02 09:47:41,002 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 134 transitions. [2018-02-02 09:47:41,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 09:47:41,003 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:41,003 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:41,003 INFO L371 AbstractCegarLoop]: === Iteration 45 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:47:41,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1988666113, now seen corresponding path program 10 times [2018-02-02 09:47:41,003 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:41,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:41,017 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:42,151 WARN L146 SmtUtils]: Spent 382ms on a formula simplification. DAG size of input: 347 DAG size of output 83 [2018-02-02 09:47:42,529 WARN L146 SmtUtils]: Spent 338ms on a formula simplification. DAG size of input: 309 DAG size of output 74 [2018-02-02 09:47:42,875 WARN L146 SmtUtils]: Spent 303ms on a formula simplification. DAG size of input: 309 DAG size of output 74 [2018-02-02 09:47:43,203 WARN L146 SmtUtils]: Spent 282ms on a formula simplification. DAG size of input: 311 DAG size of output 74 Received shutdown request... [2018-02-02 09:47:43,608 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 09:47:43,611 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 09:47:43,611 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 09:47:43 BoogieIcfgContainer [2018-02-02 09:47:43,611 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 09:47:43,612 INFO L168 Benchmark]: Toolchain (without parser) took 50797.18 ms. Allocated memory was 401.1 MB in the beginning and 1.4 GB in the end (delta: 967.8 MB). Free memory was 359.3 MB in the beginning and 976.0 MB in the end (delta: -616.7 MB). Peak memory consumption was 351.1 MB. Max. memory is 5.3 GB. [2018-02-02 09:47:43,613 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 401.1 MB. Free memory is still 364.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 09:47:43,613 INFO L168 Benchmark]: CACSL2BoogieTranslator took 145.85 ms. Allocated memory is still 401.1 MB. Free memory was 358.0 MB in the beginning and 347.4 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:47:43,613 INFO L168 Benchmark]: Boogie Preprocessor took 24.80 ms. Allocated memory is still 401.1 MB. Free memory was 347.4 MB in the beginning and 346.1 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-02 09:47:43,613 INFO L168 Benchmark]: RCFGBuilder took 188.93 ms. Allocated memory is still 401.1 MB. Free memory was 346.1 MB in the beginning and 326.7 MB in the end (delta: 19.3 MB). Peak memory consumption was 19.3 MB. Max. memory is 5.3 GB. [2018-02-02 09:47:43,614 INFO L168 Benchmark]: TraceAbstraction took 50434.77 ms. Allocated memory was 401.1 MB in the beginning and 1.4 GB in the end (delta: 967.8 MB). Free memory was 326.7 MB in the beginning and 976.0 MB in the end (delta: -649.2 MB). Peak memory consumption was 318.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:47:43,614 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 401.1 MB. Free memory is still 364.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 145.85 ms. Allocated memory is still 401.1 MB. Free memory was 358.0 MB in the beginning and 347.4 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 24.80 ms. Allocated memory is still 401.1 MB. Free memory was 347.4 MB in the beginning and 346.1 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 188.93 ms. Allocated memory is still 401.1 MB. Free memory was 346.1 MB in the beginning and 326.7 MB in the end (delta: 19.3 MB). Peak memory consumption was 19.3 MB. Max. memory is 5.3 GB. * TraceAbstraction took 50434.77 ms. Allocated memory was 401.1 MB in the beginning and 1.4 GB in the end (delta: 967.8 MB). Free memory was 326.7 MB in the beginning and 976.0 MB in the end (delta: -649.2 MB). Peak memory consumption was 318.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 543). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 543). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 566). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 566). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - TimeoutResultAtElement [Line: 549]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 326. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 49 locations, 11 error locations. TIMEOUT Result, 50.3s OverallTime, 45 OverallIterations, 12 TraceHistogramMax, 25.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1322 SDtfs, 2781 SDslu, 10010 SDs, 0 SdLazy, 12351 SolverSat, 797 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1138 GetRequests, 54 SyntacticMatches, 4 SemanticMatches, 1080 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7213 ImplicationChecksByTransitivity, 35.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=170occurred in iteration=24, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 29/1230 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 44 MinimizatonAttempts, 586 StatesRemovedByMinimization, 37 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 21.4s InterpolantComputationTime, 1444 NumberOfCodeBlocks, 1444 NumberOfCodeBlocksAsserted, 44 NumberOfCheckSat, 1400 ConstructedInterpolants, 0 QuantifiedInterpolants, 1367245 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 44 InterpolantComputations, 16 PerfectInterpolantSequences, 29/1230 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_09-47-43-620.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_09-47-43-620.csv Completed graceful shutdown