java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/cstrncat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 09:47:51,957 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 09:47:51,958 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 09:47:51,968 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 09:47:51,968 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 09:47:51,968 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 09:47:51,969 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 09:47:51,970 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 09:47:51,971 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 09:47:51,972 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 09:47:51,972 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 09:47:51,972 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 09:47:51,973 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 09:47:51,974 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 09:47:51,975 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 09:47:51,976 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 09:47:51,978 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 09:47:51,980 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 09:47:51,981 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 09:47:51,982 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 09:47:51,983 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-02-02 09:47:51,988 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 09:47:51,998 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 09:47:51,999 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 09:47:52,000 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 09:47:52,000 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 09:47:52,000 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 09:47:52,000 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 09:47:52,000 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 09:47:52,000 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 09:47:52,001 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 09:47:52,002 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 09:47:52,002 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 09:47:52,002 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 09:47:52,002 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 09:47:52,002 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 09:47:52,002 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:47:52,003 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 09:47:52,003 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 09:47:52,031 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 09:47:52,044 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 09:47:52,049 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 09:47:52,050 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 09:47:52,050 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 09:47:52,052 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:47:52,183 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 09:47:52,184 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 09:47:52,185 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 09:47:52,185 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 09:47:52,191 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 09:47:52,191 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,194 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7206572c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52, skipping insertion in model container [2018-02-02 09:47:52,194 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,207 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:47:52,234 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:47:52,334 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:47:52,349 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:47:52,354 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52 WrapperNode [2018-02-02 09:47:52,354 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 09:47:52,355 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 09:47:52,355 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 09:47:52,355 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 09:47:52,364 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,364 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,372 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,372 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,375 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,377 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,378 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... [2018-02-02 09:47:52,379 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 09:47:52,379 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 09:47:52,379 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 09:47:52,379 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 09:47:52,380 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:47:52,416 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 09:47:52,416 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 09:47:52,416 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrncat [2018-02-02 09:47:52,416 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 09:47:52,416 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 09:47:52,416 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 09:47:52,416 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 09:47:52,416 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 09:47:52,416 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 09:47:52,417 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 09:47:52,417 INFO L128 BoogieDeclarations]: Found specification of procedure cstrncat [2018-02-02 09:47:52,417 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 09:47:52,417 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 09:47:52,417 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 09:47:52,580 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 09:47:52,581 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:47:52 BoogieIcfgContainer [2018-02-02 09:47:52,581 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 09:47:52,581 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 09:47:52,581 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 09:47:52,583 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 09:47:52,583 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 09:47:52" (1/3) ... [2018-02-02 09:47:52,584 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@d701189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:47:52, skipping insertion in model container [2018-02-02 09:47:52,584 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:47:52" (2/3) ... [2018-02-02 09:47:52,584 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@d701189 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:47:52, skipping insertion in model container [2018-02-02 09:47:52,584 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:47:52" (3/3) ... [2018-02-02 09:47:52,586 INFO L107 eAbstractionObserver]: Analyzing ICFG cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:47:52,592 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 09:47:52,596 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 15 error locations. [2018-02-02 09:47:52,619 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 09:47:52,619 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 09:47:52,619 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 09:47:52,620 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 09:47:52,620 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 09:47:52,620 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 09:47:52,620 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 09:47:52,620 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 09:47:52,621 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 09:47:52,632 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states. [2018-02-02 09:47:52,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-02-02 09:47:52,641 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:52,641 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:52,642 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:52,646 INFO L82 PathProgramCache]: Analyzing trace with hash 1927484354, now seen corresponding path program 1 times [2018-02-02 09:47:52,694 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:52,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:52,741 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:52,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:52,811 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:52,811 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 09:47:52,812 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:52,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:52,812 INFO L182 omatonBuilderFactory]: Interpolants [61#true, 62#false, 63#(= |#valid| |old(#valid)|)] [2018-02-02 09:47:52,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:52,814 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 09:47:52,821 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 09:47:52,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:47:52,823 INFO L87 Difference]: Start difference. First operand 58 states. Second operand 3 states. [2018-02-02 09:47:52,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:52,912 INFO L93 Difference]: Finished difference Result 59 states and 66 transitions. [2018-02-02 09:47:52,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 09:47:52,969 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-02-02 09:47:52,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:52,977 INFO L225 Difference]: With dead ends: 59 [2018-02-02 09:47:52,977 INFO L226 Difference]: Without dead ends: 55 [2018-02-02 09:47:52,978 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:47:52,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-02-02 09:47:53,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-02-02 09:47:53,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-02-02 09:47:53,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 61 transitions. [2018-02-02 09:47:53,007 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 61 transitions. Word has length 11 [2018-02-02 09:47:53,008 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,008 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 61 transitions. [2018-02-02 09:47:53,008 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 09:47:53,008 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 61 transitions. [2018-02-02 09:47:53,008 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:47:53,008 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,009 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,009 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,009 INFO L82 PathProgramCache]: Analyzing trace with hash 1621249811, now seen corresponding path program 1 times [2018-02-02 09:47:53,010 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,021 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,062 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,062 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:47:53,063 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,063 INFO L182 omatonBuilderFactory]: Interpolants [178#true, 179#false, 180#(<= main_~length1~0 1), 181#(<= main_~length1~0 main_~length2~0), 182#(<= (+ main_~length1~0 1) (+ main_~n~0 main_~length2~0))] [2018-02-02 09:47:53,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,065 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:47:53,065 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:47:53,065 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:47:53,066 INFO L87 Difference]: Start difference. First operand 55 states and 61 transitions. Second operand 5 states. [2018-02-02 09:47:53,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:53,124 INFO L93 Difference]: Finished difference Result 58 states and 65 transitions. [2018-02-02 09:47:53,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:47:53,125 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 15 [2018-02-02 09:47:53,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:53,126 INFO L225 Difference]: With dead ends: 58 [2018-02-02 09:47:53,126 INFO L226 Difference]: Without dead ends: 55 [2018-02-02 09:47:53,127 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:47:53,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-02-02 09:47:53,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2018-02-02 09:47:53,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 55 states. [2018-02-02 09:47:53,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 60 transitions. [2018-02-02 09:47:53,132 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 60 transitions. Word has length 15 [2018-02-02 09:47:53,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,132 INFO L432 AbstractCegarLoop]: Abstraction has 55 states and 60 transitions. [2018-02-02 09:47:53,132 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:47:53,133 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 60 transitions. [2018-02-02 09:47:53,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:47:53,133 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,133 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,133 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,134 INFO L82 PathProgramCache]: Analyzing trace with hash -1993659115, now seen corresponding path program 1 times [2018-02-02 09:47:53,135 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,151 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,212 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,212 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:47:53,212 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,213 INFO L182 omatonBuilderFactory]: Interpolants [300#true, 301#false, 302#(= 1 (select |#valid| |main_#t~malloc13.base|)), 303#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-02-02 09:47:53,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,213 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:47:53,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:47:53,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:47:53,214 INFO L87 Difference]: Start difference. First operand 55 states and 60 transitions. Second operand 4 states. [2018-02-02 09:47:53,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:53,262 INFO L93 Difference]: Finished difference Result 54 states and 59 transitions. [2018-02-02 09:47:53,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:47:53,263 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-02-02 09:47:53,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:53,264 INFO L225 Difference]: With dead ends: 54 [2018-02-02 09:47:53,264 INFO L226 Difference]: Without dead ends: 54 [2018-02-02 09:47:53,265 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:47:53,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-02-02 09:47:53,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2018-02-02 09:47:53,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-02-02 09:47:53,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 59 transitions. [2018-02-02 09:47:53,269 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 59 transitions. Word has length 15 [2018-02-02 09:47:53,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,269 INFO L432 AbstractCegarLoop]: Abstraction has 54 states and 59 transitions. [2018-02-02 09:47:53,269 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:47:53,269 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 59 transitions. [2018-02-02 09:47:53,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:47:53,270 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,270 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,270 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,270 INFO L82 PathProgramCache]: Analyzing trace with hash -1993659114, now seen corresponding path program 1 times [2018-02-02 09:47:53,271 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,284 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,388 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,388 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 09:47:53,389 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,389 INFO L182 omatonBuilderFactory]: Interpolants [416#(<= 1 main_~length2~0), 417#(and (<= 1 main_~length2~0) (<= 1 main_~n~0)), 418#(and (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0)), 419#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 420#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 421#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 414#true, 415#false] [2018-02-02 09:47:53,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,389 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:47:53,389 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:47:53,390 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:47:53,390 INFO L87 Difference]: Start difference. First operand 54 states and 59 transitions. Second operand 8 states. [2018-02-02 09:47:53,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:53,480 INFO L93 Difference]: Finished difference Result 53 states and 58 transitions. [2018-02-02 09:47:53,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:47:53,481 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 15 [2018-02-02 09:47:53,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:53,482 INFO L225 Difference]: With dead ends: 53 [2018-02-02 09:47:53,482 INFO L226 Difference]: Without dead ends: 53 [2018-02-02 09:47:53,482 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=84, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:47:53,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-02-02 09:47:53,485 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2018-02-02 09:47:53,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-02-02 09:47:53,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-02-02 09:47:53,486 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 15 [2018-02-02 09:47:53,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,487 INFO L432 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-02-02 09:47:53,487 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:47:53,487 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-02-02 09:47:53,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:47:53,487 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,487 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,488 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,488 INFO L82 PathProgramCache]: Analyzing trace with hash -1673890416, now seen corresponding path program 1 times [2018-02-02 09:47:53,489 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,499 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,520 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,520 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:47:53,520 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,520 INFO L182 omatonBuilderFactory]: Interpolants [536#true, 537#false, 538#(= 1 (select |#valid| |main_#t~malloc14.base|)), 539#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-02-02 09:47:53,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,520 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:47:53,520 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:47:53,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:47:53,521 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 4 states. [2018-02-02 09:47:53,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:53,557 INFO L93 Difference]: Finished difference Result 52 states and 57 transitions. [2018-02-02 09:47:53,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:47:53,558 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-02-02 09:47:53,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:53,558 INFO L225 Difference]: With dead ends: 52 [2018-02-02 09:47:53,558 INFO L226 Difference]: Without dead ends: 52 [2018-02-02 09:47:53,558 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:47:53,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-02-02 09:47:53,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2018-02-02 09:47:53,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-02-02 09:47:53,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 57 transitions. [2018-02-02 09:47:53,561 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 57 transitions. Word has length 16 [2018-02-02 09:47:53,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,561 INFO L432 AbstractCegarLoop]: Abstraction has 52 states and 57 transitions. [2018-02-02 09:47:53,561 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:47:53,561 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 57 transitions. [2018-02-02 09:47:53,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:47:53,561 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,561 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,562 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,562 INFO L82 PathProgramCache]: Analyzing trace with hash -1673890415, now seen corresponding path program 1 times [2018-02-02 09:47:53,562 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,627 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,627 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 09:47:53,627 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,628 INFO L182 omatonBuilderFactory]: Interpolants [646#true, 647#false, 648#(<= 1 main_~length2~0), 649#(and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 650#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))] [2018-02-02 09:47:53,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,628 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:47:53,628 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:47:53,628 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:47:53,629 INFO L87 Difference]: Start difference. First operand 52 states and 57 transitions. Second operand 5 states. [2018-02-02 09:47:53,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:53,664 INFO L93 Difference]: Finished difference Result 51 states and 56 transitions. [2018-02-02 09:47:53,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:47:53,665 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-02-02 09:47:53,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:53,665 INFO L225 Difference]: With dead ends: 51 [2018-02-02 09:47:53,665 INFO L226 Difference]: Without dead ends: 51 [2018-02-02 09:47:53,666 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:47:53,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-02-02 09:47:53,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-02-02 09:47:53,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-02 09:47:53,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 56 transitions. [2018-02-02 09:47:53,669 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 56 transitions. Word has length 16 [2018-02-02 09:47:53,669 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,669 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 56 transitions. [2018-02-02 09:47:53,669 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:47:53,669 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 56 transitions. [2018-02-02 09:47:53,670 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-02 09:47:53,670 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,670 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,670 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,670 INFO L82 PathProgramCache]: Analyzing trace with hash 1745382581, now seen corresponding path program 1 times [2018-02-02 09:47:53,671 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,680 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,708 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,709 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 09:47:53,709 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,709 INFO L182 omatonBuilderFactory]: Interpolants [755#true, 756#false, 757#(= 1 (select |#valid| main_~nondetString1~0.base)), 758#(= 1 (select |#valid| |cstrncat_#in~s1.base|)), 759#(= 1 (select |#valid| cstrncat_~s~0.base))] [2018-02-02 09:47:53,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,710 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:47:53,710 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:47:53,710 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:47:53,710 INFO L87 Difference]: Start difference. First operand 51 states and 56 transitions. Second operand 5 states. [2018-02-02 09:47:53,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:53,782 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-02-02 09:47:53,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:47:53,783 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-02-02 09:47:53,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:53,783 INFO L225 Difference]: With dead ends: 47 [2018-02-02 09:47:53,783 INFO L226 Difference]: Without dead ends: 47 [2018-02-02 09:47:53,784 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:47:53,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-02 09:47:53,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-02-02 09:47:53,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-02-02 09:47:53,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-02-02 09:47:53,786 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 20 [2018-02-02 09:47:53,787 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:53,787 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-02-02 09:47:53,787 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:47:53,787 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-02-02 09:47:53,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-02 09:47:53,787 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:53,787 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:53,787 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:53,788 INFO L82 PathProgramCache]: Analyzing trace with hash 1745382582, now seen corresponding path program 1 times [2018-02-02 09:47:53,788 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:53,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:53,800 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:53,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,898 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:53,898 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 09:47:53,898 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:53,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,898 INFO L182 omatonBuilderFactory]: Interpolants [864#(and (= cstrncat_~s~0.offset 0) (<= 1 (select |#length| cstrncat_~s~0.base))), 856#true, 857#false, 858#(<= 1 main_~length2~0), 859#(<= (+ main_~n~0 1) main_~length1~0), 860#(and (<= (+ main_~n~0 1) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 861#(and (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 862#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 863#(and (= 0 |cstrncat_#in~s1.offset|) (<= 1 (select |#length| |cstrncat_#in~s1.base|)))] [2018-02-02 09:47:53,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:53,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:47:53,899 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:47:53,899 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:47:53,899 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 9 states. [2018-02-02 09:47:54,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:54,042 INFO L93 Difference]: Finished difference Result 65 states and 74 transitions. [2018-02-02 09:47:54,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:47:54,044 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 20 [2018-02-02 09:47:54,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:54,047 INFO L225 Difference]: With dead ends: 65 [2018-02-02 09:47:54,047 INFO L226 Difference]: Without dead ends: 65 [2018-02-02 09:47:54,048 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:47:54,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-02-02 09:47:54,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 60. [2018-02-02 09:47:54,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-02-02 09:47:54,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 71 transitions. [2018-02-02 09:47:54,052 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 71 transitions. Word has length 20 [2018-02-02 09:47:54,052 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:54,052 INFO L432 AbstractCegarLoop]: Abstraction has 60 states and 71 transitions. [2018-02-02 09:47:54,052 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:47:54,052 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 71 transitions. [2018-02-02 09:47:54,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-02-02 09:47:54,053 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:54,053 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:54,053 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:54,053 INFO L82 PathProgramCache]: Analyzing trace with hash 1818413707, now seen corresponding path program 1 times [2018-02-02 09:47:54,054 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:54,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:54,072 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:54,192 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,192 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:54,192 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 09:47:54,192 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:54,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,193 INFO L182 omatonBuilderFactory]: Interpolants [1008#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 2 main_~length1~0)), 1009#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 2 main_~length1~0)), 1010#(and (= 0 main_~nondetString1~0.offset) (<= 2 (select |#length| main_~nondetString1~0.base))), 1011#(and (= 0 |cstrncat_#in~s1.offset|) (<= 2 (select |#length| |cstrncat_#in~s1.base|))), 1012#(and (<= 2 (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 1013#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 1002#true, 1003#false, 1004#(<= 1 main_~length2~0), 1005#(<= 2 (+ main_~n~0 main_~length2~0)), 1006#(<= 2 main_~length1~0), 1007#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 2 main_~length1~0) (= 0 |main_#t~malloc13.offset|))] [2018-02-02 09:47:54,193 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,193 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 09:47:54,193 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 09:47:54,194 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:47:54,194 INFO L87 Difference]: Start difference. First operand 60 states and 71 transitions. Second operand 12 states. [2018-02-02 09:47:54,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:54,433 INFO L93 Difference]: Finished difference Result 83 states and 96 transitions. [2018-02-02 09:47:54,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 09:47:54,433 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 23 [2018-02-02 09:47:54,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:54,434 INFO L225 Difference]: With dead ends: 83 [2018-02-02 09:47:54,434 INFO L226 Difference]: Without dead ends: 83 [2018-02-02 09:47:54,434 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=75, Invalid=267, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:47:54,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states. [2018-02-02 09:47:54,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 70. [2018-02-02 09:47:54,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-02-02 09:47:54,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 86 transitions. [2018-02-02 09:47:54,439 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 86 transitions. Word has length 23 [2018-02-02 09:47:54,439 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:54,439 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 86 transitions. [2018-02-02 09:47:54,439 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 09:47:54,439 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 86 transitions. [2018-02-02 09:47:54,440 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-02 09:47:54,440 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:54,440 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:54,440 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:54,441 INFO L82 PathProgramCache]: Analyzing trace with hash -557502487, now seen corresponding path program 1 times [2018-02-02 09:47:54,441 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:54,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:54,450 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:54,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,476 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:54,476 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:47:54,477 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:54,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,477 INFO L182 omatonBuilderFactory]: Interpolants [1184#(= 1 (select |#valid| |cstrncat_#in~s2.base|)), 1185#(= 1 (select |#valid| cstrncat_~s2.base)), 1186#(= 1 (select |#valid| |cstrncat_#t~post2.base|)), 1181#true, 1182#false, 1183#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-02-02 09:47:54,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,477 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:47:54,477 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:47:54,477 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:47:54,477 INFO L87 Difference]: Start difference. First operand 70 states and 86 transitions. Second operand 6 states. [2018-02-02 09:47:54,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:54,523 INFO L93 Difference]: Finished difference Result 72 states and 89 transitions. [2018-02-02 09:47:54,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:47:54,523 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-02-02 09:47:54,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:54,525 INFO L225 Difference]: With dead ends: 72 [2018-02-02 09:47:54,525 INFO L226 Difference]: Without dead ends: 72 [2018-02-02 09:47:54,525 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:47:54,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-02-02 09:47:54,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 69. [2018-02-02 09:47:54,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-02-02 09:47:54,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 83 transitions. [2018-02-02 09:47:54,531 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 83 transitions. Word has length 25 [2018-02-02 09:47:54,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:54,531 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 83 transitions. [2018-02-02 09:47:54,531 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:47:54,531 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 83 transitions. [2018-02-02 09:47:54,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-02 09:47:54,532 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:54,532 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:54,532 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:54,532 INFO L82 PathProgramCache]: Analyzing trace with hash -557502486, now seen corresponding path program 1 times [2018-02-02 09:47:54,533 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:54,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:54,545 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:54,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,603 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:47:54,604 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 09:47:54,604 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:54,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,604 INFO L182 omatonBuilderFactory]: Interpolants [1332#true, 1333#false, 1334#(<= 1 main_~length2~0), 1335#(and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 1336#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 1337#(and (= 0 main_~nondetString2~0.offset) (<= 1 (select |#length| main_~nondetString2~0.base))), 1338#(and (= 0 |cstrncat_#in~s2.offset|) (<= 1 (select |#length| |cstrncat_#in~s2.base|))), 1339#(and (<= 1 (select |#length| cstrncat_~s2.base)) (= 0 cstrncat_~s2.offset)), 1340#(and (<= 1 (select |#length| |cstrncat_#t~post2.base|)) (= |cstrncat_#t~post2.offset| 0))] [2018-02-02 09:47:54,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,604 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:47:54,604 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:47:54,605 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:47:54,605 INFO L87 Difference]: Start difference. First operand 69 states and 83 transitions. Second operand 9 states. [2018-02-02 09:47:54,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:54,677 INFO L93 Difference]: Finished difference Result 98 states and 120 transitions. [2018-02-02 09:47:54,677 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:47:54,677 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 25 [2018-02-02 09:47:54,677 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:54,678 INFO L225 Difference]: With dead ends: 98 [2018-02-02 09:47:54,678 INFO L226 Difference]: Without dead ends: 98 [2018-02-02 09:47:54,678 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:47:54,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-02-02 09:47:54,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 80. [2018-02-02 09:47:54,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-02-02 09:47:54,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 98 transitions. [2018-02-02 09:47:54,681 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 98 transitions. Word has length 25 [2018-02-02 09:47:54,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:54,681 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 98 transitions. [2018-02-02 09:47:54,681 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:47:54,681 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 98 transitions. [2018-02-02 09:47:54,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 09:47:54,682 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:54,682 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:54,682 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:54,682 INFO L82 PathProgramCache]: Analyzing trace with hash -59760490, now seen corresponding path program 2 times [2018-02-02 09:47:54,683 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:54,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:54,694 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:54,899 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,900 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:54,900 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 09:47:54,900 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:54,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,900 INFO L182 omatonBuilderFactory]: Interpolants [1536#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 1537#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 1525#true, 1526#false, 1527#(<= 1 main_~n~0), 1528#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 1529#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1530#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1531#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1532#(and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (<= 3 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 1533#(and (= 0 |cstrncat_#in~s1.offset|) (or (<= 3 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 1534#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= 3 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 1535#(and (= cstrncat_~s~0.offset 0) (or (<= 3 (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))))] [2018-02-02 09:47:54,900 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:54,901 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 09:47:54,901 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 09:47:54,901 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:47:54,901 INFO L87 Difference]: Start difference. First operand 80 states and 98 transitions. Second operand 13 states. [2018-02-02 09:47:55,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:55,322 INFO L93 Difference]: Finished difference Result 149 states and 181 transitions. [2018-02-02 09:47:55,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:47:55,322 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 26 [2018-02-02 09:47:55,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:55,323 INFO L225 Difference]: With dead ends: 149 [2018-02-02 09:47:55,323 INFO L226 Difference]: Without dead ends: 149 [2018-02-02 09:47:55,323 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=106, Invalid=494, Unknown=0, NotChecked=0, Total=600 [2018-02-02 09:47:55,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-02-02 09:47:55,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 83. [2018-02-02 09:47:55,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-02-02 09:47:55,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 102 transitions. [2018-02-02 09:47:55,326 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 102 transitions. Word has length 26 [2018-02-02 09:47:55,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:55,326 INFO L432 AbstractCegarLoop]: Abstraction has 83 states and 102 transitions. [2018-02-02 09:47:55,326 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 09:47:55,326 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 102 transitions. [2018-02-02 09:47:55,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:47:55,326 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:55,327 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:55,327 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:55,327 INFO L82 PathProgramCache]: Analyzing trace with hash 2086668971, now seen corresponding path program 3 times [2018-02-02 09:47:55,327 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:55,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:55,339 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:55,641 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:55,641 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:55,641 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-02-02 09:47:55,641 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:55,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:55,642 INFO L182 omatonBuilderFactory]: Interpolants [1794#true, 1795#false, 1796#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 1797#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= 0 |main_#t~malloc13.offset|)), 1798#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 1799#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 1800#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 1801#(and (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 1802#(and (or (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (<= (select |#length| |cstrncat_#in~s1.base|) 2)) (= 0 |cstrncat_#in~s1.offset|)), 1803#(and (= cstrncat_~s~0.offset 0) (or (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= 4 (select |#length| cstrncat_~s~0.base)))), 1804#(and (= cstrncat_~s~0.offset 1) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 1805#(and (= cstrncat_~s~0.offset 1) (or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 1806#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 1807#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 1808#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:47:55,642 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:55,642 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 09:47:55,642 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 09:47:55,642 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=180, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:47:55,642 INFO L87 Difference]: Start difference. First operand 83 states and 102 transitions. Second operand 15 states. [2018-02-02 09:47:56,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:56,219 INFO L93 Difference]: Finished difference Result 244 states and 300 transitions. [2018-02-02 09:47:56,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:47:56,219 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 29 [2018-02-02 09:47:56,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:56,221 INFO L225 Difference]: With dead ends: 244 [2018-02-02 09:47:56,221 INFO L226 Difference]: Without dead ends: 244 [2018-02-02 09:47:56,221 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=131, Invalid=739, Unknown=0, NotChecked=0, Total=870 [2018-02-02 09:47:56,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-02-02 09:47:56,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 166. [2018-02-02 09:47:56,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-02-02 09:47:56,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 216 transitions. [2018-02-02 09:47:56,231 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 216 transitions. Word has length 29 [2018-02-02 09:47:56,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:56,231 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 216 transitions. [2018-02-02 09:47:56,231 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 09:47:56,231 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 216 transitions. [2018-02-02 09:47:56,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:47:56,233 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:56,233 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:56,233 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:56,233 INFO L82 PathProgramCache]: Analyzing trace with hash -1785596499, now seen corresponding path program 1 times [2018-02-02 09:47:56,234 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:56,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:56,247 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:56,572 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:56,572 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:56,572 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:47:56,572 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:56,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:56,573 INFO L182 omatonBuilderFactory]: Interpolants [2249#true, 2250#false, 2251#(<= 1 main_~n~0), 2252#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 2253#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (<= 1 main_~n~0)) (= main_~nondetString1~0.offset 0)), 2254#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (<= 1 main_~n~0)) (= main_~nondetString1~0.offset 0)), 2255#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (<= 1 main_~n~0)) (= main_~nondetString1~0.offset 0)), 2256#(and (or (not (= main_~n~0 1)) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) (* 2 main_~n~0))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 1 main_~n~0) (<= (+ main_~n~0 2) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= main_~n~0 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2257#(and (= 0 |cstrncat_#in~s1.offset|) (or (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)) (<= (select |#length| |cstrncat_#in~s1.base|) 2))), 2258#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= 4 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 2259#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (<= 4 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 2260#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 2261#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 2262#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 2263#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 2264#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:47:56,573 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:56,573 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:47:56,574 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:47:56,574 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:47:56,574 INFO L87 Difference]: Start difference. First operand 166 states and 216 transitions. Second operand 16 states. [2018-02-02 09:47:57,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:57,148 INFO L93 Difference]: Finished difference Result 340 states and 424 transitions. [2018-02-02 09:47:57,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:47:57,149 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 29 [2018-02-02 09:47:57,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:57,150 INFO L225 Difference]: With dead ends: 340 [2018-02-02 09:47:57,150 INFO L226 Difference]: Without dead ends: 340 [2018-02-02 09:47:57,151 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=147, Invalid=975, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:47:57,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-02-02 09:47:57,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 86. [2018-02-02 09:47:57,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-02-02 09:47:57,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 106 transitions. [2018-02-02 09:47:57,157 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 106 transitions. Word has length 29 [2018-02-02 09:47:57,157 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:57,157 INFO L432 AbstractCegarLoop]: Abstraction has 86 states and 106 transitions. [2018-02-02 09:47:57,157 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:47:57,157 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 106 transitions. [2018-02-02 09:47:57,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-02 09:47:57,158 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:57,158 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:57,158 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:57,158 INFO L82 PathProgramCache]: Analyzing trace with hash 933708271, now seen corresponding path program 1 times [2018-02-02 09:47:57,159 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:57,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:57,167 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:57,232 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:57,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:57,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 09:47:57,232 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:57,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:57,232 INFO L182 omatonBuilderFactory]: Interpolants [2727#true, 2728#false, 2729#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 2730#(and (<= |cstrncat_#in~n| 1) (<= 1 |cstrncat_#in~n|)), 2731#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 1)), 2732#(and (<= cstrncat_~n 0) (<= 0 cstrncat_~n)), 2733#(not |cstrncat_#t~short5|)] [2018-02-02 09:47:57,232 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:57,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:47:57,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:47:57,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:47:57,233 INFO L87 Difference]: Start difference. First operand 86 states and 106 transitions. Second operand 7 states. [2018-02-02 09:47:57,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:57,286 INFO L93 Difference]: Finished difference Result 175 states and 206 transitions. [2018-02-02 09:47:57,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:47:57,286 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 32 [2018-02-02 09:47:57,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:57,287 INFO L225 Difference]: With dead ends: 175 [2018-02-02 09:47:57,287 INFO L226 Difference]: Without dead ends: 175 [2018-02-02 09:47:57,287 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:47:57,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-02-02 09:47:57,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 147. [2018-02-02 09:47:57,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-02-02 09:47:57,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 181 transitions. [2018-02-02 09:47:57,291 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 181 transitions. Word has length 32 [2018-02-02 09:47:57,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:57,291 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 181 transitions. [2018-02-02 09:47:57,291 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:47:57,291 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 181 transitions. [2018-02-02 09:47:57,292 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-02 09:47:57,292 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:57,292 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:57,292 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:57,292 INFO L82 PathProgramCache]: Analyzing trace with hash -1401328522, now seen corresponding path program 4 times [2018-02-02 09:47:57,293 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:57,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:57,303 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:57,557 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:57,557 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:57,557 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:47:57,557 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:57,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:57,558 INFO L182 omatonBuilderFactory]: Interpolants [3072#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1))))), 3073#(and (= cstrncat_~s~0.offset 0) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 3074#(and (<= 1 cstrncat_~s~0.offset) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 3075#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset))), 3076#(or (and (or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 3077#(and (<= 3 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 3078#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 3 cstrncat_~s~0.offset)), 3079#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 3064#true, 3065#false, 3066#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 3067#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= 0 |main_#t~malloc13.offset|)), 3068#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 3069#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 3070#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 3071#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ main_~n~0 (- 1))) (+ main_~nondetString1~0.offset (+ (- main_~n~0) (- 1)))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:47:57,558 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:57,558 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:47:57,558 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:47:57,558 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:47:57,558 INFO L87 Difference]: Start difference. First operand 147 states and 181 transitions. Second operand 16 states. [2018-02-02 09:47:58,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:58,236 INFO L93 Difference]: Finished difference Result 239 states and 276 transitions. [2018-02-02 09:47:58,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-02 09:47:58,236 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 32 [2018-02-02 09:47:58,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:58,237 INFO L225 Difference]: With dead ends: 239 [2018-02-02 09:47:58,237 INFO L226 Difference]: Without dead ends: 239 [2018-02-02 09:47:58,238 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 308 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=209, Invalid=1123, Unknown=0, NotChecked=0, Total=1332 [2018-02-02 09:47:58,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-02-02 09:47:58,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 114. [2018-02-02 09:47:58,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-02-02 09:47:58,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 135 transitions. [2018-02-02 09:47:58,242 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 135 transitions. Word has length 32 [2018-02-02 09:47:58,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:58,242 INFO L432 AbstractCegarLoop]: Abstraction has 114 states and 135 transitions. [2018-02-02 09:47:58,242 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:47:58,242 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 135 transitions. [2018-02-02 09:47:58,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-02 09:47:58,243 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:58,243 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:58,243 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:58,243 INFO L82 PathProgramCache]: Analyzing trace with hash 799694765, now seen corresponding path program 1 times [2018-02-02 09:47:58,247 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:58,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:58,254 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:58,371 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:58,371 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:58,371 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 09:47:58,371 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:58,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:58,372 INFO L182 omatonBuilderFactory]: Interpolants [3475#true, 3476#false, 3477#(<= 1 main_~length2~0), 3478#(and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 3479#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length2~0) 1) (and (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))))), 3480#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 2 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 3481#(and (= 0 |cstrncat_#in~s2.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) |cstrncat_#in~s2.offset|)) (<= 2 (select |#length| |cstrncat_#in~s2.base|)))), 3482#(and (= 0 cstrncat_~s2.offset) (or (= 0 (select (select |#memory_int| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 2 (select |#length| cstrncat_~s2.base)))), 3483#(and (= |cstrncat_#t~post2.offset| 0) (<= (+ |cstrncat_#t~post2.offset| 1) cstrncat_~s2.offset) (or (<= (+ cstrncat_~s2.offset 1) (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset|)) (= 0 (select (select |#memory_int| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|)))), 3484#(and (or (= 0 |cstrncat_#t~mem4|) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (<= 1 cstrncat_~s2.offset)), 3485#(and (<= 1 cstrncat_~s2.offset) (or (not |cstrncat_#t~short5|) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))), 3486#(and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))), 3487#(and (<= (+ |cstrncat_#t~post2.offset| 1) (select |#length| |cstrncat_#t~post2.base|)) (<= 1 |cstrncat_#t~post2.offset|))] [2018-02-02 09:47:58,372 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:58,372 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 09:47:58,372 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 09:47:58,372 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=129, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:47:58,372 INFO L87 Difference]: Start difference. First operand 114 states and 135 transitions. Second operand 13 states. [2018-02-02 09:47:58,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:58,620 INFO L93 Difference]: Finished difference Result 174 states and 203 transitions. [2018-02-02 09:47:58,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 09:47:58,620 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 32 [2018-02-02 09:47:58,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:58,621 INFO L225 Difference]: With dead ends: 174 [2018-02-02 09:47:58,621 INFO L226 Difference]: Without dead ends: 174 [2018-02-02 09:47:58,621 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=70, Invalid=350, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:47:58,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-02 09:47:58,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 124. [2018-02-02 09:47:58,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-02 09:47:58,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 148 transitions. [2018-02-02 09:47:58,625 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 148 transitions. Word has length 32 [2018-02-02 09:47:58,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:58,625 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 148 transitions. [2018-02-02 09:47:58,625 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 09:47:58,625 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 148 transitions. [2018-02-02 09:47:58,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-02 09:47:58,626 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:58,626 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:58,626 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:58,626 INFO L82 PathProgramCache]: Analyzing trace with hash -1535342028, now seen corresponding path program 2 times [2018-02-02 09:47:58,627 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:58,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:58,637 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:47:58,965 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:58,966 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:47:58,966 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:47:58,966 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:47:58,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:58,966 INFO L182 omatonBuilderFactory]: Interpolants [3808#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 3809#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 3810#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 3811#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (or (<= 5 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 3812#(and (= cstrncat_~s~0.offset 0) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= 5 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrncat_~s~0.base))))), 3813#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))))) (= cstrncat_~s~0.offset 1)), 3814#(and (or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (= cstrncat_~s~0.offset 1)), 3815#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 3816#(or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 3817#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 3 cstrncat_~s~0.offset)), 3818#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 3802#true, 3803#false, 3804#(<= 1 main_~n~0), 3805#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 3806#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 3807#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))))] [2018-02-02 09:47:58,967 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:47:58,967 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:47:58,967 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:47:58,967 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:47:58,967 INFO L87 Difference]: Start difference. First operand 124 states and 148 transitions. Second operand 17 states. [2018-02-02 09:47:59,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:47:59,961 INFO L93 Difference]: Finished difference Result 335 states and 391 transitions. [2018-02-02 09:47:59,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:47:59,962 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 32 [2018-02-02 09:47:59,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:47:59,963 INFO L225 Difference]: With dead ends: 335 [2018-02-02 09:47:59,963 INFO L226 Difference]: Without dead ends: 335 [2018-02-02 09:47:59,964 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 261 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=164, Invalid=1168, Unknown=0, NotChecked=0, Total=1332 [2018-02-02 09:47:59,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states. [2018-02-02 09:47:59,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 127. [2018-02-02 09:47:59,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-02-02 09:47:59,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 152 transitions. [2018-02-02 09:47:59,968 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 152 transitions. Word has length 32 [2018-02-02 09:47:59,968 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:47:59,968 INFO L432 AbstractCegarLoop]: Abstraction has 127 states and 152 transitions. [2018-02-02 09:47:59,968 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:47:59,969 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 152 transitions. [2018-02-02 09:47:59,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:47:59,969 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:47:59,969 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:47:59,969 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:47:59,969 INFO L82 PathProgramCache]: Analyzing trace with hash 2027344973, now seen corresponding path program 3 times [2018-02-02 09:47:59,970 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:47:59,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:47:59,985 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:00,611 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:00,611 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:00,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 09:48:00,611 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:00,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:00,611 INFO L182 omatonBuilderFactory]: Interpolants [4321#true, 4322#false, 4323#(<= 1 main_~n~0), 4324#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 4325#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 4326#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 4327#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 4328#(and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~n~0)) (<= 1 main_~n~0) (<= (+ (* 2 main_~n~0) 1) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 1) (+ main_~n~0 (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ main_~nondetString1~0.offset (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)))))) (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 2) (+ main_~n~0 (select |#length| main_~nondetString1~0.base)))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 4329#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) 2))) (<= 1 (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) 2))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (<= 6 (select |#length| |cstrncat_#in~s1.base|)) (and (<= (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 3) 2) 1) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 4330#(and (or (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 1 (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 4331#(and (or (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 1 (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (<= 6 (select |#length| cstrncat_~s~0.base))) (= cstrncat_~s~0.offset 0)), 4332#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2))) (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 2)) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))) (= cstrncat_~s~0.offset 1)), 4333#(and (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 2)) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (or (<= (+ cstrncat_~s~0.offset 1) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))))) (= cstrncat_~s~0.offset 1)), 4334#(or (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 4335#(or (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) 2) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 4336#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 4337#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 4338#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 4339#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 4340#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:48:00,612 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:00,612 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:48:00,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:48:00,612 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:48:00,612 INFO L87 Difference]: Start difference. First operand 127 states and 152 transitions. Second operand 20 states. [2018-02-02 09:48:01,014 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 75 DAG size of output 68 [2018-02-02 09:48:01,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:01,756 INFO L93 Difference]: Finished difference Result 392 states and 461 transitions. [2018-02-02 09:48:01,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-02 09:48:01,757 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 35 [2018-02-02 09:48:01,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:01,758 INFO L225 Difference]: With dead ends: 392 [2018-02-02 09:48:01,758 INFO L226 Difference]: Without dead ends: 392 [2018-02-02 09:48:01,758 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 469 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=248, Invalid=1474, Unknown=0, NotChecked=0, Total=1722 [2018-02-02 09:48:01,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states. [2018-02-02 09:48:01,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 130. [2018-02-02 09:48:01,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-02-02 09:48:01,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 156 transitions. [2018-02-02 09:48:01,763 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 156 transitions. Word has length 35 [2018-02-02 09:48:01,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:01,763 INFO L432 AbstractCegarLoop]: Abstraction has 130 states and 156 transitions. [2018-02-02 09:48:01,763 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:48:01,763 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 156 transitions. [2018-02-02 09:48:01,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 09:48:01,764 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:01,764 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:01,764 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:01,764 INFO L82 PathProgramCache]: Analyzing trace with hash -1376138118, now seen corresponding path program 1 times [2018-02-02 09:48:01,765 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:01,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:01,770 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:01,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:01,801 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:48:01,801 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:48:01,802 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:01,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:01,802 INFO L182 omatonBuilderFactory]: Interpolants [4912#(<= |cstrncat_#in~n| 0), 4907#true, 4908#false, 4909#(<= 1 main_~n~0), 4910#(<= |cstrncat_#in~n| cstrncat_~n), 4911#(or |cstrncat_#t~short5| (<= |cstrncat_#in~n| 0))] [2018-02-02 09:48:01,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:01,802 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:48:01,802 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:48:01,802 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:48:01,803 INFO L87 Difference]: Start difference. First operand 130 states and 156 transitions. Second operand 6 states. [2018-02-02 09:48:01,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:01,839 INFO L93 Difference]: Finished difference Result 168 states and 197 transitions. [2018-02-02 09:48:01,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:48:01,840 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-02-02 09:48:01,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:01,841 INFO L225 Difference]: With dead ends: 168 [2018-02-02 09:48:01,841 INFO L226 Difference]: Without dead ends: 154 [2018-02-02 09:48:01,841 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:48:01,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-02 09:48:01,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 134. [2018-02-02 09:48:01,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-02-02 09:48:01,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 158 transitions. [2018-02-02 09:48:01,844 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 158 transitions. Word has length 36 [2018-02-02 09:48:01,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:01,844 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 158 transitions. [2018-02-02 09:48:01,844 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:48:01,844 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 158 transitions. [2018-02-02 09:48:01,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 09:48:01,845 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:01,845 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:01,845 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:01,845 INFO L82 PathProgramCache]: Analyzing trace with hash 803973012, now seen corresponding path program 4 times [2018-02-02 09:48:01,845 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:01,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:01,858 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:02,236 WARN L146 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 69 DAG size of output 61 [2018-02-02 09:48:02,702 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:02,703 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:02,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 09:48:02,703 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:02,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:02,704 INFO L182 omatonBuilderFactory]: Interpolants [5219#true, 5220#false, 5221#(<= 1 main_~n~0), 5222#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 5223#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 5224#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 5225#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5226#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5227#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ 3 (- 1)))) (<= 5 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1))))))), 5228#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 5 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (<= 6 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 5229#(and (= cstrncat_~s~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 5 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (<= 6 (select |#length| cstrncat_~s~0.base))))), 5230#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))))) (= cstrncat_~s~0.offset 1)), 5231#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))))) (= cstrncat_~s~0.offset 1)), 5232#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 5233#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 5234#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 5235#(or (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 5236#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 5237#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset))), 5238#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 5239#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))] [2018-02-02 09:48:02,704 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:02,705 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 09:48:02,705 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 09:48:02,705 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=359, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:48:02,705 INFO L87 Difference]: Start difference. First operand 134 states and 158 transitions. Second operand 21 states. [2018-02-02 09:48:03,057 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 82 DAG size of output 81 [2018-02-02 09:48:04,141 WARN L143 SmtUtils]: Spent 106ms on a formula simplification that was a NOOP. DAG size: 46 [2018-02-02 09:48:04,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:04,349 INFO L93 Difference]: Finished difference Result 298 states and 340 transitions. [2018-02-02 09:48:04,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:48:04,349 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 38 [2018-02-02 09:48:04,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:04,350 INFO L225 Difference]: With dead ends: 298 [2018-02-02 09:48:04,350 INFO L226 Difference]: Without dead ends: 294 [2018-02-02 09:48:04,350 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 377 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=248, Invalid=1474, Unknown=0, NotChecked=0, Total=1722 [2018-02-02 09:48:04,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294 states. [2018-02-02 09:48:04,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294 to 137. [2018-02-02 09:48:04,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-02-02 09:48:04,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 162 transitions. [2018-02-02 09:48:04,353 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 162 transitions. Word has length 38 [2018-02-02 09:48:04,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:04,353 INFO L432 AbstractCegarLoop]: Abstraction has 137 states and 162 transitions. [2018-02-02 09:48:04,353 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 09:48:04,353 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 162 transitions. [2018-02-02 09:48:04,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 09:48:04,353 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:04,353 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:04,353 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:04,353 INFO L82 PathProgramCache]: Analyzing trace with hash 336762589, now seen corresponding path program 1 times [2018-02-02 09:48:04,354 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:04,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:04,358 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:04,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:04,412 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:48:04,412 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:48:04,412 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:04,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:04,412 INFO L182 omatonBuilderFactory]: Interpolants [5717#true, 5718#false, 5719#(= |#valid| |old(#valid)|), 5720#(and (= (select |#valid| |main_#t~malloc13.base|) 1) (= |old(#valid)| (store |#valid| |main_#t~malloc13.base| 0))), 5721#(and (= (store (store |#valid| |main_#t~malloc13.base| 0) |main_#t~malloc14.base| 0) |old(#valid)|) (not (= |main_#t~malloc13.base| |main_#t~malloc14.base|))), 5722#(= (store |#valid| |main_#t~malloc14.base| 0) |old(#valid)|)] [2018-02-02 09:48:04,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:04,412 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:48:04,412 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:48:04,412 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:48:04,413 INFO L87 Difference]: Start difference. First operand 137 states and 162 transitions. Second operand 6 states. [2018-02-02 09:48:04,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:04,498 INFO L93 Difference]: Finished difference Result 136 states and 161 transitions. [2018-02-02 09:48:04,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:48:04,501 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-02-02 09:48:04,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:04,501 INFO L225 Difference]: With dead ends: 136 [2018-02-02 09:48:04,502 INFO L226 Difference]: Without dead ends: 94 [2018-02-02 09:48:04,502 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:48:04,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-02-02 09:48:04,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 90. [2018-02-02 09:48:04,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-02-02 09:48:04,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 104 transitions. [2018-02-02 09:48:04,504 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 104 transitions. Word has length 39 [2018-02-02 09:48:04,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:04,504 INFO L432 AbstractCegarLoop]: Abstraction has 90 states and 104 transitions. [2018-02-02 09:48:04,504 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:48:04,504 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 104 transitions. [2018-02-02 09:48:04,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 09:48:04,505 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:04,505 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:04,505 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:04,505 INFO L82 PathProgramCache]: Analyzing trace with hash -2098962228, now seen corresponding path program 2 times [2018-02-02 09:48:04,506 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:04,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:04,516 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:04,872 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:04,872 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:04,873 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:48:04,873 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:04,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:04,873 INFO L182 omatonBuilderFactory]: Interpolants [5953#true, 5954#false, 5955#(= (select |#valid| |main_#t~malloc13.base|) 1), 5956#(= (select |#valid| main_~nondetString1~0.base) 1), 5957#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 5958#(and (= 0 main_~nondetString2~0.offset) (or (not (= (+ main_~nondetString2~0.offset main_~length2~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 5959#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)) 1) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 5960#(and (= 0 |cstrncat_#in~s2.offset|) (or (and (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) 1))) (<= (select |#length| |cstrncat_#in~s2.base|) 1) (<= 3 (select |#length| |cstrncat_#in~s2.base|)))), 5961#(and (= 0 cstrncat_~s2.offset) (or (<= 3 (select |#length| cstrncat_~s2.base)) (<= (select |#length| cstrncat_~s2.base) 1) (and (= 0 (select (select |#memory_int| cstrncat_~s2.base) 1)) (not (= cstrncat_~s~0.base cstrncat_~s2.base))))), 5962#(and (= |cstrncat_#t~post2.offset| 0) (or (and (not (= |cstrncat_#t~post2.base| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| |cstrncat_#t~post2.base|) 1)) (<= cstrncat_~s2.offset (+ |cstrncat_#t~post2.offset| 1)) (= |cstrncat_#t~post2.base| cstrncat_~s2.base) (<= (+ |cstrncat_#t~post2.offset| 1) cstrncat_~s2.offset)) (and (or (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset|) cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 2) (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset|))) (<= (+ |cstrncat_#t~post2.offset| 1) cstrncat_~s2.offset)))), 5963#(or (and (<= 1 cstrncat_~s2.offset) (= 0 (select (select (store |#memory_int| cstrncat_~s~0.base (store (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset |cstrncat_#t~mem4|)) cstrncat_~s2.base) 1)) (<= cstrncat_~s2.offset 1)) (and (<= 1 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 2) (select |#length| cstrncat_~s2.base))))), 5964#(or (and (<= 1 cstrncat_~s2.offset) (or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 2) (select |#length| cstrncat_~s2.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s2.base) 1)) (<= 1 cstrncat_~s2.offset) (<= cstrncat_~s2.offset 1))), 5965#(or (and (= 1 |cstrncat_#t~post2.offset|) (= 0 (select (select |#memory_int| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|))) (and (<= 2 cstrncat_~s2.offset) (or (<= (select |#length| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))))), 5966#(or (= 0 |cstrncat_#t~mem4|) (and (<= 2 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))), 5967#(or (not |cstrncat_#t~short5|) (and (<= 2 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))), 5968#(and (<= 2 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))), 5969#(and (<= (+ |cstrncat_#t~post2.offset| 1) (select |#length| |cstrncat_#t~post2.base|)) (<= 2 |cstrncat_#t~post2.offset|))] [2018-02-02 09:48:04,873 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:04,874 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:48:04,874 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:48:04,874 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:48:04,874 INFO L87 Difference]: Start difference. First operand 90 states and 104 transitions. Second operand 17 states. [2018-02-02 09:48:05,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:05,496 INFO L93 Difference]: Finished difference Result 124 states and 138 transitions. [2018-02-02 09:48:05,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-02 09:48:05,496 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-02-02 09:48:05,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:05,496 INFO L225 Difference]: With dead ends: 124 [2018-02-02 09:48:05,496 INFO L226 Difference]: Without dead ends: 124 [2018-02-02 09:48:05,497 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=104, Invalid=652, Unknown=0, NotChecked=0, Total=756 [2018-02-02 09:48:05,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-02-02 09:48:05,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 97. [2018-02-02 09:48:05,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-02 09:48:05,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 114 transitions. [2018-02-02 09:48:05,498 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 114 transitions. Word has length 39 [2018-02-02 09:48:05,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:05,498 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 114 transitions. [2018-02-02 09:48:05,498 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:48:05,498 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 114 transitions. [2018-02-02 09:48:05,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-02 09:48:05,499 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:05,499 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:05,499 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:05,499 INFO L82 PathProgramCache]: Analyzing trace with hash -643319614, now seen corresponding path program 1 times [2018-02-02 09:48:05,500 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:05,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:05,507 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:05,758 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:05,758 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:05,758 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 09:48:05,758 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:05,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:05,758 INFO L182 omatonBuilderFactory]: Interpolants [6213#true, 6214#false, 6215#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 6216#(and (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 6217#(and (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 6218#(and (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 6219#(and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 6220#(and (= 0 main_~nondetString2~0.offset) (<= (+ main_~length2~0 main_~nondetString1~0.offset) (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6221#(and (= 0 main_~nondetString2~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 6222#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (select |#length| |cstrncat_#in~s2.base|) (select |#length| |cstrncat_#in~s1.base|))), 6223#(and (= 0 cstrncat_~s2.offset) (= cstrncat_~s~0.offset 0) (<= (select |#length| cstrncat_~s2.base) (select |#length| cstrncat_~s~0.base))), 6224#(and (= |cstrncat_#t~post2.offset| 0) (= cstrncat_~s~0.offset 0) (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset| 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 6225#(and (<= (+ (select |#length| cstrncat_~s2.base) 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= cstrncat_~s~0.offset 0)), 6226#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 6227#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 6228#(and (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 6229#(and (<= (+ (select |#length| |cstrncat_#t~post2.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post2.offset|)) (<= 2 cstrncat_~s~0.offset)), 6230#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))] [2018-02-02 09:48:05,758 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:05,759 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 09:48:05,759 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 09:48:05,759 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:48:05,759 INFO L87 Difference]: Start difference. First operand 97 states and 114 transitions. Second operand 18 states. [2018-02-02 09:48:06,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:06,142 INFO L93 Difference]: Finished difference Result 131 states and 149 transitions. [2018-02-02 09:48:06,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:48:06,142 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 40 [2018-02-02 09:48:06,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:06,143 INFO L225 Difference]: With dead ends: 131 [2018-02-02 09:48:06,143 INFO L226 Difference]: Without dead ends: 126 [2018-02-02 09:48:06,143 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=144, Invalid=786, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:48:06,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-02-02 09:48:06,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-02-02 09:48:06,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-02 09:48:06,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 144 transitions. [2018-02-02 09:48:06,146 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 144 transitions. Word has length 40 [2018-02-02 09:48:06,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:06,146 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 144 transitions. [2018-02-02 09:48:06,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 09:48:06,146 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 144 transitions. [2018-02-02 09:48:06,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-02 09:48:06,147 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:06,147 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:06,147 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:06,147 INFO L82 PathProgramCache]: Analyzing trace with hash -643310578, now seen corresponding path program 1 times [2018-02-02 09:48:06,148 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:06,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:06,156 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:06,389 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:06,389 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:06,389 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 09:48:06,389 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:06,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:06,390 INFO L182 omatonBuilderFactory]: Interpolants [6528#(and (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 6529#(and (<= 2 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short5|)), 6530#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 6512#true, 6513#false, 6514#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 6515#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 6516#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 6517#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 6518#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 6519#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 6520#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base))), 6521#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|))), 6522#(and (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 6523#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset| 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= |cstrncat_#t~post2.offset| 0) (= cstrncat_~s~0.offset 0)), 6524#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= cstrncat_~s~0.offset 0)), 6525#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 6526#(and (<= (+ cstrncat_~n (select |#length| |cstrncat_#t~post2.base|) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post2.offset|)) (<= 1 cstrncat_~s~0.offset)), 6527#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:48:06,390 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:06,390 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 09:48:06,390 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 09:48:06,390 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=297, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:48:06,390 INFO L87 Difference]: Start difference. First operand 124 states and 144 transitions. Second operand 19 states. [2018-02-02 09:48:06,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:06,843 INFO L93 Difference]: Finished difference Result 125 states and 143 transitions. [2018-02-02 09:48:06,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:48:06,843 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 40 [2018-02-02 09:48:06,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:06,844 INFO L225 Difference]: With dead ends: 125 [2018-02-02 09:48:06,844 INFO L226 Difference]: Without dead ends: 123 [2018-02-02 09:48:06,844 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=147, Invalid=845, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:48:06,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2018-02-02 09:48:06,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 122. [2018-02-02 09:48:06,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-02-02 09:48:06,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 140 transitions. [2018-02-02 09:48:06,846 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 140 transitions. Word has length 40 [2018-02-02 09:48:06,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:06,847 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 140 transitions. [2018-02-02 09:48:06,847 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 09:48:06,847 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 140 transitions. [2018-02-02 09:48:06,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-02 09:48:06,847 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:06,847 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:06,848 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:06,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1872610579, now seen corresponding path program 5 times [2018-02-02 09:48:06,848 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:06,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:06,867 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:07,589 WARN L146 SmtUtils]: Spent 140ms on a formula simplification. DAG size of input: 83 DAG size of output 56 [2018-02-02 09:48:07,722 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 83 DAG size of output 50 [2018-02-02 09:48:08,083 WARN L146 SmtUtils]: Spent 215ms on a formula simplification. DAG size of input: 101 DAG size of output 60 [2018-02-02 09:48:08,357 WARN L146 SmtUtils]: Spent 236ms on a formula simplification. DAG size of input: 104 DAG size of output 63 [2018-02-02 09:48:08,872 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:08,872 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:08,872 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:48:08,872 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:08,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:08,873 INFO L182 omatonBuilderFactory]: Interpolants [6816#(or (and (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 4)) 2) 2) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 4))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (- 1)))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 4))) 2))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 1))) 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 2) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 1))) 2))) (and (<= (+ cstrncat_~s~0.offset 1) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 4))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))), 6817#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) (- 1))))) (and (<= cstrncat_~s~0.offset (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2))) (or (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))) (and (<= cstrncat_~s~0.offset (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2)))) (- 1)))))), 6818#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (and (<= cstrncat_~s~0.offset (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2)))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= cstrncat_~s~0.offset (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2)))) (- 1)))))), 6819#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 2)) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 6820#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 2)) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 2) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 6821#(or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 6822#(or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 2)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 6823#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 6824#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 6825#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6826#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 6827#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 6804#true, 6805#false, 6806#(<= 1 main_~n~0), 6807#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 6808#(and (or (<= (+ main_~nondetString1~0.offset main_~length1~0) (* 2 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (<= 1 main_~n~0) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 6809#(and (or (<= (+ main_~nondetString1~0.offset main_~length1~0) (* 2 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (<= 1 main_~n~0) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 6810#(and (or (<= (+ main_~nondetString1~0.offset main_~length1~0) (* 2 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (<= 1 main_~n~0) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6811#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (or (and (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 1) (+ main_~n~0 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) (+ main_~nondetString1~0.offset (- 1))))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~n~0)) (<= 1 main_~n~0) (<= (+ (* 2 main_~n~0) 1) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (or (<= (+ main_~n~0 4) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 3) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 5))) 2) 1) (+ main_~n~0 (select |#length| main_~nondetString1~0.base)))))), 6812#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) 2))) (<= 1 (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) 2))) (and (<= 3 (div (select |#length| |cstrncat_#in~s1.base|) 2)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (div (select |#length| |cstrncat_#in~s1.base|) 2) (- 1)))) (<= 4 (div (select |#length| |cstrncat_#in~s1.base|) 2)))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)))) (<= 2 (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 3)) 2))) (and (<= (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 3) 2) 1) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 3) 2) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (- (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 3)) 2)) (select |#length| |cstrncat_#in~s1.base|)) (- 1)))) (<= 1 (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 3)) 2))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 6813#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) (- 1)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 1) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 1 (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) 1) (select |#length| cstrncat_~s~0.base))) (and (<= 3 (div (select |#length| cstrncat_~s~0.base) 2)) (or (<= 4 (div (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (select |#length| cstrncat_~s~0.base) 2) (- 1))))))) (= cstrncat_~s~0.offset 0)), 6814#(and (= cstrncat_~s~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) (- 1)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 1) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 1 (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) 1) (select |#length| cstrncat_~s~0.base))) (and (<= 3 (div (select |#length| cstrncat_~s~0.base) 2)) (or (<= 4 (div (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (select |#length| cstrncat_~s~0.base) 2) (- 1)))))))), 6815#(or (and (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1)) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 4)) 2) 2) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 4))) 2)) (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (- 1)))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 4))) 2))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 1))) 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 2) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 1))) 2))) (and (<= (+ cstrncat_~s~0.offset 1) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 4))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))))] [2018-02-02 09:48:08,873 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:08,873 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:48:08,873 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:48:08,873 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=476, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:48:08,873 INFO L87 Difference]: Start difference. First operand 122 states and 140 transitions. Second operand 24 states. [2018-02-02 09:48:09,710 WARN L146 SmtUtils]: Spent 193ms on a formula simplification. DAG size of input: 116 DAG size of output 114 [2018-02-02 09:48:09,993 WARN L146 SmtUtils]: Spent 215ms on a formula simplification. DAG size of input: 110 DAG size of output 107 [2018-02-02 09:48:10,170 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 113 DAG size of output 102 [2018-02-02 09:48:10,336 WARN L146 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 109 DAG size of output 86 [2018-02-02 09:48:10,468 WARN L146 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 87 DAG size of output 83 [2018-02-02 09:48:10,657 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 94 DAG size of output 89 [2018-02-02 09:48:11,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:11,495 INFO L93 Difference]: Finished difference Result 185 states and 204 transitions. [2018-02-02 09:48:11,495 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-02 09:48:11,495 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 41 [2018-02-02 09:48:11,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:11,496 INFO L225 Difference]: With dead ends: 185 [2018-02-02 09:48:11,496 INFO L226 Difference]: Without dead ends: 177 [2018-02-02 09:48:11,497 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 410 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=277, Invalid=1615, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 09:48:11,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-02 09:48:11,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 125. [2018-02-02 09:48:11,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-02 09:48:11,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 144 transitions. [2018-02-02 09:48:11,500 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 144 transitions. Word has length 41 [2018-02-02 09:48:11,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:11,500 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 144 transitions. [2018-02-02 09:48:11,500 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:48:11,500 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 144 transitions. [2018-02-02 09:48:11,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-02-02 09:48:11,501 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:11,501 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:11,501 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:11,501 INFO L82 PathProgramCache]: Analyzing trace with hash -154740261, now seen corresponding path program 1 times [2018-02-02 09:48:11,502 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:11,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:11,511 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:11,856 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:11,856 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:11,856 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-02 09:48:11,857 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:11,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:11,857 INFO L182 omatonBuilderFactory]: Interpolants [7200#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 7178#true, 7179#false, 7180#(<= 1 main_~n~0), 7181#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7182#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 7183#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7184#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7185#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7186#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 7187#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 7188#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (<= 1 |cstrncat_#in~n|)), 7189#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 7190#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 7191#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n |cstrncat_#t~post2.offset| (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= |cstrncat_#t~post2.offset| 0)), 7192#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7193#(and (<= 0 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7194#(and (or (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)) (not |cstrncat_#t~short5|)) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7195#(and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7196#(and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= 0 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7197#(and (<= 1 cstrncat_~s~0.offset) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7198#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 7199#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post2.base|) cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post2.offset|)))] [2018-02-02 09:48:11,857 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 5 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:11,857 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-02 09:48:11,857 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-02 09:48:11,857 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=431, Unknown=0, NotChecked=0, Total=506 [2018-02-02 09:48:11,858 INFO L87 Difference]: Start difference. First operand 125 states and 144 transitions. Second operand 23 states. [2018-02-02 09:48:12,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:12,288 INFO L93 Difference]: Finished difference Result 160 states and 180 transitions. [2018-02-02 09:48:12,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:48:12,288 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 43 [2018-02-02 09:48:12,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:12,289 INFO L225 Difference]: With dead ends: 160 [2018-02-02 09:48:12,289 INFO L226 Difference]: Without dead ends: 157 [2018-02-02 09:48:12,289 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 387 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=240, Invalid=1242, Unknown=0, NotChecked=0, Total=1482 [2018-02-02 09:48:12,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-02-02 09:48:12,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 150. [2018-02-02 09:48:12,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-02-02 09:48:12,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 172 transitions. [2018-02-02 09:48:12,292 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 172 transitions. Word has length 43 [2018-02-02 09:48:12,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:12,292 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 172 transitions. [2018-02-02 09:48:12,292 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-02 09:48:12,292 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 172 transitions. [2018-02-02 09:48:12,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-02-02 09:48:12,293 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:12,293 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:12,293 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:12,293 INFO L82 PathProgramCache]: Analyzing trace with hash -154731225, now seen corresponding path program 1 times [2018-02-02 09:48:12,294 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:12,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:12,301 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:12,493 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:12,493 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:12,493 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 09:48:12,493 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:12,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:12,494 INFO L182 omatonBuilderFactory]: Interpolants [7552#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|))), 7553#(and (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 7554#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 7555#(and (<= (+ cstrncat_~n |cstrncat_#t~post2.offset| (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)) (= |cstrncat_#t~post2.offset| 0)), 7556#(<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)), 7557#(<= (+ cstrncat_~n (select |#length| |cstrncat_#t~post2.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post2.offset|)), 7558#(<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)), 7559#(and (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 7560#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 7561#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short5|)), 7562#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 7543#true, 7544#false, 7545#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 7546#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 7547#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7548#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7549#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7550#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 7551#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)))] [2018-02-02 09:48:12,494 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:12,494 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:48:12,494 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:48:12,494 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=329, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:48:12,494 INFO L87 Difference]: Start difference. First operand 150 states and 172 transitions. Second operand 20 states. [2018-02-02 09:48:12,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:12,852 INFO L93 Difference]: Finished difference Result 155 states and 175 transitions. [2018-02-02 09:48:12,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:48:12,852 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 43 [2018-02-02 09:48:12,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:12,853 INFO L225 Difference]: With dead ends: 155 [2018-02-02 09:48:12,853 INFO L226 Difference]: Without dead ends: 151 [2018-02-02 09:48:12,853 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 330 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=219, Invalid=1187, Unknown=0, NotChecked=0, Total=1406 [2018-02-02 09:48:12,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-02-02 09:48:12,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 125. [2018-02-02 09:48:12,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-02 09:48:12,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 144 transitions. [2018-02-02 09:48:12,855 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 144 transitions. Word has length 43 [2018-02-02 09:48:12,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:12,855 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 144 transitions. [2018-02-02 09:48:12,855 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:48:12,855 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 144 transitions. [2018-02-02 09:48:12,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 09:48:12,856 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:12,856 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:12,856 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:12,856 INFO L82 PathProgramCache]: Analyzing trace with hash 388447476, now seen corresponding path program 6 times [2018-02-02 09:48:12,856 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:12,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:12,869 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:13,248 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 111 DAG size of output 80 [2018-02-02 09:48:13,692 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 93 DAG size of output 59 [2018-02-02 09:48:13,829 WARN L146 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 96 DAG size of output 62 [2018-02-02 09:48:14,400 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:14,400 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:14,400 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-02 09:48:14,400 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:14,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:14,401 INFO L182 omatonBuilderFactory]: Interpolants [7879#true, 7880#false, 7881#(<= 1 main_~n~0), 7882#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (= 0 |main_#t~malloc13.offset|)), 7883#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1)), 7884#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|))), 7885#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7886#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 4)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ main_~nondetString1~0.offset (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 5)) (+ main_~nondetString1~0.offset (- 1))))))))), 7887#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (or (<= 9 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| |cstrncat_#in~s1.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 5 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ 4 (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 7888#(and (= cstrncat_~s~0.offset 0) (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (or (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 7 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 5 (- 1))))))), 7889#(and (or (and (<= 8 (select |#length| cstrncat_~s~0.base)) (or (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))))) (and (<= 6 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 4 (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 7 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 5 (- 1)))))) (= cstrncat_~s~0.offset 0)), 7890#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))))))), 7891#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 4) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))))))), 7892#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (<= 2 cstrncat_~s~0.offset))), 7893#(or (and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (<= 2 cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 7894#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 3 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))))))), 7895#(or (and (<= 3 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 7896#(and (<= 4 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))))), 7897#(and (<= 4 cstrncat_~s~0.offset) (or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 7898#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (<= 5 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 7899#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (<= 5 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 7900#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= 6 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 7901#(or (and (<= 6 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 7902#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 7 cstrncat_~s~0.offset)), 7903#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 8 cstrncat_~s~0.offset))] [2018-02-02 09:48:14,401 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:14,401 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-02 09:48:14,401 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-02 09:48:14,402 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=545, Unknown=0, NotChecked=0, Total=600 [2018-02-02 09:48:14,402 INFO L87 Difference]: Start difference. First operand 125 states and 144 transitions. Second operand 25 states. [2018-02-02 09:48:15,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:15,864 INFO L93 Difference]: Finished difference Result 188 states and 213 transitions. [2018-02-02 09:48:15,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:48:15,865 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 44 [2018-02-02 09:48:15,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:15,865 INFO L225 Difference]: With dead ends: 188 [2018-02-02 09:48:15,865 INFO L226 Difference]: Without dead ends: 184 [2018-02-02 09:48:15,866 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 397 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=165, Invalid=1815, Unknown=0, NotChecked=0, Total=1980 [2018-02-02 09:48:15,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-02-02 09:48:15,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 128. [2018-02-02 09:48:15,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 128 states. [2018-02-02 09:48:15,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 148 transitions. [2018-02-02 09:48:15,868 INFO L78 Accepts]: Start accepts. Automaton has 128 states and 148 transitions. Word has length 44 [2018-02-02 09:48:15,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:15,868 INFO L432 AbstractCegarLoop]: Abstraction has 128 states and 148 transitions. [2018-02-02 09:48:15,868 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-02 09:48:15,868 INFO L276 IsEmpty]: Start isEmpty. Operand 128 states and 148 transitions. [2018-02-02 09:48:15,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 09:48:15,869 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:15,869 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:15,869 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:15,869 INFO L82 PathProgramCache]: Analyzing trace with hash 1876668109, now seen corresponding path program 3 times [2018-02-02 09:48:15,870 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:15,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:15,876 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:16,126 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:48:16,126 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:16,126 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 09:48:16,126 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:16,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:16,127 INFO L182 omatonBuilderFactory]: Interpolants [8260#true, 8261#false, 8262#(= (select |#valid| |main_#t~malloc13.base|) 1), 8263#(= (select |#valid| main_~nondetString1~0.base) 1), 8264#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= 0 |main_#t~malloc14.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|))), 8265#(and (= main_~nondetString2~0.offset 0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 8266#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 8267#(and (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s2.base|) (+ (select |#length| |cstrncat_#in~s2.base|) (- 1))))), 8268#(and (= 0 (select (select |#memory_int| cstrncat_~s2.base) (+ (select |#length| cstrncat_~s2.base) (- 1)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 8269#(and (= |cstrncat_#t~post2.base| cstrncat_~s2.base) (= 0 (select (select |#memory_int| |cstrncat_#t~post2.base|) (+ (select |#length| cstrncat_~s2.base) (- 1)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 8270#(and (not (= |cstrncat_#t~post2.base| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s2.base) (+ (select |#length| cstrncat_~s2.base) (- 1)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 8271#(= 0 (select (select (store |#memory_int| cstrncat_~s~0.base (store (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset |cstrncat_#t~mem4|)) cstrncat_~s2.base) (+ (select |#length| cstrncat_~s2.base) (- 1)))), 8272#(= 0 (select (select |#memory_int| cstrncat_~s2.base) (+ (select |#length| cstrncat_~s2.base) (- 1)))), 8273#(or (and (<= (+ |cstrncat_#t~post2.offset| 1) cstrncat_~s2.offset) (or (<= (select |#length| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base)))) (= 0 (select (select |#memory_int| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|))), 8274#(or (and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (= 0 |cstrncat_#t~mem4|)), 8275#(or (and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))) (not |cstrncat_#t~short5|)), 8276#(and (<= 1 cstrncat_~s2.offset) (<= (+ cstrncat_~s2.offset 1) (select |#length| cstrncat_~s2.base))), 8277#(and (<= (+ |cstrncat_#t~post2.offset| 1) (select |#length| |cstrncat_#t~post2.base|)) (<= 1 |cstrncat_#t~post2.offset|))] [2018-02-02 09:48:16,127 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:48:16,127 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 09:48:16,127 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 09:48:16,127 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=262, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:48:16,127 INFO L87 Difference]: Start difference. First operand 128 states and 148 transitions. Second operand 18 states. [2018-02-02 09:48:16,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:16,532 INFO L93 Difference]: Finished difference Result 139 states and 155 transitions. [2018-02-02 09:48:16,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 09:48:16,532 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 46 [2018-02-02 09:48:16,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:16,532 INFO L225 Difference]: With dead ends: 139 [2018-02-02 09:48:16,532 INFO L226 Difference]: Without dead ends: 114 [2018-02-02 09:48:16,533 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 130 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=173, Invalid=819, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:48:16,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-02-02 09:48:16,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 77. [2018-02-02 09:48:16,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-02-02 09:48:16,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 87 transitions. [2018-02-02 09:48:16,534 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 87 transitions. Word has length 46 [2018-02-02 09:48:16,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:16,535 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 87 transitions. [2018-02-02 09:48:16,535 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 09:48:16,535 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 87 transitions. [2018-02-02 09:48:16,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 09:48:16,535 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:16,535 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:16,535 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:16,535 INFO L82 PathProgramCache]: Analyzing trace with hash -531401182, now seen corresponding path program 2 times [2018-02-02 09:48:16,536 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:16,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:16,542 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:16,828 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 3 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:16,829 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:16,829 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 09:48:16,829 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:16,829 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:16,829 INFO L182 omatonBuilderFactory]: Interpolants [8522#true, 8523#false, 8524#(<= 1 main_~n~0), 8525#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8526#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 8527#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8528#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8529#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8530#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 8531#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 8532#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (<= 1 |cstrncat_#in~n|)), 8533#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 8534#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 8535#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 2)) (= 0 cstrncat_~s2.offset) (<= 2 cstrncat_~s~0.offset)), 8536#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n |cstrncat_#t~post2.offset| (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (= |cstrncat_#t~post2.offset| 0) (<= 2 cstrncat_~s~0.offset)), 8537#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= 2 cstrncat_~s~0.offset)), 8538#(and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= cstrncat_~n 0)) (<= 3 cstrncat_~s~0.offset) (<= 0 cstrncat_~n)), 8539#(or (not |cstrncat_#t~short5|) (and (<= 3 cstrncat_~s~0.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n))), 8540#(and (<= 3 cstrncat_~s~0.offset) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 8541#(and (<= 4 cstrncat_~s~0.offset) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset))), 8542#(and (<= 4 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post2.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post2.offset|))), 8543#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:48:16,829 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 3 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:16,830 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:48:16,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:48:16,830 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=403, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:48:16,830 INFO L87 Difference]: Start difference. First operand 77 states and 87 transitions. Second operand 22 states. [2018-02-02 09:48:17,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:17,366 INFO L93 Difference]: Finished difference Result 106 states and 116 transitions. [2018-02-02 09:48:17,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:48:17,366 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 46 [2018-02-02 09:48:17,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:17,366 INFO L225 Difference]: With dead ends: 106 [2018-02-02 09:48:17,367 INFO L226 Difference]: Without dead ends: 101 [2018-02-02 09:48:17,367 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 347 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=201, Invalid=1281, Unknown=0, NotChecked=0, Total=1482 [2018-02-02 09:48:17,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-02-02 09:48:17,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 96. [2018-02-02 09:48:17,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-02-02 09:48:17,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 107 transitions. [2018-02-02 09:48:17,368 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 107 transitions. Word has length 46 [2018-02-02 09:48:17,368 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:17,368 INFO L432 AbstractCegarLoop]: Abstraction has 96 states and 107 transitions. [2018-02-02 09:48:17,368 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:48:17,368 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 107 transitions. [2018-02-02 09:48:17,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 09:48:17,368 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:17,369 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:17,369 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:17,369 INFO L82 PathProgramCache]: Analyzing trace with hash -531392146, now seen corresponding path program 2 times [2018-02-02 09:48:17,369 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:17,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:17,374 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:17,895 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:17,895 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:17,895 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 09:48:17,895 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:17,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:17,895 INFO L182 omatonBuilderFactory]: Interpolants [8800#(and (<= 4 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short5|)), 8801#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 8780#true, 8781#false, 8782#(<= (+ main_~n~0 main_~length2~0) main_~length1~0), 8783#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 8784#(and (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~nondetString1~0.offset 0)), 8785#(and (or (and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~nondetString1~0.offset 0)), 8786#(and (or (and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8787#(and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~length2~0 main_~nondetString1~0.offset) 1)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8788#(and (or (and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) 1))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8789#(and (= 0 |cstrncat_#in~s1.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (= 0 |cstrncat_#in~s2.offset|) (or (<= (select |#length| |cstrncat_#in~s2.base|) 1) (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~s1.base|))))) (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|))), 8790#(and (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 cstrncat_~s2.offset) (or (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 1)))) (= cstrncat_~s~0.offset 0) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 8791#(and (<= 1 cstrncat_~s~0.offset) (or (and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 1)) (= 0 cstrncat_~s2.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 8792#(and (<= 1 cstrncat_~s~0.offset) (or (and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) 1)) (= 0 cstrncat_~s2.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 1 cstrncat_~s~0.offset) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 8793#(and (or (<= (select |#length| cstrncat_~s2.base) 1) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (= 0 cstrncat_~s2.offset) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (<= 2 cstrncat_~s~0.offset)), 8794#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ |cstrncat_#t~post2.offset| (select |#length| cstrncat_~s2.base)) cstrncat_~s2.offset)) (not (= |cstrncat_#t~post2.base| cstrncat_~s~0.base)) (= |cstrncat_#t~post2.offset| 0) (<= 2 cstrncat_~s~0.offset)), 8795#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 8796#(and (<= 3 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset))), 8797#(and (<= 3 cstrncat_~s~0.offset) (or (<= (select |#length| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 8798#(and (<= 3 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 8799#(and (<= 4 cstrncat_~s~0.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:48:17,896 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 5 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:17,896 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:48:17,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:48:17,896 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=408, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:48:17,896 INFO L87 Difference]: Start difference. First operand 96 states and 107 transitions. Second operand 22 states. [2018-02-02 09:48:18,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:18,620 INFO L93 Difference]: Finished difference Result 117 states and 127 transitions. [2018-02-02 09:48:18,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 09:48:18,620 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 46 [2018-02-02 09:48:18,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:18,620 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:48:18,620 INFO L226 Difference]: Without dead ends: 94 [2018-02-02 09:48:18,621 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 202 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=170, Invalid=1162, Unknown=0, NotChecked=0, Total=1332 [2018-02-02 09:48:18,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-02-02 09:48:18,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 77. [2018-02-02 09:48:18,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-02-02 09:48:18,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 86 transitions. [2018-02-02 09:48:18,622 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 86 transitions. Word has length 46 [2018-02-02 09:48:18,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:18,622 INFO L432 AbstractCegarLoop]: Abstraction has 77 states and 86 transitions. [2018-02-02 09:48:18,622 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:48:18,622 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 86 transitions. [2018-02-02 09:48:18,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 09:48:18,622 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:18,623 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:18,623 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:18,623 INFO L82 PathProgramCache]: Analyzing trace with hash 1596860813, now seen corresponding path program 7 times [2018-02-02 09:48:18,623 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:18,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:18,635 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:19,596 WARN L146 SmtUtils]: Spent 338ms on a formula simplification. DAG size of input: 151 DAG size of output 99 [2018-02-02 09:48:19,823 WARN L146 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 135 DAG size of output 92 [2018-02-02 09:48:20,016 WARN L146 SmtUtils]: Spent 164ms on a formula simplification. DAG size of input: 126 DAG size of output 62 [2018-02-02 09:48:20,203 WARN L146 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 126 DAG size of output 62 [2018-02-02 09:48:20,379 WARN L146 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 129 DAG size of output 65 [2018-02-02 09:48:20,629 WARN L146 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 148 DAG size of output 71 [2018-02-02 09:48:20,890 WARN L146 SmtUtils]: Spent 199ms on a formula simplification. DAG size of input: 151 DAG size of output 74 [2018-02-02 09:48:21,241 WARN L146 SmtUtils]: Spent 266ms on a formula simplification. DAG size of input: 132 DAG size of output 78 [2018-02-02 09:48:21,563 WARN L146 SmtUtils]: Spent 250ms on a formula simplification. DAG size of input: 135 DAG size of output 75 [2018-02-02 09:48:21,775 WARN L146 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 127 DAG size of output 57 [2018-02-02 09:48:21,997 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 130 DAG size of output 60 [2018-02-02 09:48:22,423 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:22,423 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:22,423 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-02-02 09:48:22,423 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:22,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:22,424 INFO L182 omatonBuilderFactory]: Interpolants [9026#true, 9027#false, 9028#(<= 1 main_~length2~0), 9029#(and (<= 1 main_~length2~0) (<= 1 main_~n~0)), 9030#(and (<= 1 main_~length2~0) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9031#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (<= 1 main_~length2~0) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 9032#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (or (< (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)) (and (<= 1 main_~length2~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~nondetString1~0.offset 0)), 9033#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (or (< (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)) (and (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~nondetString1~0.offset 0)), 9034#(and (or (< (+ main_~n~0 2) (+ main_~nondetString1~0.offset main_~length1~0)) (and (= main_~nondetString2~0.offset 0) (= 1 (+ main_~nondetString2~0.offset main_~length2~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~nondetString2~0.offset main_~n~0 main_~length2~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 9035#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 1) (+ main_~n~0 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1))))))) (and (= main_~nondetString2~0.offset 0) (= 1 (+ main_~nondetString2~0.offset main_~length2~0)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 5))) 2) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 5))) 2) 2) (+ main_~n~0 (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 3) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 2) (+ main_~n~0 (select |#length| main_~nondetString1~0.base)))) (and (or (<= (+ main_~n~0 5) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 4) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~n~0)) (<= 2 main_~n~0) (<= (+ (* 2 main_~n~0) 1) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= main_~nondetString1~0.offset 0)), 9036#(and (or (and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 5))) 2) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 5))) 2) 3) (+ main_~n~0 (select |#length| main_~nondetString1~0.base)))) (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 5))) 2) 2) (+ main_~n~0 (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 1) (+ main_~n~0 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) 2) (+ main_~n~0 (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString1~0.offset) 3))) 2) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 3) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset))) (and (<= (+ main_~n~0 4) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (div (+ (* 2 main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (- main_~nondetString1~0.offset))) 2) (+ main_~nondetString1~0.offset (- 1))))))) (and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~n~0)) (<= 2 main_~n~0) (<= (+ (* 2 main_~n~0) 1) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 9037#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (<= (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 3) 2) 2) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 3) 2) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (div (select |#length| |cstrncat_#in~s1.base|) 2) (- 1)))) (<= 4 (div (select |#length| |cstrncat_#in~s1.base|) 2))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ 3 (- 1)))) (<= 3 (div (select |#length| |cstrncat_#in~s1.base|) 2))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) 2))) (<= 2 (div (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) 2))) (and (<= (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 3) 2) 1) (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1))))) (and (<= (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 5) 2) 2) (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 5) 2) (- 1)))) (<= (+ (div (+ (select |#length| |cstrncat_#in~s1.base|) 5) 2) 3) (select |#length| |cstrncat_#in~s1.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)))), 9038#(and (or (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2))) (<= 2 (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 3 (div (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1))))) (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) 2) (select |#length| cstrncat_~s~0.base)) (or (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) (- 1)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 2) (select |#length| cstrncat_~s~0.base))) (and (<= 4 (div (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (select |#length| cstrncat_~s~0.base) 2) (- 1)))))) (= cstrncat_~s~0.offset 0)), 9039#(and (or (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2))) (<= 2 (div (+ (select |#length| cstrncat_~s~0.base) (- 1)) 2))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (<= 3 (div (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1))))) (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) 2) (select |#length| cstrncat_~s~0.base)) (or (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) 5) 2) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) (- 1)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) 3) 2) 2) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 4 (div (select |#length| cstrncat_~s~0.base) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (select |#length| cstrncat_~s~0.base) 2) (- 1)))))) (= cstrncat_~s~0.offset 0)), 9040#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1)) (and (or (and (<= cstrncat_~s~0.offset (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 1) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2))) 2))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2))) 2)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 2) (select |#length| cstrncat_~s~0.base))) (and (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 4)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 4)) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 1) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 2) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2))) (and (<= (+ cstrncat_~s~0.offset 3) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2))))), 9041#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (and (<= cstrncat_~s~0.offset (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~s~0.offset 1) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2))) 2))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 2))) 2)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 2) (select |#length| cstrncat_~s~0.base))) (and (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 4)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 4)) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 1) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 2) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2))) (and (<= (+ cstrncat_~s~0.offset 3) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 4) (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) 2))))), 9042#(or (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2)) (- 2)))) (- 1)))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2))) (and (<= (+ cstrncat_~s~0.offset 2) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2)) (- 1)))) (- 1)))) (<= (+ cstrncat_~s~0.offset 1) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2))) (or (and (<= cstrncat_~s~0.offset (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2)))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 3)) 2) 3) (select |#length| cstrncat_~s~0.base)) (and (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) 2) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))), 9043#(or (and (<= cstrncat_~s~0.offset (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2)) (- 2)))) (- 1)))) (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2))) (and (<= (+ cstrncat_~s~0.offset 2) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 2))) 2) (- 1))))) (and (<= cstrncat_~s~0.offset (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 3))) 2)) (- 2)))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (+ (- (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2)) (- 1)))) (- 1)))) (<= (+ cstrncat_~s~0.offset 1) (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset (- 5))) 2))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (<= (+ (div (+ (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 3)) 2) 3) (select |#length| cstrncat_~s~0.base))), 9044#(or (and (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 2) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 3) (select |#length| cstrncat_~s~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ (div (+ cstrncat_~s~0.offset (select |#length| cstrncat_~s~0.base)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (select |#length| cstrncat_~s~0.base)) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= cstrncat_~s~0.offset (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 4))) 2) 2))) (and (<= cstrncat_~s~0.offset (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 4))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (+ (- (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 4))) 2)) (- 3)))) (- 1)))))), 9045#(or (and (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 2) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) (- 1)))) (<= (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) 2)) 2) 3) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ (div (+ cstrncat_~s~0.offset (select |#length| cstrncat_~s~0.base)) 2) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (div (+ cstrncat_~s~0.offset (select |#length| cstrncat_~s~0.base)) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= cstrncat_~s~0.offset (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 4))) 2) 2))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= cstrncat_~s~0.offset (+ (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 4))) 2) 1)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (+ (- (div (+ cstrncat_~s~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 4))) 2)) (- 3)))) (- 1)))))), 9046#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 2)) (- 1)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 9047#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 2)) (- 1)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 3)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))), 9048#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 3))), 9049#(or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 3)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9050#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))), 9051#(or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 2)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9052#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 9053#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9054#(or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9055#(and (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 9056#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))] [2018-02-02 09:48:22,425 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:22,425 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-02 09:48:22,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-02 09:48:22,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=810, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:48:22,426 INFO L87 Difference]: Start difference. First operand 77 states and 86 transitions. Second operand 31 states. [2018-02-02 09:48:22,870 WARN L146 SmtUtils]: Spent 173ms on a formula simplification. DAG size of input: 134 DAG size of output 124 [2018-02-02 09:48:23,343 WARN L143 SmtUtils]: Spent 103ms on a formula simplification that was a NOOP. DAG size: 125 [2018-02-02 09:48:23,615 WARN L146 SmtUtils]: Spent 242ms on a formula simplification. DAG size of input: 131 DAG size of output 129 [2018-02-02 09:48:23,889 WARN L146 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 136 DAG size of output 132 [2018-02-02 09:48:24,108 WARN L146 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 141 DAG size of output 132 [2018-02-02 09:48:24,303 WARN L146 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 121 DAG size of output 105 [2018-02-02 09:48:24,532 WARN L146 SmtUtils]: Spent 180ms on a formula simplification. DAG size of input: 138 DAG size of output 120 [2018-02-02 09:48:24,730 WARN L146 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 103 DAG size of output 98 [2018-02-02 09:48:24,914 WARN L146 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 113 DAG size of output 107 [2018-02-02 09:48:25,069 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 92 DAG size of output 86 [2018-02-02 09:48:25,296 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 95 DAG size of output 89 [2018-02-02 09:48:25,584 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 88 DAG size of output 83 [2018-02-02 09:48:26,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:26,168 INFO L93 Difference]: Finished difference Result 139 states and 150 transitions. [2018-02-02 09:48:26,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-02 09:48:26,169 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 47 [2018-02-02 09:48:26,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:26,169 INFO L225 Difference]: With dead ends: 139 [2018-02-02 09:48:26,169 INFO L226 Difference]: Without dead ends: 131 [2018-02-02 09:48:26,170 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 707 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=420, Invalid=2442, Unknown=0, NotChecked=0, Total=2862 [2018-02-02 09:48:26,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-02-02 09:48:26,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 80. [2018-02-02 09:48:26,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-02-02 09:48:26,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 90 transitions. [2018-02-02 09:48:26,172 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 90 transitions. Word has length 47 [2018-02-02 09:48:26,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:26,172 INFO L432 AbstractCegarLoop]: Abstraction has 80 states and 90 transitions. [2018-02-02 09:48:26,172 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-02 09:48:26,172 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 90 transitions. [2018-02-02 09:48:26,172 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-02-02 09:48:26,172 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:26,173 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:26,173 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:26,173 INFO L82 PathProgramCache]: Analyzing trace with hash 1112645755, now seen corresponding path program 3 times [2018-02-02 09:48:26,173 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:26,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:26,182 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:26,567 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 3 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:26,567 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:26,567 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-02 09:48:26,567 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:26,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:26,568 INFO L182 omatonBuilderFactory]: Interpolants [9344#(and (<= 1 cstrncat_~s~0.offset) (or (not |cstrncat_#t~short5|) (<= (+ (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset)))), 9345#(and (<= 1 cstrncat_~s~0.offset) (<= (+ (select |#length| |cstrncat_#t~post2.base|) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post2.offset|))), 9346#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 9322#true, 9323#false, 9324#(<= 1 main_~n~0), 9325#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9326#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 9327#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9328#(and (= 0 main_~nondetString1~0.offset) (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9329#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9330#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 9331#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 9332#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (<= 1 |cstrncat_#in~n|)), 9333#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0)), 9334#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset)), 9335#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 2)) (= 0 cstrncat_~s2.offset)), 9336#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 3))), 9337#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post2.offset| 0) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset| cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2))), 9338#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2))), 9339#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2)) (<= 0 cstrncat_~n)), 9340#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 2)) (or (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)) (not |cstrncat_#t~short5|))), 9341#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)), 9342#(and (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n) (<= 0 cstrncat_~s~0.offset)), 9343#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) cstrncat_~s2.offset 1)) (<= cstrncat_~n 0)) (<= 0 cstrncat_~n))] [2018-02-02 09:48:26,568 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 3 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:26,568 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-02 09:48:26,568 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-02 09:48:26,568 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=509, Unknown=0, NotChecked=0, Total=600 [2018-02-02 09:48:26,568 INFO L87 Difference]: Start difference. First operand 80 states and 90 transitions. Second operand 25 states. [2018-02-02 09:48:27,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:27,178 INFO L93 Difference]: Finished difference Result 109 states and 119 transitions. [2018-02-02 09:48:27,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:48:27,178 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 49 [2018-02-02 09:48:27,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:27,179 INFO L225 Difference]: With dead ends: 109 [2018-02-02 09:48:27,179 INFO L226 Difference]: Without dead ends: 104 [2018-02-02 09:48:27,179 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 475 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=315, Invalid=1577, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 09:48:27,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-02-02 09:48:27,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 99. [2018-02-02 09:48:27,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-02-02 09:48:27,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 110 transitions. [2018-02-02 09:48:27,181 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 110 transitions. Word has length 49 [2018-02-02 09:48:27,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:27,181 INFO L432 AbstractCegarLoop]: Abstraction has 99 states and 110 transitions. [2018-02-02 09:48:27,181 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-02 09:48:27,181 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 110 transitions. [2018-02-02 09:48:27,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-02-02 09:48:27,181 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:27,181 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:27,181 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:27,181 INFO L82 PathProgramCache]: Analyzing trace with hash 1112654791, now seen corresponding path program 3 times [2018-02-02 09:48:27,182 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:27,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:27,190 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:27,613 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:27,614 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:27,614 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 09:48:27,614 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:27,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:27,614 INFO L182 omatonBuilderFactory]: Interpolants [9600#(and (= 0 |cstrncat_#in~s1.offset|) (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|)) (or (<= (+ (* 2 |cstrncat_#in~n|) 2) (select |#length| |cstrncat_#in~s1.base|)) (<= (select |#length| |cstrncat_#in~s1.base|) (* 2 |cstrncat_#in~n|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~n|)))), 9601#(and (= cstrncat_~s~0.offset 0) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (<= (+ (* 2 cstrncat_~n) 2) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~n)) (<= (select |#length| cstrncat_~s~0.base) (* 2 cstrncat_~n)))), 9602#(and (or (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset)) (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ cstrncat_~n (+ cstrncat_~s~0.offset (- 1)))))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 9603#(and (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= cstrncat_~n 1) (<= 3 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset)))), 9604#(and (or (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (<= cstrncat_~n 1) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (<= 3 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 9605#(and (or (<= (+ (select |#length| cstrncat_~s~0.base) 3) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset)) (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (<= cstrncat_~n 1) (<= 3 cstrncat_~n)) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 9606#(and (not (= |cstrncat_#t~post2.base| cstrncat_~s~0.base)) (or (<= (+ (select |#length| cstrncat_~s~0.base) 3) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset)) (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (<= cstrncat_~n 1) (<= 3 cstrncat_~n))), 9607#(or (<= (+ (select |#length| cstrncat_~s~0.base) 3) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset)) (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (<= cstrncat_~n 1) (<= 3 cstrncat_~n)), 9608#(or (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (<= cstrncat_~n 0) (<= 2 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset))), 9609#(and (or (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (<= cstrncat_~n 0) (<= 2 cstrncat_~n)) (<= 0 cstrncat_~s~0.offset)), 9610#(and (<= 1 cstrncat_~s~0.offset) (or (<= 1 cstrncat_~n) (<= (+ cstrncat_~n 1) 0) (<= (+ (* 2 cstrncat_~n) cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 9611#(or (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) |cstrncat_#t~short5|), 9612#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 9593#true, 9594#false, 9595#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (= 0 |main_#t~malloc13.offset|)), 9596#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 9597#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 9598#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 9599#(and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~n~0)) (<= (+ (* 2 main_~n~0) 2) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) (* 2 main_~n~0))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:48:27,614 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 33 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:27,614 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:48:27,615 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:48:27,615 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=337, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:48:27,615 INFO L87 Difference]: Start difference. First operand 99 states and 110 transitions. Second operand 20 states. [2018-02-02 09:48:28,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:28,191 INFO L93 Difference]: Finished difference Result 129 states and 140 transitions. [2018-02-02 09:48:28,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:48:28,191 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 49 [2018-02-02 09:48:28,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:28,191 INFO L225 Difference]: With dead ends: 129 [2018-02-02 09:48:28,192 INFO L226 Difference]: Without dead ends: 127 [2018-02-02 09:48:28,192 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 170 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=136, Invalid=1124, Unknown=0, NotChecked=0, Total=1260 [2018-02-02 09:48:28,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-02-02 09:48:28,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 106. [2018-02-02 09:48:28,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-02 09:48:28,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 117 transitions. [2018-02-02 09:48:28,193 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 117 transitions. Word has length 49 [2018-02-02 09:48:28,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:28,194 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 117 transitions. [2018-02-02 09:48:28,194 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:48:28,194 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 117 transitions. [2018-02-02 09:48:28,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 09:48:28,194 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:28,194 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:28,195 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:28,195 INFO L82 PathProgramCache]: Analyzing trace with hash 1022708308, now seen corresponding path program 8 times [2018-02-02 09:48:28,195 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:28,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:28,211 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:29,932 WARN L146 SmtUtils]: Spent 437ms on a formula simplification. DAG size of input: 177 DAG size of output 99 [2018-02-02 09:48:30,278 WARN L146 SmtUtils]: Spent 320ms on a formula simplification. DAG size of input: 160 DAG size of output 90 [2018-02-02 09:48:30,533 WARN L146 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-02 09:48:30,808 WARN L146 SmtUtils]: Spent 249ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-02 09:48:31,097 WARN L146 SmtUtils]: Spent 262ms on a formula simplification. DAG size of input: 112 DAG size of output 66 [2018-02-02 09:48:31,384 WARN L146 SmtUtils]: Spent 246ms on a formula simplification. DAG size of input: 126 DAG size of output 70 [2018-02-02 09:48:31,681 WARN L146 SmtUtils]: Spent 262ms on a formula simplification. DAG size of input: 129 DAG size of output 73 [2018-02-02 09:48:31,874 WARN L146 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-02 09:48:32,112 WARN L146 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-02 09:48:32,255 WARN L146 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-02 09:48:32,393 WARN L146 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-02 09:48:33,011 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:33,011 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:33,011 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-02 09:48:33,011 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:33,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:33,012 INFO L182 omatonBuilderFactory]: Interpolants [9880#true, 9881#false, 9882#(<= 1 main_~length2~0), 9883#(and (<= 1 main_~length2~0) (<= 1 main_~n~0)), 9884#(and (<= 1 main_~length2~0) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9885#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (<= 1 main_~length2~0) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 9886#(and (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length2~0) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 9887#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc14.offset|) (<= 1 main_~length2~0) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 9888#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (= main_~nondetString2~0.offset 0) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~nondetString2~0.offset main_~n~0 main_~length2~0))) (<= 1 main_~length2~0) (or (= 1 (+ main_~nondetString2~0.offset main_~length2~0)) (<= 1 main_~n~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 9889#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= main_~nondetString2~0.offset 0) (<= 1 main_~length2~0) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 1 (+ main_~nondetString2~0.offset main_~length2~0)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))))))), 9890#(and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (= main_~nondetString2~0.offset 0) (or (and (or (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 9891#(and (= 0 |cstrncat_#in~s1.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ 3 (- 1)))) (<= 9 (select |#length| |cstrncat_#in~s1.base|))) (and (<= 10 (select |#length| |cstrncat_#in~s1.base|)) (or (<= 11 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (<= 5 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) |cstrncat_#in~s1.offset|)) (and (<= 4 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1))))) (and (<= 7 (select |#length| |cstrncat_#in~s1.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))))), 9892#(and (= cstrncat_~s~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1))))) (and (or (<= 11 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 10 (select |#length| cstrncat_~s~0.base))))), 9893#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)))) (<= 5 (select |#length| cstrncat_~s~0.base))) (and (<= 8 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (or (<= 11 (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 10 (select |#length| cstrncat_~s~0.base)))) (= cstrncat_~s~0.offset 0)), 9894#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))), 9895#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= cstrncat_~s~0.offset 1) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 10) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))), 9896#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))), 9897#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~s~0.offset 9) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1))))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))), 9898#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))), 9899#(or (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base))) (and (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~s~0.offset 8) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))), 9900#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))), 9901#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 7) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1)))))), 9902#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))))), 9903#(or (and (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))) (<= (+ cstrncat_~s~0.offset 6) (select |#length| cstrncat_~s~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))))), 9904#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 9905#(or (and (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (or (<= (+ cstrncat_~s~0.offset 5) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 3) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1)))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9906#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)))), 9907#(or (and (or (<= (+ cstrncat_~s~0.offset 4) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ cstrncat_~s~0.offset 2) (- 1))))) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 9908#(or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base))), 9909#(and (or (<= (+ cstrncat_~s~0.offset 3) (select |#length| cstrncat_~s~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (<= 0 cstrncat_~s~0.offset)), 9910#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base))), 9911#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))] [2018-02-02 09:48:33,013 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:33,013 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-02 09:48:33,013 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-02 09:48:33,013 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=838, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:48:33,013 INFO L87 Difference]: Start difference. First operand 106 states and 117 transitions. Second operand 32 states. [2018-02-02 09:48:33,417 WARN L146 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 133 DAG size of output 126 [2018-02-02 09:48:33,872 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 125 DAG size of output 123 [2018-02-02 09:48:34,011 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 114 DAG size of output 112 [2018-02-02 09:48:34,146 WARN L146 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 119 DAG size of output 114 [2018-02-02 09:48:34,402 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 116 DAG size of output 108 [2018-02-02 09:48:35,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:35,799 INFO L93 Difference]: Finished difference Result 168 states and 181 transitions. [2018-02-02 09:48:35,799 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-02-02 09:48:35,799 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 50 [2018-02-02 09:48:35,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:35,800 INFO L225 Difference]: With dead ends: 168 [2018-02-02 09:48:35,800 INFO L226 Difference]: Without dead ends: 160 [2018-02-02 09:48:35,800 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 798 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=491, Invalid=2701, Unknown=0, NotChecked=0, Total=3192 [2018-02-02 09:48:35,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-02-02 09:48:35,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 109. [2018-02-02 09:48:35,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-02 09:48:35,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 121 transitions. [2018-02-02 09:48:35,801 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 121 transitions. Word has length 50 [2018-02-02 09:48:35,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:35,802 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 121 transitions. [2018-02-02 09:48:35,802 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-02 09:48:35,802 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 121 transitions. [2018-02-02 09:48:35,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-02 09:48:35,802 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:35,802 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:35,802 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:35,802 INFO L82 PathProgramCache]: Analyzing trace with hash -892097662, now seen corresponding path program 4 times [2018-02-02 09:48:35,803 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:35,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:35,808 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:36,537 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 3 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:36,537 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:36,537 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:48:36,537 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:36,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:36,538 INFO L182 omatonBuilderFactory]: Interpolants [10240#false, 10241#(<= 1 main_~n~0), 10242#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10243#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= 0 |main_#t~malloc13.offset|)), 10244#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10245#(and (= 0 |main_#t~malloc14.offset|) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~length2~0 (select |#length| |main_#t~malloc14.base|)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10246#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10247#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 10248#(and (= 0 main_~nondetString2~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 10249#(and (= 0 |cstrncat_#in~s1.offset|) (= 0 |cstrncat_#in~s2.offset|) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (select |#length| |cstrncat_#in~s1.base|) (- |cstrncat_#in~n|)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~s2.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~s1.base|))) (<= 1 |cstrncat_#in~n|)), 10250#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s2.offset) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base)) (select |#length| cstrncat_~s~0.base)) (= cstrncat_~s~0.offset 0) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) 1) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- cstrncat_~n)) (- 1)))))), 10251#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (+ (select |#length| cstrncat_~s~0.base) 1)) (= 0 cstrncat_~s2.offset) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~s2.base) cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (+ (- cstrncat_~n) (+ (- (select |#length| cstrncat_~s~0.base)) (select |#length| cstrncat_~s~0.base)))) (- 1)))))), 10252#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 10253#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 10254#(and (<= 1 cstrncat_~n) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 10255#(and (<= 1 cstrncat_~n) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base)))), 10256#(and (<= 1 cstrncat_~n) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (and (= 0 cstrncat_~s2.offset) (<= (select |#length| cstrncat_~s2.base) 2)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~s~0.offset)), 10257#(and (<= 1 cstrncat_~n) (not (= cstrncat_~s~0.base |cstrncat_#t~post2.base|)) (or (and (<= (+ (select |#length| cstrncat_~s2.base) |cstrncat_#t~post2.offset|) (+ cstrncat_~s2.offset 1)) (= |cstrncat_#t~post2.offset| 0)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~s~0.offset)), 10258#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~s~0.offset)), 10259#(and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)), 10260#(and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s2.base) (+ cstrncat_~s2.offset 1)) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (or (and (not (= cstrncat_~n 0)) (<= 0 cstrncat_~n)) (not |cstrncat_#t~short5|))), 10261#(and (<= 1 cstrncat_~s~0.offset) (not (= cstrncat_~n 0)) (or (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n)), 10262#(and (or (<= cstrncat_~n 0) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset) (<= (+ cstrncat_~n cstrncat_~s~0.offset) (select |#length| cstrncat_~s~0.base))) (<= 0 cstrncat_~n) (<= 2 cstrncat_~s~0.offset)), 10263#(and (or (not |cstrncat_#t~short5|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s2.base) cstrncat_~s2.offset)) (<= 2 cstrncat_~s~0.offset)), 10264#(and (or (<= (select |#length| |cstrncat_#t~post2.base|) |cstrncat_#t~post2.offset|) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset)), 10265#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 10239#true] [2018-02-02 09:48:36,538 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 3 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:36,538 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:48:36,539 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:48:36,539 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=619, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:48:36,539 INFO L87 Difference]: Start difference. First operand 109 states and 121 transitions. Second operand 27 states. [2018-02-02 09:48:37,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:37,370 INFO L93 Difference]: Finished difference Result 155 states and 167 transitions. [2018-02-02 09:48:37,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:48:37,371 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 52 [2018-02-02 09:48:37,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:37,371 INFO L225 Difference]: With dead ends: 155 [2018-02-02 09:48:37,371 INFO L226 Difference]: Without dead ends: 150 [2018-02-02 09:48:37,372 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 496 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=248, Invalid=1644, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 09:48:37,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-02-02 09:48:37,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 109. [2018-02-02 09:48:37,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-02 09:48:37,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 121 transitions. [2018-02-02 09:48:37,373 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 121 transitions. Word has length 52 [2018-02-02 09:48:37,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:37,373 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 121 transitions. [2018-02-02 09:48:37,373 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:48:37,373 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 121 transitions. [2018-02-02 09:48:37,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-02 09:48:37,373 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:37,374 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:37,374 INFO L371 AbstractCegarLoop]: === Iteration 38 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:37,374 INFO L82 PathProgramCache]: Analyzing trace with hash -892088626, now seen corresponding path program 4 times [2018-02-02 09:48:37,374 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:37,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:37,379 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:37,771 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 09:48:37,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:48:37,772 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 09:48:37,772 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:48:37,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:48:37,772 INFO L182 omatonBuilderFactory]: Interpolants [10564#true, 10565#false, 10566#(and (= main_~length1~0 (select |#length| |main_#t~malloc13.base|)) (= (select |#valid| |main_#t~malloc13.base|) 1) (= 0 |main_#t~malloc13.offset|)), 10567#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 10568#(and (not (= main_~nondetString1~0.base |main_#t~malloc14.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 10569#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 10570#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 10571#(and (not (= |cstrncat_#in~s1.base| |cstrncat_#in~s2.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~s1.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~s1.base|)) (- 1))))), 10572#(and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (+ (select |#length| cstrncat_~s~0.base) (- cstrncat_~n)) (- 1)))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 10573#(and (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~n cstrncat_~s~0.offset)))), 10574#(and (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~n cstrncat_~s~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset))))), 10575#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ cstrncat_~n cstrncat_~s~0.offset))) (not (= cstrncat_~s~0.base cstrncat_~s2.base))), 10576#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ cstrncat_~n cstrncat_~s~0.offset))) (not (= cstrncat_~s~0.base cstrncat_~s2.base)) (<= 0 cstrncat_~s~0.offset)), 10577#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ cstrncat_~n cstrncat_~s~0.offset))) (not (= |cstrncat_#t~post2.base| cstrncat_~s~0.base)) (<= 0 cstrncat_~s~0.offset)), 10578#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ cstrncat_~n cstrncat_~s~0.offset))) (<= 0 cstrncat_~s~0.offset)), 10579#(and (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (+ cstrncat_~n cstrncat_~s~0.offset))) (<= 1 cstrncat_~s~0.offset)), 10580#(and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~n))), 10581#(and (or (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= 2 cstrncat_~s~0.offset)), 10582#(and (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) |cstrncat_#t~short5|) (<= 2 cstrncat_~s~0.offset)), 10583#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))] [2018-02-02 09:48:37,772 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 09:48:37,773 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:48:37,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:48:37,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=335, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:48:37,773 INFO L87 Difference]: Start difference. First operand 109 states and 121 transitions. Second operand 20 states. [2018-02-02 09:48:38,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:48:38,413 INFO L93 Difference]: Finished difference Result 126 states and 137 transitions. [2018-02-02 09:48:38,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:48:38,413 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 52 [2018-02-02 09:48:38,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:48:38,414 INFO L225 Difference]: With dead ends: 126 [2018-02-02 09:48:38,414 INFO L226 Difference]: Without dead ends: 87 [2018-02-02 09:48:38,414 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 1 SyntacticMatches, 3 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 203 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=269, Invalid=1213, Unknown=0, NotChecked=0, Total=1482 [2018-02-02 09:48:38,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-02-02 09:48:38,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 74. [2018-02-02 09:48:38,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-02-02 09:48:38,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-02-02 09:48:38,415 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 52 [2018-02-02 09:48:38,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:48:38,415 INFO L432 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-02-02 09:48:38,415 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:48:38,415 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-02-02 09:48:38,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 09:48:38,416 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:48:38,416 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:48:38,416 INFO L371 AbstractCegarLoop]: === Iteration 39 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr9RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr8RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:48:38,416 INFO L82 PathProgramCache]: Analyzing trace with hash -994795475, now seen corresponding path program 9 times [2018-02-02 09:48:38,416 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:48:38,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:48:38,426 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:48:39,611 WARN L146 SmtUtils]: Spent 476ms on a formula simplification. DAG size of input: 192 DAG size of output 116 [2018-02-02 09:48:40,099 WARN L146 SmtUtils]: Spent 429ms on a formula simplification. DAG size of input: 177 DAG size of output 78 [2018-02-02 09:48:40,495 WARN L146 SmtUtils]: Spent 372ms on a formula simplification. DAG size of input: 177 DAG size of output 79 [2018-02-02 09:48:40,919 WARN L146 SmtUtils]: Spent 393ms on a formula simplification. DAG size of input: 180 DAG size of output 82 [2018-02-02 09:48:43,652 WARN L146 SmtUtils]: Spent 2684ms on a formula simplification. DAG size of input: 197 DAG size of output 90 [2018-02-02 09:48:44,326 WARN L146 SmtUtils]: Spent 613ms on a formula simplification. DAG size of input: 200 DAG size of output 93 Received shutdown request... [2018-02-02 09:48:44,741 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 09:48:44,744 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 09:48:44,745 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 09:48:44 BoogieIcfgContainer [2018-02-02 09:48:44,745 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 09:48:44,745 INFO L168 Benchmark]: Toolchain (without parser) took 52561.66 ms. Allocated memory was 401.6 MB in the beginning and 1.2 GB in the end (delta: 767.6 MB). Free memory was 358.3 MB in the beginning and 599.2 MB in the end (delta: -241.0 MB). Peak memory consumption was 526.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:48:44,746 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 401.6 MB. Free memory is still 363.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 09:48:44,747 INFO L168 Benchmark]: CACSL2BoogieTranslator took 169.61 ms. Allocated memory is still 401.6 MB. Free memory was 358.3 MB in the beginning and 347.7 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:48:44,747 INFO L168 Benchmark]: Boogie Preprocessor took 24.10 ms. Allocated memory is still 401.6 MB. Free memory was 347.7 MB in the beginning and 345.1 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:48:44,747 INFO L168 Benchmark]: RCFGBuilder took 201.72 ms. Allocated memory is still 401.6 MB. Free memory was 345.1 MB in the beginning and 322.6 MB in the end (delta: 22.5 MB). Peak memory consumption was 22.5 MB. Max. memory is 5.3 GB. [2018-02-02 09:48:44,747 INFO L168 Benchmark]: TraceAbstraction took 52163.56 ms. Allocated memory was 401.6 MB in the beginning and 1.2 GB in the end (delta: 767.6 MB). Free memory was 322.6 MB in the beginning and 599.2 MB in the end (delta: -276.6 MB). Peak memory consumption was 490.9 MB. Max. memory is 5.3 GB. [2018-02-02 09:48:44,748 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 401.6 MB. Free memory is still 363.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 169.61 ms. Allocated memory is still 401.6 MB. Free memory was 358.3 MB in the beginning and 347.7 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 24.10 ms. Allocated memory is still 401.6 MB. Free memory was 347.7 MB in the beginning and 345.1 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 201.72 ms. Allocated memory is still 401.6 MB. Free memory was 345.1 MB in the beginning and 322.6 MB in the end (delta: 22.5 MB). Peak memory consumption was 22.5 MB. Max. memory is 5.3 GB. * TraceAbstraction took 52163.56 ms. Allocated memory was 401.6 MB in the beginning and 1.2 GB in the end (delta: 767.6 MB). Free memory was 322.6 MB in the beginning and 599.2 MB in the end (delta: -276.6 MB). Peak memory consumption was 490.9 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 570). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 569). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 570). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 569). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 553]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 553). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 543). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 550). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 543). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 550). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 54 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 174. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 58 locations, 15 error locations. TIMEOUT Result, 52.1s OverallTime, 39 OverallIterations, 12 TraceHistogramMax, 24.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1614 SDtfs, 4272 SDslu, 10909 SDs, 0 SdLazy, 12411 SolverSat, 1169 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1021 GetRequests, 49 SyntacticMatches, 16 SemanticMatches, 956 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7482 ImplicationChecksByTransitivity, 33.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=166occurred in iteration=13, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 36/982 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 38 MinimizatonAttempts, 1703 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 20.1s InterpolantComputationTime, 1288 NumberOfCodeBlocks, 1288 NumberOfCodeBlocksAsserted, 38 NumberOfCheckSat, 1250 ConstructedInterpolants, 0 QuantifiedInterpolants, 1196614 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 38 InterpolantComputations, 12 PerfectInterpolantSequences, 36/982 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_09-48-44-754.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_09-48-44-754.csv Completed graceful shutdown