java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_false-valid-free.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 10:16:59,080 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 10:16:59,081 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 10:16:59,095 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 10:16:59,095 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 10:16:59,096 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 10:16:59,097 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 10:16:59,099 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 10:16:59,100 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 10:16:59,101 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 10:16:59,102 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 10:16:59,102 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 10:16:59,103 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 10:16:59,104 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 10:16:59,104 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 10:16:59,106 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 10:16:59,108 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 10:16:59,109 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 10:16:59,110 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 10:16:59,111 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 10:16:59,113 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-02 10:16:59,113 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-02 10:16:59,114 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-02 10:16:59,115 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-02 10:16:59,115 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-02 10:16:59,116 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-02 10:16:59,116 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-02 10:16:59,117 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-02 10:16:59,117 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-02 10:16:59,117 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-02 10:16:59,118 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-02 10:16:59,118 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 10:16:59,128 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 10:16:59,128 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 10:16:59,129 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 10:16:59,129 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 10:16:59,129 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 10:16:59,129 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 10:16:59,129 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 10:16:59,130 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 10:16:59,130 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 10:16:59,130 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 10:16:59,130 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 10:16:59,130 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 10:16:59,130 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 10:16:59,131 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 10:16:59,131 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 10:16:59,131 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 10:16:59,131 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 10:16:59,131 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 10:16:59,131 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 10:16:59,131 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 10:16:59,132 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 10:16:59,132 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 10:16:59,132 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 10:16:59,160 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 10:16:59,171 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 10:16:59,174 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 10:16:59,177 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 10:16:59,178 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 10:16:59,178 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_false-valid-free.i [2018-02-02 10:16:59,355 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 10:16:59,356 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 10:16:59,357 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 10:16:59,357 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 10:16:59,361 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 10:16:59,362 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,364 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@82d65fb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59, skipping insertion in model container [2018-02-02 10:16:59,364 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,374 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 10:16:59,412 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 10:16:59,530 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 10:16:59,564 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 10:16:59,577 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59 WrapperNode [2018-02-02 10:16:59,578 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 10:16:59,578 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 10:16:59,579 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 10:16:59,579 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 10:16:59,588 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,589 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,600 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,601 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,614 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,619 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,622 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... [2018-02-02 10:16:59,626 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 10:16:59,626 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 10:16:59,626 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 10:16:59,627 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 10:16:59,627 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-02-02 10:16:59,667 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-02 10:16:59,668 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_get_clientdata [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_set_clientdata [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure master_xfer [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_transfer [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_m88ts2022_rd_reg [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure alloc_12 [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure free_12 [2018-02-02 10:16:59,669 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-02 10:16:59,670 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 10:16:59,670 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 10:16:59,670 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 10:16:59,670 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-02 10:16:59,670 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-02 10:16:59,670 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 10:16:59,670 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 10:16:59,671 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 10:16:59,671 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-02-02 10:16:59,671 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-02-02 10:16:59,671 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-02 10:16:59,671 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-02 10:16:59,671 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 10:16:59,671 INFO L128 BoogieDeclarations]: Found specification of procedure memcpy [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-02-02 10:16:59,672 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_get_clientdata [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_set_clientdata [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure master_xfer [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_transfer [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-02 10:16:59,673 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_m88ts2022_rd_reg [2018-02-02 10:16:59,674 INFO L128 BoogieDeclarations]: Found specification of procedure alloc_12 [2018-02-02 10:16:59,674 INFO L128 BoogieDeclarations]: Found specification of procedure free_12 [2018-02-02 10:16:59,674 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-02 10:16:59,674 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 10:16:59,674 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 10:16:59,674 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 10:17:00,328 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-02 10:17:00,420 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 10:17:00,420 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 10:17:00 BoogieIcfgContainer [2018-02-02 10:17:00,420 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 10:17:00,421 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 10:17:00,421 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 10:17:00,423 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 10:17:00,423 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 10:16:59" (1/3) ... [2018-02-02 10:17:00,424 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42b581b3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 10:17:00, skipping insertion in model container [2018-02-02 10:17:00,424 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:16:59" (2/3) ... [2018-02-02 10:17:00,425 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@42b581b3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 10:17:00, skipping insertion in model container [2018-02-02 10:17:00,425 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 10:17:00" (3/3) ... [2018-02-02 10:17:00,426 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test12_false-valid-free.i [2018-02-02 10:17:00,431 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 10:17:00,439 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 141 error locations. [2018-02-02 10:17:00,464 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 10:17:00,464 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 10:17:00,464 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 10:17:00,464 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 10:17:00,464 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 10:17:00,464 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 10:17:00,464 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 10:17:00,465 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 10:17:00,465 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 10:17:00,482 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states. [2018-02-02 10:17:00,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-02 10:17:00,489 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:00,490 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-02 10:17:00,490 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:00,493 INFO L82 PathProgramCache]: Analyzing trace with hash 18685926, now seen corresponding path program 1 times [2018-02-02 10:17:00,531 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:00,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:00,622 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:00,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:00,656 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:00,656 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 10:17:00,657 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:00,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:00,658 INFO L182 omatonBuilderFactory]: Interpolants [401#true, 402#false, 403#(= 1 (select |#valid| |~#ldv_global_msg_list.base|))] [2018-02-02 10:17:00,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:00,659 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 10:17:00,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 10:17:00,668 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 10:17:00,669 INFO L87 Difference]: Start difference. First operand 398 states. Second operand 3 states. [2018-02-02 10:17:00,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:00,941 INFO L93 Difference]: Finished difference Result 487 states and 527 transitions. [2018-02-02 10:17:00,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 10:17:00,942 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-02 10:17:00,942 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:00,956 INFO L225 Difference]: With dead ends: 487 [2018-02-02 10:17:00,956 INFO L226 Difference]: Without dead ends: 481 [2018-02-02 10:17:00,958 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 10:17:00,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-02 10:17:01,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 436. [2018-02-02 10:17:01,007 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-02-02 10:17:01,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 491 transitions. [2018-02-02 10:17:01,010 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 491 transitions. Word has length 4 [2018-02-02 10:17:01,010 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:01,010 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 491 transitions. [2018-02-02 10:17:01,010 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 10:17:01,010 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 491 transitions. [2018-02-02 10:17:01,010 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-02 10:17:01,011 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:01,011 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-02 10:17:01,011 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:01,011 INFO L82 PathProgramCache]: Analyzing trace with hash 18685927, now seen corresponding path program 1 times [2018-02-02 10:17:01,013 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:01,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:01,025 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:01,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,068 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:01,069 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 10:17:01,069 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:01,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,069 INFO L182 omatonBuilderFactory]: Interpolants [1328#false, 1329#(and (= |~#ldv_global_msg_list.offset| 0) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 1327#true] [2018-02-02 10:17:01,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,070 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 10:17:01,070 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 10:17:01,070 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 10:17:01,070 INFO L87 Difference]: Start difference. First operand 436 states and 491 transitions. Second operand 3 states. [2018-02-02 10:17:01,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:01,314 INFO L93 Difference]: Finished difference Result 567 states and 652 transitions. [2018-02-02 10:17:01,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 10:17:01,314 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-02 10:17:01,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:01,316 INFO L225 Difference]: With dead ends: 567 [2018-02-02 10:17:01,316 INFO L226 Difference]: Without dead ends: 567 [2018-02-02 10:17:01,317 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 10:17:01,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-02-02 10:17:01,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 497. [2018-02-02 10:17:01,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 497 states. [2018-02-02 10:17:01,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 497 states to 497 states and 602 transitions. [2018-02-02 10:17:01,337 INFO L78 Accepts]: Start accepts. Automaton has 497 states and 602 transitions. Word has length 4 [2018-02-02 10:17:01,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:01,338 INFO L432 AbstractCegarLoop]: Abstraction has 497 states and 602 transitions. [2018-02-02 10:17:01,338 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 10:17:01,338 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 602 transitions. [2018-02-02 10:17:01,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 10:17:01,338 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:01,339 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:01,339 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:01,339 INFO L82 PathProgramCache]: Analyzing trace with hash -2098584656, now seen corresponding path program 1 times [2018-02-02 10:17:01,340 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:01,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:01,361 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:01,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,417 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:01,417 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:01,417 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:01,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,417 INFO L182 omatonBuilderFactory]: Interpolants [2394#true, 2395#false, 2396#(not (= |ldv_malloc_#t~malloc4.base| 0)), 2397#(not (= |ldv_malloc_#res.base| 0)), 2398#(not (= |entry_point_#t~ret59.base| 0)), 2399#(not (= entry_point_~client~0.base 0))] [2018-02-02 10:17:01,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,418 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:01,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:01,418 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:01,418 INFO L87 Difference]: Start difference. First operand 497 states and 602 transitions. Second operand 6 states. [2018-02-02 10:17:01,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:01,508 INFO L93 Difference]: Finished difference Result 543 states and 666 transitions. [2018-02-02 10:17:01,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:01,509 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-02 10:17:01,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:01,512 INFO L225 Difference]: With dead ends: 543 [2018-02-02 10:17:01,512 INFO L226 Difference]: Without dead ends: 543 [2018-02-02 10:17:01,512 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:01,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-02-02 10:17:01,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 496. [2018-02-02 10:17:01,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 496 states. [2018-02-02 10:17:01,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 604 transitions. [2018-02-02 10:17:01,530 INFO L78 Accepts]: Start accepts. Automaton has 496 states and 604 transitions. Word has length 21 [2018-02-02 10:17:01,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:01,531 INFO L432 AbstractCegarLoop]: Abstraction has 496 states and 604 transitions. [2018-02-02 10:17:01,531 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:01,531 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 604 transitions. [2018-02-02 10:17:01,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 10:17:01,532 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:01,532 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:01,532 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:01,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1744465714, now seen corresponding path program 1 times [2018-02-02 10:17:01,534 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:01,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:01,558 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:01,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,640 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:01,641 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 10:17:01,641 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:01,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,642 INFO L182 omatonBuilderFactory]: Interpolants [3441#true, 3442#false, 3443#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 3444#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 3445#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-02 10:17:01,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:01,642 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:01,642 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:01,643 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:01,643 INFO L87 Difference]: Start difference. First operand 496 states and 604 transitions. Second operand 5 states. [2018-02-02 10:17:01,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:01,998 INFO L93 Difference]: Finished difference Result 571 states and 703 transitions. [2018-02-02 10:17:01,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:01,998 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2018-02-02 10:17:01,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:02,000 INFO L225 Difference]: With dead ends: 571 [2018-02-02 10:17:02,000 INFO L226 Difference]: Without dead ends: 571 [2018-02-02 10:17:02,000 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:02,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-02 10:17:02,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 538. [2018-02-02 10:17:02,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-02 10:17:02,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 661 transitions. [2018-02-02 10:17:02,015 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 661 transitions. Word has length 21 [2018-02-02 10:17:02,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:02,015 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 661 transitions. [2018-02-02 10:17:02,015 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:02,015 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 661 transitions. [2018-02-02 10:17:02,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 10:17:02,016 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:02,016 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:02,019 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:02,019 INFO L82 PathProgramCache]: Analyzing trace with hash -1744465713, now seen corresponding path program 1 times [2018-02-02 10:17:02,021 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:02,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:02,036 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:02,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:02,219 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:02,219 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:02,219 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:02,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:02,220 INFO L182 omatonBuilderFactory]: Interpolants [4560#false, 4561#(and (= 0 |~#ldv_global_msg_list.offset|) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 4562#(and (= 8 (select |#length| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 4563#(= |old(#length)| |#length|), 4564#(and (= 0 |ldv_destroy_msgs_#t~mem23.offset|) (= 8 (select |#length| |ldv_destroy_msgs_#t~mem23.base|))), 4565#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 4) 0) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4)) (= (select |#length| ldv_destroy_msgs_~msg~1.base) 8)), 4559#true] [2018-02-02 10:17:02,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:02,221 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:02,221 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:02,221 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:02,221 INFO L87 Difference]: Start difference. First operand 538 states and 661 transitions. Second operand 7 states. [2018-02-02 10:17:03,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:03,657 INFO L93 Difference]: Finished difference Result 668 states and 771 transitions. [2018-02-02 10:17:03,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:17:03,657 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-02-02 10:17:03,658 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:03,662 INFO L225 Difference]: With dead ends: 668 [2018-02-02 10:17:03,662 INFO L226 Difference]: Without dead ends: 668 [2018-02-02 10:17:03,662 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:17:03,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states. [2018-02-02 10:17:03,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 538. [2018-02-02 10:17:03,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-02 10:17:03,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 660 transitions. [2018-02-02 10:17:03,689 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 660 transitions. Word has length 21 [2018-02-02 10:17:03,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:03,689 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 660 transitions. [2018-02-02 10:17:03,689 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:03,689 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 660 transitions. [2018-02-02 10:17:03,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 10:17:03,690 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:03,690 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:03,690 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:03,692 INFO L82 PathProgramCache]: Analyzing trace with hash -1603523080, now seen corresponding path program 1 times [2018-02-02 10:17:03,693 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:03,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:03,715 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:03,784 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:03,784 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:03,784 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:17:03,784 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:03,785 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:03,785 INFO L182 omatonBuilderFactory]: Interpolants [5784#true, 5785#false, 5786#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 5787#(and (= 0 |entry_point_#t~ret59.base|) (= 0 |entry_point_#t~ret59.offset|)), 5788#(and (= 0 entry_point_~client~0.offset) (= entry_point_~client~0.base 0))] [2018-02-02 10:17:03,785 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:03,785 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:03,785 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:03,785 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:03,785 INFO L87 Difference]: Start difference. First operand 538 states and 660 transitions. Second operand 5 states. [2018-02-02 10:17:03,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:03,829 INFO L93 Difference]: Finished difference Result 503 states and 588 transitions. [2018-02-02 10:17:03,829 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 10:17:03,829 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-02-02 10:17:03,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:03,832 INFO L225 Difference]: With dead ends: 503 [2018-02-02 10:17:03,832 INFO L226 Difference]: Without dead ends: 503 [2018-02-02 10:17:03,832 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:03,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-02 10:17:03,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 495. [2018-02-02 10:17:03,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-02-02 10:17:03,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 574 transitions. [2018-02-02 10:17:03,843 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 574 transitions. Word has length 24 [2018-02-02 10:17:03,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:03,843 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 574 transitions. [2018-02-02 10:17:03,843 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:03,843 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 574 transitions. [2018-02-02 10:17:03,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 10:17:03,844 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:03,844 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:03,844 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:03,844 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705302, now seen corresponding path program 1 times [2018-02-02 10:17:03,845 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:03,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:03,856 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:03,906 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:03,906 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:03,906 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:17:03,906 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:03,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:03,907 INFO L182 omatonBuilderFactory]: Interpolants [6787#true, 6788#false, 6789#(= 0 |ldv_malloc_#t~malloc4.offset|), 6790#(= 0 |ldv_malloc_#res.offset|), 6791#(= 0 |entry_point_#t~ret59.offset|), 6792#(= 0 entry_point_~client~0.offset)] [2018-02-02 10:17:03,907 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:03,907 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:03,907 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:03,907 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:03,908 INFO L87 Difference]: Start difference. First operand 495 states and 574 transitions. Second operand 6 states. [2018-02-02 10:17:03,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:03,948 INFO L93 Difference]: Finished difference Result 496 states and 579 transitions. [2018-02-02 10:17:03,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:03,949 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-02-02 10:17:03,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:03,951 INFO L225 Difference]: With dead ends: 496 [2018-02-02 10:17:03,951 INFO L226 Difference]: Without dead ends: 496 [2018-02-02 10:17:03,951 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:03,952 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-02-02 10:17:03,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 494. [2018-02-02 10:17:03,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 494 states. [2018-02-02 10:17:03,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 494 states to 494 states and 572 transitions. [2018-02-02 10:17:03,961 INFO L78 Accepts]: Start accepts. Automaton has 494 states and 572 transitions. Word has length 26 [2018-02-02 10:17:03,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:03,961 INFO L432 AbstractCegarLoop]: Abstraction has 494 states and 572 transitions. [2018-02-02 10:17:03,962 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:03,962 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 572 transitions. [2018-02-02 10:17:03,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 10:17:03,962 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:03,962 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:03,963 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:03,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705303, now seen corresponding path program 1 times [2018-02-02 10:17:03,964 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:03,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:03,974 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:04,020 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,021 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:04,021 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 10:17:04,021 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:04,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,021 INFO L182 omatonBuilderFactory]: Interpolants [7792#(= |#valid| |old(#valid)|), 7786#true, 7787#false, 7788#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 7789#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 7790#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 7791#(= 1 (select |#valid| entry_point_~client~0.base))] [2018-02-02 10:17:04,021 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,021 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:04,022 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:04,022 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:04,022 INFO L87 Difference]: Start difference. First operand 494 states and 572 transitions. Second operand 7 states. [2018-02-02 10:17:04,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:04,787 INFO L93 Difference]: Finished difference Result 597 states and 705 transitions. [2018-02-02 10:17:04,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:04,787 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-02-02 10:17:04,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:04,790 INFO L225 Difference]: With dead ends: 597 [2018-02-02 10:17:04,790 INFO L226 Difference]: Without dead ends: 592 [2018-02-02 10:17:04,790 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:04,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2018-02-02 10:17:04,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 521. [2018-02-02 10:17:04,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-02-02 10:17:04,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 620 transitions. [2018-02-02 10:17:04,803 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 620 transitions. Word has length 26 [2018-02-02 10:17:04,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:04,803 INFO L432 AbstractCegarLoop]: Abstraction has 521 states and 620 transitions. [2018-02-02 10:17:04,803 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:04,803 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 620 transitions. [2018-02-02 10:17:04,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 10:17:04,804 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:04,804 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:04,804 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:04,804 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705304, now seen corresponding path program 1 times [2018-02-02 10:17:04,805 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:04,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:04,814 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:04,847 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:04,847 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:04,847 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 10:17:04,847 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:04,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,847 INFO L182 omatonBuilderFactory]: Interpolants [8913#true, 8914#false, 8915#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 8916#(and (= 0 |entry_point_#t~ret60.base|) (= 0 |entry_point_#t~ret60.offset|)), 8917#(and (= 0 entry_point_~cfg~2.offset) (= 0 entry_point_~cfg~2.base))] [2018-02-02 10:17:04,847 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:04,848 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:04,848 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:04,848 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:04,848 INFO L87 Difference]: Start difference. First operand 521 states and 620 transitions. Second operand 5 states. [2018-02-02 10:17:04,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:04,861 INFO L93 Difference]: Finished difference Result 523 states and 619 transitions. [2018-02-02 10:17:04,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 10:17:04,864 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-02-02 10:17:04,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:04,866 INFO L225 Difference]: With dead ends: 523 [2018-02-02 10:17:04,866 INFO L226 Difference]: Without dead ends: 523 [2018-02-02 10:17:04,866 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:04,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-02-02 10:17:04,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 520. [2018-02-02 10:17:04,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-02-02 10:17:04,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 617 transitions. [2018-02-02 10:17:04,874 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 617 transitions. Word has length 26 [2018-02-02 10:17:04,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:04,874 INFO L432 AbstractCegarLoop]: Abstraction has 520 states and 617 transitions. [2018-02-02 10:17:04,874 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:04,874 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 617 transitions. [2018-02-02 10:17:04,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-02 10:17:04,875 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:04,875 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:04,875 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:04,876 INFO L82 PathProgramCache]: Analyzing trace with hash -1000460798, now seen corresponding path program 1 times [2018-02-02 10:17:04,877 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:04,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:04,886 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:04,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,907 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:04,907 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 10:17:04,907 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:04,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,908 INFO L182 omatonBuilderFactory]: Interpolants [9961#true, 9962#false, 9963#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base)), 9964#(= 1 (select |#valid| |ldv_list_del_#in~entry.base|)), 9965#(= 1 (select |#valid| ldv_list_del_~entry.base))] [2018-02-02 10:17:04,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:04,908 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:04,908 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:04,908 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:04,908 INFO L87 Difference]: Start difference. First operand 520 states and 617 transitions. Second operand 5 states. [2018-02-02 10:17:05,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:05,171 INFO L93 Difference]: Finished difference Result 541 states and 644 transitions. [2018-02-02 10:17:05,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:05,172 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-02-02 10:17:05,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:05,173 INFO L225 Difference]: With dead ends: 541 [2018-02-02 10:17:05,173 INFO L226 Difference]: Without dead ends: 541 [2018-02-02 10:17:05,173 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:05,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-02-02 10:17:05,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 537. [2018-02-02 10:17:05,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-02-02 10:17:05,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 638 transitions. [2018-02-02 10:17:05,180 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 638 transitions. Word has length 27 [2018-02-02 10:17:05,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:05,180 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 638 transitions. [2018-02-02 10:17:05,180 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:05,180 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 638 transitions. [2018-02-02 10:17:05,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-02 10:17:05,180 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:05,180 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:05,181 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:05,181 INFO L82 PathProgramCache]: Analyzing trace with hash -1000460797, now seen corresponding path program 1 times [2018-02-02 10:17:05,181 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:05,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:05,188 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:05,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:05,378 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:05,378 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 10:17:05,378 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:05,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:05,379 INFO L182 omatonBuilderFactory]: Interpolants [11046#true, 11047#false, 11048#(and (= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11049#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11050#(and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= (+ |~#ldv_global_msg_list.offset| 8) (select |#length| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11051#(and (<= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 11052#(and (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|) (<= |~#ldv_global_msg_list.offset| 0) (<= 0 |~#ldv_global_msg_list.offset|)), 11053#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|))] [2018-02-02 10:17:05,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:05,379 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 10:17:05,379 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 10:17:05,380 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:05,380 INFO L87 Difference]: Start difference. First operand 537 states and 638 transitions. Second operand 8 states. [2018-02-02 10:17:05,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:05,702 INFO L93 Difference]: Finished difference Result 500 states and 568 transitions. [2018-02-02 10:17:05,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:17:05,702 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-02-02 10:17:05,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:05,704 INFO L225 Difference]: With dead ends: 500 [2018-02-02 10:17:05,704 INFO L226 Difference]: Without dead ends: 488 [2018-02-02 10:17:05,705 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:17:05,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2018-02-02 10:17:05,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 477. [2018-02-02 10:17:05,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 477 states. [2018-02-02 10:17:05,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 550 transitions. [2018-02-02 10:17:05,713 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 550 transitions. Word has length 27 [2018-02-02 10:17:05,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:05,713 INFO L432 AbstractCegarLoop]: Abstraction has 477 states and 550 transitions. [2018-02-02 10:17:05,713 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 10:17:05,713 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 550 transitions. [2018-02-02 10:17:05,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 10:17:05,714 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:05,714 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:05,714 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:05,715 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219079, now seen corresponding path program 1 times [2018-02-02 10:17:05,716 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:05,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:05,724 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:05,754 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:05,755 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:05,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:05,755 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:05,755 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 10:17:05,756 INFO L182 omatonBuilderFactory]: Interpolants [12039#true, 12040#false, 12041#(not (= |ldv_malloc_#t~malloc4.base| 0)), 12042#(not (= |ldv_malloc_#res.base| 0)), 12043#(not (= |entry_point_#t~ret60.base| 0)), 12044#(not (= entry_point_~cfg~2.base 0))] [2018-02-02 10:17:05,756 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:05,756 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:05,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:05,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:05,756 INFO L87 Difference]: Start difference. First operand 477 states and 550 transitions. Second operand 6 states. [2018-02-02 10:17:05,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:05,787 INFO L93 Difference]: Finished difference Result 478 states and 549 transitions. [2018-02-02 10:17:05,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:05,788 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-02 10:17:05,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:05,789 INFO L225 Difference]: With dead ends: 478 [2018-02-02 10:17:05,789 INFO L226 Difference]: Without dead ends: 478 [2018-02-02 10:17:05,789 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:05,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-02 10:17:05,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 476. [2018-02-02 10:17:05,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 476 states. [2018-02-02 10:17:05,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 476 states to 476 states and 547 transitions. [2018-02-02 10:17:05,797 INFO L78 Accepts]: Start accepts. Automaton has 476 states and 547 transitions. Word has length 28 [2018-02-02 10:17:05,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:05,797 INFO L432 AbstractCegarLoop]: Abstraction has 476 states and 547 transitions. [2018-02-02 10:17:05,797 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:05,797 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 547 transitions. [2018-02-02 10:17:05,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 10:17:05,798 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:05,798 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:05,798 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:05,798 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219079, now seen corresponding path program 1 times [2018-02-02 10:17:05,799 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:05,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:05,807 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:05,871 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:05,872 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:05,872 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 10:17:05,872 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:05,872 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:05,872 INFO L182 omatonBuilderFactory]: Interpolants [13008#(and (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 13009#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 13001#true, 13002#false, 13003#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 13004#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 13005#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 13006#(= 1 (select |#valid| entry_point_~client~0.base)), 13007#(= |#valid| |old(#valid)|)] [2018-02-02 10:17:05,872 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:05,873 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 10:17:05,873 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 10:17:05,873 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:17:05,873 INFO L87 Difference]: Start difference. First operand 476 states and 547 transitions. Second operand 9 states. [2018-02-02 10:17:06,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:06,770 INFO L93 Difference]: Finished difference Result 582 states and 680 transitions. [2018-02-02 10:17:06,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 10:17:06,771 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-02-02 10:17:06,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:06,772 INFO L225 Difference]: With dead ends: 582 [2018-02-02 10:17:06,772 INFO L226 Difference]: Without dead ends: 582 [2018-02-02 10:17:06,773 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:17:06,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2018-02-02 10:17:06,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 461. [2018-02-02 10:17:06,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-02 10:17:06,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-02 10:17:06,778 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 28 [2018-02-02 10:17:06,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:06,778 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-02 10:17:06,778 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 10:17:06,778 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-02 10:17:06,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 10:17:06,779 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:06,779 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:06,779 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:06,779 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219078, now seen corresponding path program 1 times [2018-02-02 10:17:06,780 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:06,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:06,790 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:06,976 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:06,976 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:06,977 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 10:17:06,977 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:06,977 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:06,977 INFO L182 omatonBuilderFactory]: Interpolants [14064#(and (<= 20 (select |#length| |entry_point_#t~ret59.base|)) (= 0 |entry_point_#t~ret59.offset|) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 14065#(and (= (select |#valid| entry_point_~client~0.base) 1) (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 14066#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 14067#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 14068#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 14069#(and (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 14059#true, 14060#false, 14061#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 14062#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 14063#(and (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|)))] [2018-02-02 10:17:06,978 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:06,978 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 10:17:06,978 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 10:17:06,978 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:17:06,978 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 11 states. [2018-02-02 10:17:08,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:08,475 INFO L93 Difference]: Finished difference Result 632 states and 736 transitions. [2018-02-02 10:17:08,475 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 10:17:08,475 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 28 [2018-02-02 10:17:08,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:08,477 INFO L225 Difference]: With dead ends: 632 [2018-02-02 10:17:08,477 INFO L226 Difference]: Without dead ends: 632 [2018-02-02 10:17:08,477 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=217, Unknown=0, NotChecked=0, Total=272 [2018-02-02 10:17:08,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 632 states. [2018-02-02 10:17:08,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 632 to 473. [2018-02-02 10:17:08,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-02 10:17:08,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 544 transitions. [2018-02-02 10:17:08,485 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 544 transitions. Word has length 28 [2018-02-02 10:17:08,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:08,485 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 544 transitions. [2018-02-02 10:17:08,485 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 10:17:08,485 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 544 transitions. [2018-02-02 10:17:08,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 10:17:08,486 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:08,486 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:08,486 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:08,486 INFO L82 PathProgramCache]: Analyzing trace with hash -562803403, now seen corresponding path program 1 times [2018-02-02 10:17:08,487 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:08,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:08,494 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:08,614 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:08,614 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:08,615 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 10:17:08,615 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:08,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:08,615 INFO L182 omatonBuilderFactory]: Interpolants [15187#true, 15188#false, 15189#(= 1 (select |#valid| |~#ldv_global_msg_list.base|)), 15190#(= |#valid| |old(#valid)|), 15191#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 15192#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15193#(and (not (= |entry_point_#t~ret59.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 15194#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:08,616 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:08,616 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 10:17:08,616 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 10:17:08,616 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:08,616 INFO L87 Difference]: Start difference. First operand 473 states and 544 transitions. Second operand 8 states. [2018-02-02 10:17:09,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:09,412 INFO L93 Difference]: Finished difference Result 569 states and 639 transitions. [2018-02-02 10:17:09,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 10:17:09,412 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-02-02 10:17:09,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:09,414 INFO L225 Difference]: With dead ends: 569 [2018-02-02 10:17:09,414 INFO L226 Difference]: Without dead ends: 569 [2018-02-02 10:17:09,414 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:17:09,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states. [2018-02-02 10:17:09,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 473. [2018-02-02 10:17:09,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-02 10:17:09,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 543 transitions. [2018-02-02 10:17:09,420 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 543 transitions. Word has length 29 [2018-02-02 10:17:09,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:09,420 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 543 transitions. [2018-02-02 10:17:09,420 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 10:17:09,420 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 543 transitions. [2018-02-02 10:17:09,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 10:17:09,420 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:09,420 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:09,420 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:09,421 INFO L82 PathProgramCache]: Analyzing trace with hash -562803402, now seen corresponding path program 1 times [2018-02-02 10:17:09,421 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:09,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:09,427 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:09,515 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:09,515 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:09,515 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 10:17:09,515 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:09,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:09,516 INFO L182 omatonBuilderFactory]: Interpolants [16243#true, 16244#false, 16245#(and (= |~#ldv_global_msg_list.offset| 0) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 16246#(and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 16247#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16248#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 16249#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16250#(= |old(#length)| |#length|)] [2018-02-02 10:17:09,516 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:09,516 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 10:17:09,516 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 10:17:09,516 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:09,516 INFO L87 Difference]: Start difference. First operand 473 states and 543 transitions. Second operand 8 states. [2018-02-02 10:17:10,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:10,310 INFO L93 Difference]: Finished difference Result 635 states and 718 transitions. [2018-02-02 10:17:10,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 10:17:10,311 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-02-02 10:17:10,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:10,312 INFO L225 Difference]: With dead ends: 635 [2018-02-02 10:17:10,312 INFO L226 Difference]: Without dead ends: 635 [2018-02-02 10:17:10,312 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:17:10,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states. [2018-02-02 10:17:10,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 472. [2018-02-02 10:17:10,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 10:17:10,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 541 transitions. [2018-02-02 10:17:10,319 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 541 transitions. Word has length 29 [2018-02-02 10:17:10,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:10,319 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 541 transitions. [2018-02-02 10:17:10,319 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 10:17:10,319 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 541 transitions. [2018-02-02 10:17:10,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-02-02 10:17:10,320 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:10,320 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:10,320 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:10,320 INFO L82 PathProgramCache]: Analyzing trace with hash 311817911, now seen corresponding path program 1 times [2018-02-02 10:17:10,321 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:10,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:10,329 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:10,405 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:17:10,406 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:10,406 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 10:17:10,406 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:10,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:10,406 INFO L182 omatonBuilderFactory]: Interpolants [17370#true, 17371#false, 17372#(= 0 |~#ldv_global_msg_list.offset|), 17373#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 17374#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 17375#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4)))] [2018-02-02 10:17:10,406 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:17:10,407 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:10,407 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:10,407 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:10,407 INFO L87 Difference]: Start difference. First operand 472 states and 541 transitions. Second operand 6 states. [2018-02-02 10:17:10,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:10,660 INFO L93 Difference]: Finished difference Result 481 states and 550 transitions. [2018-02-02 10:17:10,660 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:10,660 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-02-02 10:17:10,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:10,662 INFO L225 Difference]: With dead ends: 481 [2018-02-02 10:17:10,662 INFO L226 Difference]: Without dead ends: 481 [2018-02-02 10:17:10,662 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:17:10,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-02 10:17:10,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 472. [2018-02-02 10:17:10,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 10:17:10,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 540 transitions. [2018-02-02 10:17:10,666 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 540 transitions. Word has length 31 [2018-02-02 10:17:10,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:10,666 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 540 transitions. [2018-02-02 10:17:10,666 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:10,666 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 540 transitions. [2018-02-02 10:17:10,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 10:17:10,667 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:10,667 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:10,667 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:10,667 INFO L82 PathProgramCache]: Analyzing trace with hash -156377544, now seen corresponding path program 1 times [2018-02-02 10:17:10,668 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:10,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:10,678 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:10,699 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:10,699 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:10,699 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 10:17:10,699 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:10,699 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:17:10,699 INFO L182 omatonBuilderFactory]: Interpolants [18338#true, 18339#false, 18340#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 18341#(and (= 0 |entry_point_#t~ret62.base|) (= 0 |entry_point_#t~ret62.offset|)), 18342#(and (= 0 entry_point_~fe~2.base) (= 0 entry_point_~fe~2.offset))] [2018-02-02 10:17:10,700 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:10,700 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:10,700 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:10,700 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:10,700 INFO L87 Difference]: Start difference. First operand 472 states and 540 transitions. Second operand 5 states. [2018-02-02 10:17:10,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:10,711 INFO L93 Difference]: Finished difference Result 478 states and 542 transitions. [2018-02-02 10:17:10,711 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 10:17:10,711 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 36 [2018-02-02 10:17:10,711 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:10,712 INFO L225 Difference]: With dead ends: 478 [2018-02-02 10:17:10,712 INFO L226 Difference]: Without dead ends: 478 [2018-02-02 10:17:10,713 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:10,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-02 10:17:10,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 470. [2018-02-02 10:17:10,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-02 10:17:10,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-02 10:17:10,718 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-02 10:17:10,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:10,719 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-02 10:17:10,719 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:10,719 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-02 10:17:10,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 10:17:10,719 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:10,719 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:10,719 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:10,720 INFO L82 PathProgramCache]: Analyzing trace with hash -156377559, now seen corresponding path program 1 times [2018-02-02 10:17:10,720 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:10,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:10,728 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:10,754 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:10,755 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:10,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:17:10,755 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:10,755 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 10:17:10,755 INFO L182 omatonBuilderFactory]: Interpolants [19296#(= 0 entry_point_~cfg~2.offset), 19291#true, 19292#false, 19293#(= 0 |ldv_malloc_#t~malloc4.offset|), 19294#(= 0 |ldv_malloc_#res.offset|), 19295#(= 0 |entry_point_#t~ret60.offset|)] [2018-02-02 10:17:10,756 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:10,756 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:10,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:10,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:10,756 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 6 states. [2018-02-02 10:17:10,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:10,785 INFO L93 Difference]: Finished difference Result 469 states and 532 transitions. [2018-02-02 10:17:10,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:10,786 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-02-02 10:17:10,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:10,787 INFO L225 Difference]: With dead ends: 469 [2018-02-02 10:17:10,787 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 10:17:10,788 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:10,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 10:17:10,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 469. [2018-02-02 10:17:10,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-02 10:17:10,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 532 transitions. [2018-02-02 10:17:10,795 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 532 transitions. Word has length 36 [2018-02-02 10:17:10,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:10,796 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 532 transitions. [2018-02-02 10:17:10,796 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:10,796 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 532 transitions. [2018-02-02 10:17:10,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 10:17:10,796 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:10,797 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:10,797 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:10,797 INFO L82 PathProgramCache]: Analyzing trace with hash -156377558, now seen corresponding path program 1 times [2018-02-02 10:17:10,798 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:10,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:10,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:10,853 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:10,853 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:10,854 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 10:17:10,854 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:10,854 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 10:17:10,854 INFO L182 omatonBuilderFactory]: Interpolants [20240#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 20241#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 20242#(= 1 (select |#valid| entry_point_~cfg~2.base)), 20243#(= |#valid| |old(#valid)|), 20237#true, 20238#false, 20239#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))] [2018-02-02 10:17:10,855 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:10,855 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:10,855 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:10,855 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:10,855 INFO L87 Difference]: Start difference. First operand 469 states and 532 transitions. Second operand 7 states. [2018-02-02 10:17:11,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:11,499 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-02 10:17:11,499 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:11,499 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-02-02 10:17:11,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:11,501 INFO L225 Difference]: With dead ends: 540 [2018-02-02 10:17:11,501 INFO L226 Difference]: Without dead ends: 540 [2018-02-02 10:17:11,501 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:11,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-02 10:17:11,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 470. [2018-02-02 10:17:11,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-02 10:17:11,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-02 10:17:11,508 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-02 10:17:11,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:11,508 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-02 10:17:11,508 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:11,508 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-02 10:17:11,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-02-02 10:17:11,509 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:11,509 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:11,509 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:11,509 INFO L82 PathProgramCache]: Analyzing trace with hash -552736786, now seen corresponding path program 1 times [2018-02-02 10:17:11,510 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:11,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:11,519 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:11,652 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:11,652 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:11,652 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 10:17:11,653 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:11,653 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:11,653 INFO L182 omatonBuilderFactory]: Interpolants [21264#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 21265#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 21266#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 21267#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 21256#true, 21257#false, 21258#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 21259#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 21260#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 21261#(= 1 (select |#valid| entry_point_~client~0.base)), 21262#(= |#valid| |old(#valid)|), 21263#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)))] [2018-02-02 10:17:11,653 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:11,653 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 10:17:11,654 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 10:17:11,654 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:17:11,654 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 12 states. [2018-02-02 10:17:12,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:12,420 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-02 10:17:12,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:17:12,421 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 37 [2018-02-02 10:17:12,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:12,422 INFO L225 Difference]: With dead ends: 540 [2018-02-02 10:17:12,422 INFO L226 Difference]: Without dead ends: 540 [2018-02-02 10:17:12,422 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:17:12,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-02 10:17:12,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 471. [2018-02-02 10:17:12,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-02 10:17:12,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-02 10:17:12,427 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 37 [2018-02-02 10:17:12,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:12,427 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-02 10:17:12,427 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 10:17:12,427 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-02 10:17:12,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 10:17:12,427 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:12,428 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:12,428 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:12,428 INFO L82 PathProgramCache]: Analyzing trace with hash -689007910, now seen corresponding path program 1 times [2018-02-02 10:17:12,429 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:12,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:12,438 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:12,520 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:12,520 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:12,520 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 10:17:12,520 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:12,521 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 10:17:12,521 INFO L182 omatonBuilderFactory]: Interpolants [22288#(= 1 (select |#valid| entry_point_~cfg~2.base)), 22289#(= |#valid| |old(#valid)|), 22290#(and (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 22291#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 22283#true, 22284#false, 22285#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 22286#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 22287#(= 1 (select |#valid| |entry_point_#t~ret60.base|))] [2018-02-02 10:17:12,521 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:12,521 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 10:17:12,521 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 10:17:12,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:17:12,521 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 9 states. [2018-02-02 10:17:13,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:13,351 INFO L93 Difference]: Finished difference Result 577 states and 667 transitions. [2018-02-02 10:17:13,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 10:17:13,351 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-02-02 10:17:13,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:13,353 INFO L225 Difference]: With dead ends: 577 [2018-02-02 10:17:13,353 INFO L226 Difference]: Without dead ends: 577 [2018-02-02 10:17:13,353 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:17:13,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states. [2018-02-02 10:17:13,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 471. [2018-02-02 10:17:13,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-02 10:17:13,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-02 10:17:13,358 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 38 [2018-02-02 10:17:13,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:13,358 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-02 10:17:13,358 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 10:17:13,358 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-02 10:17:13,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 10:17:13,359 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:13,359 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:13,359 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:13,359 INFO L82 PathProgramCache]: Analyzing trace with hash -689007909, now seen corresponding path program 1 times [2018-02-02 10:17:13,360 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:13,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:13,367 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:13,499 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 10:17:13,500 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:13,500 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 10:17:13,500 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:13,500 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:13,500 INFO L182 omatonBuilderFactory]: Interpolants [23344#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 23345#(and (= 0 |ldv_malloc_#t~malloc4.offset|) (or (and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|))) (<= (+ |ldv_malloc_#in~size| 1) 0) (<= 2147483648 |ldv_malloc_#in~size|))), 23346#(and (= 0 |ldv_malloc_#res.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (= (select |#valid| |ldv_malloc_#res.base|) 1)) (<= 2147483648 |ldv_malloc_#in~size|))), 23347#(and (= 0 |entry_point_#t~ret60.offset|) (= (select |#valid| |entry_point_#t~ret60.base|) 1) (<= 4 (select |#length| |entry_point_#t~ret60.base|))), 23348#(and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (= 0 entry_point_~cfg~2.offset)), 23349#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 23350#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 23351#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 23352#(and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= entry_point_~cfg~2.offset 0)), 23342#true, 23343#false] [2018-02-02 10:17:13,500 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 10:17:13,500 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 10:17:13,501 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 10:17:13,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:17:13,501 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 11 states. [2018-02-02 10:17:14,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:14,854 INFO L93 Difference]: Finished difference Result 620 states and 717 transitions. [2018-02-02 10:17:14,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:17:14,855 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-02-02 10:17:14,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:14,856 INFO L225 Difference]: With dead ends: 620 [2018-02-02 10:17:14,857 INFO L226 Difference]: Without dead ends: 620 [2018-02-02 10:17:14,857 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=141, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:17:14,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 620 states. [2018-02-02 10:17:14,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 620 to 470. [2018-02-02 10:17:14,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-02 10:17:14,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-02 10:17:14,866 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 38 [2018-02-02 10:17:14,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:14,867 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-02 10:17:14,867 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 10:17:14,867 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-02 10:17:14,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 10:17:14,868 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:14,868 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:14,868 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:14,868 INFO L82 PathProgramCache]: Analyzing trace with hash 115591052, now seen corresponding path program 1 times [2018-02-02 10:17:14,869 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:14,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:14,879 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:14,925 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:14,925 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:14,925 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:14,925 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:14,926 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:17:14,926 INFO L182 omatonBuilderFactory]: Interpolants [24450#true, 24451#false, 24452#(not (= |ldv_malloc_#t~malloc4.base| 0)), 24453#(not (= |ldv_malloc_#res.base| 0)), 24454#(not (= |entry_point_#t~ret62.base| 0)), 24455#(not (= entry_point_~fe~2.base 0))] [2018-02-02 10:17:14,926 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:14,926 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:14,926 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:14,926 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:14,927 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 6 states. [2018-02-02 10:17:14,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:14,949 INFO L93 Difference]: Finished difference Result 472 states and 535 transitions. [2018-02-02 10:17:14,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:14,949 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-02-02 10:17:14,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:14,951 INFO L225 Difference]: With dead ends: 472 [2018-02-02 10:17:14,951 INFO L226 Difference]: Without dead ends: 472 [2018-02-02 10:17:14,951 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:14,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 472 states. [2018-02-02 10:17:14,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 472 to 469. [2018-02-02 10:17:14,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-02 10:17:14,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 531 transitions. [2018-02-02 10:17:14,957 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 531 transitions. Word has length 39 [2018-02-02 10:17:14,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:14,957 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 531 transitions. [2018-02-02 10:17:14,957 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:14,957 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 531 transitions. [2018-02-02 10:17:14,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-02 10:17:14,958 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:14,958 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:14,958 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:14,958 INFO L82 PathProgramCache]: Analyzing trace with hash 323501758, now seen corresponding path program 1 times [2018-02-02 10:17:14,959 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:14,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:14,969 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:15,191 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:15,191 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:15,192 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 10:17:15,192 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:15,192 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:17:15,192 INFO L182 omatonBuilderFactory]: Interpolants [25408#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~cfg~2.base 0)) (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 25409#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= 1 (select |#valid| entry_point_~client~0.base))) (= 1 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0))), 25399#true, 25400#false, 25401#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 25402#(= |#valid| |old(#valid)|), 25403#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 25404#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 25405#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 25406#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 25407#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)))) (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:15,192 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:15,192 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 10:17:15,192 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 10:17:15,192 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:17:15,193 INFO L87 Difference]: Start difference. First operand 469 states and 531 transitions. Second operand 11 states. [2018-02-02 10:17:16,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:16,189 INFO L93 Difference]: Finished difference Result 566 states and 631 transitions. [2018-02-02 10:17:16,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 10:17:16,190 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 40 [2018-02-02 10:17:16,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:16,191 INFO L225 Difference]: With dead ends: 566 [2018-02-02 10:17:16,191 INFO L226 Difference]: Without dead ends: 566 [2018-02-02 10:17:16,191 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 9 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:17:16,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 566 states. [2018-02-02 10:17:16,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 566 to 472. [2018-02-02 10:17:16,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 10:17:16,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 535 transitions. [2018-02-02 10:17:16,196 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 535 transitions. Word has length 40 [2018-02-02 10:17:16,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:16,196 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 535 transitions. [2018-02-02 10:17:16,196 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 10:17:16,196 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 535 transitions. [2018-02-02 10:17:16,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 10:17:16,197 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:16,197 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:16,197 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:16,197 INFO L82 PathProgramCache]: Analyzing trace with hash 1592821110, now seen corresponding path program 1 times [2018-02-02 10:17:16,198 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:16,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:16,208 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:16,317 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:16,317 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:16,317 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 10:17:16,317 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:16,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:17:16,318 INFO L182 omatonBuilderFactory]: Interpolants [26464#(and (= |#valid| (store |old(#valid)| entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0))), 26458#true, 26459#false, 26460#(= |#valid| |old(#valid)|), 26461#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 26462#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0))), 26463#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (= |#valid| (store |old(#valid)| |entry_point_#t~ret59.base| (select |#valid| |entry_point_#t~ret59.base|))))] [2018-02-02 10:17:16,318 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:16,318 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:16,318 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:16,318 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:16,319 INFO L87 Difference]: Start difference. First operand 472 states and 535 transitions. Second operand 7 states. [2018-02-02 10:17:16,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:16,874 INFO L93 Difference]: Finished difference Result 532 states and 608 transitions. [2018-02-02 10:17:16,874 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 10:17:16,874 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 39 [2018-02-02 10:17:16,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:16,875 INFO L225 Difference]: With dead ends: 532 [2018-02-02 10:17:16,876 INFO L226 Difference]: Without dead ends: 514 [2018-02-02 10:17:16,876 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:17:16,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 514 states. [2018-02-02 10:17:16,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 514 to 455. [2018-02-02 10:17:16,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 455 states. [2018-02-02 10:17:16,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 517 transitions. [2018-02-02 10:17:16,880 INFO L78 Accepts]: Start accepts. Automaton has 455 states and 517 transitions. Word has length 39 [2018-02-02 10:17:16,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:16,880 INFO L432 AbstractCegarLoop]: Abstraction has 455 states and 517 transitions. [2018-02-02 10:17:16,880 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:16,880 INFO L276 IsEmpty]: Start isEmpty. Operand 455 states and 517 transitions. [2018-02-02 10:17:16,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 10:17:16,880 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:16,880 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:16,880 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:16,881 INFO L82 PathProgramCache]: Analyzing trace with hash 1647553023, now seen corresponding path program 1 times [2018-02-02 10:17:16,881 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:16,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:16,888 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:16,979 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:16,980 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:16,980 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 10:17:16,980 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:16,980 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:16,980 INFO L182 omatonBuilderFactory]: Interpolants [27456#true, 27457#false, 27458#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 27459#(not (= |ldv_malloc_#t~malloc4.base| 0)), 27460#(not (= |ldv_malloc_#res.base| 0)), 27461#(and (not (= |entry_point_#t~ret59.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 27462#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 27463#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 27464#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 27465#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-02 10:17:16,981 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:16,981 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 10:17:16,981 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 10:17:16,981 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:17:16,981 INFO L87 Difference]: Start difference. First operand 455 states and 517 transitions. Second operand 10 states. [2018-02-02 10:17:17,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:17,391 INFO L93 Difference]: Finished difference Result 481 states and 547 transitions. [2018-02-02 10:17:17,392 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 10:17:17,392 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-02 10:17:17,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:17,393 INFO L225 Difference]: With dead ends: 481 [2018-02-02 10:17:17,393 INFO L226 Difference]: Without dead ends: 481 [2018-02-02 10:17:17,394 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=215, Unknown=0, NotChecked=0, Total=272 [2018-02-02 10:17:17,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-02 10:17:17,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 464. [2018-02-02 10:17:17,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 10:17:17,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 528 transitions. [2018-02-02 10:17:17,397 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 528 transitions. Word has length 42 [2018-02-02 10:17:17,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:17,397 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 528 transitions. [2018-02-02 10:17:17,397 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 10:17:17,397 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 528 transitions. [2018-02-02 10:17:17,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 10:17:17,397 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:17,398 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:17,398 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:17,398 INFO L82 PathProgramCache]: Analyzing trace with hash 1647553024, now seen corresponding path program 1 times [2018-02-02 10:17:17,399 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:17,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:17,405 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:17,597 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:17,597 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:17,597 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 10:17:17,598 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:17,598 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:17,598 INFO L182 omatonBuilderFactory]: Interpolants [28432#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 28433#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 28434#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 28435#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 28425#true, 28426#false, 28427#(= 0 |~#ldv_global_msg_list.offset|), 28428#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 28429#(not (= |ldv_malloc_#t~malloc4.base| 0)), 28430#(not (= |ldv_malloc_#res.base| 0)), 28431#(and (or (not (= |entry_point_#t~ret59.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|))] [2018-02-02 10:17:17,598 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:17,599 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 10:17:17,599 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 10:17:17,599 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:17:17,599 INFO L87 Difference]: Start difference. First operand 464 states and 528 transitions. Second operand 11 states. [2018-02-02 10:17:18,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:18,355 INFO L93 Difference]: Finished difference Result 482 states and 548 transitions. [2018-02-02 10:17:18,355 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 10:17:18,355 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 42 [2018-02-02 10:17:18,355 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:18,357 INFO L225 Difference]: With dead ends: 482 [2018-02-02 10:17:18,357 INFO L226 Difference]: Without dead ends: 482 [2018-02-02 10:17:18,357 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=113, Invalid=439, Unknown=0, NotChecked=0, Total=552 [2018-02-02 10:17:18,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 482 states. [2018-02-02 10:17:18,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 482 to 464. [2018-02-02 10:17:18,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 10:17:18,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-02 10:17:18,363 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 42 [2018-02-02 10:17:18,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:18,363 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-02 10:17:18,363 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 10:17:18,363 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-02 10:17:18,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 10:17:18,364 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:18,364 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:18,364 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:18,364 INFO L82 PathProgramCache]: Analyzing trace with hash -824107646, now seen corresponding path program 1 times [2018-02-02 10:17:18,365 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:18,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:18,374 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:18,411 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 10:17:18,412 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:18,412 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:17:18,412 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:18,412 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 10:17:18,413 INFO L182 omatonBuilderFactory]: Interpolants [29409#true, 29410#false, 29411#(= 0 |ldv_malloc_#t~malloc4.offset|), 29412#(= 0 |ldv_malloc_#res.offset|), 29413#(= 0 |entry_point_#t~ret62.offset|), 29414#(= 0 entry_point_~fe~2.offset)] [2018-02-02 10:17:18,413 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 10:17:18,413 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:18,413 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:18,413 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:18,414 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 6 states. [2018-02-02 10:17:18,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:18,434 INFO L93 Difference]: Finished difference Result 463 states and 526 transitions. [2018-02-02 10:17:18,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:18,435 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-02-02 10:17:18,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:18,436 INFO L225 Difference]: With dead ends: 463 [2018-02-02 10:17:18,437 INFO L226 Difference]: Without dead ends: 463 [2018-02-02 10:17:18,437 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:18,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2018-02-02 10:17:18,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 463. [2018-02-02 10:17:18,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 10:17:18,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 526 transitions. [2018-02-02 10:17:18,443 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 526 transitions. Word has length 46 [2018-02-02 10:17:18,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:18,444 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 526 transitions. [2018-02-02 10:17:18,444 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:18,444 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 526 transitions. [2018-02-02 10:17:18,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 10:17:18,446 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:18,446 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:18,446 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:18,446 INFO L82 PathProgramCache]: Analyzing trace with hash -824107645, now seen corresponding path program 1 times [2018-02-02 10:17:18,447 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:18,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:18,456 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:18,508 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:18,509 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:18,509 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 10:17:18,509 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:18,510 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:17:18,510 INFO L182 omatonBuilderFactory]: Interpolants [30343#true, 30344#false, 30345#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 30346#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 30347#(= 1 (select |#valid| |entry_point_#t~ret62.base|)), 30348#(= 1 (select |#valid| entry_point_~fe~2.base)), 30349#(= |#valid| |old(#valid)|)] [2018-02-02 10:17:18,510 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:18,510 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:18,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:18,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:18,511 INFO L87 Difference]: Start difference. First operand 463 states and 526 transitions. Second operand 7 states. [2018-02-02 10:17:19,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:19,203 INFO L93 Difference]: Finished difference Result 531 states and 610 transitions. [2018-02-02 10:17:19,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:19,204 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 46 [2018-02-02 10:17:19,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:19,205 INFO L225 Difference]: With dead ends: 531 [2018-02-02 10:17:19,205 INFO L226 Difference]: Without dead ends: 531 [2018-02-02 10:17:19,206 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:19,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states. [2018-02-02 10:17:19,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 464. [2018-02-02 10:17:19,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 10:17:19,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-02 10:17:19,212 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 46 [2018-02-02 10:17:19,213 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:19,213 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-02 10:17:19,213 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:19,213 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-02 10:17:19,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 10:17:19,214 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:19,214 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:19,214 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:19,214 INFO L82 PathProgramCache]: Analyzing trace with hash 222466993, now seen corresponding path program 1 times [2018-02-02 10:17:19,215 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:19,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:19,223 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:19,335 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 10:17:19,335 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:19,335 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 10:17:19,335 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:19,336 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 10:17:19,336 INFO L182 omatonBuilderFactory]: Interpolants [31347#true, 31348#false, 31349#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 31350#(= (select |#valid| |ldv_malloc_#res.base|) 1), 31351#(= (select |#valid| |entry_point_#t~ret60.base|) 1), 31352#(= (select |#valid| entry_point_~cfg~2.base) 1), 31353#(= |#valid| |old(#valid)|), 31354#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 31355#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 31356#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 31357#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 31358#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)))] [2018-02-02 10:17:19,336 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 10:17:19,336 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 10:17:19,337 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 10:17:19,337 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:17:19,337 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 12 states. [2018-02-02 10:17:20,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:20,154 INFO L93 Difference]: Finished difference Result 534 states and 613 transitions. [2018-02-02 10:17:20,155 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:17:20,155 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 47 [2018-02-02 10:17:20,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:20,156 INFO L225 Difference]: With dead ends: 534 [2018-02-02 10:17:20,156 INFO L226 Difference]: Without dead ends: 534 [2018-02-02 10:17:20,156 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:17:20,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2018-02-02 10:17:20,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 465. [2018-02-02 10:17:20,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 465 states. [2018-02-02 10:17:20,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 528 transitions. [2018-02-02 10:17:20,161 INFO L78 Accepts]: Start accepts. Automaton has 465 states and 528 transitions. Word has length 47 [2018-02-02 10:17:20,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:20,161 INFO L432 AbstractCegarLoop]: Abstraction has 465 states and 528 transitions. [2018-02-02 10:17:20,161 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 10:17:20,161 INFO L276 IsEmpty]: Start isEmpty. Operand 465 states and 528 transitions. [2018-02-02 10:17:20,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 10:17:20,161 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:20,161 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:20,162 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:20,162 INFO L82 PathProgramCache]: Analyzing trace with hash 1340530292, now seen corresponding path program 1 times [2018-02-02 10:17:20,162 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:20,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:20,169 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:20,403 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:20,404 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:20,404 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 10:17:20,404 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:20,404 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:20,404 INFO L182 omatonBuilderFactory]: Interpolants [32368#(and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 32369#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 32370#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 32371#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 32372#(and (or (= |~#ldv_global_msg_list.offset| 0) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4))) (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 32373#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 32362#true, 32363#false, 32364#(= 0 |~#ldv_global_msg_list.offset|), 32365#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 32366#(not (= |ldv_malloc_#t~malloc4.base| 0)), 32367#(not (= |ldv_malloc_#res.base| 0))] [2018-02-02 10:17:20,404 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:20,405 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 10:17:20,405 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 10:17:20,405 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:17:20,405 INFO L87 Difference]: Start difference. First operand 465 states and 528 transitions. Second operand 12 states. [2018-02-02 10:17:20,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:20,957 INFO L93 Difference]: Finished difference Result 469 states and 529 transitions. [2018-02-02 10:17:20,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 10:17:20,957 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 48 [2018-02-02 10:17:20,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:20,958 INFO L225 Difference]: With dead ends: 469 [2018-02-02 10:17:20,958 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 10:17:20,958 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=104, Invalid=402, Unknown=0, NotChecked=0, Total=506 [2018-02-02 10:17:20,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 10:17:20,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 463. [2018-02-02 10:17:20,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 10:17:20,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 524 transitions. [2018-02-02 10:17:20,962 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 524 transitions. Word has length 48 [2018-02-02 10:17:20,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:20,962 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 524 transitions. [2018-02-02 10:17:20,962 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 10:17:20,962 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 524 transitions. [2018-02-02 10:17:20,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 10:17:20,962 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:20,962 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:20,962 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:20,963 INFO L82 PathProgramCache]: Analyzing trace with hash 1800754789, now seen corresponding path program 1 times [2018-02-02 10:17:20,963 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:20,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:20,968 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:20,994 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 10:17:20,995 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:20,995 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:20,995 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:20,995 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:20,995 INFO L182 omatonBuilderFactory]: Interpolants [33328#true, 33329#false, 33330#(not (= |ldv_malloc_#t~malloc4.base| 0)), 33331#(not (= |ldv_malloc_#res.base| 0)), 33332#(not (= |entry_point_#t~ret64.base| 0)), 33333#(not (= entry_point_~addr~0.base 0))] [2018-02-02 10:17:20,996 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 10:17:20,996 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:20,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:20,996 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:20,996 INFO L87 Difference]: Start difference. First operand 463 states and 524 transitions. Second operand 6 states. [2018-02-02 10:17:21,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:21,023 INFO L93 Difference]: Finished difference Result 484 states and 549 transitions. [2018-02-02 10:17:21,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:21,023 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-02-02 10:17:21,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:21,025 INFO L225 Difference]: With dead ends: 484 [2018-02-02 10:17:21,025 INFO L226 Difference]: Without dead ends: 484 [2018-02-02 10:17:21,025 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:21,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states. [2018-02-02 10:17:21,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 463. [2018-02-02 10:17:21,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 10:17:21,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 523 transitions. [2018-02-02 10:17:21,031 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 523 transitions. Word has length 48 [2018-02-02 10:17:21,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:21,031 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 523 transitions. [2018-02-02 10:17:21,032 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:21,032 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 523 transitions. [2018-02-02 10:17:21,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 10:17:21,032 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:21,032 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:21,032 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:21,032 INFO L82 PathProgramCache]: Analyzing trace with hash 1800754818, now seen corresponding path program 1 times [2018-02-02 10:17:21,033 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:21,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:21,045 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:21,334 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:21,334 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:21,334 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 10:17:21,334 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:21,335 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:21,335 INFO L182 omatonBuilderFactory]: Interpolants [34283#true, 34284#false, 34285#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (and (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0)) (<= |ldv_malloc_#in~size| ldv_malloc_~size))) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (div ldv_malloc_~size 4294967296) 0))), 34286#(or (and (or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (= 0 |ldv_malloc_#t~malloc4.offset|) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|))) (<= 2147483648 |ldv_malloc_#in~size|)) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1)) (<= 4294967296 |ldv_malloc_#in~size|)), 34287#(or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (= 0 |ldv_malloc_#res.offset|) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (= (select |#valid| |ldv_malloc_#res.base|) 1)) (<= 2147483648 |ldv_malloc_#in~size|)), 34288#(and (<= 20 (select |#length| |entry_point_#t~ret59.base|)) (= 0 |entry_point_#t~ret59.offset|) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 34289#(and (= (select |#valid| entry_point_~client~0.base) 1) (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 34290#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 34291#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 34292#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 34293#(and (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 34294#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 34295#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 10:17:21,335 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:21,335 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 10:17:21,336 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 10:17:21,336 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:17:21,336 INFO L87 Difference]: Start difference. First operand 463 states and 523 transitions. Second operand 13 states. [2018-02-02 10:17:22,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:22,805 INFO L93 Difference]: Finished difference Result 596 states and 688 transitions. [2018-02-02 10:17:22,805 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 10:17:22,805 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 48 [2018-02-02 10:17:22,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:22,807 INFO L225 Difference]: With dead ends: 596 [2018-02-02 10:17:22,807 INFO L226 Difference]: Without dead ends: 596 [2018-02-02 10:17:22,807 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2018-02-02 10:17:22,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 596 states. [2018-02-02 10:17:22,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 596 to 456. [2018-02-02 10:17:22,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 456 states. [2018-02-02 10:17:22,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 456 states to 456 states and 513 transitions. [2018-02-02 10:17:22,811 INFO L78 Accepts]: Start accepts. Automaton has 456 states and 513 transitions. Word has length 48 [2018-02-02 10:17:22,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:22,811 INFO L432 AbstractCegarLoop]: Abstraction has 456 states and 513 transitions. [2018-02-02 10:17:22,811 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 10:17:22,811 INFO L276 IsEmpty]: Start isEmpty. Operand 456 states and 513 transitions. [2018-02-02 10:17:22,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 10:17:22,811 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:22,812 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:22,812 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:22,812 INFO L82 PathProgramCache]: Analyzing trace with hash -1693457593, now seen corresponding path program 1 times [2018-02-02 10:17:22,812 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:22,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:22,819 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:23,102 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-02 10:17:23,102 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:23,102 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 10:17:23,103 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:23,103 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 10:17:23,103 INFO L182 omatonBuilderFactory]: Interpolants [35360#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 35361#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 35362#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 35363#(= 1 (select |#valid| entry_point_~client~0.base)), 35364#(= |#valid| |old(#valid)|), 35365#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 35366#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 35367#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 35368#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 35369#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35370#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 35371#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 35372#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35373#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35358#true, 35359#false] [2018-02-02 10:17:23,104 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-02 10:17:23,104 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 10:17:23,104 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 10:17:23,104 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:17:23,104 INFO L87 Difference]: Start difference. First operand 456 states and 513 transitions. Second operand 16 states. [2018-02-02 10:17:23,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:23,986 INFO L93 Difference]: Finished difference Result 517 states and 587 transitions. [2018-02-02 10:17:23,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 10:17:23,986 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 48 [2018-02-02 10:17:23,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:23,987 INFO L225 Difference]: With dead ends: 517 [2018-02-02 10:17:23,987 INFO L226 Difference]: Without dead ends: 517 [2018-02-02 10:17:23,988 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:17:23,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-02-02 10:17:23,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 457. [2018-02-02 10:17:23,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 457 states. [2018-02-02 10:17:23,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 514 transitions. [2018-02-02 10:17:23,992 INFO L78 Accepts]: Start accepts. Automaton has 457 states and 514 transitions. Word has length 48 [2018-02-02 10:17:23,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:23,992 INFO L432 AbstractCegarLoop]: Abstraction has 457 states and 514 transitions. [2018-02-02 10:17:23,992 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 10:17:23,992 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 514 transitions. [2018-02-02 10:17:23,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-02 10:17:23,992 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:23,993 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:23,993 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:23,993 INFO L82 PathProgramCache]: Analyzing trace with hash -1108813627, now seen corresponding path program 1 times [2018-02-02 10:17:23,993 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:24,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:24,004 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:24,303 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:24,303 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:24,303 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 10:17:24,303 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:24,304 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 10:17:24,304 INFO L182 omatonBuilderFactory]: Interpolants [36354#true, 36355#false, 36356#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 36357#(= |#valid| |old(#valid)|), 36358#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 36359#(and (or (= (@diff |old(#valid)| |#valid|) |ldv_malloc_#res.base|) (= |#valid| |old(#valid)|)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 36360#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 36361#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 36362#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 36363#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 36364#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret60.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 36365#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 36366#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 36367#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:24,304 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:24,304 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 10:17:24,304 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 10:17:24,304 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:17:24,304 INFO L87 Difference]: Start difference. First operand 457 states and 514 transitions. Second operand 14 states. [2018-02-02 10:17:25,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:25,066 INFO L93 Difference]: Finished difference Result 551 states and 611 transitions. [2018-02-02 10:17:25,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-02 10:17:25,067 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 51 [2018-02-02 10:17:25,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:25,068 INFO L225 Difference]: With dead ends: 551 [2018-02-02 10:17:25,068 INFO L226 Difference]: Without dead ends: 551 [2018-02-02 10:17:25,068 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 9 SyntacticMatches, 8 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=56, Invalid=216, Unknown=0, NotChecked=0, Total=272 [2018-02-02 10:17:25,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-02-02 10:17:25,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 460. [2018-02-02 10:17:25,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-02 10:17:25,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 518 transitions. [2018-02-02 10:17:25,072 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 518 transitions. Word has length 51 [2018-02-02 10:17:25,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:25,072 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 518 transitions. [2018-02-02 10:17:25,072 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 10:17:25,072 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 518 transitions. [2018-02-02 10:17:25,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 10:17:25,073 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:25,073 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:25,073 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:25,073 INFO L82 PathProgramCache]: Analyzing trace with hash -491855937, now seen corresponding path program 1 times [2018-02-02 10:17:25,074 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:25,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:25,081 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:25,344 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:25,344 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:25,344 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 10:17:25,344 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:25,344 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:17:25,344 INFO L182 omatonBuilderFactory]: Interpolants [37392#(and (not (= |entry_point_#t~ret60.base| 0)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))))) (not (= entry_point_~client~0.base 0))), 37393#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base 0))), 37394#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 37385#true, 37386#false, 37387#(= |#valid| |old(#valid)|), 37388#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 37389#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0))), 37390#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 37391#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 10:17:25,345 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:25,345 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 10:17:25,345 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 10:17:25,345 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:17:25,345 INFO L87 Difference]: Start difference. First operand 460 states and 518 transitions. Second operand 10 states. [2018-02-02 10:17:26,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:26,328 INFO L93 Difference]: Finished difference Result 520 states and 591 transitions. [2018-02-02 10:17:26,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 10:17:26,328 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 50 [2018-02-02 10:17:26,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:26,329 INFO L225 Difference]: With dead ends: 520 [2018-02-02 10:17:26,330 INFO L226 Difference]: Without dead ends: 503 [2018-02-02 10:17:26,330 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 10 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:17:26,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-02 10:17:26,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 446. [2018-02-02 10:17:26,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-02-02 10:17:26,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 503 transitions. [2018-02-02 10:17:26,335 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 503 transitions. Word has length 50 [2018-02-02 10:17:26,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:26,335 INFO L432 AbstractCegarLoop]: Abstraction has 446 states and 503 transitions. [2018-02-02 10:17:26,335 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 10:17:26,335 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 503 transitions. [2018-02-02 10:17:26,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 10:17:26,336 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:26,336 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:26,336 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:26,336 INFO L82 PathProgramCache]: Analyzing trace with hash -417997242, now seen corresponding path program 1 times [2018-02-02 10:17:26,337 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:26,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:26,344 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:26,532 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:17:26,532 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:26,532 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 10:17:26,532 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:26,533 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 10:17:26,533 INFO L182 omatonBuilderFactory]: Interpolants [38368#false, 38369#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 38370#(not (= |ldv_malloc_#t~malloc4.base| 0)), 38371#(not (= |ldv_malloc_#res.base| 0)), 38372#(and (not (= |entry_point_#t~ret59.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 38373#(and (not (= entry_point_~client~0.base 0)) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 38374#(and (or (and (not (= |entry_point_#t~ret60.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 38375#(and (or (and (or (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 38376#(and (or (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (not (= entry_point_~client~0.base 0))), 38377#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 38378#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 38379#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base)), 38367#true] [2018-02-02 10:17:26,533 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:17:26,533 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 10:17:26,534 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 10:17:26,534 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:17:26,534 INFO L87 Difference]: Start difference. First operand 446 states and 503 transitions. Second operand 13 states. [2018-02-02 10:17:27,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:27,154 INFO L93 Difference]: Finished difference Result 485 states and 548 transitions. [2018-02-02 10:17:27,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 10:17:27,154 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-02-02 10:17:27,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:27,155 INFO L225 Difference]: With dead ends: 485 [2018-02-02 10:17:27,155 INFO L226 Difference]: Without dead ends: 485 [2018-02-02 10:17:27,156 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 4 SyntacticMatches, 7 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=455, Unknown=0, NotChecked=0, Total=552 [2018-02-02 10:17:27,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 485 states. [2018-02-02 10:17:27,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 485 to 462. [2018-02-02 10:17:27,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-02 10:17:27,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 529 transitions. [2018-02-02 10:17:27,159 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 529 transitions. Word has length 53 [2018-02-02 10:17:27,159 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:27,159 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 529 transitions. [2018-02-02 10:17:27,159 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 10:17:27,159 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 529 transitions. [2018-02-02 10:17:27,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 10:17:27,160 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:27,160 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:27,160 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:27,160 INFO L82 PathProgramCache]: Analyzing trace with hash -417997241, now seen corresponding path program 1 times [2018-02-02 10:17:27,160 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:27,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:27,166 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:27,423 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:17:27,423 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:27,423 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 10:17:27,423 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:27,424 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 10:17:27,424 INFO L182 omatonBuilderFactory]: Interpolants [39360#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 39361#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 39362#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 39349#true, 39350#false, 39351#(= 0 |~#ldv_global_msg_list.offset|), 39352#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 39353#(not (= |ldv_malloc_#t~malloc4.base| 0)), 39354#(not (= |ldv_malloc_#res.base| 0)), 39355#(and (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 39356#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39357#(and (or (and (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39358#(and (or (and (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (or (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base) (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39359#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:27,424 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:17:27,424 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 10:17:27,424 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 10:17:27,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:17:27,424 INFO L87 Difference]: Start difference. First operand 462 states and 529 transitions. Second operand 14 states. [2018-02-02 10:17:28,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:28,357 INFO L93 Difference]: Finished difference Result 486 states and 549 transitions. [2018-02-02 10:17:28,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 10:17:28,357 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-02-02 10:17:28,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:28,358 INFO L225 Difference]: With dead ends: 486 [2018-02-02 10:17:28,358 INFO L226 Difference]: Without dead ends: 486 [2018-02-02 10:17:28,358 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=163, Invalid=767, Unknown=0, NotChecked=0, Total=930 [2018-02-02 10:17:28,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2018-02-02 10:17:28,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 462. [2018-02-02 10:17:28,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-02 10:17:28,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 528 transitions. [2018-02-02 10:17:28,364 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 528 transitions. Word has length 53 [2018-02-02 10:17:28,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:28,364 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 528 transitions. [2018-02-02 10:17:28,364 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 10:17:28,364 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 528 transitions. [2018-02-02 10:17:28,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-02 10:17:28,365 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:28,365 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:28,365 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:28,365 INFO L82 PathProgramCache]: Analyzing trace with hash -2129232769, now seen corresponding path program 1 times [2018-02-02 10:17:28,366 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:28,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:28,373 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:28,417 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-02 10:17:28,417 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:28,418 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:17:28,418 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:28,418 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:28,418 INFO L182 omatonBuilderFactory]: Interpolants [40346#true, 40347#false, 40348#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 40349#(and (= 0 |entry_point_#t~ret64.offset|) (= 0 |entry_point_#t~ret64.base|)), 40350#(and (= entry_point_~addr~0.offset 0) (= entry_point_~addr~0.base 0))] [2018-02-02 10:17:28,418 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-02 10:17:28,418 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:28,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:28,418 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:28,418 INFO L87 Difference]: Start difference. First operand 462 states and 528 transitions. Second operand 5 states. [2018-02-02 10:17:28,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:28,440 INFO L93 Difference]: Finished difference Result 464 states and 529 transitions. [2018-02-02 10:17:28,440 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 10:17:28,441 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2018-02-02 10:17:28,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:28,442 INFO L225 Difference]: With dead ends: 464 [2018-02-02 10:17:28,442 INFO L226 Difference]: Without dead ends: 464 [2018-02-02 10:17:28,443 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:28,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2018-02-02 10:17:28,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 462. [2018-02-02 10:17:28,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-02 10:17:28,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 527 transitions. [2018-02-02 10:17:28,450 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 527 transitions. Word has length 54 [2018-02-02 10:17:28,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:28,450 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 527 transitions. [2018-02-02 10:17:28,451 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:28,451 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 527 transitions. [2018-02-02 10:17:28,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 10:17:28,451 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:28,451 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:28,451 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:28,452 INFO L82 PathProgramCache]: Analyzing trace with hash 1178383201, now seen corresponding path program 2 times [2018-02-02 10:17:28,452 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:28,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:28,464 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:28,510 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-02 10:17:28,510 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:28,511 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:17:28,511 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:28,511 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:17:28,511 INFO L182 omatonBuilderFactory]: Interpolants [41280#(= 0 |ldv_malloc_#res.offset|), 41281#(= 0 |entry_point_#t~ret64.offset|), 41282#(= entry_point_~addr~0.offset 0), 41277#true, 41278#false, 41279#(= 0 |ldv_malloc_#t~malloc4.offset|)] [2018-02-02 10:17:28,511 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-02 10:17:28,512 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:28,512 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:28,512 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:28,512 INFO L87 Difference]: Start difference. First operand 462 states and 527 transitions. Second operand 6 states. [2018-02-02 10:17:28,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:28,530 INFO L93 Difference]: Finished difference Result 461 states and 525 transitions. [2018-02-02 10:17:28,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:28,531 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2018-02-02 10:17:28,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:28,532 INFO L225 Difference]: With dead ends: 461 [2018-02-02 10:17:28,533 INFO L226 Difference]: Without dead ends: 461 [2018-02-02 10:17:28,533 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:28,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states. [2018-02-02 10:17:28,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 461. [2018-02-02 10:17:28,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-02 10:17:28,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 525 transitions. [2018-02-02 10:17:28,539 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 525 transitions. Word has length 56 [2018-02-02 10:17:28,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:28,539 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 525 transitions. [2018-02-02 10:17:28,539 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:28,539 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 525 transitions. [2018-02-02 10:17:28,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 10:17:28,540 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:28,540 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:28,540 INFO L371 AbstractCegarLoop]: === Iteration 42 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:28,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1178383202, now seen corresponding path program 1 times [2018-02-02 10:17:28,541 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:28,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:28,549 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:28,589 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 10:17:28,590 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:28,590 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 10:17:28,590 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:28,590 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 10:17:28,591 INFO L182 omatonBuilderFactory]: Interpolants [42208#false, 42209#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 42210#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 42211#(= 1 (select |#valid| |entry_point_#t~ret64.base|)), 42212#(= 1 (select |#valid| entry_point_~addr~0.base)), 42213#(= |#valid| |old(#valid)|), 42207#true] [2018-02-02 10:17:28,591 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 10:17:28,591 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:28,591 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:28,591 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:28,591 INFO L87 Difference]: Start difference. First operand 461 states and 525 transitions. Second operand 7 states. [2018-02-02 10:17:29,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:29,119 INFO L93 Difference]: Finished difference Result 526 states and 607 transitions. [2018-02-02 10:17:29,119 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:29,119 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 56 [2018-02-02 10:17:29,119 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:29,120 INFO L225 Difference]: With dead ends: 526 [2018-02-02 10:17:29,120 INFO L226 Difference]: Without dead ends: 526 [2018-02-02 10:17:29,121 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:17:29,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states. [2018-02-02 10:17:29,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 464. [2018-02-02 10:17:29,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 10:17:29,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 529 transitions. [2018-02-02 10:17:29,124 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 529 transitions. Word has length 56 [2018-02-02 10:17:29,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:29,125 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 529 transitions. [2018-02-02 10:17:29,125 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:29,125 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 529 transitions. [2018-02-02 10:17:29,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-02 10:17:29,125 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:29,125 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:29,125 INFO L371 AbstractCegarLoop]: === Iteration 43 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:29,125 INFO L82 PathProgramCache]: Analyzing trace with hash -2124826194, now seen corresponding path program 1 times [2018-02-02 10:17:29,126 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:29,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:29,132 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:29,243 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 31 proven. 7 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:17:29,244 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:29,244 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 10:17:29,244 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:29,244 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 10:17:29,244 INFO L182 omatonBuilderFactory]: Interpolants [43216#(and (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 43206#true, 43207#false, 43208#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 43209#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 43210#(= 1 (select |#valid| |entry_point_#t~ret62.base|)), 43211#(= 1 (select |#valid| entry_point_~fe~2.base)), 43212#(= |#valid| |old(#valid)|), 43213#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 43214#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 43215#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= |entry_point_#t~ret64.base| entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~fe~2.base)))] [2018-02-02 10:17:29,244 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 31 proven. 7 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:17:29,245 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 10:17:29,245 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 10:17:29,245 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:17:29,245 INFO L87 Difference]: Start difference. First operand 464 states and 529 transitions. Second operand 11 states. [2018-02-02 10:17:30,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:30,176 INFO L93 Difference]: Finished difference Result 522 states and 600 transitions. [2018-02-02 10:17:30,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 10:17:30,176 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 57 [2018-02-02 10:17:30,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:30,178 INFO L225 Difference]: With dead ends: 522 [2018-02-02 10:17:30,178 INFO L226 Difference]: Without dead ends: 522 [2018-02-02 10:17:30,178 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:17:30,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-02-02 10:17:30,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 464. [2018-02-02 10:17:30,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 10:17:30,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 528 transitions. [2018-02-02 10:17:30,182 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 528 transitions. Word has length 57 [2018-02-02 10:17:30,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:30,183 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 528 transitions. [2018-02-02 10:17:30,183 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 10:17:30,183 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 528 transitions. [2018-02-02 10:17:30,183 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-02 10:17:30,183 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:30,183 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:30,183 INFO L371 AbstractCegarLoop]: === Iteration 44 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:30,183 INFO L82 PathProgramCache]: Analyzing trace with hash -2124824882, now seen corresponding path program 1 times [2018-02-02 10:17:30,184 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:30,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:30,189 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:30,221 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-02 10:17:30,221 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:30,221 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 10:17:30,221 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:30,221 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-02 10:17:30,221 INFO L182 omatonBuilderFactory]: Interpolants [44208#false, 44209#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 44210#(and (= 0 |entry_point_#t~ret66.base|) (= 0 |entry_point_#t~ret66.offset|)), 44211#(and (= entry_point_~adapter~0.base 0) (= 0 entry_point_~adapter~0.offset)), 44207#true] [2018-02-02 10:17:30,221 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-02 10:17:30,222 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:30,222 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:30,222 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:30,222 INFO L87 Difference]: Start difference. First operand 464 states and 528 transitions. Second operand 5 states. [2018-02-02 10:17:30,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:30,257 INFO L93 Difference]: Finished difference Result 469 states and 529 transitions. [2018-02-02 10:17:30,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 10:17:30,257 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-02-02 10:17:30,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:30,259 INFO L225 Difference]: With dead ends: 469 [2018-02-02 10:17:30,259 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 10:17:30,259 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:30,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 10:17:30,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 464. [2018-02-02 10:17:30,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 10:17:30,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-02 10:17:30,265 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 57 [2018-02-02 10:17:30,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:30,265 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-02 10:17:30,265 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:30,265 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-02 10:17:30,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-02 10:17:30,266 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:30,266 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:30,266 INFO L371 AbstractCegarLoop]: === Iteration 45 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:30,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1982392068, now seen corresponding path program 1 times [2018-02-02 10:17:30,267 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:30,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:30,273 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:30,297 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 10:17:30,297 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:30,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:30,297 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:30,298 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:30,298 INFO L182 omatonBuilderFactory]: Interpolants [45145#true, 45146#false, 45147#(not (= |ldv_malloc_#t~malloc4.base| 0)), 45148#(not (= |ldv_malloc_#res.base| 0)), 45149#(not (= |entry_point_#t~ret66.base| 0)), 45150#(not (= entry_point_~adapter~0.base 0))] [2018-02-02 10:17:30,298 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 10:17:30,298 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:30,298 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:30,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:30,299 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 6 states. [2018-02-02 10:17:30,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:30,321 INFO L93 Difference]: Finished difference Result 467 states and 526 transitions. [2018-02-02 10:17:30,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:30,322 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2018-02-02 10:17:30,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:30,323 INFO L225 Difference]: With dead ends: 467 [2018-02-02 10:17:30,323 INFO L226 Difference]: Without dead ends: 467 [2018-02-02 10:17:30,323 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:30,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 467 states. [2018-02-02 10:17:30,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 467 to 463. [2018-02-02 10:17:30,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 10:17:30,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 524 transitions. [2018-02-02 10:17:30,327 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 524 transitions. Word has length 58 [2018-02-02 10:17:30,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:30,327 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 524 transitions. [2018-02-02 10:17:30,327 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:30,327 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 524 transitions. [2018-02-02 10:17:30,327 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-02 10:17:30,327 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:30,327 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:30,328 INFO L371 AbstractCegarLoop]: === Iteration 46 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:30,328 INFO L82 PathProgramCache]: Analyzing trace with hash -1445102362, now seen corresponding path program 1 times [2018-02-02 10:17:30,328 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:30,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:30,334 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:30,559 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 30 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:30,559 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:30,559 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 10:17:30,559 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:30,559 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:30,559 INFO L182 omatonBuilderFactory]: Interpolants [46083#true, 46084#false, 46085#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 46086#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 46087#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 46088#(= 1 (select |#valid| entry_point_~cfg~2.base)), 46089#(= |#valid| |old(#valid)|), 46090#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 46091#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 46092#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 46093#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 46094#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 46095#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 46096#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 46097#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret64.base|))), 46098#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)))] [2018-02-02 10:17:30,560 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 30 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 10:17:30,560 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 10:17:30,560 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 10:17:30,560 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:17:30,560 INFO L87 Difference]: Start difference. First operand 463 states and 524 transitions. Second operand 16 states. [2018-02-02 10:17:31,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:31,232 INFO L93 Difference]: Finished difference Result 520 states and 595 transitions. [2018-02-02 10:17:31,232 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 10:17:31,232 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 58 [2018-02-02 10:17:31,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:31,233 INFO L225 Difference]: With dead ends: 520 [2018-02-02 10:17:31,233 INFO L226 Difference]: Without dead ends: 520 [2018-02-02 10:17:31,233 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:17:31,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 520 states. [2018-02-02 10:17:31,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 520 to 463. [2018-02-02 10:17:31,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 10:17:31,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 523 transitions. [2018-02-02 10:17:31,237 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 523 transitions. Word has length 58 [2018-02-02 10:17:31,237 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:31,237 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 523 transitions. [2018-02-02 10:17:31,237 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 10:17:31,237 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 523 transitions. [2018-02-02 10:17:31,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 10:17:31,237 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:31,238 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:31,238 INFO L371 AbstractCegarLoop]: === Iteration 47 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:31,238 INFO L82 PathProgramCache]: Analyzing trace with hash -1825799813, now seen corresponding path program 1 times [2018-02-02 10:17:31,239 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:31,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:31,246 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:31,609 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:17:31,609 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:31,609 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 10:17:31,609 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:31,610 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 10:17:31,610 INFO L182 omatonBuilderFactory]: Interpolants [47088#true, 47089#false, 47090#(= 0 |~#ldv_global_msg_list.offset|), 47091#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 47092#(not (= |ldv_malloc_#t~malloc4.base| 0)), 47093#(not (= |ldv_malloc_#res.base| 0)), 47094#(and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 47095#(and (not (= entry_point_~client~0.base 0)) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 47096#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 47097#(and (or (and (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (or (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 47098#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0))), 47099#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 47100#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 47101#(and (or (and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)) (< (+ ldv_destroy_msgs_~msg~1.offset 4) |~#ldv_global_msg_list.offset|)) (or (= |~#ldv_global_msg_list.offset| 0) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)))), 47102#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|))] [2018-02-02 10:17:31,610 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:17:31,610 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 10:17:31,611 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 10:17:31,611 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-02-02 10:17:31,611 INFO L87 Difference]: Start difference. First operand 463 states and 523 transitions. Second operand 15 states. [2018-02-02 10:17:32,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:32,563 INFO L93 Difference]: Finished difference Result 469 states and 523 transitions. [2018-02-02 10:17:32,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 10:17:32,563 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2018-02-02 10:17:32,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:32,564 INFO L225 Difference]: With dead ends: 469 [2018-02-02 10:17:32,564 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 10:17:32,565 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=152, Invalid=718, Unknown=0, NotChecked=0, Total=870 [2018-02-02 10:17:32,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 10:17:32,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 461. [2018-02-02 10:17:32,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-02 10:17:32,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-02 10:17:32,568 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 59 [2018-02-02 10:17:32,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:32,568 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-02 10:17:32,568 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 10:17:32,568 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-02 10:17:32,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 10:17:32,569 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:32,569 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:32,569 INFO L371 AbstractCegarLoop]: === Iteration 48 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:32,569 INFO L82 PathProgramCache]: Analyzing trace with hash 1324613484, now seen corresponding path program 1 times [2018-02-02 10:17:32,569 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:32,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:32,574 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:32,597 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 10:17:32,598 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:32,598 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 10:17:32,598 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:32,598 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:32,598 INFO L182 omatonBuilderFactory]: Interpolants [48064#false, 48065#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 48066#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 48067#(= 1 (select |#valid| |entry_point_#t~ret66.base|)), 48068#(= 1 (select |#valid| entry_point_~adapter~0.base)), 48063#true] [2018-02-02 10:17:32,598 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 10:17:32,599 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:17:32,599 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:17:32,599 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:32,599 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 6 states. [2018-02-02 10:17:32,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:32,872 INFO L93 Difference]: Finished difference Result 460 states and 517 transitions. [2018-02-02 10:17:32,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:17:32,872 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2018-02-02 10:17:32,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:32,873 INFO L225 Difference]: With dead ends: 460 [2018-02-02 10:17:32,873 INFO L226 Difference]: Without dead ends: 460 [2018-02-02 10:17:32,874 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:32,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states. [2018-02-02 10:17:32,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 460. [2018-02-02 10:17:32,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-02 10:17:32,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 517 transitions. [2018-02-02 10:17:32,880 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 517 transitions. Word has length 59 [2018-02-02 10:17:32,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:32,880 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 517 transitions. [2018-02-02 10:17:32,880 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:17:32,880 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 517 transitions. [2018-02-02 10:17:32,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 10:17:32,881 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:32,881 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:32,881 INFO L371 AbstractCegarLoop]: === Iteration 49 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:32,881 INFO L82 PathProgramCache]: Analyzing trace with hash 1324613485, now seen corresponding path program 1 times [2018-02-02 10:17:32,882 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:32,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:32,894 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:33,002 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-02-02 10:17:33,002 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:33,002 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:17:33,002 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:33,002 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:17:33,002 INFO L182 omatonBuilderFactory]: Interpolants [48992#false, 48993#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 48994#(and (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 48995#(and (= 0 |ldv_malloc_#res.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 48996#(and (<= 4 (select |#length| |entry_point_#t~ret66.base|)) (= 0 |entry_point_#t~ret66.offset|)), 48997#(and (<= 4 (select |#length| entry_point_~adapter~0.base)) (= 0 entry_point_~adapter~0.offset)), 48991#true] [2018-02-02 10:17:33,003 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-02-02 10:17:33,003 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:17:33,003 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:17:33,003 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:17:33,003 INFO L87 Difference]: Start difference. First operand 460 states and 517 transitions. Second operand 7 states. [2018-02-02 10:17:33,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:33,438 INFO L93 Difference]: Finished difference Result 459 states and 516 transitions. [2018-02-02 10:17:33,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:17:33,438 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 59 [2018-02-02 10:17:33,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:33,439 INFO L225 Difference]: With dead ends: 459 [2018-02-02 10:17:33,439 INFO L226 Difference]: Without dead ends: 459 [2018-02-02 10:17:33,440 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:17:33,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459 states. [2018-02-02 10:17:33,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459 to 459. [2018-02-02 10:17:33,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-02 10:17:33,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 516 transitions. [2018-02-02 10:17:33,445 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 516 transitions. Word has length 59 [2018-02-02 10:17:33,445 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:33,445 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 516 transitions. [2018-02-02 10:17:33,446 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:17:33,446 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 516 transitions. [2018-02-02 10:17:33,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 10:17:33,446 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:33,446 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:33,446 INFO L371 AbstractCegarLoop]: === Iteration 50 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:33,447 INFO L82 PathProgramCache]: Analyzing trace with hash -1848500046, now seen corresponding path program 1 times [2018-02-02 10:17:33,447 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:33,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:33,455 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:33,722 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 14 proven. 20 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:33,722 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:33,722 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 10:17:33,723 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:33,723 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-02 10:17:33,723 INFO L182 omatonBuilderFactory]: Interpolants [49920#true, 49921#false, 49922#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 49923#(= (select |#valid| |ldv_malloc_#res.base|) 1), 49924#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 49925#(= (select |#valid| entry_point_~client~0.base) 1), 49926#(= |#valid| |old(#valid)|), 49927#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 49928#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 49929#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|))), 49930#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 49931#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49932#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 49933#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 49934#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= (select |#valid| entry_point_~client~0.base) 1) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49935#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49936#(and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49937#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49938#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)))] [2018-02-02 10:17:33,723 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 14 proven. 20 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:33,723 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 10:17:33,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 10:17:33,723 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=290, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:17:33,723 INFO L87 Difference]: Start difference. First operand 459 states and 516 transitions. Second operand 19 states. [2018-02-02 10:17:34,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:34,585 INFO L93 Difference]: Finished difference Result 518 states and 587 transitions. [2018-02-02 10:17:34,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 10:17:34,585 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-02-02 10:17:34,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:34,586 INFO L225 Difference]: With dead ends: 518 [2018-02-02 10:17:34,586 INFO L226 Difference]: Without dead ends: 518 [2018-02-02 10:17:34,587 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 7 SyntacticMatches, 5 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=429, Unknown=0, NotChecked=0, Total=506 [2018-02-02 10:17:34,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states. [2018-02-02 10:17:34,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 459. [2018-02-02 10:17:34,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-02 10:17:34,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 515 transitions. [2018-02-02 10:17:34,590 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 515 transitions. Word has length 59 [2018-02-02 10:17:34,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:34,590 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 515 transitions. [2018-02-02 10:17:34,590 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 10:17:34,590 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 515 transitions. [2018-02-02 10:17:34,590 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-02-02 10:17:34,590 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:34,590 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:34,590 INFO L371 AbstractCegarLoop]: === Iteration 51 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:34,591 INFO L82 PathProgramCache]: Analyzing trace with hash 1406279546, now seen corresponding path program 1 times [2018-02-02 10:17:34,591 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:34,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:34,598 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:35,027 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 4 proven. 12 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 10:17:35,028 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:35,028 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 10:17:35,028 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:35,028 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:17:35,029 INFO L182 omatonBuilderFactory]: Interpolants [50924#true, 50925#false, 50926#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 50927#(= |#valid| |old(#valid)|), 50928#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 50929#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 50930#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 50931#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 50932#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 50933#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret60.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 50934#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50935#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| entry_point_~client~0.base) 1) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50936#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50937#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50938#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |entry_point_#t~ret64.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50939#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:35,029 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 4 proven. 12 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 10:17:35,029 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 10:17:35,029 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 10:17:35,029 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=187, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:17:35,030 INFO L87 Difference]: Start difference. First operand 459 states and 515 transitions. Second operand 16 states. [2018-02-02 10:17:35,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:35,815 INFO L93 Difference]: Finished difference Result 547 states and 603 transitions. [2018-02-02 10:17:35,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 10:17:35,816 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-02-02 10:17:35,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:35,817 INFO L225 Difference]: With dead ends: 547 [2018-02-02 10:17:35,817 INFO L226 Difference]: Without dead ends: 547 [2018-02-02 10:17:35,817 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 13 SyntacticMatches, 7 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-02-02 10:17:35,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-02-02 10:17:35,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 453. [2018-02-02 10:17:35,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 453 states. [2018-02-02 10:17:35,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 507 transitions. [2018-02-02 10:17:35,821 INFO L78 Accepts]: Start accepts. Automaton has 453 states and 507 transitions. Word has length 62 [2018-02-02 10:17:35,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:35,821 INFO L432 AbstractCegarLoop]: Abstraction has 453 states and 507 transitions. [2018-02-02 10:17:35,821 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 10:17:35,821 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 507 transitions. [2018-02-02 10:17:35,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-02 10:17:35,821 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:35,822 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:35,822 INFO L371 AbstractCegarLoop]: === Iteration 52 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:35,822 INFO L82 PathProgramCache]: Analyzing trace with hash 1796726022, now seen corresponding path program 1 times [2018-02-02 10:17:35,822 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:35,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:35,832 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:36,700 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:36,700 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:36,700 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 10:17:36,700 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:36,701 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 10:17:36,701 INFO L182 omatonBuilderFactory]: Interpolants [51968#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store |#valid| entry_point_~cfg~2.base 0) (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~cfg~2.base) (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 51969#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 51954#true, 51955#false, 51956#(= |#valid| |old(#valid)|), 51957#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 51958#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51959#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51960#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51961#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 51962#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= (select |#valid| |ldv_malloc_#res.base|) 1) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51963#(and (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (= (select |#valid| |entry_point_#t~ret60.base|) 1))) (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base 0))), 51964#(and (not (= entry_point_~cfg~2.base 0)) (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |#valid| entry_point_~cfg~2.base) 1))) (not (= entry_point_~client~0.base 0))), 51965#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (select |#valid| entry_point_~client~0.base) 1) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |#valid| entry_point_~cfg~2.base) 1))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 51966#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (store (store (store |old(#valid)| |entry_point_#t~ret62.base| (select |#valid| |entry_point_#t~ret62.base|)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| |entry_point_#t~ret62.base|) 0) (not (= |entry_point_#t~ret62.base| entry_point_~client~0.base)))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 51967#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (not (= entry_point_~fe~2.base 0)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:36,701 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:17:36,701 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 10:17:36,701 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 10:17:36,701 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:17:36,701 INFO L87 Difference]: Start difference. First operand 453 states and 507 transitions. Second operand 16 states. [2018-02-02 10:17:38,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:38,217 INFO L93 Difference]: Finished difference Result 517 states and 584 transitions. [2018-02-02 10:17:38,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 10:17:38,217 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-02-02 10:17:38,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:38,218 INFO L225 Difference]: With dead ends: 517 [2018-02-02 10:17:38,218 INFO L226 Difference]: Without dead ends: 508 [2018-02-02 10:17:38,218 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 10 SyntacticMatches, 7 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=60, Invalid=320, Unknown=0, NotChecked=0, Total=380 [2018-02-02 10:17:38,219 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states. [2018-02-02 10:17:38,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 451. [2018-02-02 10:17:38,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2018-02-02 10:17:38,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 504 transitions. [2018-02-02 10:17:38,223 INFO L78 Accepts]: Start accepts. Automaton has 451 states and 504 transitions. Word has length 61 [2018-02-02 10:17:38,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:38,224 INFO L432 AbstractCegarLoop]: Abstraction has 451 states and 504 transitions. [2018-02-02 10:17:38,224 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 10:17:38,224 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 504 transitions. [2018-02-02 10:17:38,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-02 10:17:38,224 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:38,224 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:38,224 INFO L371 AbstractCegarLoop]: === Iteration 53 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:38,224 INFO L82 PathProgramCache]: Analyzing trace with hash 169449372, now seen corresponding path program 1 times [2018-02-02 10:17:38,225 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:38,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:38,232 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:38,272 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-02 10:17:38,272 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:17:38,272 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 10:17:38,273 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:38,273 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 10:17:38,273 INFO L182 omatonBuilderFactory]: Interpolants [52946#true, 52947#false, 52948#(= (select |#valid| entry_point_~client~0.base) 1), 52949#(= (select |#valid| |alloc_12_#in~client.base|) 1), 52950#(= 1 (select |#valid| alloc_12_~client.base))] [2018-02-02 10:17:38,273 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-02 10:17:38,273 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 10:17:38,273 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 10:17:38,273 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 10:17:38,273 INFO L87 Difference]: Start difference. First operand 451 states and 504 transitions. Second operand 5 states. [2018-02-02 10:17:38,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:38,443 INFO L93 Difference]: Finished difference Result 450 states and 503 transitions. [2018-02-02 10:17:38,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 10:17:38,446 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 64 [2018-02-02 10:17:38,446 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:38,448 INFO L225 Difference]: With dead ends: 450 [2018-02-02 10:17:38,448 INFO L226 Difference]: Without dead ends: 450 [2018-02-02 10:17:38,448 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:17:38,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-02-02 10:17:38,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 450. [2018-02-02 10:17:38,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 450 states. [2018-02-02 10:17:38,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 503 transitions. [2018-02-02 10:17:38,454 INFO L78 Accepts]: Start accepts. Automaton has 450 states and 503 transitions. Word has length 64 [2018-02-02 10:17:38,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:38,454 INFO L432 AbstractCegarLoop]: Abstraction has 450 states and 503 transitions. [2018-02-02 10:17:38,454 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 10:17:38,455 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 503 transitions. [2018-02-02 10:17:38,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-02 10:17:38,455 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:38,455 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:38,455 INFO L371 AbstractCegarLoop]: === Iteration 54 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:38,456 INFO L82 PathProgramCache]: Analyzing trace with hash 169449373, now seen corresponding path program 1 times [2018-02-02 10:17:38,456 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:38,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:38,467 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:38,529 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 10:17:38,529 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:38,529 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 10:17:38,529 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:38,530 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-02 10:17:38,530 INFO L182 omatonBuilderFactory]: Interpolants [53856#(= 0 |ldv_malloc_#res.offset|), 53857#(= 0 |entry_point_#t~ret59.offset|), 53858#(= 0 entry_point_~client~0.offset), 53859#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 0 entry_point_~client~0.offset) (<= 16 (select |#length| entry_point_~client~0.base))), 53860#(and (<= 16 (select |#length| |alloc_12_#in~client.base|)) (= 0 |alloc_12_#in~client.offset|) (= (select |#valid| |alloc_12_#in~client.base|) 1)), 53861#(and (= alloc_12_~client.offset 0) (= (select |#valid| alloc_12_~client.base) 1) (<= 16 (select |#length| alloc_12_~client.base))), 53862#(and (= alloc_12_~client.offset 0) (<= 16 (select |#length| alloc_12_~client.base))), 53853#true, 53854#false, 53855#(= 0 |ldv_malloc_#t~malloc4.offset|)] [2018-02-02 10:17:38,530 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 10:17:38,530 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 10:17:38,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 10:17:38,530 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:17:38,531 INFO L87 Difference]: Start difference. First operand 450 states and 503 transitions. Second operand 10 states. [2018-02-02 10:17:38,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:38,800 INFO L93 Difference]: Finished difference Result 449 states and 502 transitions. [2018-02-02 10:17:38,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:17:38,800 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 64 [2018-02-02 10:17:38,800 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:38,801 INFO L225 Difference]: With dead ends: 449 [2018-02-02 10:17:38,801 INFO L226 Difference]: Without dead ends: 449 [2018-02-02 10:17:38,801 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:17:38,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states. [2018-02-02 10:17:38,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2018-02-02 10:17:38,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 10:17:38,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 502 transitions. [2018-02-02 10:17:38,805 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 502 transitions. Word has length 64 [2018-02-02 10:17:38,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:38,805 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 502 transitions. [2018-02-02 10:17:38,805 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 10:17:38,806 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 502 transitions. [2018-02-02 10:17:38,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-02 10:17:38,806 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:38,806 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:38,806 INFO L371 AbstractCegarLoop]: === Iteration 55 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:38,806 INFO L82 PathProgramCache]: Analyzing trace with hash -367900259, now seen corresponding path program 1 times [2018-02-02 10:17:38,807 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:38,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:38,821 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:39,149 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 27 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:17:39,150 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:39,150 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 10:17:39,150 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:39,150 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:17:39,150 INFO L182 omatonBuilderFactory]: Interpolants [54784#(and (or (= entry_point_~adapter~0.base (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) (= 1 (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)))) (not (= entry_point_~client~0.base entry_point_~adapter~0.base))), 54785#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|))), 54786#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset))), 54787#(= 1 (select |#valid| |alloc_12_#t~mem46.base|)), 54788#(= 1 (select |#valid| alloc_12_~cfg~0.base)), 54765#true, 54766#false, 54767#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 54768#(= (select |#valid| |ldv_malloc_#res.base|) 1), 54769#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 54770#(= (select |#valid| entry_point_~client~0.base) 1), 54771#(= |#valid| |old(#valid)|), 54772#(= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)), 54773#(= 0 (select |old(#valid)| |ldv_malloc_#res.base|)), 54774#(not (= entry_point_~client~0.base |entry_point_#t~ret60.base|)), 54775#(not (= entry_point_~client~0.base entry_point_~cfg~2.base)), 54776#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54777#(and (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54778#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54779#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 54780#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 54781#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)))), 54782#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 54783#(and (or (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= |entry_point_#t~ret66.base| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|)))] [2018-02-02 10:17:39,150 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 27 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:17:39,150 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 10:17:39,151 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 10:17:39,151 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-02-02 10:17:39,151 INFO L87 Difference]: Start difference. First operand 449 states and 502 transitions. Second operand 24 states. [2018-02-02 10:17:40,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:40,784 INFO L93 Difference]: Finished difference Result 549 states and 629 transitions. [2018-02-02 10:17:40,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 10:17:40,784 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 66 [2018-02-02 10:17:40,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:40,786 INFO L225 Difference]: With dead ends: 549 [2018-02-02 10:17:40,786 INFO L226 Difference]: Without dead ends: 549 [2018-02-02 10:17:40,786 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 7 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 254 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=163, Invalid=1397, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 10:17:40,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states. [2018-02-02 10:17:40,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 447. [2018-02-02 10:17:40,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 447 states. [2018-02-02 10:17:40,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 447 states to 447 states and 500 transitions. [2018-02-02 10:17:40,793 INFO L78 Accepts]: Start accepts. Automaton has 447 states and 500 transitions. Word has length 66 [2018-02-02 10:17:40,793 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:40,793 INFO L432 AbstractCegarLoop]: Abstraction has 447 states and 500 transitions. [2018-02-02 10:17:40,794 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 10:17:40,794 INFO L276 IsEmpty]: Start isEmpty. Operand 447 states and 500 transitions. [2018-02-02 10:17:40,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-02 10:17:40,794 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:40,794 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:40,794 INFO L371 AbstractCegarLoop]: === Iteration 56 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:40,795 INFO L82 PathProgramCache]: Analyzing trace with hash -367900258, now seen corresponding path program 1 times [2018-02-02 10:17:40,795 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:40,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:40,806 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:41,488 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 30 proven. 24 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:17:41,488 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:41,488 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 10:17:41,488 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:41,488 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 10:17:41,488 INFO L182 omatonBuilderFactory]: Interpolants [55817#true, 55818#false, 55819#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 55820#(= (select |#valid| |ldv_malloc_#res.base|) 1), 55821#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 55822#(= (select |#valid| entry_point_~client~0.base) 1), 55823#(= |#valid| |old(#valid)|), 55824#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|)), 55825#(and (= 0 |ldv_malloc_#res.offset|) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|))), 55826#(and (= 0 |entry_point_#t~ret60.offset|) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|))), 55827#(and (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= 0 entry_point_~cfg~2.offset)), 55828#(and (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (= entry_point_~cfg~2.offset 0) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 55829#(and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset))), 55830#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 55831#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 55832#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 55833#(and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 0))), 55834#(and (= (select |#valid| entry_point_~client~0.base) 1) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 0))), 55835#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 55836#(and (or (= |#valid| |old(#valid)|) (and (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= 0 |ldv_malloc_#res.offset|) (= (select |#length| |ldv_malloc_#res.base|) (select |#length| (@diff |old(#valid)| |#valid|))))) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (and (= (select |#length| |ldv_malloc_#res.base|) (select |#length| (@diff |old(#length)| |#length|))) (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| (@diff |old(#length)| |#length|)) 1)) (= |old(#length)| |#length|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 55837#(and (or (and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 0))) (and (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= (select |#length| |entry_point_#t~ret66.base|) (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= 0 |entry_point_#t~ret66.offset|))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|))), 55838#(and (or (and (= (select |#length| entry_point_~adapter~0.base) (select |#length| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset))) (= 0 entry_point_~adapter~0.offset) (= (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) 1)) (and (<= 4 (select |#length| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset))) (not (= (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) 0)))) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (= 0 (select (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.offset) entry_point_~client~0.offset))), 55839#(and (= 0 (select (select |#memory_$Pointer$.offset| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|)) 0)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|)))), 55840#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_12_~client.base) alloc_12_~client.offset)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset)) 0))), 55841#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_12_~client.base) alloc_12_~client.offset)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset)))), 55842#(and (= 0 |alloc_12_#t~mem46.offset|) (<= 4 (select |#length| |alloc_12_#t~mem46.base|))), 55843#(and (= alloc_12_~cfg~0.offset 0) (< 3 (select |#length| alloc_12_~cfg~0.base)))] [2018-02-02 10:17:41,488 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 30 proven. 24 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:17:41,489 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 10:17:41,489 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 10:17:41,489 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=639, Unknown=0, NotChecked=0, Total=702 [2018-02-02 10:17:41,489 INFO L87 Difference]: Start difference. First operand 447 states and 500 transitions. Second operand 27 states. [2018-02-02 10:17:44,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:17:44,745 INFO L93 Difference]: Finished difference Result 557 states and 637 transitions. [2018-02-02 10:17:44,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 10:17:44,745 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 66 [2018-02-02 10:17:44,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:17:44,746 INFO L225 Difference]: With dead ends: 557 [2018-02-02 10:17:44,746 INFO L226 Difference]: Without dead ends: 557 [2018-02-02 10:17:44,746 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 2 SyntacticMatches, 6 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 273 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=186, Invalid=1706, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 10:17:44,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-02-02 10:17:44,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 449. [2018-02-02 10:17:44,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 10:17:44,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 506 transitions. [2018-02-02 10:17:44,750 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 506 transitions. Word has length 66 [2018-02-02 10:17:44,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:17:44,750 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 506 transitions. [2018-02-02 10:17:44,750 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 10:17:44,750 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 506 transitions. [2018-02-02 10:17:44,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-02-02 10:17:44,750 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:17:44,750 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:17:44,751 INFO L371 AbstractCegarLoop]: === Iteration 57 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 10:17:44,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1079248251, now seen corresponding path program 1 times [2018-02-02 10:17:44,751 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:17:44,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:17:44,762 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:17:48,876 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-02 10:17:48,876 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:17:48,877 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 10:17:48,877 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:17:48,877 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:17:48,877 INFO L182 omatonBuilderFactory]: Interpolants [56896#(and (not (= |entry_point_#t~ret62.base| 0)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (store (store (store |old(#valid)| |entry_point_#t~ret62.base| (select |#valid| |entry_point_#t~ret62.base|)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| |entry_point_#t~ret62.base|) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56897#(and (not (= entry_point_~fe~2.base 0)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56898#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56899#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (not (= |entry_point_#t~ret64.base| entry_point_~cfg~2.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (or (= entry_point_~fe~2.base |entry_point_#t~ret64.base|) (and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (= (select |old(#valid)| |entry_point_#t~ret64.base|) 0) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |old(#valid)| entry_point_~fe~2.base) 0) (= |#valid| (store (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |entry_point_#t~ret64.base| (select |#valid| |entry_point_#t~ret64.base|))))) (not (= entry_point_~fe~2.base entry_point_~client~0.base)))) (not (= |entry_point_#t~ret64.base| 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56900#(and (or (= entry_point_~addr~0.base entry_point_~fe~2.base) (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= |#valid| (store (store (store (store |old(#valid)| entry_point_~addr~0.base (select |#valid| entry_point_~addr~0.base)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~addr~0.base) 0) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (not (= entry_point_~addr~0.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0) (not (= entry_point_~addr~0.base entry_point_~client~0.base)))) (not (= entry_point_~addr~0.base 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56901#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (= (select |#valid| entry_point_~fe~2.base) 0) (and (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~cfg~2.base)) entry_point_~fe~2.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~fe~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~fe~2.base 0)) (= (select |old(#valid)| entry_point_~fe~2.base) (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)))) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56902#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= (store |#valid| entry_point_~cfg~2.base 0) (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~cfg~2.base) (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56903#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 56904#(and (= |#valid| |old(#valid)|) (= (select |#valid| |~#ldv_global_msg_list.base|) 1)), 56884#true, 56885#false, 56886#(= |#valid| |old(#valid)|), 56887#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 56888#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0))), 56889#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56890#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56891#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 56892#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= 1 (select |#valid| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56893#(and (not (= |entry_point_#t~ret60.base| 0)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= 1 (select |#valid| |entry_point_#t~ret60.base|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))))) (not (= entry_point_~client~0.base 0))), 56894#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= entry_point_~cfg~2.base (@diff |old(#valid)| |#valid|))) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= 1 (select |#valid| entry_point_~cfg~2.base)) (or (= entry_point_~client~0.base (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)) (= entry_point_~cfg~2.base (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))))) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base 0))), 56895#(and (= 1 (select |#valid| entry_point_~client~0.base)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= 1 (select |#valid| entry_point_~cfg~2.base)))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 10:17:48,877 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-02 10:17:48,878 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 10:17:48,878 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 10:17:48,878 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2018-02-02 10:17:48,878 INFO L87 Difference]: Start difference. First operand 449 states and 506 transitions. Second operand 21 states. Received shutdown request... [2018-02-02 10:17:49,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 10:17:49,122 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 10:17:49,128 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 10:17:49,128 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 10:17:49 BoogieIcfgContainer [2018-02-02 10:17:49,128 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 10:17:49,129 INFO L168 Benchmark]: Toolchain (without parser) took 49773.10 ms. Allocated memory was 402.7 MB in the beginning and 1.6 GB in the end (delta: 1.2 GB). Free memory was 359.5 MB in the beginning and 488.2 MB in the end (delta: -128.6 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. [2018-02-02 10:17:49,130 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 402.7 MB. Free memory is still 366.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 10:17:49,130 INFO L168 Benchmark]: CACSL2BoogieTranslator took 221.16 ms. Allocated memory is still 402.7 MB. Free memory was 359.5 MB in the beginning and 342.1 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. [2018-02-02 10:17:49,130 INFO L168 Benchmark]: Boogie Preprocessor took 47.59 ms. Allocated memory is still 402.7 MB. Free memory was 342.1 MB in the beginning and 339.5 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-02 10:17:49,131 INFO L168 Benchmark]: RCFGBuilder took 794.09 ms. Allocated memory was 402.7 MB in the beginning and 428.9 MB in the end (delta: 26.2 MB). Free memory was 339.5 MB in the beginning and 387.7 MB in the end (delta: -48.2 MB). Peak memory consumption was 100.9 MB. Max. memory is 5.3 GB. [2018-02-02 10:17:49,131 INFO L168 Benchmark]: TraceAbstraction took 48707.27 ms. Allocated memory was 428.9 MB in the beginning and 1.6 GB in the end (delta: 1.2 GB). Free memory was 387.7 MB in the beginning and 488.2 MB in the end (delta: -100.4 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. [2018-02-02 10:17:49,132 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 402.7 MB. Free memory is still 366.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 221.16 ms. Allocated memory is still 402.7 MB. Free memory was 359.5 MB in the beginning and 342.1 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 47.59 ms. Allocated memory is still 402.7 MB. Free memory was 342.1 MB in the beginning and 339.5 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 794.09 ms. Allocated memory was 402.7 MB in the beginning and 428.9 MB in the end (delta: 26.2 MB). Free memory was 339.5 MB in the beginning and 387.7 MB in the end (delta: -48.2 MB). Peak memory consumption was 100.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 48707.27 ms. Allocated memory was 428.9 MB in the beginning and 1.6 GB in the end (delta: 1.2 GB). Free memory was 387.7 MB in the beginning and 488.2 MB in the end (delta: -100.4 MB). Peak memory consumption was 1.1 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1559). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1563). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1563). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1559). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1619]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1619). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1569). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1574). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1569). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1574). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1592). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1609). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1613). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1584). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1584). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1607). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1613). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1597). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1599). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1605). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1588). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1611). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1597). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1607). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1609). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1611). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1592). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1588). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1599). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1605). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was constructing difference of abstraction (449states) and interpolant automaton (currently 15 states, 21 states before enhancement), while ReachableStatesComputation was computing reachable states (36 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 28 procedures, 416 locations, 141 error locations. TIMEOUT Result, 48.6s OverallTime, 57 OverallIterations, 5 TraceHistogramMax, 35.0s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 20250 SDtfs, 12751 SDslu, 78437 SDs, 0 SdLazy, 61934 SolverSat, 3092 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 26.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 966 GetRequests, 194 SyntacticMatches, 127 SemanticMatches, 645 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1702 ImplicationChecksByTransitivity, 10.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=538occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 1178/1454 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 56 MinimizatonAttempts, 2742 StatesRemovedByMinimization, 49 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 12.2s InterpolantComputationTime, 2448 NumberOfCodeBlocks, 2448 NumberOfCodeBlocksAsserted, 57 NumberOfCheckSat, 2391 ConstructedInterpolants, 0 QuantifiedInterpolants, 984370 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 57 InterpolantComputations, 18 PerfectInterpolantSequences, 1178/1454 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_10-17-49-141.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_10-17-49-141.csv Completed graceful shutdown