java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 10:18:19,256 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 10:18:19,257 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 10:18:19,270 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 10:18:19,271 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 10:18:19,271 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 10:18:19,272 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 10:18:19,273 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 10:18:19,275 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 10:18:19,276 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 10:18:19,277 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 10:18:19,277 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 10:18:19,278 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 10:18:19,279 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 10:18:19,280 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 10:18:19,282 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 10:18:19,283 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 10:18:19,285 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 10:18:19,286 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 10:18:19,287 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 10:18:19,288 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-02 10:18:19,289 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-02 10:18:19,289 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-02 10:18:19,290 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-02 10:18:19,290 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-02 10:18:19,291 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-02 10:18:19,292 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-02 10:18:19,292 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-02 10:18:19,292 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-02 10:18:19,292 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-02 10:18:19,293 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-02 10:18:19,293 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 10:18:19,301 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 10:18:19,302 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 10:18:19,302 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 10:18:19,303 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 10:18:19,303 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 10:18:19,304 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 10:18:19,304 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 10:18:19,305 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 10:18:19,305 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 10:18:19,334 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 10:18:19,342 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 10:18:19,344 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 10:18:19,345 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 10:18:19,346 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 10:18:19,346 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i [2018-02-02 10:18:19,617 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 10:18:19,618 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 10:18:19,619 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 10:18:19,619 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 10:18:19,624 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 10:18:19,625 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,628 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4398c585 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19, skipping insertion in model container [2018-02-02 10:18:19,628 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,642 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 10:18:19,681 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 10:18:19,767 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 10:18:19,787 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 10:18:19,796 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19 WrapperNode [2018-02-02 10:18:19,796 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 10:18:19,797 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 10:18:19,797 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 10:18:19,797 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 10:18:19,805 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,806 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,813 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,813 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,820 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,822 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,823 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... [2018-02-02 10:18:19,825 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 10:18:19,825 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 10:18:19,825 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 10:18:19,825 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 10:18:19,826 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 10:18:19,860 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 10:18:19,860 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 10:18:19,860 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-02-02 10:18:19,860 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-02-02 10:18:19,860 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-02 10:18:19,860 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_get_drvdata [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_set_drvdata [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_arvo_device_struct [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_specials_unsafe [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure lvd_arvo_remove_specials [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_probe_unsafe [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_remove [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-02 10:18:19,861 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 10:18:19,861 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-02 10:18:19,861 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-02 10:18:19,861 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-02-02 10:18:19,862 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_get_drvdata [2018-02-02 10:18:19,862 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_set_drvdata [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_arvo_device_struct [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_specials_unsafe [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure lvd_arvo_remove_specials [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_probe_unsafe [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_remove [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 10:18:19,863 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 10:18:20,213 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 10:18:20,214 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 10:18:20 BoogieIcfgContainer [2018-02-02 10:18:20,214 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 10:18:20,215 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 10:18:20,215 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 10:18:20,217 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 10:18:20,218 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 10:18:19" (1/3) ... [2018-02-02 10:18:20,218 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@209bc743 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 10:18:20, skipping insertion in model container [2018-02-02 10:18:20,218 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 10:18:19" (2/3) ... [2018-02-02 10:18:20,219 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@209bc743 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 10:18:20, skipping insertion in model container [2018-02-02 10:18:20,219 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 10:18:20" (3/3) ... [2018-02-02 10:18:20,220 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test15_false-valid-memtrack.i [2018-02-02 10:18:20,227 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 10:18:20,232 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 45 error locations. [2018-02-02 10:18:20,265 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 10:18:20,265 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 10:18:20,265 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 10:18:20,265 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 10:18:20,265 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 10:18:20,265 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 10:18:20,266 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 10:18:20,266 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 10:18:20,267 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 10:18:20,281 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states. [2018-02-02 10:18:20,289 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-02-02 10:18:20,290 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:20,291 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:20,291 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:20,295 INFO L82 PathProgramCache]: Analyzing trace with hash 462743197, now seen corresponding path program 1 times [2018-02-02 10:18:20,353 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:20,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:20,401 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:20,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:18:20,567 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:18:20,567 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:18:20,568 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:20,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:18:20,569 INFO L182 omatonBuilderFactory]: Interpolants [168#true, 169#false, 170#(not (= 0 |ldv_zalloc_#t~malloc1.base|)), 171#(not (= 0 |ldv_zalloc_#res.base|)), 172#(not (= 0 |entry_point_#t~ret22.base|)), 173#(not (= 0 entry_point_~hdev~0.base))] [2018-02-02 10:18:20,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 10:18:20,570 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:18:20,578 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:18:20,579 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:18:20,580 INFO L87 Difference]: Start difference. First operand 165 states. Second operand 6 states. [2018-02-02 10:18:20,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:20,630 INFO L93 Difference]: Finished difference Result 165 states and 177 transitions. [2018-02-02 10:18:20,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:18:20,631 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-02-02 10:18:20,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:20,638 INFO L225 Difference]: With dead ends: 165 [2018-02-02 10:18:20,638 INFO L226 Difference]: Without dead ends: 162 [2018-02-02 10:18:20,639 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:18:20,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-02 10:18:20,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-02 10:18:20,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-02 10:18:20,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 174 transitions. [2018-02-02 10:18:20,671 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 174 transitions. Word has length 22 [2018-02-02 10:18:20,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:20,672 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 174 transitions. [2018-02-02 10:18:20,672 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:18:20,673 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 174 transitions. [2018-02-02 10:18:20,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-02 10:18:20,674 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:20,674 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:20,674 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:20,675 INFO L82 PathProgramCache]: Analyzing trace with hash -844495449, now seen corresponding path program 1 times [2018-02-02 10:18:20,676 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:20,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:20,699 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:20,755 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:18:20,755 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:18:20,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:18:20,756 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:20,756 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:18:20,756 INFO L182 omatonBuilderFactory]: Interpolants [503#true, 504#false, 505#(not (= 0 |ldv_zalloc_#t~malloc1.base|)), 506#(not (= 0 |ldv_zalloc_#res.base|)), 507#(not (= 0 |entry_point_#t~ret23.base|)), 508#(not (= 0 entry_point_~intf~2.base))] [2018-02-02 10:18:20,756 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 10:18:20,758 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:18:20,758 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:18:20,758 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:18:20,758 INFO L87 Difference]: Start difference. First operand 162 states and 174 transitions. Second operand 6 states. [2018-02-02 10:18:20,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:20,847 INFO L93 Difference]: Finished difference Result 162 states and 173 transitions. [2018-02-02 10:18:20,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:18:20,851 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-02-02 10:18:20,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:20,852 INFO L225 Difference]: With dead ends: 162 [2018-02-02 10:18:20,852 INFO L226 Difference]: Without dead ends: 162 [2018-02-02 10:18:20,853 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:18:20,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-02 10:18:20,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-02 10:18:20,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-02 10:18:20,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 173 transitions. [2018-02-02 10:18:20,862 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 173 transitions. Word has length 33 [2018-02-02 10:18:20,863 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:20,863 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 173 transitions. [2018-02-02 10:18:20,863 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:18:20,864 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 173 transitions. [2018-02-02 10:18:20,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 10:18:20,864 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:20,865 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:20,865 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:20,865 INFO L82 PathProgramCache]: Analyzing trace with hash 902320110, now seen corresponding path program 1 times [2018-02-02 10:18:20,866 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:20,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:20,899 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:21,008 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:21,008 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:21,008 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 10:18:21,008 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:21,009 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:21,009 INFO L182 omatonBuilderFactory]: Interpolants [835#true, 836#false, 837#(= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|)), 838#(= 1 (select |#valid| |ldv_zalloc_#res.base|)), 839#(= 1 (select |#valid| |entry_point_#t~ret23.base|)), 840#(= 1 (select |#valid| entry_point_~intf~2.base)), 841#(= |#valid| |old(#valid)|), 842#(and (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|))), 843#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 10:18:21,009 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:21,009 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 10:18:21,009 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 10:18:21,009 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:18:21,009 INFO L87 Difference]: Start difference. First operand 162 states and 173 transitions. Second operand 9 states. [2018-02-02 10:18:21,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:21,477 INFO L93 Difference]: Finished difference Result 184 states and 200 transitions. [2018-02-02 10:18:21,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 10:18:21,478 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 44 [2018-02-02 10:18:21,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:21,481 INFO L225 Difference]: With dead ends: 184 [2018-02-02 10:18:21,481 INFO L226 Difference]: Without dead ends: 184 [2018-02-02 10:18:21,481 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:18:21,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-02-02 10:18:21,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 175. [2018-02-02 10:18:21,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-02 10:18:21,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 192 transitions. [2018-02-02 10:18:21,490 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 192 transitions. Word has length 44 [2018-02-02 10:18:21,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:21,491 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 192 transitions. [2018-02-02 10:18:21,491 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 10:18:21,491 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 192 transitions. [2018-02-02 10:18:21,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 10:18:21,492 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:21,492 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:21,492 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:21,492 INFO L82 PathProgramCache]: Analyzing trace with hash 902320111, now seen corresponding path program 1 times [2018-02-02 10:18:21,493 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:21,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:21,512 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:21,672 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:21,673 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:21,673 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 10:18:21,673 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:21,673 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:21,674 INFO L182 omatonBuilderFactory]: Interpolants [1205#true, 1206#false, 1207#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 1208#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))) (< 0 (div ldv_zalloc_~size 4294967296)))), 1209#(= |#Ultimate.meminit_#t~loopctr33| 0), 1210#(<= |#Ultimate.meminit_#product| 0), 1211#(or (<= 2147483648 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 0))] [2018-02-02 10:18:21,674 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:21,674 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:18:21,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:18:21,674 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:18:21,675 INFO L87 Difference]: Start difference. First operand 175 states and 192 transitions. Second operand 7 states. [2018-02-02 10:18:21,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:21,761 INFO L93 Difference]: Finished difference Result 181 states and 198 transitions. [2018-02-02 10:18:21,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:18:21,761 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 44 [2018-02-02 10:18:21,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:21,762 INFO L225 Difference]: With dead ends: 181 [2018-02-02 10:18:21,762 INFO L226 Difference]: Without dead ends: 176 [2018-02-02 10:18:21,762 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:18:21,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-02-02 10:18:21,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2018-02-02 10:18:21,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-02-02 10:18:21,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 193 transitions. [2018-02-02 10:18:21,771 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 193 transitions. Word has length 44 [2018-02-02 10:18:21,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:21,771 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 193 transitions. [2018-02-02 10:18:21,771 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:18:21,771 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 193 transitions. [2018-02-02 10:18:21,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 10:18:21,772 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:21,772 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:21,772 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:21,772 INFO L82 PathProgramCache]: Analyzing trace with hash -506792821, now seen corresponding path program 1 times [2018-02-02 10:18:21,773 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:21,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:21,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:21,898 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-02 10:18:21,898 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:21,898 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 10:18:21,898 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:21,899 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-02 10:18:21,899 INFO L182 omatonBuilderFactory]: Interpolants [1573#true, 1574#false, 1575#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 1576#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 1577#(= |#Ultimate.meminit_#t~loopctr33| 0), 1578#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 1 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|))), 1579#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 1 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| |#Ultimate.meminit_#sizeOfFields|))), 1580#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 1))] [2018-02-02 10:18:21,899 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-02 10:18:21,899 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 10:18:21,900 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 10:18:21,900 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-02-02 10:18:21,900 INFO L87 Difference]: Start difference. First operand 176 states and 193 transitions. Second operand 8 states. [2018-02-02 10:18:21,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:21,986 INFO L93 Difference]: Finished difference Result 182 states and 199 transitions. [2018-02-02 10:18:21,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 10:18:21,986 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 47 [2018-02-02 10:18:21,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:21,987 INFO L225 Difference]: With dead ends: 182 [2018-02-02 10:18:21,988 INFO L226 Difference]: Without dead ends: 177 [2018-02-02 10:18:21,988 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:18:21,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-02 10:18:21,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-02-02 10:18:21,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-02-02 10:18:21,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 194 transitions. [2018-02-02 10:18:21,995 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 194 transitions. Word has length 47 [2018-02-02 10:18:21,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:21,996 INFO L432 AbstractCegarLoop]: Abstraction has 177 states and 194 transitions. [2018-02-02 10:18:21,996 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 10:18:21,996 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 194 transitions. [2018-02-02 10:18:21,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 10:18:21,997 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:21,997 INFO L351 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:21,997 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:21,997 INFO L82 PathProgramCache]: Analyzing trace with hash -1284083601, now seen corresponding path program 2 times [2018-02-02 10:18:21,998 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:22,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:22,026 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:22,159 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-02 10:18:22,159 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:22,159 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 10:18:22,159 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:22,160 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-02 10:18:22,160 INFO L182 omatonBuilderFactory]: Interpolants [1952#(or (<= |ldv_zalloc_#in~size| 2) (<= 4294967296 |ldv_zalloc_#in~size|)), 1944#true, 1945#false, 1946#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 1947#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 1948#(= |#Ultimate.meminit_#t~loopctr33| 0), 1949#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 1950#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ |#Ultimate.meminit_#t~loopctr33| 2) (* 2 |#Ultimate.meminit_#product|)))), 1951#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#product| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= 2 |#Ultimate.meminit_#product|)))] [2018-02-02 10:18:22,160 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-02 10:18:22,160 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 10:18:22,161 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 10:18:22,161 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:18:22,161 INFO L87 Difference]: Start difference. First operand 177 states and 194 transitions. Second operand 9 states. [2018-02-02 10:18:22,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:22,281 INFO L93 Difference]: Finished difference Result 183 states and 200 transitions. [2018-02-02 10:18:22,281 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 10:18:22,281 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 50 [2018-02-02 10:18:22,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:22,282 INFO L225 Difference]: With dead ends: 183 [2018-02-02 10:18:22,283 INFO L226 Difference]: Without dead ends: 178 [2018-02-02 10:18:22,283 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:18:22,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-02-02 10:18:22,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2018-02-02 10:18:22,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-02-02 10:18:22,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 195 transitions. [2018-02-02 10:18:22,290 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 195 transitions. Word has length 50 [2018-02-02 10:18:22,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:22,290 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 195 transitions. [2018-02-02 10:18:22,290 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 10:18:22,291 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 195 transitions. [2018-02-02 10:18:22,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 10:18:22,292 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:22,292 INFO L351 BasicCegarLoop]: trace histogram [9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:22,292 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:22,292 INFO L82 PathProgramCache]: Analyzing trace with hash -202175989, now seen corresponding path program 3 times [2018-02-02 10:18:22,293 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:22,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:22,313 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:22,490 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-02 10:18:22,490 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:22,491 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 10:18:22,491 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:22,491 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-02-02 10:18:22,491 INFO L182 omatonBuilderFactory]: Interpolants [2320#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 2321#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 2322#(= |#Ultimate.meminit_#t~loopctr33| 0), 2323#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 2324#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 2325#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (+ (* 2 |#Ultimate.meminit_#t~loopctr33|) 3) (* 3 |#Ultimate.meminit_#product|))), 2326#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= 3 |#Ultimate.meminit_#product|)), 2327#(or (<= |ldv_zalloc_#in~size| 3) (<= 4294967296 |ldv_zalloc_#in~size|)), 2318#true, 2319#false] [2018-02-02 10:18:22,492 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-02 10:18:22,492 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 10:18:22,492 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 10:18:22,492 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:18:22,493 INFO L87 Difference]: Start difference. First operand 178 states and 195 transitions. Second operand 10 states. [2018-02-02 10:18:22,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:22,626 INFO L93 Difference]: Finished difference Result 184 states and 201 transitions. [2018-02-02 10:18:22,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 10:18:22,626 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 53 [2018-02-02 10:18:22,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:22,627 INFO L225 Difference]: With dead ends: 184 [2018-02-02 10:18:22,628 INFO L226 Difference]: Without dead ends: 179 [2018-02-02 10:18:22,628 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:18:22,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-02-02 10:18:22,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2018-02-02 10:18:22,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-02-02 10:18:22,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 196 transitions. [2018-02-02 10:18:22,636 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 196 transitions. Word has length 53 [2018-02-02 10:18:22,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:22,636 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 196 transitions. [2018-02-02 10:18:22,636 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 10:18:22,636 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 196 transitions. [2018-02-02 10:18:22,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 10:18:22,637 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:22,637 INFO L351 BasicCegarLoop]: trace histogram [12, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:22,637 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:22,637 INFO L82 PathProgramCache]: Analyzing trace with hash -734121745, now seen corresponding path program 4 times [2018-02-02 10:18:22,638 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:22,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:22,660 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:22,820 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-02 10:18:22,821 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:22,821 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 10:18:22,821 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:22,821 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 10:18:22,821 INFO L182 omatonBuilderFactory]: Interpolants [2704#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 4 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 2705#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 4)), 2695#true, 2696#false, 2697#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 2698#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 2699#(= |#Ultimate.meminit_#t~loopctr33| 0), 2700#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 2701#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 2702#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 2703#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 3 |#Ultimate.meminit_#t~loopctr33|) 4) (* 4 |#Ultimate.meminit_#product|))))] [2018-02-02 10:18:22,822 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-02 10:18:22,822 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 10:18:22,822 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 10:18:22,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-02-02 10:18:22,822 INFO L87 Difference]: Start difference. First operand 179 states and 196 transitions. Second operand 11 states. [2018-02-02 10:18:22,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:22,972 INFO L93 Difference]: Finished difference Result 185 states and 202 transitions. [2018-02-02 10:18:22,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:18:22,972 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 56 [2018-02-02 10:18:22,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:22,974 INFO L225 Difference]: With dead ends: 185 [2018-02-02 10:18:22,974 INFO L226 Difference]: Without dead ends: 180 [2018-02-02 10:18:22,974 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:18:22,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-02-02 10:18:22,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-02-02 10:18:22,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-02-02 10:18:22,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 197 transitions. [2018-02-02 10:18:22,979 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 197 transitions. Word has length 56 [2018-02-02 10:18:22,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:22,980 INFO L432 AbstractCegarLoop]: Abstraction has 180 states and 197 transitions. [2018-02-02 10:18:22,980 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 10:18:22,980 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 197 transitions. [2018-02-02 10:18:22,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 10:18:22,981 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:22,981 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:22,981 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:22,981 INFO L82 PathProgramCache]: Analyzing trace with hash 1514307467, now seen corresponding path program 5 times [2018-02-02 10:18:22,982 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:23,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:23,009 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:23,331 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 50 proven. 58 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-02-02 10:18:23,331 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:23,331 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 10:18:23,331 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:23,331 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 20 proven. 13 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 10:18:23,332 INFO L182 omatonBuilderFactory]: Interpolants [3075#true, 3076#false, 3077#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 3078#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296) ldv_zalloc_~size) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3079#(= |#Ultimate.meminit_#t~loopctr33| 0), 3080#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 3081#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 3082#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 3083#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 3084#(<= (+ (* 4 |#Ultimate.meminit_#t~loopctr33|) 5) (* 5 |#Ultimate.meminit_#product|)), 3085#(<= 5 |#Ultimate.meminit_#product|), 3086#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|)))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3087#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|)))) (= 0 |ldv_zalloc_#res.offset|)), 3088#(and (= 0 |entry_point_#t~ret23.offset|) (<= 20 (select |#length| |entry_point_#t~ret23.base|)) (= (select |#valid| |entry_point_#t~ret23.base|) 1)), 3089#(and (= (select |#valid| entry_point_~intf~2.base) 1) (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base))), 3090#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 3091#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 3092#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 3093#(and (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base)))] [2018-02-02 10:18:23,332 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 50 proven. 58 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-02-02 10:18:23,332 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 10:18:23,332 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 10:18:23,333 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=304, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:18:23,333 INFO L87 Difference]: Start difference. First operand 180 states and 197 transitions. Second operand 19 states. [2018-02-02 10:18:24,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:24,623 INFO L93 Difference]: Finished difference Result 235 states and 272 transitions. [2018-02-02 10:18:24,624 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 10:18:24,624 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-02-02 10:18:24,624 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:24,625 INFO L225 Difference]: With dead ends: 235 [2018-02-02 10:18:24,625 INFO L226 Difference]: Without dead ends: 235 [2018-02-02 10:18:24,625 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=104, Invalid=766, Unknown=0, NotChecked=0, Total=870 [2018-02-02 10:18:24,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-02-02 10:18:24,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 211. [2018-02-02 10:18:24,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 211 states. [2018-02-02 10:18:24,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211 states to 211 states and 251 transitions. [2018-02-02 10:18:24,630 INFO L78 Accepts]: Start accepts. Automaton has 211 states and 251 transitions. Word has length 59 [2018-02-02 10:18:24,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:24,630 INFO L432 AbstractCegarLoop]: Abstraction has 211 states and 251 transitions. [2018-02-02 10:18:24,630 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 10:18:24,630 INFO L276 IsEmpty]: Start isEmpty. Operand 211 states and 251 transitions. [2018-02-02 10:18:24,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-02 10:18:24,631 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:24,631 INFO L351 BasicCegarLoop]: trace histogram [17, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:24,631 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:24,631 INFO L82 PathProgramCache]: Analyzing trace with hash -986148649, now seen corresponding path program 6 times [2018-02-02 10:18:24,632 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:24,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:24,647 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:24,894 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-02-02 10:18:24,895 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:24,895 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 10:18:24,895 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:24,895 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-02-02 10:18:24,895 INFO L182 omatonBuilderFactory]: Interpolants [3568#(and (= 0 |entry_point_#t~ret23.offset|) (<= 20 (select |#length| |entry_point_#t~ret23.base|)) (= (select |#valid| |entry_point_#t~ret23.base|) 1)), 3569#(and (= (select |#valid| entry_point_~intf~2.base) 1) (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base))), 3570#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 3571#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 3572#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 3573#(and (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base))), 3562#true, 3563#false, 3564#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 3565#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)) (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296) ldv_zalloc_~size) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3566#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3567#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|))))) (= 0 |ldv_zalloc_#res.offset|))] [2018-02-02 10:18:24,896 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-02-02 10:18:24,896 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 10:18:24,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 10:18:24,896 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:18:24,896 INFO L87 Difference]: Start difference. First operand 211 states and 251 transitions. Second operand 12 states. [2018-02-02 10:18:25,181 WARN L146 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 65 DAG size of output 56 [2018-02-02 10:18:25,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:25,695 INFO L93 Difference]: Finished difference Result 221 states and 267 transitions. [2018-02-02 10:18:25,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:18:25,696 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 61 [2018-02-02 10:18:25,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:25,696 INFO L225 Difference]: With dead ends: 221 [2018-02-02 10:18:25,697 INFO L226 Difference]: Without dead ends: 221 [2018-02-02 10:18:25,697 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=46, Invalid=164, Unknown=0, NotChecked=0, Total=210 [2018-02-02 10:18:25,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states. [2018-02-02 10:18:25,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 175. [2018-02-02 10:18:25,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-02 10:18:25,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 190 transitions. [2018-02-02 10:18:25,701 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 190 transitions. Word has length 61 [2018-02-02 10:18:25,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:25,702 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 190 transitions. [2018-02-02 10:18:25,702 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 10:18:25,702 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 190 transitions. [2018-02-02 10:18:25,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-02 10:18:25,703 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:25,703 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:25,703 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:25,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1708156291, now seen corresponding path program 1 times [2018-02-02 10:18:25,704 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:25,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:25,720 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:25,769 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-02 10:18:25,770 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:25,770 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 10:18:25,770 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:25,770 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-02 10:18:25,771 INFO L182 omatonBuilderFactory]: Interpolants [3976#true, 3977#false, 3978#(= 0 |ldv_zalloc_#t~malloc1.offset|), 3979#(= 0 |ldv_zalloc_#res.offset|), 3980#(= 0 |entry_point_#t~ret22.offset|), 3981#(= 0 entry_point_~hdev~0.offset)] [2018-02-02 10:18:25,771 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-02 10:18:25,771 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 10:18:25,771 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 10:18:25,771 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 10:18:25,771 INFO L87 Difference]: Start difference. First operand 175 states and 190 transitions. Second operand 6 states. [2018-02-02 10:18:25,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:25,791 INFO L93 Difference]: Finished difference Result 174 states and 189 transitions. [2018-02-02 10:18:25,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 10:18:25,792 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 64 [2018-02-02 10:18:25,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:25,793 INFO L225 Difference]: With dead ends: 174 [2018-02-02 10:18:25,793 INFO L226 Difference]: Without dead ends: 174 [2018-02-02 10:18:25,793 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:18:25,793 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-02 10:18:25,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-02 10:18:25,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-02 10:18:25,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 189 transitions. [2018-02-02 10:18:25,797 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 189 transitions. Word has length 64 [2018-02-02 10:18:25,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:25,798 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 189 transitions. [2018-02-02 10:18:25,798 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 10:18:25,798 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 189 transitions. [2018-02-02 10:18:25,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-02 10:18:25,799 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:25,799 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:25,799 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:25,799 INFO L82 PathProgramCache]: Analyzing trace with hash 1708156292, now seen corresponding path program 1 times [2018-02-02 10:18:25,800 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:25,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:25,816 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:25,863 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-02 10:18:25,863 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:18:25,863 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 10:18:25,863 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:25,864 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-02 10:18:25,864 INFO L182 omatonBuilderFactory]: Interpolants [4336#(not (= 0 |entry_point_#t~ret24.base|)), 4337#(not (= 0 (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 4338#(not (= 0 |entry_point_#t~mem26.base|)), 4332#true, 4333#false, 4334#(not (= 0 |ldv_zalloc_#t~malloc1.base|)), 4335#(not (= 0 |ldv_zalloc_#res.base|))] [2018-02-02 10:18:25,864 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-02 10:18:25,864 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:18:25,865 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:18:25,865 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:18:25,865 INFO L87 Difference]: Start difference. First operand 174 states and 189 transitions. Second operand 7 states. [2018-02-02 10:18:25,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:25,923 INFO L93 Difference]: Finished difference Result 173 states and 187 transitions. [2018-02-02 10:18:25,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 10:18:25,923 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 64 [2018-02-02 10:18:25,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:25,924 INFO L225 Difference]: With dead ends: 173 [2018-02-02 10:18:25,924 INFO L226 Difference]: Without dead ends: 173 [2018-02-02 10:18:25,924 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:18:25,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-02-02 10:18:25,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2018-02-02 10:18:25,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-02 10:18:25,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 187 transitions. [2018-02-02 10:18:25,929 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 187 transitions. Word has length 64 [2018-02-02 10:18:25,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:25,929 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 187 transitions. [2018-02-02 10:18:25,929 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:18:25,930 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 187 transitions. [2018-02-02 10:18:25,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-02 10:18:25,930 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:25,930 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:25,930 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:25,931 INFO L82 PathProgramCache]: Analyzing trace with hash 1413269325, now seen corresponding path program 1 times [2018-02-02 10:18:25,931 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:25,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:25,946 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:25,994 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-02 10:18:25,995 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:18:25,995 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 10:18:25,995 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:25,995 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-02 10:18:25,995 INFO L182 omatonBuilderFactory]: Interpolants [4691#true, 4692#false, 4693#(= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|)), 4694#(= 1 (select |#valid| |ldv_zalloc_#res.base|)), 4695#(= 1 (select |#valid| |entry_point_#t~ret24.base|)), 4696#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 4697#(= 1 (select |#valid| |entry_point_#t~mem27.base|))] [2018-02-02 10:18:25,995 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-02 10:18:25,996 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 10:18:25,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 10:18:25,996 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 10:18:25,996 INFO L87 Difference]: Start difference. First operand 173 states and 187 transitions. Second operand 7 states. [2018-02-02 10:18:26,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:26,122 INFO L93 Difference]: Finished difference Result 172 states and 186 transitions. [2018-02-02 10:18:26,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 10:18:26,123 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2018-02-02 10:18:26,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:26,123 INFO L225 Difference]: With dead ends: 172 [2018-02-02 10:18:26,123 INFO L226 Difference]: Without dead ends: 172 [2018-02-02 10:18:26,124 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-02 10:18:26,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-02 10:18:26,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 172. [2018-02-02 10:18:26,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-02-02 10:18:26,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 186 transitions. [2018-02-02 10:18:26,126 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 186 transitions. Word has length 65 [2018-02-02 10:18:26,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:26,126 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 186 transitions. [2018-02-02 10:18:26,126 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 10:18:26,126 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 186 transitions. [2018-02-02 10:18:26,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-02 10:18:26,127 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:26,127 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:26,127 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:26,127 INFO L82 PathProgramCache]: Analyzing trace with hash 1413269326, now seen corresponding path program 1 times [2018-02-02 10:18:26,128 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:26,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:26,144 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:26,300 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 101 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-02-02 10:18:26,300 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:26,300 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 10:18:26,300 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:26,301 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-02 10:18:26,301 INFO L182 omatonBuilderFactory]: Interpolants [5056#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 5057#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 4 |#Ultimate.meminit_#t~loopctr33|) 5) (* 5 |#Ultimate.meminit_#product|)))), 5058#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 5 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 5059#(or (<= |ldv_zalloc_#in~size| 5) (<= 4294967296 |ldv_zalloc_#in~size|)), 5048#true, 5049#false, 5050#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 5051#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 5052#(= |#Ultimate.meminit_#t~loopctr33| 0), 5053#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 5054#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 5055#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-02 10:18:26,301 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 101 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-02-02 10:18:26,301 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 10:18:26,301 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 10:18:26,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2018-02-02 10:18:26,302 INFO L87 Difference]: Start difference. First operand 172 states and 186 transitions. Second operand 12 states. [2018-02-02 10:18:26,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:26,446 INFO L93 Difference]: Finished difference Result 178 states and 192 transitions. [2018-02-02 10:18:26,446 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 10:18:26,446 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 65 [2018-02-02 10:18:26,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:26,447 INFO L225 Difference]: With dead ends: 178 [2018-02-02 10:18:26,447 INFO L226 Difference]: Without dead ends: 173 [2018-02-02 10:18:26,448 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:18:26,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-02-02 10:18:26,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2018-02-02 10:18:26,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-02 10:18:26,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 187 transitions. [2018-02-02 10:18:26,452 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 187 transitions. Word has length 65 [2018-02-02 10:18:26,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:26,452 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 187 transitions. [2018-02-02 10:18:26,452 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 10:18:26,452 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 187 transitions. [2018-02-02 10:18:26,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-02-02 10:18:26,452 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:26,453 INFO L351 BasicCegarLoop]: trace histogram [18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:26,453 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:26,453 INFO L82 PathProgramCache]: Analyzing trace with hash 342744626, now seen corresponding path program 2 times [2018-02-02 10:18:26,454 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:26,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:26,477 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:26,688 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 0 proven. 133 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-02-02 10:18:26,688 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:26,688 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 10:18:26,688 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:26,688 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 10:18:26,689 INFO L182 omatonBuilderFactory]: Interpolants [5415#true, 5416#false, 5417#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 5418#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 5419#(= |#Ultimate.meminit_#t~loopctr33| 0), 5420#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 5421#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 5422#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 5423#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 5424#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 5425#(and (<= (+ (* 5 |#Ultimate.meminit_#t~loopctr33|) 6) (* 6 |#Ultimate.meminit_#product|)) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 5426#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 6 |#Ultimate.meminit_#sizeOfFields|))) (<= 6 |#Ultimate.meminit_#product|)), 5427#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 6))] [2018-02-02 10:18:26,689 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 0 proven. 133 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-02-02 10:18:26,689 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 10:18:26,689 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 10:18:26,689 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:18:26,689 INFO L87 Difference]: Start difference. First operand 173 states and 187 transitions. Second operand 13 states. [2018-02-02 10:18:26,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:26,812 INFO L93 Difference]: Finished difference Result 179 states and 193 transitions. [2018-02-02 10:18:26,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 10:18:26,813 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2018-02-02 10:18:26,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:26,813 INFO L225 Difference]: With dead ends: 179 [2018-02-02 10:18:26,814 INFO L226 Difference]: Without dead ends: 174 [2018-02-02 10:18:26,814 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-02-02 10:18:26,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-02 10:18:26,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-02 10:18:26,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-02 10:18:26,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-02 10:18:26,818 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 68 [2018-02-02 10:18:26,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:26,818 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-02 10:18:26,818 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 10:18:26,818 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-02 10:18:26,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-02-02 10:18:26,819 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:26,819 INFO L351 BasicCegarLoop]: trace histogram [21, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:26,819 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:26,820 INFO L82 PathProgramCache]: Analyzing trace with hash 1946516686, now seen corresponding path program 3 times [2018-02-02 10:18:26,820 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:26,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:26,838 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:27,038 INFO L134 CoverageAnalysis]: Checked inductivity of 303 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-02-02 10:18:27,038 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:27,038 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-02-02 10:18:27,041 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:27,041 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-02 10:18:27,041 INFO L182 omatonBuilderFactory]: Interpolants [5792#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 5793#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 5794#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 5795#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 5796#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (+ (* 6 |#Ultimate.meminit_#t~loopctr33|) 7) (* 7 |#Ultimate.meminit_#product|))), 5797#(and (<= 7 |#Ultimate.meminit_#product|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 5798#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 7)), 5785#true, 5786#false, 5787#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 5788#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 5789#(= |#Ultimate.meminit_#t~loopctr33| 0), 5790#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 5791#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-02 10:18:27,042 INFO L134 CoverageAnalysis]: Checked inductivity of 303 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-02-02 10:18:27,042 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 10:18:27,042 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 10:18:27,042 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=156, Unknown=0, NotChecked=0, Total=182 [2018-02-02 10:18:27,043 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 14 states. [2018-02-02 10:18:27,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:27,249 INFO L93 Difference]: Finished difference Result 180 states and 194 transitions. [2018-02-02 10:18:27,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-02 10:18:27,249 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-02-02 10:18:27,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:27,250 INFO L225 Difference]: With dead ends: 180 [2018-02-02 10:18:27,250 INFO L226 Difference]: Without dead ends: 175 [2018-02-02 10:18:27,250 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:18:27,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-02-02 10:18:27,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 175. [2018-02-02 10:18:27,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-02 10:18:27,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 189 transitions. [2018-02-02 10:18:27,255 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 189 transitions. Word has length 71 [2018-02-02 10:18:27,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:27,255 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 189 transitions. [2018-02-02 10:18:27,255 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 10:18:27,255 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 189 transitions. [2018-02-02 10:18:27,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-02 10:18:27,255 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:27,256 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:27,256 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:27,256 INFO L82 PathProgramCache]: Analyzing trace with hash 395214514, now seen corresponding path program 4 times [2018-02-02 10:18:27,257 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:27,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:27,278 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:27,541 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 174 proven. 36 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-02 10:18:27,541 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:27,542 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 10:18:27,542 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:27,542 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 10:18:27,542 INFO L182 omatonBuilderFactory]: Interpolants [6158#true, 6159#false, 6160#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6161#(= |#Ultimate.meminit_#t~loopctr33| 0), 6162#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 6163#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6164#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6165#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6166#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6167#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6168#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6169#(<= (+ (* 7 |#Ultimate.meminit_#t~loopctr33|) 8) (* 8 |#Ultimate.meminit_#product|)), 6170#(<= 8 |#Ultimate.meminit_#product|), 6171#(and (<= 8 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6172#(and (<= 8 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 6173#(and (= 0 |entry_point_#t~ret24.offset|) (<= 8 (select |#length| |entry_point_#t~ret24.base|))), 6174#(and (<= 8 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 6175#(and (= |entry_point_#t~mem27.offset| 0) (<= 8 (select |#length| |entry_point_#t~mem27.base|)))] [2018-02-02 10:18:27,543 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 174 proven. 36 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-02 10:18:27,543 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 10:18:27,543 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 10:18:27,543 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=273, Unknown=0, NotChecked=0, Total=306 [2018-02-02 10:18:27,543 INFO L87 Difference]: Start difference. First operand 175 states and 189 transitions. Second operand 18 states. [2018-02-02 10:18:27,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:27,895 INFO L93 Difference]: Finished difference Result 189 states and 207 transitions. [2018-02-02 10:18:27,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 10:18:27,896 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 74 [2018-02-02 10:18:27,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:27,896 INFO L225 Difference]: With dead ends: 189 [2018-02-02 10:18:27,896 INFO L226 Difference]: Without dead ends: 189 [2018-02-02 10:18:27,897 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=451, Unknown=0, NotChecked=0, Total=506 [2018-02-02 10:18:27,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-02-02 10:18:27,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 188. [2018-02-02 10:18:27,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-02-02 10:18:27,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 206 transitions. [2018-02-02 10:18:27,900 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 206 transitions. Word has length 74 [2018-02-02 10:18:27,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:27,900 INFO L432 AbstractCegarLoop]: Abstraction has 188 states and 206 transitions. [2018-02-02 10:18:27,900 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 10:18:27,900 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 206 transitions. [2018-02-02 10:18:27,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-02 10:18:27,901 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:27,901 INFO L351 BasicCegarLoop]: trace histogram [25, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:27,901 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:27,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1901565606, now seen corresponding path program 5 times [2018-02-02 10:18:27,902 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:27,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:27,920 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:28,146 INFO L134 CoverageAnalysis]: Checked inductivity of 405 backedges. 192 proven. 45 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-02 10:18:28,146 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:28,146 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 10:18:28,146 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:28,146 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 10:18:28,146 INFO L182 omatonBuilderFactory]: Interpolants [6563#true, 6564#false, 6565#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6566#(= |#Ultimate.meminit_#t~loopctr33| 0), 6567#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 6568#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6569#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6570#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6571#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6572#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6573#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6574#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6575#(<= (+ (* 8 |#Ultimate.meminit_#t~loopctr33|) 9) (* 9 |#Ultimate.meminit_#product|)), 6576#(<= 9 |#Ultimate.meminit_#product|), 6577#(and (<= 9 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6578#(and (<= 9 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 6579#(and (<= 9 (select |#length| |entry_point_#t~ret24.base|)) (= 0 |entry_point_#t~ret24.offset|)), 6580#(and (<= 9 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 6581#(and (= |entry_point_#t~mem27.offset| 0) (<= 9 (select |#length| |entry_point_#t~mem27.base|)))] [2018-02-02 10:18:28,147 INFO L134 CoverageAnalysis]: Checked inductivity of 405 backedges. 192 proven. 45 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-02 10:18:28,147 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 10:18:28,147 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 10:18:28,147 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=307, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:18:28,147 INFO L87 Difference]: Start difference. First operand 188 states and 206 transitions. Second operand 19 states. [2018-02-02 10:18:28,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:28,606 INFO L93 Difference]: Finished difference Result 202 states and 224 transitions. [2018-02-02 10:18:28,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-02 10:18:28,606 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 75 [2018-02-02 10:18:28,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:28,607 INFO L225 Difference]: With dead ends: 202 [2018-02-02 10:18:28,607 INFO L226 Difference]: Without dead ends: 202 [2018-02-02 10:18:28,608 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=495, Unknown=0, NotChecked=0, Total=552 [2018-02-02 10:18:28,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-02-02 10:18:28,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 189. [2018-02-02 10:18:28,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-02-02 10:18:28,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 208 transitions. [2018-02-02 10:18:28,612 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 208 transitions. Word has length 75 [2018-02-02 10:18:28,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:28,612 INFO L432 AbstractCegarLoop]: Abstraction has 189 states and 208 transitions. [2018-02-02 10:18:28,612 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 10:18:28,612 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 208 transitions. [2018-02-02 10:18:28,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-02-02 10:18:28,613 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:28,613 INFO L351 BasicCegarLoop]: trace histogram [28, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:28,613 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:28,613 INFO L82 PathProgramCache]: Analyzing trace with hash -781159886, now seen corresponding path program 6 times [2018-02-02 10:18:28,614 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:28,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:28,632 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:28,866 INFO L134 CoverageAnalysis]: Checked inductivity of 492 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 482 trivial. 0 not checked. [2018-02-02 10:18:28,867 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 10:18:28,867 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 10:18:28,867 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:28,867 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2018-02-02 10:18:28,867 INFO L182 omatonBuilderFactory]: Interpolants [6983#true, 6984#false, 6985#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 6986#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6987#(and (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6988#(and (= 0 |ldv_zalloc_#res.offset|) (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|)))), 6989#(and (<= 9 (select |#length| |entry_point_#t~ret24.base|)) (= 0 |entry_point_#t~ret24.offset|)), 6990#(and (<= 9 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 6991#(and (= |entry_point_#t~mem27.offset| 0) (<= 9 (select |#length| |entry_point_#t~mem27.base|)))] [2018-02-02 10:18:28,868 INFO L134 CoverageAnalysis]: Checked inductivity of 492 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 482 trivial. 0 not checked. [2018-02-02 10:18:28,868 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 10:18:28,868 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 10:18:28,868 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-02-02 10:18:28,868 INFO L87 Difference]: Start difference. First operand 189 states and 208 transitions. Second operand 9 states. [2018-02-02 10:18:29,108 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 51 DAG size of output 42 [2018-02-02 10:18:29,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:29,270 INFO L93 Difference]: Finished difference Result 188 states and 207 transitions. [2018-02-02 10:18:29,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 10:18:29,270 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 78 [2018-02-02 10:18:29,270 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:29,271 INFO L225 Difference]: With dead ends: 188 [2018-02-02 10:18:29,271 INFO L226 Difference]: Without dead ends: 188 [2018-02-02 10:18:29,272 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:18:29,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-02-02 10:18:29,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 174. [2018-02-02 10:18:29,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-02 10:18:29,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-02 10:18:29,275 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 78 [2018-02-02 10:18:29,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:29,276 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-02 10:18:29,276 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 10:18:29,276 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-02 10:18:29,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-02 10:18:29,276 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:29,277 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:29,277 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:29,277 INFO L82 PathProgramCache]: Analyzing trace with hash 1844027634, now seen corresponding path program 1 times [2018-02-02 10:18:29,278 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:29,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:29,304 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:29,460 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2018-02-02 10:18:29,461 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:29,461 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 10:18:29,461 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:29,461 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-02 10:18:29,462 INFO L182 omatonBuilderFactory]: Interpolants [7362#true, 7363#false, 7364#(= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|)), 7365#(= 1 (select |#valid| |ldv_zalloc_#res.base|)), 7366#(= 1 (select |#valid| |entry_point_#t~ret22.base|)), 7367#(= 1 (select |#valid| entry_point_~hdev~0.base)), 7368#(= |#valid| |old(#valid)|), 7369#(= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))), 7370#(and (or (= |ldv_zalloc_#res.base| (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 7371#(or (= entry_point_~hdev~0.base |entry_point_#t~ret23.base|) (= 1 (select |#valid| entry_point_~hdev~0.base))), 7372#(or (= entry_point_~hdev~0.base entry_point_~intf~2.base) (= 1 (select |#valid| entry_point_~hdev~0.base))), 7373#(and (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|))), 7374#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 10:18:29,462 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2018-02-02 10:18:29,462 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 10:18:29,462 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 10:18:29,462 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-02 10:18:29,463 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 13 states. [2018-02-02 10:18:29,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:29,849 INFO L93 Difference]: Finished difference Result 183 states and 198 transitions. [2018-02-02 10:18:29,850 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 10:18:29,850 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 76 [2018-02-02 10:18:29,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:29,850 INFO L225 Difference]: With dead ends: 183 [2018-02-02 10:18:29,850 INFO L226 Difference]: Without dead ends: 183 [2018-02-02 10:18:29,851 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=191, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:18:29,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-02-02 10:18:29,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 173. [2018-02-02 10:18:29,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-02 10:18:29,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 187 transitions. [2018-02-02 10:18:29,854 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 187 transitions. Word has length 76 [2018-02-02 10:18:29,854 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:29,855 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 187 transitions. [2018-02-02 10:18:29,855 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 10:18:29,855 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 187 transitions. [2018-02-02 10:18:29,855 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-02 10:18:29,855 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:29,855 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:29,855 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:29,855 INFO L82 PathProgramCache]: Analyzing trace with hash 1844027635, now seen corresponding path program 1 times [2018-02-02 10:18:29,856 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:29,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:29,878 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:30,112 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 166 trivial. 0 not checked. [2018-02-02 10:18:30,112 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:30,113 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 10:18:30,113 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:30,113 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 10:18:30,113 INFO L182 omatonBuilderFactory]: Interpolants [7744#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 7745#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 7746#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 7747#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 7748#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 7749#(and (<= (+ (* 7 |#Ultimate.meminit_#t~loopctr33|) 8) (* 8 |#Ultimate.meminit_#product|)) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)))), 7750#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 8 |#Ultimate.meminit_#sizeOfFields|))) (<= 8 |#Ultimate.meminit_#product|)), 7751#(or (<= |ldv_zalloc_#in~size| 8) (<= 4294967296 |ldv_zalloc_#in~size|)), 7737#true, 7738#false, 7739#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 7740#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 7741#(= |#Ultimate.meminit_#t~loopctr33| 0), 7742#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 7743#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-02 10:18:30,114 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 166 trivial. 0 not checked. [2018-02-02 10:18:30,114 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 10:18:30,114 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 10:18:30,114 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=182, Unknown=0, NotChecked=0, Total=210 [2018-02-02 10:18:30,114 INFO L87 Difference]: Start difference. First operand 173 states and 187 transitions. Second operand 15 states. [2018-02-02 10:18:30,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:30,263 INFO L93 Difference]: Finished difference Result 179 states and 193 transitions. [2018-02-02 10:18:30,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-02 10:18:30,263 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 76 [2018-02-02 10:18:30,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:30,264 INFO L225 Difference]: With dead ends: 179 [2018-02-02 10:18:30,264 INFO L226 Difference]: Without dead ends: 174 [2018-02-02 10:18:30,264 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-02-02 10:18:30,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-02 10:18:30,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-02 10:18:30,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-02 10:18:30,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-02 10:18:30,267 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 76 [2018-02-02 10:18:30,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:30,268 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-02 10:18:30,268 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 10:18:30,268 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-02 10:18:30,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-02-02 10:18:30,268 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:30,268 INFO L351 BasicCegarLoop]: trace histogram [27, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:30,268 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:30,269 INFO L82 PathProgramCache]: Analyzing trace with hash 10632591, now seen corresponding path program 2 times [2018-02-02 10:18:30,269 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:30,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:30,319 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:30,550 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 107 proven. 152 refuted. 0 times theorem prover too weak. 203 trivial. 0 not checked. [2018-02-02 10:18:30,550 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:30,550 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 10:18:30,550 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:30,550 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 17 proven. 17 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-02-02 10:18:30,551 INFO L182 omatonBuilderFactory]: Interpolants [8109#true, 8110#false, 8111#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 8112#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 8113#(= |#Ultimate.meminit_#t~loopctr33| 0), 8114#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 8115#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8116#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 8117#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 8118#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 8119#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8120#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 8121#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8122#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 8 |#Ultimate.meminit_#t~loopctr33|) 9) (* 9 |#Ultimate.meminit_#product|)))), 8123#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 9 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 9 |#Ultimate.meminit_#sizeOfFields|)))), 8124#(or (<= |ldv_zalloc_#in~size| 9) (<= 4294967296 |ldv_zalloc_#in~size|))] [2018-02-02 10:18:30,551 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 107 proven. 152 refuted. 0 times theorem prover too weak. 203 trivial. 0 not checked. [2018-02-02 10:18:30,551 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 10:18:30,551 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 10:18:30,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=210, Unknown=0, NotChecked=0, Total=240 [2018-02-02 10:18:30,552 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 16 states. [2018-02-02 10:18:30,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:30,768 INFO L93 Difference]: Finished difference Result 183 states and 199 transitions. [2018-02-02 10:18:30,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 10:18:30,770 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 79 [2018-02-02 10:18:30,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:30,771 INFO L225 Difference]: With dead ends: 183 [2018-02-02 10:18:30,771 INFO L226 Difference]: Without dead ends: 183 [2018-02-02 10:18:30,771 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2018-02-02 10:18:30,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-02-02 10:18:30,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 183. [2018-02-02 10:18:30,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-02-02 10:18:30,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 199 transitions. [2018-02-02 10:18:30,777 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 199 transitions. Word has length 79 [2018-02-02 10:18:30,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:30,777 INFO L432 AbstractCegarLoop]: Abstraction has 183 states and 199 transitions. [2018-02-02 10:18:30,777 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 10:18:30,777 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 199 transitions. [2018-02-02 10:18:30,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-02 10:18:30,778 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:30,778 INFO L351 BasicCegarLoop]: trace histogram [29, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:30,778 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:30,778 INFO L82 PathProgramCache]: Analyzing trace with hash 826541595, now seen corresponding path program 3 times [2018-02-02 10:18:30,779 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:30,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:30,821 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:31,155 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 223 trivial. 0 not checked. [2018-02-02 10:18:31,155 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:31,155 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 10:18:31,156 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:31,156 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:31,158 INFO L182 omatonBuilderFactory]: Interpolants [8495#true, 8496#false, 8497#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 8498#(or (and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))) (and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))), 8499#(= |#Ultimate.meminit_#t~loopctr33| 0), 8500#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 8501#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8502#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 8503#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 8504#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 8505#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8506#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 8507#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8508#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8509#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 9 |#Ultimate.meminit_#t~loopctr33|) 10) (* 10 |#Ultimate.meminit_#product|)))), 8510#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 10 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 8511#(or (<= 2147483648 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 10))] [2018-02-02 10:18:31,159 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 223 trivial. 0 not checked. [2018-02-02 10:18:31,159 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 10:18:31,159 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 10:18:31,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=240, Unknown=0, NotChecked=0, Total=272 [2018-02-02 10:18:31,160 INFO L87 Difference]: Start difference. First operand 183 states and 199 transitions. Second operand 17 states. [2018-02-02 10:18:31,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:31,434 INFO L93 Difference]: Finished difference Result 192 states and 208 transitions. [2018-02-02 10:18:31,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 10:18:31,434 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 81 [2018-02-02 10:18:31,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:31,435 INFO L225 Difference]: With dead ends: 192 [2018-02-02 10:18:31,436 INFO L226 Difference]: Without dead ends: 186 [2018-02-02 10:18:31,436 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=301, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:18:31,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-02-02 10:18:31,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 184. [2018-02-02 10:18:31,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-02-02 10:18:31,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 200 transitions. [2018-02-02 10:18:31,441 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 200 transitions. Word has length 81 [2018-02-02 10:18:31,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:31,441 INFO L432 AbstractCegarLoop]: Abstraction has 184 states and 200 transitions. [2018-02-02 10:18:31,441 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 10:18:31,442 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 200 transitions. [2018-02-02 10:18:31,442 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-02 10:18:31,442 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:31,442 INFO L351 BasicCegarLoop]: trace histogram [31, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:31,442 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:31,444 INFO L82 PathProgramCache]: Analyzing trace with hash 132830479, now seen corresponding path program 4 times [2018-02-02 10:18:31,447 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:31,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:31,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:31,769 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 0 proven. 344 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2018-02-02 10:18:31,769 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:31,769 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 10:18:31,769 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:31,770 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:31,770 INFO L182 omatonBuilderFactory]: Interpolants [8896#(= |#Ultimate.meminit_#t~loopctr33| 0), 8897#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 8898#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 8899#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 8900#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 8901#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 8902#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 8903#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 8904#(and (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)))), 8905#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 8906#(and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 8907#(and (<= (+ (* 10 |#Ultimate.meminit_#t~loopctr33|) 11) (* 11 |#Ultimate.meminit_#product|)) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 8908#(and (<= 11 |#Ultimate.meminit_#product|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 8909#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 11)), 8892#true, 8893#false, 8894#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 8895#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)))] [2018-02-02 10:18:31,771 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 0 proven. 344 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2018-02-02 10:18:31,771 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 10:18:31,771 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 10:18:31,771 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=272, Unknown=0, NotChecked=0, Total=306 [2018-02-02 10:18:31,771 INFO L87 Difference]: Start difference. First operand 184 states and 200 transitions. Second operand 18 states. [2018-02-02 10:18:32,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:32,078 INFO L93 Difference]: Finished difference Result 192 states and 209 transitions. [2018-02-02 10:18:32,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 10:18:32,079 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 83 [2018-02-02 10:18:32,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:32,080 INFO L225 Difference]: With dead ends: 192 [2018-02-02 10:18:32,081 INFO L226 Difference]: Without dead ends: 189 [2018-02-02 10:18:32,081 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=43, Invalid=337, Unknown=0, NotChecked=0, Total=380 [2018-02-02 10:18:32,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-02-02 10:18:32,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 185. [2018-02-02 10:18:32,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-02-02 10:18:32,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 202 transitions. [2018-02-02 10:18:32,086 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 202 transitions. Word has length 83 [2018-02-02 10:18:32,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:32,086 INFO L432 AbstractCegarLoop]: Abstraction has 185 states and 202 transitions. [2018-02-02 10:18:32,086 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 10:18:32,086 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 202 transitions. [2018-02-02 10:18:32,087 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-02 10:18:32,087 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:32,087 INFO L351 BasicCegarLoop]: trace histogram [33, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:32,087 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:32,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1935927963, now seen corresponding path program 5 times [2018-02-02 10:18:32,088 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:32,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:32,122 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:32,670 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 4 proven. 393 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2018-02-02 10:18:32,670 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:32,670 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 10:18:32,670 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:32,670 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 2 proven. 29 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:32,670 INFO L182 omatonBuilderFactory]: Interpolants [9291#true, 9292#false, 9293#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 9294#(= |#Ultimate.meminit_#t~loopctr33| 0), 9295#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 9296#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9297#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9298#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9299#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9300#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9301#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9302#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9303#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9304#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9305#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9306#(<= (+ (* 11 |#Ultimate.meminit_#t~loopctr33|) 12) (* 12 |#Ultimate.meminit_#product|)), 9307#(<= 12 |#Ultimate.meminit_#product|), 9308#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 12 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 9309#(and (<= 12 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 9310#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 12 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 9311#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 9312#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 9313#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 9314#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 9315#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 9316#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 9317#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-02 10:18:32,671 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 4 proven. 393 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2018-02-02 10:18:32,671 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 10:18:32,671 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 10:18:32,671 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=643, Unknown=0, NotChecked=0, Total=702 [2018-02-02 10:18:32,672 INFO L87 Difference]: Start difference. First operand 185 states and 202 transitions. Second operand 27 states. [2018-02-02 10:18:34,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:34,506 INFO L93 Difference]: Finished difference Result 243 states and 278 transitions. [2018-02-02 10:18:34,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 10:18:34,506 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 85 [2018-02-02 10:18:34,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:34,507 INFO L225 Difference]: With dead ends: 243 [2018-02-02 10:18:34,507 INFO L226 Difference]: Without dead ends: 243 [2018-02-02 10:18:34,508 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=183, Invalid=1887, Unknown=0, NotChecked=0, Total=2070 [2018-02-02 10:18:34,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-02-02 10:18:34,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 206. [2018-02-02 10:18:34,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-02-02 10:18:34,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 230 transitions. [2018-02-02 10:18:34,512 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 230 transitions. Word has length 85 [2018-02-02 10:18:34,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:34,512 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 230 transitions. [2018-02-02 10:18:34,512 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 10:18:34,512 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 230 transitions. [2018-02-02 10:18:34,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-02 10:18:34,513 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:34,513 INFO L351 BasicCegarLoop]: trace histogram [35, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:34,513 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:34,513 INFO L82 PathProgramCache]: Analyzing trace with hash -1427501937, now seen corresponding path program 6 times [2018-02-02 10:18:34,513 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:34,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:34,546 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:34,923 INFO L134 CoverageAnalysis]: Checked inductivity of 730 backedges. 203 proven. 238 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-02 10:18:34,923 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:34,923 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 10:18:34,923 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:34,923 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 21 proven. 10 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 10:18:34,924 INFO L182 omatonBuilderFactory]: Interpolants [9824#(or (<= |ldv_zalloc_#in~size| 13) (<= 4294967296 |ldv_zalloc_#in~size|)), 9805#true, 9806#false, 9807#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 9808#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 9809#(= |#Ultimate.meminit_#t~loopctr33| 0), 9810#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 9811#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9812#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 9813#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 9814#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 9815#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9816#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 9817#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9818#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9819#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 9820#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 9821#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 9822#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (+ (* 12 |#Ultimate.meminit_#t~loopctr33|) 13) (* 13 |#Ultimate.meminit_#product|)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|)))), 9823#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 13 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 13 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-02 10:18:34,924 INFO L134 CoverageAnalysis]: Checked inductivity of 730 backedges. 203 proven. 238 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-02 10:18:34,924 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 10:18:34,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 10:18:34,925 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=342, Unknown=0, NotChecked=0, Total=380 [2018-02-02 10:18:34,925 INFO L87 Difference]: Start difference. First operand 206 states and 230 transitions. Second operand 20 states. [2018-02-02 10:18:35,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:35,297 INFO L93 Difference]: Finished difference Result 222 states and 249 transitions. [2018-02-02 10:18:35,297 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 10:18:35,297 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 87 [2018-02-02 10:18:35,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:35,298 INFO L225 Difference]: With dead ends: 222 [2018-02-02 10:18:35,298 INFO L226 Difference]: Without dead ends: 222 [2018-02-02 10:18:35,299 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=47, Invalid=415, Unknown=0, NotChecked=0, Total=462 [2018-02-02 10:18:35,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-02-02 10:18:35,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 215. [2018-02-02 10:18:35,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-02-02 10:18:35,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 241 transitions. [2018-02-02 10:18:35,303 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 241 transitions. Word has length 87 [2018-02-02 10:18:35,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:35,304 INFO L432 AbstractCegarLoop]: Abstraction has 215 states and 241 transitions. [2018-02-02 10:18:35,304 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 10:18:35,304 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 241 transitions. [2018-02-02 10:18:35,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-02-02 10:18:35,307 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:35,307 INFO L351 BasicCegarLoop]: trace histogram [34, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:35,307 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:35,307 INFO L82 PathProgramCache]: Analyzing trace with hash -586112205, now seen corresponding path program 7 times [2018-02-02 10:18:35,308 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:35,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:35,349 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:35,653 INFO L134 CoverageAnalysis]: Checked inductivity of 693 backedges. 189 proven. 215 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-02 10:18:35,653 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:35,653 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 10:18:35,653 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:35,654 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:35,654 INFO L182 omatonBuilderFactory]: Interpolants [10272#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10273#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 10274#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 10275#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 10276#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10277#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 10278#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10279#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10280#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 10281#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 10282#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (+ (* 11 |#Ultimate.meminit_#t~loopctr33|) 12) (* 12 |#Ultimate.meminit_#product|)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 10283#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#product| (* 12 |#Ultimate.meminit_#sizeOfFields|)) (<= 12 |#Ultimate.meminit_#product|))), 10284#(or (<= |ldv_zalloc_#in~size| 12) (<= 4294967296 |ldv_zalloc_#in~size|)), 10266#true, 10267#false, 10268#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 10269#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 10270#(= |#Ultimate.meminit_#t~loopctr33| 0), 10271#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1)))] [2018-02-02 10:18:35,654 INFO L134 CoverageAnalysis]: Checked inductivity of 693 backedges. 189 proven. 215 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-02 10:18:35,655 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 10:18:35,655 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 10:18:35,655 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=306, Unknown=0, NotChecked=0, Total=342 [2018-02-02 10:18:35,655 INFO L87 Difference]: Start difference. First operand 215 states and 241 transitions. Second operand 19 states. [2018-02-02 10:18:36,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:36,054 INFO L93 Difference]: Finished difference Result 225 states and 249 transitions. [2018-02-02 10:18:36,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 10:18:36,054 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 86 [2018-02-02 10:18:36,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:36,055 INFO L225 Difference]: With dead ends: 225 [2018-02-02 10:18:36,055 INFO L226 Difference]: Without dead ends: 219 [2018-02-02 10:18:36,055 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=375, Unknown=0, NotChecked=0, Total=420 [2018-02-02 10:18:36,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-02-02 10:18:36,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 215. [2018-02-02 10:18:36,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-02-02 10:18:36,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 239 transitions. [2018-02-02 10:18:36,059 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 239 transitions. Word has length 86 [2018-02-02 10:18:36,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:36,059 INFO L432 AbstractCegarLoop]: Abstraction has 215 states and 239 transitions. [2018-02-02 10:18:36,059 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 10:18:36,060 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 239 transitions. [2018-02-02 10:18:36,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-02-02 10:18:36,060 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:36,060 INFO L351 BasicCegarLoop]: trace histogram [36, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:36,060 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:36,060 INFO L82 PathProgramCache]: Analyzing trace with hash -1740779853, now seen corresponding path program 8 times [2018-02-02 10:18:36,061 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:36,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:36,128 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:36,380 INFO L134 CoverageAnalysis]: Checked inductivity of 768 backedges. 0 proven. 455 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-02 10:18:36,380 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:36,380 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 10:18:36,380 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:36,381 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:36,381 INFO L182 omatonBuilderFactory]: Interpolants [10729#true, 10730#false, 10731#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 10732#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 10733#(= |#Ultimate.meminit_#t~loopctr33| 0), 10734#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 10735#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10736#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10737#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10738#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10739#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10740#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10741#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10742#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10743#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10744#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10745#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10746#(<= (+ (* 12 |#Ultimate.meminit_#t~loopctr33|) 13) (* 13 |#Ultimate.meminit_#product|)), 10747#(<= 13 |#Ultimate.meminit_#product|), 10748#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 13 |ldv_zalloc_#in~size|))] [2018-02-02 10:18:36,381 INFO L134 CoverageAnalysis]: Checked inductivity of 768 backedges. 0 proven. 455 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-02 10:18:36,381 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 10:18:36,382 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 10:18:36,382 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=342, Unknown=0, NotChecked=0, Total=380 [2018-02-02 10:18:36,382 INFO L87 Difference]: Start difference. First operand 215 states and 239 transitions. Second operand 20 states. [2018-02-02 10:18:36,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:36,878 INFO L93 Difference]: Finished difference Result 225 states and 247 transitions. [2018-02-02 10:18:36,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 10:18:36,880 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 88 [2018-02-02 10:18:36,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:36,881 INFO L225 Difference]: With dead ends: 225 [2018-02-02 10:18:36,881 INFO L226 Difference]: Without dead ends: 217 [2018-02-02 10:18:36,881 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=47, Invalid=415, Unknown=0, NotChecked=0, Total=462 [2018-02-02 10:18:36,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-02-02 10:18:36,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 213. [2018-02-02 10:18:36,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-02-02 10:18:36,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 235 transitions. [2018-02-02 10:18:36,886 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 235 transitions. Word has length 88 [2018-02-02 10:18:36,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:36,886 INFO L432 AbstractCegarLoop]: Abstraction has 213 states and 235 transitions. [2018-02-02 10:18:36,886 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 10:18:36,886 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 235 transitions. [2018-02-02 10:18:36,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-02 10:18:36,886 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:36,887 INFO L351 BasicCegarLoop]: trace histogram [37, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:36,887 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:36,887 INFO L82 PathProgramCache]: Analyzing trace with hash 318451483, now seen corresponding path program 9 times [2018-02-02 10:18:36,887 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:36,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:36,923 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:37,294 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 232 proven. 262 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-02 10:18:37,294 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:37,294 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 10:18:37,294 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:37,295 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:37,295 INFO L182 omatonBuilderFactory]: Interpolants [11200#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 11201#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11202#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 11203#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11204#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11205#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 11206#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 11207#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 11208#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|)))), 11209#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (+ (* 13 |#Ultimate.meminit_#t~loopctr33|) 14) (* 14 |#Ultimate.meminit_#product|)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|)))), 11210#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#product| (* 14 |#Ultimate.meminit_#sizeOfFields|)) (<= 14 |#Ultimate.meminit_#product|))), 11211#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 14)), 11191#true, 11192#false, 11193#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 11194#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 11195#(= |#Ultimate.meminit_#t~loopctr33| 0), 11196#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 11197#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11198#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 11199#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-02 10:18:37,295 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 232 proven. 262 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-02 10:18:37,295 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 10:18:37,296 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 10:18:37,296 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=380, Unknown=0, NotChecked=0, Total=420 [2018-02-02 10:18:37,296 INFO L87 Difference]: Start difference. First operand 213 states and 235 transitions. Second operand 21 states. [2018-02-02 10:18:37,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:37,700 INFO L93 Difference]: Finished difference Result 223 states and 247 transitions. [2018-02-02 10:18:37,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-02 10:18:37,701 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 89 [2018-02-02 10:18:37,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:37,701 INFO L225 Difference]: With dead ends: 223 [2018-02-02 10:18:37,702 INFO L226 Difference]: Without dead ends: 220 [2018-02-02 10:18:37,702 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=49, Invalid=457, Unknown=0, NotChecked=0, Total=506 [2018-02-02 10:18:37,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-02-02 10:18:37,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 216. [2018-02-02 10:18:37,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-02-02 10:18:37,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 240 transitions. [2018-02-02 10:18:37,706 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 240 transitions. Word has length 89 [2018-02-02 10:18:37,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:37,706 INFO L432 AbstractCegarLoop]: Abstraction has 216 states and 240 transitions. [2018-02-02 10:18:37,707 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 10:18:37,707 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 240 transitions. [2018-02-02 10:18:37,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-02 10:18:37,707 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:37,707 INFO L351 BasicCegarLoop]: trace histogram [38, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:37,708 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:37,708 INFO L82 PathProgramCache]: Analyzing trace with hash 844168615, now seen corresponding path program 10 times [2018-02-02 10:18:37,708 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:37,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:37,749 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:38,324 INFO L134 CoverageAnalysis]: Checked inductivity of 847 backedges. 4 proven. 511 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:38,324 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:38,324 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-02 10:18:38,324 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:38,325 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:38,325 INFO L182 omatonBuilderFactory]: Interpolants [11655#true, 11656#false, 11657#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 11658#(= |#Ultimate.meminit_#t~loopctr33| 0), 11659#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 11660#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11661#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11662#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11663#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11664#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11665#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11666#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11667#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11668#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11669#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11670#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11671#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11672#(<= (+ (* 13 |#Ultimate.meminit_#t~loopctr33|) 14) (* 14 |#Ultimate.meminit_#product|)), 11673#(<= 14 |#Ultimate.meminit_#product|), 11674#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 14 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 11675#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 14 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 11676#(and (<= 14 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 11677#(and (<= 14 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 11678#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 11679#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 11680#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 11681#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 11682#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 11683#(and (<= 14 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-02 10:18:38,325 INFO L134 CoverageAnalysis]: Checked inductivity of 847 backedges. 4 proven. 511 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:38,325 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-02 10:18:38,325 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-02 10:18:38,326 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=749, Unknown=0, NotChecked=0, Total=812 [2018-02-02 10:18:38,326 INFO L87 Difference]: Start difference. First operand 216 states and 240 transitions. Second operand 29 states. [2018-02-02 10:18:40,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:40,244 INFO L93 Difference]: Finished difference Result 271 states and 310 transitions. [2018-02-02 10:18:40,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 10:18:40,244 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 90 [2018-02-02 10:18:40,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:40,245 INFO L225 Difference]: With dead ends: 271 [2018-02-02 10:18:40,245 INFO L226 Difference]: Without dead ends: 271 [2018-02-02 10:18:40,246 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 210 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=199, Invalid=2251, Unknown=0, NotChecked=0, Total=2450 [2018-02-02 10:18:40,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-02-02 10:18:40,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 214. [2018-02-02 10:18:40,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-02-02 10:18:40,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 237 transitions. [2018-02-02 10:18:40,250 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 237 transitions. Word has length 90 [2018-02-02 10:18:40,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:40,250 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 237 transitions. [2018-02-02 10:18:40,250 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-02 10:18:40,250 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 237 transitions. [2018-02-02 10:18:40,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-02-02 10:18:40,251 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:40,251 INFO L351 BasicCegarLoop]: trace histogram [39, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:40,251 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:40,251 INFO L82 PathProgramCache]: Analyzing trace with hash -214440945, now seen corresponding path program 11 times [2018-02-02 10:18:40,252 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:40,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:40,279 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:40,771 INFO L134 CoverageAnalysis]: Checked inductivity of 888 backedges. 4 proven. 552 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:40,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:40,772 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 10:18:40,772 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:40,772 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:40,772 INFO L182 omatonBuilderFactory]: Interpolants [12224#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12225#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12226#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12227#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12228#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12229#(<= (+ (* 14 |#Ultimate.meminit_#t~loopctr33|) 15) (* 15 |#Ultimate.meminit_#product|)), 12230#(<= 15 |#Ultimate.meminit_#product|), 12231#(and (<= 15 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 12232#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 15 (select |#length| |ldv_zalloc_#res.base|))), 12233#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 15 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 12234#(and (<= 15 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 12235#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 12236#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 12237#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 12238#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 12239#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 12240#(and (<= 15 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 12211#true, 12212#false, 12213#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 12214#(= |#Ultimate.meminit_#t~loopctr33| 0), 12215#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 12216#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12217#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12218#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12219#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12220#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12221#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12222#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12223#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-02 10:18:40,772 INFO L134 CoverageAnalysis]: Checked inductivity of 888 backedges. 4 proven. 552 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:40,773 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 10:18:40,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 10:18:40,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=805, Unknown=0, NotChecked=0, Total=870 [2018-02-02 10:18:40,773 INFO L87 Difference]: Start difference. First operand 214 states and 237 transitions. Second operand 30 states. [2018-02-02 10:18:42,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:42,706 INFO L93 Difference]: Finished difference Result 277 states and 321 transitions. [2018-02-02 10:18:42,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 10:18:42,706 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 91 [2018-02-02 10:18:42,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:42,707 INFO L225 Difference]: With dead ends: 277 [2018-02-02 10:18:42,707 INFO L226 Difference]: Without dead ends: 277 [2018-02-02 10:18:42,707 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=207, Invalid=2445, Unknown=0, NotChecked=0, Total=2652 [2018-02-02 10:18:42,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-02-02 10:18:42,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 217. [2018-02-02 10:18:42,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-02-02 10:18:42,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 243 transitions. [2018-02-02 10:18:42,712 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 243 transitions. Word has length 91 [2018-02-02 10:18:42,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:42,713 INFO L432 AbstractCegarLoop]: Abstraction has 217 states and 243 transitions. [2018-02-02 10:18:42,713 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 10:18:42,713 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 243 transitions. [2018-02-02 10:18:42,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-02 10:18:42,714 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:42,714 INFO L351 BasicCegarLoop]: trace histogram [40, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:42,714 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:42,714 INFO L82 PathProgramCache]: Analyzing trace with hash 1328401063, now seen corresponding path program 12 times [2018-02-02 10:18:42,715 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:42,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:42,756 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:43,032 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 592 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-02 10:18:43,032 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:43,033 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 10:18:43,033 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:43,033 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:43,033 INFO L182 omatonBuilderFactory]: Interpolants [12800#(<= 16 |#Ultimate.meminit_#product|), 12801#(or (<= 16 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0)), 12779#true, 12780#false, 12781#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 12782#(and (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)) (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1)))), 12783#(= |#Ultimate.meminit_#t~loopctr33| 0), 12784#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 12785#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12786#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12787#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12788#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12789#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12790#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12791#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12792#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12793#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12794#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12795#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12796#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12797#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12798#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12799#(<= (+ (* 15 |#Ultimate.meminit_#t~loopctr33|) 16) (* 16 |#Ultimate.meminit_#product|))] [2018-02-02 10:18:43,034 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 592 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-02 10:18:43,034 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-02 10:18:43,034 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-02 10:18:43,034 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=462, Unknown=0, NotChecked=0, Total=506 [2018-02-02 10:18:43,035 INFO L87 Difference]: Start difference. First operand 217 states and 243 transitions. Second operand 23 states. [2018-02-02 10:18:43,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:43,432 INFO L93 Difference]: Finished difference Result 232 states and 260 transitions. [2018-02-02 10:18:43,432 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 10:18:43,432 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 92 [2018-02-02 10:18:43,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:43,433 INFO L225 Difference]: With dead ends: 232 [2018-02-02 10:18:43,433 INFO L226 Difference]: Without dead ends: 226 [2018-02-02 10:18:43,433 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=547, Unknown=0, NotChecked=0, Total=600 [2018-02-02 10:18:43,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-02-02 10:18:43,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 220. [2018-02-02 10:18:43,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-02-02 10:18:43,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 247 transitions. [2018-02-02 10:18:43,437 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 247 transitions. Word has length 92 [2018-02-02 10:18:43,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:43,437 INFO L432 AbstractCegarLoop]: Abstraction has 220 states and 247 transitions. [2018-02-02 10:18:43,437 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-02 10:18:43,437 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 247 transitions. [2018-02-02 10:18:43,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-02 10:18:43,438 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:43,438 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:43,438 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:43,438 INFO L82 PathProgramCache]: Analyzing trace with hash 1911863055, now seen corresponding path program 13 times [2018-02-02 10:18:43,439 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:43,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:43,475 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:44,138 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 4 proven. 637 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:44,139 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:44,139 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-02 10:18:44,139 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:44,139 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:44,139 INFO L182 omatonBuilderFactory]: Interpolants [13258#true, 13259#false, 13260#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13261#(= |#Ultimate.meminit_#t~loopctr33| 0), 13262#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 13263#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13264#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13265#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13266#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13267#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13268#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13269#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13270#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13271#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13272#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13273#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13274#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13275#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13276#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13277#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13278#(<= (+ (* 16 |#Ultimate.meminit_#t~loopctr33|) 17) (* 17 |#Ultimate.meminit_#product|)), 13279#(<= 17 |#Ultimate.meminit_#product|), 13280#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 17 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13281#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 17 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 13282#(and (<= 17 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 13283#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 17 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 13284#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 13285#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13286#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 13287#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13288#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 13289#(and (= entry_point_~hdev~0.offset 0) (<= 17 (select |#length| entry_point_~hdev~0.base)))] [2018-02-02 10:18:44,139 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 4 proven. 637 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:44,140 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-02 10:18:44,140 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-02 10:18:44,140 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=923, Unknown=0, NotChecked=0, Total=992 [2018-02-02 10:18:44,140 INFO L87 Difference]: Start difference. First operand 220 states and 247 transitions. Second operand 32 states. [2018-02-02 10:18:46,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:46,334 INFO L93 Difference]: Finished difference Result 283 states and 331 transitions. [2018-02-02 10:18:46,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-02 10:18:46,334 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 93 [2018-02-02 10:18:46,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:46,335 INFO L225 Difference]: With dead ends: 283 [2018-02-02 10:18:46,335 INFO L226 Difference]: Without dead ends: 283 [2018-02-02 10:18:46,335 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 276 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=223, Invalid=2857, Unknown=0, NotChecked=0, Total=3080 [2018-02-02 10:18:46,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283 states. [2018-02-02 10:18:46,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283 to 221. [2018-02-02 10:18:46,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-02-02 10:18:46,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 249 transitions. [2018-02-02 10:18:46,338 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 249 transitions. Word has length 93 [2018-02-02 10:18:46,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:46,339 INFO L432 AbstractCegarLoop]: Abstraction has 221 states and 249 transitions. [2018-02-02 10:18:46,339 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-02 10:18:46,339 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 249 transitions. [2018-02-02 10:18:46,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-02-02 10:18:46,340 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:46,340 INFO L351 BasicCegarLoop]: trace histogram [42, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:46,340 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:46,340 INFO L82 PathProgramCache]: Analyzing trace with hash -1475651673, now seen corresponding path program 14 times [2018-02-02 10:18:46,341 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:46,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:46,385 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:47,076 INFO L134 CoverageAnalysis]: Checked inductivity of 1017 backedges. 4 proven. 681 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:47,077 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:47,077 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-02 10:18:47,077 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:47,077 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:47,077 INFO L182 omatonBuilderFactory]: Interpolants [13842#true, 13843#false, 13844#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13845#(= |#Ultimate.meminit_#t~loopctr33| 0), 13846#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 13847#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13848#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13849#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13850#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13851#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13852#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13853#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13854#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13855#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13856#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13857#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13858#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13859#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13860#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13861#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13862#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13863#(<= (+ (* 17 |#Ultimate.meminit_#t~loopctr33|) 18) (* 18 |#Ultimate.meminit_#product|)), 13864#(<= 18 |#Ultimate.meminit_#product|), 13865#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 18 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13866#(and (<= 18 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 13867#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 18 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 13868#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 18 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 13869#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 13870#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13871#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 13872#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13873#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 13874#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-02 10:18:47,077 INFO L134 CoverageAnalysis]: Checked inductivity of 1017 backedges. 4 proven. 681 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:47,078 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-02 10:18:47,078 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-02 10:18:47,078 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=985, Unknown=0, NotChecked=0, Total=1056 [2018-02-02 10:18:47,078 INFO L87 Difference]: Start difference. First operand 221 states and 249 transitions. Second operand 33 states. [2018-02-02 10:18:49,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:49,465 INFO L93 Difference]: Finished difference Result 286 states and 337 transitions. [2018-02-02 10:18:49,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 10:18:49,465 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 94 [2018-02-02 10:18:49,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:49,466 INFO L225 Difference]: With dead ends: 286 [2018-02-02 10:18:49,466 INFO L226 Difference]: Without dead ends: 286 [2018-02-02 10:18:49,467 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 300 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=231, Invalid=3075, Unknown=0, NotChecked=0, Total=3306 [2018-02-02 10:18:49,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2018-02-02 10:18:49,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 222. [2018-02-02 10:18:49,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-02-02 10:18:49,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 251 transitions. [2018-02-02 10:18:49,471 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 251 transitions. Word has length 94 [2018-02-02 10:18:49,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:49,471 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 251 transitions. [2018-02-02 10:18:49,471 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-02 10:18:49,471 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 251 transitions. [2018-02-02 10:18:49,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-02-02 10:18:49,472 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:49,472 INFO L351 BasicCegarLoop]: trace histogram [43, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:49,472 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:49,472 INFO L82 PathProgramCache]: Analyzing trace with hash 885574159, now seen corresponding path program 15 times [2018-02-02 10:18:49,472 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:49,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:49,503 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:50,132 INFO L134 CoverageAnalysis]: Checked inductivity of 1062 backedges. 4 proven. 726 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:50,132 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:50,132 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-02-02 10:18:50,132 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:50,133 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:50,133 INFO L182 omatonBuilderFactory]: Interpolants [14464#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 14465#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 14466#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 14433#true, 14434#false, 14435#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 14436#(= |#Ultimate.meminit_#t~loopctr33| 0), 14437#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 14438#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14439#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14440#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14441#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14442#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14443#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14444#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14445#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14446#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14447#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14448#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14449#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14450#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14451#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14452#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14453#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14454#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14455#(<= (+ (* 18 |#Ultimate.meminit_#t~loopctr33|) 19) (* 19 |#Ultimate.meminit_#product|)), 14456#(<= 19 |#Ultimate.meminit_#product|), 14457#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 19 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 14458#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 19 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 14459#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 19 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 14460#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 19 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 14461#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 14462#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 14463#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 10:18:50,133 INFO L134 CoverageAnalysis]: Checked inductivity of 1062 backedges. 4 proven. 726 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:50,133 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-02-02 10:18:50,133 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-02-02 10:18:50,133 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=1049, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 10:18:50,134 INFO L87 Difference]: Start difference. First operand 222 states and 251 transitions. Second operand 34 states. [2018-02-02 10:18:52,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:52,385 INFO L93 Difference]: Finished difference Result 289 states and 343 transitions. [2018-02-02 10:18:52,385 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-02-02 10:18:52,385 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 95 [2018-02-02 10:18:52,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:52,386 INFO L225 Difference]: With dead ends: 289 [2018-02-02 10:18:52,386 INFO L226 Difference]: Without dead ends: 289 [2018-02-02 10:18:52,387 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 325 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=239, Invalid=3301, Unknown=0, NotChecked=0, Total=3540 [2018-02-02 10:18:52,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2018-02-02 10:18:52,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 223. [2018-02-02 10:18:52,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-02-02 10:18:52,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 253 transitions. [2018-02-02 10:18:52,390 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 253 transitions. Word has length 95 [2018-02-02 10:18:52,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:52,390 INFO L432 AbstractCegarLoop]: Abstraction has 223 states and 253 transitions. [2018-02-02 10:18:52,390 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-02-02 10:18:52,390 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 253 transitions. [2018-02-02 10:18:52,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-02-02 10:18:52,391 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:52,391 INFO L351 BasicCegarLoop]: trace histogram [44, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:52,391 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:52,391 INFO L82 PathProgramCache]: Analyzing trace with hash 1069130919, now seen corresponding path program 16 times [2018-02-02 10:18:52,392 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:52,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:52,415 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:53,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1108 backedges. 4 proven. 772 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:53,083 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:53,084 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-02-02 10:18:53,084 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:53,084 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:53,084 INFO L182 omatonBuilderFactory]: Interpolants [15040#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15041#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15042#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15043#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15044#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15045#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15046#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15047#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15048#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15049#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15050#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15051#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15052#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15053#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15054#(<= (+ (* 19 |#Ultimate.meminit_#t~loopctr33|) 20) (* 20 |#Ultimate.meminit_#product|)), 15055#(<= 20 |#Ultimate.meminit_#product|), 15056#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 20 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15057#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 20 (select |#length| |ldv_zalloc_#res.base|))), 15058#(and (<= 20 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 15059#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset) (<= 20 (select |#length| entry_point_~hdev~0.base))), 15060#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 15061#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15062#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15063#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15064#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 15065#(and (= entry_point_~hdev~0.offset 0) (<= 20 (select |#length| entry_point_~hdev~0.base))), 15031#true, 15032#false, 15033#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15034#(= |#Ultimate.meminit_#t~loopctr33| 0), 15035#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 15036#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15037#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15038#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15039#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-02 10:18:53,084 INFO L134 CoverageAnalysis]: Checked inductivity of 1108 backedges. 4 proven. 772 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:53,084 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-02-02 10:18:53,084 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-02-02 10:18:53,085 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=1115, Unknown=0, NotChecked=0, Total=1190 [2018-02-02 10:18:53,085 INFO L87 Difference]: Start difference. First operand 223 states and 253 transitions. Second operand 35 states. [2018-02-02 10:18:55,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:55,651 INFO L93 Difference]: Finished difference Result 292 states and 349 transitions. [2018-02-02 10:18:55,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-02 10:18:55,651 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 96 [2018-02-02 10:18:55,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:55,652 INFO L225 Difference]: With dead ends: 292 [2018-02-02 10:18:55,652 INFO L226 Difference]: Without dead ends: 292 [2018-02-02 10:18:55,653 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 351 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=247, Invalid=3535, Unknown=0, NotChecked=0, Total=3782 [2018-02-02 10:18:55,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2018-02-02 10:18:55,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 224. [2018-02-02 10:18:55,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-02-02 10:18:55,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 255 transitions. [2018-02-02 10:18:55,656 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 255 transitions. Word has length 96 [2018-02-02 10:18:55,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:55,656 INFO L432 AbstractCegarLoop]: Abstraction has 224 states and 255 transitions. [2018-02-02 10:18:55,656 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-02-02 10:18:55,657 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 255 transitions. [2018-02-02 10:18:55,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-02-02 10:18:55,657 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:55,658 INFO L351 BasicCegarLoop]: trace histogram [45, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:55,658 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:55,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1830544113, now seen corresponding path program 17 times [2018-02-02 10:18:55,658 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:55,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:55,684 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:56,394 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 4 proven. 819 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:56,394 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:56,394 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-02 10:18:56,395 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:56,395 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:56,395 INFO L182 omatonBuilderFactory]: Interpolants [15636#true, 15637#false, 15638#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15639#(= |#Ultimate.meminit_#t~loopctr33| 0), 15640#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 15641#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15642#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15643#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15644#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15645#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15646#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15647#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15648#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15649#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15650#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15651#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15652#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15653#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15654#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15655#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15656#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15657#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15658#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15659#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15660#(<= (+ (* 20 |#Ultimate.meminit_#t~loopctr33|) 21) (* 21 |#Ultimate.meminit_#product|)), 15661#(<= 21 |#Ultimate.meminit_#product|), 15662#(and (<= 21 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15663#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 21 (select |#length| |ldv_zalloc_#res.base|))), 15664#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 21 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 15665#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 21 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 15666#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 15667#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15668#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15669#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15670#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 15671#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-02 10:18:56,395 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 4 proven. 819 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:56,395 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-02 10:18:56,395 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-02 10:18:56,396 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=1183, Unknown=0, NotChecked=0, Total=1260 [2018-02-02 10:18:56,396 INFO L87 Difference]: Start difference. First operand 224 states and 255 transitions. Second operand 36 states. [2018-02-02 10:18:59,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:18:59,050 INFO L93 Difference]: Finished difference Result 295 states and 355 transitions. [2018-02-02 10:18:59,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-02 10:18:59,051 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 97 [2018-02-02 10:18:59,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:18:59,052 INFO L225 Difference]: With dead ends: 295 [2018-02-02 10:18:59,052 INFO L226 Difference]: Without dead ends: 295 [2018-02-02 10:18:59,052 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 378 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=255, Invalid=3777, Unknown=0, NotChecked=0, Total=4032 [2018-02-02 10:18:59,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 295 states. [2018-02-02 10:18:59,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 295 to 225. [2018-02-02 10:18:59,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-02-02 10:18:59,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 257 transitions. [2018-02-02 10:18:59,056 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 257 transitions. Word has length 97 [2018-02-02 10:18:59,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:18:59,056 INFO L432 AbstractCegarLoop]: Abstraction has 225 states and 257 transitions. [2018-02-02 10:18:59,056 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-02 10:18:59,056 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 257 transitions. [2018-02-02 10:18:59,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-02-02 10:18:59,057 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:18:59,057 INFO L351 BasicCegarLoop]: trace histogram [46, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:18:59,057 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:18:59,057 INFO L82 PathProgramCache]: Analyzing trace with hash -1526156889, now seen corresponding path program 18 times [2018-02-02 10:18:59,058 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:18:59,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:18:59,101 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:18:59,793 INFO L134 CoverageAnalysis]: Checked inductivity of 1203 backedges. 4 proven. 867 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:59,793 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:18:59,793 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-02-02 10:18:59,793 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:18:59,793 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:18:59,793 INFO L182 omatonBuilderFactory]: Interpolants [16256#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16257#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16258#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16259#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16260#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16261#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16262#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16263#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16264#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16265#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16266#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16267#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16268#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16269#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16270#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16271#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16272#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16273#(<= (+ (* 21 |#Ultimate.meminit_#t~loopctr33|) 22) (* 22 |#Ultimate.meminit_#product|)), 16274#(<= 22 |#Ultimate.meminit_#product|), 16275#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|) (<= 22 (select |#length| |ldv_zalloc_#t~malloc1.base|))), 16276#(and (<= 22 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 16277#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 22 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 16278#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 22 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 16279#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16280#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16281#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 16282#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16283#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16284#(and (= entry_point_~hdev~0.offset 0) (<= 22 (select |#length| entry_point_~hdev~0.base))), 16248#true, 16249#false, 16250#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 16251#(= |#Ultimate.meminit_#t~loopctr33| 0), 16252#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 16253#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16254#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16255#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-02 10:18:59,794 INFO L134 CoverageAnalysis]: Checked inductivity of 1203 backedges. 4 proven. 867 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-02 10:18:59,794 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-02-02 10:18:59,794 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-02-02 10:18:59,794 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=1253, Unknown=0, NotChecked=0, Total=1332 [2018-02-02 10:18:59,795 INFO L87 Difference]: Start difference. First operand 225 states and 257 transitions. Second operand 37 states. [2018-02-02 10:19:02,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:19:02,692 INFO L93 Difference]: Finished difference Result 298 states and 361 transitions. [2018-02-02 10:19:02,693 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-02 10:19:02,693 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 98 [2018-02-02 10:19:02,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:19:02,694 INFO L225 Difference]: With dead ends: 298 [2018-02-02 10:19:02,694 INFO L226 Difference]: Without dead ends: 298 [2018-02-02 10:19:02,694 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 406 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=263, Invalid=4027, Unknown=0, NotChecked=0, Total=4290 [2018-02-02 10:19:02,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states. [2018-02-02 10:19:02,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 226. [2018-02-02 10:19:02,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-02-02 10:19:02,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 259 transitions. [2018-02-02 10:19:02,697 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 259 transitions. Word has length 98 [2018-02-02 10:19:02,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:19:02,698 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 259 transitions. [2018-02-02 10:19:02,698 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-02-02 10:19:02,698 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 259 transitions. [2018-02-02 10:19:02,698 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-02-02 10:19:02,698 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:19:02,698 INFO L351 BasicCegarLoop]: trace histogram [47, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:19:02,698 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:19:02,698 INFO L82 PathProgramCache]: Analyzing trace with hash -680087537, now seen corresponding path program 19 times [2018-02-02 10:19:02,699 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:19:02,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:19:02,727 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:19:04,125 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 166 proven. 960 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-02-02 10:19:04,125 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:19:04,125 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51] total 51 [2018-02-02 10:19:04,125 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:19:04,126 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 10 proven. 25 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 10:19:04,126 INFO L182 omatonBuilderFactory]: Interpolants [16896#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 23 (select |#length| |ldv_zalloc_#res.base|))), 16897#(and (<= 23 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 16898#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 23 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 16899#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16900#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16901#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 16902#(and (or (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (and (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296) ldv_zalloc_~size) (= 0 |ldv_zalloc_#t~malloc1.offset|))) (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16903#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)), 16904#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))), 16905#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))), 16906#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))), 16907#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|))), 16908#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|))), 16909#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))), 16910#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|))), 16911#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= (+ (* 10 |#Ultimate.meminit_#t~loopctr33|) 9) (+ (* 18 |#Ultimate.meminit_#sizeOfFields|) (* 9 |#Ultimate.meminit_#product|)))), 16912#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= (+ |#Ultimate.meminit_#product| 9) (* 18 |#Ultimate.meminit_#sizeOfFields|))), 16913#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16914#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16915#(and (= entry_point_~hdev~0.offset 0) (or (<= 14 (select |#length| entry_point_~hdev~0.base)) (and (= 0 |entry_point_#t~ret24.offset|) (<= (select |#length| |entry_point_#t~ret24.base|) 7)))), 16916#(and (= entry_point_~hdev~0.offset 0) (or (<= 14 (select |#length| entry_point_~hdev~0.base)) (and (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4))) (<= (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4))) 7)))), 16917#(and (or (and (= |entry_point_#t~mem27.offset| 0) (<= (select |#length| |entry_point_#t~mem27.base|) 7)) (<= 14 (select |#length| entry_point_~hdev~0.base))) (= entry_point_~hdev~0.offset 0)), 16918#(and (<= 14 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 16867#true, 16868#false, 16869#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 16870#(= |#Ultimate.meminit_#t~loopctr33| 0), 16871#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 16872#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16873#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16874#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16875#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16876#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16877#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16878#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16879#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16880#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16881#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16882#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16883#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16884#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16885#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16886#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16887#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16888#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16889#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16890#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16891#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16892#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16893#(<= (+ (* 22 |#Ultimate.meminit_#t~loopctr33|) 23) (* 23 |#Ultimate.meminit_#product|)), 16894#(<= 23 |#Ultimate.meminit_#product|), 16895#(and (<= 23 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|))] [2018-02-02 10:19:04,126 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 166 proven. 960 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-02-02 10:19:04,126 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-02-02 10:19:04,126 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-02-02 10:19:04,127 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=2499, Unknown=0, NotChecked=0, Total=2652 [2018-02-02 10:19:04,127 INFO L87 Difference]: Start difference. First operand 226 states and 259 transitions. Second operand 52 states. [2018-02-02 10:19:08,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:19:08,104 INFO L93 Difference]: Finished difference Result 301 states and 367 transitions. [2018-02-02 10:19:08,104 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-02 10:19:08,104 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 99 [2018-02-02 10:19:08,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:19:08,105 INFO L225 Difference]: With dead ends: 301 [2018-02-02 10:19:08,105 INFO L226 Difference]: Without dead ends: 301 [2018-02-02 10:19:08,106 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 578 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=411, Invalid=6395, Unknown=0, NotChecked=0, Total=6806 [2018-02-02 10:19:08,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-02-02 10:19:08,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 227. [2018-02-02 10:19:08,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-02-02 10:19:08,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 261 transitions. [2018-02-02 10:19:08,109 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 261 transitions. Word has length 99 [2018-02-02 10:19:08,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:19:08,109 INFO L432 AbstractCegarLoop]: Abstraction has 227 states and 261 transitions. [2018-02-02 10:19:08,109 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-02-02 10:19:08,109 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 261 transitions. [2018-02-02 10:19:08,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-02-02 10:19:08,109 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:19:08,109 INFO L351 BasicCegarLoop]: trace histogram [48, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:19:08,109 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:19:08,109 INFO L82 PathProgramCache]: Analyzing trace with hash -221741401, now seen corresponding path program 20 times [2018-02-02 10:19:08,110 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:19:08,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:19:08,138 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 10:19:08,479 INFO L134 CoverageAnalysis]: Checked inductivity of 1302 backedges. 0 proven. 964 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-02 10:19:08,479 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 10:19:08,479 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-02 10:19:08,479 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 10:19:08,479 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 10:19:08,480 INFO L182 omatonBuilderFactory]: Interpolants [17536#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17537#(<= (+ (* 23 |#Ultimate.meminit_#t~loopctr33|) 24) (* 24 |#Ultimate.meminit_#product|)), 17538#(<= 24 |#Ultimate.meminit_#product|), 17539#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 24 |ldv_zalloc_#in~size|)), 17509#true, 17510#false, 17511#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 17512#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 17513#(= |#Ultimate.meminit_#t~loopctr33| 0), 17514#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 17515#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17516#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17517#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17518#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17519#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17520#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17521#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17522#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17523#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17524#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17525#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17526#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17527#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17528#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17529#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17530#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17531#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17532#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17533#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17534#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17535#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-02 10:19:08,480 INFO L134 CoverageAnalysis]: Checked inductivity of 1302 backedges. 0 proven. 964 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-02 10:19:08,480 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-02 10:19:08,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-02 10:19:08,480 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=870, Unknown=0, NotChecked=0, Total=930 [2018-02-02 10:19:08,480 INFO L87 Difference]: Start difference. First operand 227 states and 261 transitions. Second operand 31 states. [2018-02-02 10:19:09,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 10:19:09,309 INFO L93 Difference]: Finished difference Result 259 states and 308 transitions. [2018-02-02 10:19:09,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-02 10:19:09,309 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 100 [2018-02-02 10:19:09,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 10:19:09,310 INFO L225 Difference]: With dead ends: 259 [2018-02-02 10:19:09,310 INFO L226 Difference]: Without dead ends: 248 [2018-02-02 10:19:09,310 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=69, Invalid=987, Unknown=0, NotChecked=0, Total=1056 [2018-02-02 10:19:09,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-02-02 10:19:09,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 228. [2018-02-02 10:19:09,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-02-02 10:19:09,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 262 transitions. [2018-02-02 10:19:09,313 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 262 transitions. Word has length 100 [2018-02-02 10:19:09,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 10:19:09,313 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 262 transitions. [2018-02-02 10:19:09,313 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-02 10:19:09,313 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 262 transitions. [2018-02-02 10:19:09,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-02-02 10:19:09,313 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 10:19:09,314 INFO L351 BasicCegarLoop]: trace histogram [49, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 10:19:09,314 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-02 10:19:09,314 INFO L82 PathProgramCache]: Analyzing trace with hash 1102086927, now seen corresponding path program 21 times [2018-02-02 10:19:09,314 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 10:19:09,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 10:19:09,343 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-02-02 10:19:09,663 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 10:19:09,670 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 10:19:09,670 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 10:19:09 BoogieIcfgContainer [2018-02-02 10:19:09,671 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 10:19:09,671 INFO L168 Benchmark]: Toolchain (without parser) took 50054.16 ms. Allocated memory was 402.7 MB in the beginning and 1.4 GB in the end (delta: 977.8 MB). Free memory was 359.3 MB in the beginning and 482.6 MB in the end (delta: -123.2 MB). Peak memory consumption was 854.6 MB. Max. memory is 5.3 GB. [2018-02-02 10:19:09,672 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 402.7 MB. Free memory is still 365.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 10:19:09,673 INFO L168 Benchmark]: CACSL2BoogieTranslator took 177.61 ms. Allocated memory is still 402.7 MB. Free memory was 359.3 MB in the beginning and 344.5 MB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 5.3 GB. [2018-02-02 10:19:09,673 INFO L168 Benchmark]: Boogie Preprocessor took 28.41 ms. Allocated memory is still 402.7 MB. Free memory was 344.5 MB in the beginning and 341.9 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-02 10:19:09,673 INFO L168 Benchmark]: RCFGBuilder took 389.06 ms. Allocated memory is still 402.7 MB. Free memory was 341.9 MB in the beginning and 300.6 MB in the end (delta: 41.3 MB). Peak memory consumption was 41.3 MB. Max. memory is 5.3 GB. [2018-02-02 10:19:09,673 INFO L168 Benchmark]: TraceAbstraction took 49455.77 ms. Allocated memory was 402.7 MB in the beginning and 1.4 GB in the end (delta: 977.8 MB). Free memory was 300.6 MB in the beginning and 482.6 MB in the end (delta: -182.0 MB). Peak memory consumption was 795.8 MB. Max. memory is 5.3 GB. [2018-02-02 10:19:09,683 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 402.7 MB. Free memory is still 365.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 177.61 ms. Allocated memory is still 402.7 MB. Free memory was 359.3 MB in the beginning and 344.5 MB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 28.41 ms. Allocated memory is still 402.7 MB. Free memory was 344.5 MB in the beginning and 341.9 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 389.06 ms. Allocated memory is still 402.7 MB. Free memory was 341.9 MB in the beginning and 300.6 MB in the end (delta: 41.3 MB). Peak memory consumption was 41.3 MB. Max. memory is 5.3 GB. * TraceAbstraction took 49455.77 ms. Allocated memory was 402.7 MB in the beginning and 1.4 GB in the end (delta: 977.8 MB). Free memory was 300.6 MB in the beginning and 482.6 MB in the end (delta: -182.0 MB). Peak memory consumption was 795.8 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1533]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1533). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was analyzing trace of length 102 with TraceHistMax 49, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 20 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 165 locations, 45 error locations. TIMEOUT Result, 49.4s OverallTime, 41 OverallIterations, 49 TraceHistogramMax, 34.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5740 SDtfs, 2903 SDslu, 70017 SDs, 0 SdLazy, 62813 SolverSat, 1118 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 23.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1108 GetRequests, 77 SyntacticMatches, 22 SemanticMatches, 1009 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3572 ImplicationChecksByTransitivity, 16.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=228occurred in iteration=40, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 9699/21053 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 40 MinimizatonAttempts, 798 StatesRemovedByMinimization, 25 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 1.0s SatisfiabilityAnalysisTime, 13.1s InterpolantComputationTime, 2968 NumberOfCodeBlocks, 2968 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 2928 ConstructedInterpolants, 0 QuantifiedInterpolants, 1146630 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 40 InterpolantComputations, 5 PerfectInterpolantSequences, 9699/21053 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_false-valid-memtrack.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_10-19-09-690.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_false-valid-memtrack.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_10-19-09-690.csv Completed graceful shutdown