java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 09:49:00,559 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 09:49:00,561 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 09:49:00,570 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 09:49:00,571 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 09:49:00,571 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 09:49:00,572 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 09:49:00,573 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 09:49:00,575 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 09:49:00,575 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 09:49:00,576 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 09:49:00,576 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 09:49:00,576 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 09:49:00,579 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 09:49:00,579 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 09:49:00,581 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 09:49:00,582 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 09:49:00,583 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 09:49:00,583 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 09:49:00,584 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 09:49:00,585 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-02-02 09:49:00,591 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 09:49:00,604 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 09:49:00,604 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 09:49:00,605 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 09:49:00,605 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 09:49:00,605 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 09:49:00,606 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 09:49:00,606 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 09:49:00,606 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 09:49:00,606 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 09:49:00,606 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 09:49:00,607 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 09:49:00,607 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 09:49:00,607 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 09:49:00,607 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 09:49:00,607 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 09:49:00,607 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 09:49:00,608 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 09:49:00,608 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 09:49:00,608 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 09:49:00,608 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 09:49:00,608 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:49:00,608 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 09:49:00,609 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 09:49:00,637 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 09:49:00,648 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 09:49:00,652 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 09:49:00,653 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 09:49:00,654 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 09:49:00,654 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:49:00,794 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 09:49:00,795 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 09:49:00,796 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 09:49:00,796 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 09:49:00,802 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 09:49:00,803 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,805 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7dce5039 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00, skipping insertion in model container [2018-02-02 09:49:00,805 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,819 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:49:00,848 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:49:00,945 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:49:00,957 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:49:00,961 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00 WrapperNode [2018-02-02 09:49:00,962 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 09:49:00,962 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 09:49:00,962 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 09:49:00,962 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 09:49:00,971 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,972 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,979 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,979 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,981 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,983 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,984 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... [2018-02-02 09:49:00,985 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 09:49:00,985 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 09:49:00,985 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 09:49:00,985 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 09:49:00,986 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:49:01,020 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 09:49:01,020 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 09:49:01,020 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrcat [2018-02-02 09:49:01,020 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 09:49:01,020 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 09:49:01,020 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure cstrcat [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 09:49:01,021 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 09:49:01,186 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 09:49:01,186 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:49:01 BoogieIcfgContainer [2018-02-02 09:49:01,186 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 09:49:01,187 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 09:49:01,187 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 09:49:01,189 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 09:49:01,189 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 09:49:00" (1/3) ... [2018-02-02 09:49:01,190 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@233e07ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:49:01, skipping insertion in model container [2018-02-02 09:49:01,190 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:49:00" (2/3) ... [2018-02-02 09:49:01,190 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@233e07ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:49:01, skipping insertion in model container [2018-02-02 09:49:01,190 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:49:01" (3/3) ... [2018-02-02 09:49:01,191 INFO L107 eAbstractionObserver]: Analyzing ICFG openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:49:01,198 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 09:49:01,202 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 11 error locations. [2018-02-02 09:49:01,225 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 09:49:01,225 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 09:49:01,225 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 09:49:01,225 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 09:49:01,225 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 09:49:01,226 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 09:49:01,226 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 09:49:01,226 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 09:49:01,226 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 09:49:01,238 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states. [2018-02-02 09:49:01,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-02-02 09:49:01,247 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:01,248 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:01,248 INFO L371 AbstractCegarLoop]: === Iteration 1 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:01,252 INFO L82 PathProgramCache]: Analyzing trace with hash 967400660, now seen corresponding path program 1 times [2018-02-02 09:49:01,301 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:01,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:01,355 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:01,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,409 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:01,409 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 09:49:01,410 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:01,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,411 INFO L182 omatonBuilderFactory]: Interpolants [53#true, 54#false, 55#(= |#valid| |old(#valid)|)] [2018-02-02 09:49:01,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,412 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 09:49:01,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 09:49:01,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:49:01,428 INFO L87 Difference]: Start difference. First operand 50 states. Second operand 3 states. [2018-02-02 09:49:01,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:01,626 INFO L93 Difference]: Finished difference Result 51 states and 56 transitions. [2018-02-02 09:49:01,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 09:49:01,628 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-02-02 09:49:01,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:01,633 INFO L225 Difference]: With dead ends: 51 [2018-02-02 09:49:01,634 INFO L226 Difference]: Without dead ends: 47 [2018-02-02 09:49:01,635 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:49:01,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-02 09:49:01,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-02-02 09:49:01,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-02-02 09:49:01,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 51 transitions. [2018-02-02 09:49:01,659 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 51 transitions. Word has length 11 [2018-02-02 09:49:01,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:01,659 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 51 transitions. [2018-02-02 09:49:01,660 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 09:49:01,660 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 51 transitions. [2018-02-02 09:49:01,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:49:01,660 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:01,660 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:01,660 INFO L371 AbstractCegarLoop]: === Iteration 2 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:01,661 INFO L82 PathProgramCache]: Analyzing trace with hash 1512837349, now seen corresponding path program 1 times [2018-02-02 09:49:01,661 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:01,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:01,685 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:01,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,755 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:01,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:49:01,756 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:01,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,756 INFO L182 omatonBuilderFactory]: Interpolants [154#true, 155#false, 156#(= 1 (select |#valid| |main_#t~malloc9.base|)), 157#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-02-02 09:49:01,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,758 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:49:01,758 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:49:01,758 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:49:01,758 INFO L87 Difference]: Start difference. First operand 47 states and 51 transitions. Second operand 4 states. [2018-02-02 09:49:01,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:01,818 INFO L93 Difference]: Finished difference Result 46 states and 50 transitions. [2018-02-02 09:49:01,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:49:01,818 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-02-02 09:49:01,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:01,819 INFO L225 Difference]: With dead ends: 46 [2018-02-02 09:49:01,819 INFO L226 Difference]: Without dead ends: 46 [2018-02-02 09:49:01,820 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:49:01,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-02-02 09:49:01,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2018-02-02 09:49:01,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-02-02 09:49:01,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-02-02 09:49:01,825 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 15 [2018-02-02 09:49:01,825 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:01,825 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-02-02 09:49:01,825 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:49:01,825 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-02-02 09:49:01,826 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:49:01,826 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:01,826 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:01,826 INFO L371 AbstractCegarLoop]: === Iteration 3 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:01,827 INFO L82 PathProgramCache]: Analyzing trace with hash 1512837350, now seen corresponding path program 1 times [2018-02-02 09:49:01,828 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:01,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:01,842 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:01,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,920 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:01,920 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:49:01,920 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:01,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,923 INFO L182 omatonBuilderFactory]: Interpolants [256#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 257#(and (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 252#true, 253#false, 254#(<= 1 main_~length1~0), 255#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1))] [2018-02-02 09:49:01,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:01,924 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:49:01,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:49:01,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:49:01,924 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 6 states. [2018-02-02 09:49:01,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:01,995 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2018-02-02 09:49:01,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:49:01,996 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-02-02 09:49:01,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:01,996 INFO L225 Difference]: With dead ends: 45 [2018-02-02 09:49:01,996 INFO L226 Difference]: Without dead ends: 45 [2018-02-02 09:49:01,997 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:49:01,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-02-02 09:49:01,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-02-02 09:49:02,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-02-02 09:49:02,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2018-02-02 09:49:02,001 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 15 [2018-02-02 09:49:02,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:02,001 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2018-02-02 09:49:02,001 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:49:02,001 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2018-02-02 09:49:02,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:49:02,002 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:02,002 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:02,002 INFO L371 AbstractCegarLoop]: === Iteration 4 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:02,002 INFO L82 PathProgramCache]: Analyzing trace with hash -346682393, now seen corresponding path program 1 times [2018-02-02 09:49:02,003 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:02,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:02,017 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:02,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,045 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:02,045 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:49:02,045 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:02,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,045 INFO L182 omatonBuilderFactory]: Interpolants [352#(= 1 (select |#valid| |main_#t~malloc10.base|)), 353#(= 1 (select |#valid| main_~nondetString2~0.base)), 350#true, 351#false] [2018-02-02 09:49:02,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,046 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:49:02,046 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:49:02,046 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:49:02,046 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 4 states. [2018-02-02 09:49:02,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:02,089 INFO L93 Difference]: Finished difference Result 44 states and 48 transitions. [2018-02-02 09:49:02,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:49:02,090 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-02-02 09:49:02,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:02,090 INFO L225 Difference]: With dead ends: 44 [2018-02-02 09:49:02,090 INFO L226 Difference]: Without dead ends: 44 [2018-02-02 09:49:02,091 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:49:02,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-02-02 09:49:02,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-02-02 09:49:02,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-02 09:49:02,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-02-02 09:49:02,093 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 16 [2018-02-02 09:49:02,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:02,093 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-02-02 09:49:02,093 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:49:02,093 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-02-02 09:49:02,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:49:02,094 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:02,094 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:02,094 INFO L371 AbstractCegarLoop]: === Iteration 5 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:02,094 INFO L82 PathProgramCache]: Analyzing trace with hash -346682392, now seen corresponding path program 1 times [2018-02-02 09:49:02,094 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:02,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:02,103 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:02,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,307 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:02,307 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:49:02,307 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:02,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,308 INFO L182 omatonBuilderFactory]: Interpolants [448#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 449#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)), 444#true, 445#false, 446#(<= 2 main_~length2~0), 447#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0))] [2018-02-02 09:49:02,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,308 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:49:02,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:49:02,309 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:49:02,309 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 6 states. [2018-02-02 09:49:02,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:02,501 INFO L93 Difference]: Finished difference Result 59 states and 63 transitions. [2018-02-02 09:49:02,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:49:02,501 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-02-02 09:49:02,501 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:02,503 INFO L225 Difference]: With dead ends: 59 [2018-02-02 09:49:02,503 INFO L226 Difference]: Without dead ends: 59 [2018-02-02 09:49:02,503 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:49:02,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-02-02 09:49:02,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 51. [2018-02-02 09:49:02,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-02 09:49:02,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 55 transitions. [2018-02-02 09:49:02,511 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 55 transitions. Word has length 16 [2018-02-02 09:49:02,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:02,511 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 55 transitions. [2018-02-02 09:49:02,511 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:49:02,511 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 55 transitions. [2018-02-02 09:49:02,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:49:02,512 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:02,512 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:02,512 INFO L371 AbstractCegarLoop]: === Iteration 6 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:02,512 INFO L82 PathProgramCache]: Analyzing trace with hash -1156029018, now seen corresponding path program 1 times [2018-02-02 09:49:02,513 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:02,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:02,526 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:02,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,592 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:02,592 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:49:02,592 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:02,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,593 INFO L182 omatonBuilderFactory]: Interpolants [566#true, 567#false, 568#(<= 1 main_~length1~0), 569#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 570#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 571#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 572#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-02-02 09:49:02,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,593 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:49:02,593 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:49:02,593 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:49:02,594 INFO L87 Difference]: Start difference. First operand 51 states and 55 transitions. Second operand 7 states. [2018-02-02 09:49:02,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:02,700 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-02-02 09:49:02,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:49:02,700 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 16 [2018-02-02 09:49:02,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:02,701 INFO L225 Difference]: With dead ends: 50 [2018-02-02 09:49:02,701 INFO L226 Difference]: Without dead ends: 50 [2018-02-02 09:49:02,701 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:49:02,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-02-02 09:49:02,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 43. [2018-02-02 09:49:02,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-02-02 09:49:02,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-02-02 09:49:02,704 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 16 [2018-02-02 09:49:02,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:02,705 INFO L432 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-02-02 09:49:02,705 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:49:02,705 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-02-02 09:49:02,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-02 09:49:02,706 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:02,706 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:02,706 INFO L371 AbstractCegarLoop]: === Iteration 7 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:02,706 INFO L82 PathProgramCache]: Analyzing trace with hash -131455439, now seen corresponding path program 1 times [2018-02-02 09:49:02,707 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:02,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:02,724 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:02,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,756 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:02,756 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 09:49:02,756 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:02,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,756 INFO L182 omatonBuilderFactory]: Interpolants [674#true, 675#false, 676#(= 1 (select |#valid| main_~nondetString2~0.base)), 677#(= 1 (select |#valid| |cstrcat_#in~s.base|)), 678#(= 1 (select |#valid| cstrcat_~s.base))] [2018-02-02 09:49:02,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,757 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:49:02,757 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:49:02,757 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:49:02,757 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 5 states. [2018-02-02 09:49:02,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:02,790 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-02-02 09:49:02,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:49:02,790 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-02-02 09:49:02,790 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:02,790 INFO L225 Difference]: With dead ends: 42 [2018-02-02 09:49:02,790 INFO L226 Difference]: Without dead ends: 42 [2018-02-02 09:49:02,791 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:49:02,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-02-02 09:49:02,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2018-02-02 09:49:02,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-02-02 09:49:02,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 46 transitions. [2018-02-02 09:49:02,792 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 46 transitions. Word has length 20 [2018-02-02 09:49:02,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:02,793 INFO L432 AbstractCegarLoop]: Abstraction has 42 states and 46 transitions. [2018-02-02 09:49:02,793 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:49:02,793 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-02-02 09:49:02,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-02 09:49:02,793 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:02,793 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:02,793 INFO L371 AbstractCegarLoop]: === Iteration 8 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:02,793 INFO L82 PathProgramCache]: Analyzing trace with hash -131455438, now seen corresponding path program 1 times [2018-02-02 09:49:02,794 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:02,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:02,804 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:02,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,886 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:02,886 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:49:02,886 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:02,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,886 INFO L182 omatonBuilderFactory]: Interpolants [768#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 769#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 770#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|))), 771#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 765#true, 766#false, 767#(<= 2 main_~length2~0)] [2018-02-02 09:49:02,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:02,887 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:49:02,887 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:49:02,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:49:02,887 INFO L87 Difference]: Start difference. First operand 42 states and 46 transitions. Second operand 7 states. [2018-02-02 09:49:02,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:02,975 INFO L93 Difference]: Finished difference Result 48 states and 53 transitions. [2018-02-02 09:49:02,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:49:02,975 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 20 [2018-02-02 09:49:02,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:02,975 INFO L225 Difference]: With dead ends: 48 [2018-02-02 09:49:02,975 INFO L226 Difference]: Without dead ends: 48 [2018-02-02 09:49:02,976 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-02-02 09:49:02,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-02-02 09:49:02,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 44. [2018-02-02 09:49:02,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-02 09:49:02,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-02-02 09:49:02,978 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 20 [2018-02-02 09:49:02,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:02,978 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-02-02 09:49:02,978 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:49:02,978 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-02-02 09:49:02,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:49:02,979 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:02,979 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:02,979 INFO L371 AbstractCegarLoop]: === Iteration 9 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:02,979 INFO L82 PathProgramCache]: Analyzing trace with hash -313436100, now seen corresponding path program 1 times [2018-02-02 09:49:02,979 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:02,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:02,989 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:03,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,031 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:03,031 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:49:03,031 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:03,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,032 INFO L182 omatonBuilderFactory]: Interpolants [872#true, 873#false, 874#(= 1 (select |#valid| main_~nondetString1~0.base)), 875#(= 1 (select |#valid| |cstrcat_#in~append.base|)), 876#(= 1 (select |#valid| cstrcat_~append.base)), 877#(= 1 (select |#valid| |cstrcat_#t~post3.base|))] [2018-02-02 09:49:03,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,032 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:49:03,032 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:49:03,032 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:49:03,032 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 6 states. [2018-02-02 09:49:03,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:03,113 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-02-02 09:49:03,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:49:03,113 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 24 [2018-02-02 09:49:03,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:03,114 INFO L225 Difference]: With dead ends: 43 [2018-02-02 09:49:03,114 INFO L226 Difference]: Without dead ends: 43 [2018-02-02 09:49:03,114 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:49:03,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-02-02 09:49:03,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-02-02 09:49:03,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-02-02 09:49:03,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-02-02 09:49:03,119 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 24 [2018-02-02 09:49:03,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:03,119 INFO L432 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-02-02 09:49:03,119 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:49:03,119 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-02-02 09:49:03,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:49:03,120 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:03,120 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:03,120 INFO L371 AbstractCegarLoop]: === Iteration 10 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:03,120 INFO L82 PathProgramCache]: Analyzing trace with hash -313436099, now seen corresponding path program 1 times [2018-02-02 09:49:03,121 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:03,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:03,130 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:03,208 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,208 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:03,208 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 09:49:03,208 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:03,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,209 INFO L182 omatonBuilderFactory]: Interpolants [976#(and (= |cstrcat_#t~post3.offset| 0) (<= 1 (select |#length| |cstrcat_#t~post3.base|))), 968#true, 969#false, 970#(<= 1 main_~length1~0), 971#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0)), 972#(and (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 973#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 974#(and (= 0 |cstrcat_#in~append.offset|) (<= 1 (select |#length| |cstrcat_#in~append.base|))), 975#(and (= 0 cstrcat_~append.offset) (<= 1 (select |#length| cstrcat_~append.base)))] [2018-02-02 09:49:03,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,209 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:49:03,209 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:49:03,209 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:49:03,210 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 9 states. [2018-02-02 09:49:03,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:03,436 INFO L93 Difference]: Finished difference Result 50 states and 55 transitions. [2018-02-02 09:49:03,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:49:03,437 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-02-02 09:49:03,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:03,437 INFO L225 Difference]: With dead ends: 50 [2018-02-02 09:49:03,437 INFO L226 Difference]: Without dead ends: 50 [2018-02-02 09:49:03,438 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:49:03,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-02-02 09:49:03,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 46. [2018-02-02 09:49:03,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-02-02 09:49:03,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-02-02 09:49:03,440 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 24 [2018-02-02 09:49:03,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:03,441 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-02-02 09:49:03,441 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:49:03,441 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-02-02 09:49:03,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:49:03,441 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:03,441 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:03,441 INFO L371 AbstractCegarLoop]: === Iteration 11 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:03,441 INFO L82 PathProgramCache]: Analyzing trace with hash -313382859, now seen corresponding path program 1 times [2018-02-02 09:49:03,442 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:03,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:03,453 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:03,591 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,592 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:03,592 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 09:49:03,592 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:03,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,592 INFO L182 omatonBuilderFactory]: Interpolants [1088#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|))), 1089#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 1090#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 1083#true, 1084#false, 1085#(<= 2 main_~length2~0), 1086#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 1087#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base)))] [2018-02-02 09:49:03,592 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,593 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:49:03,593 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:49:03,593 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:49:03,593 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 8 states. [2018-02-02 09:49:03,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:03,725 INFO L93 Difference]: Finished difference Result 66 states and 73 transitions. [2018-02-02 09:49:03,725 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:49:03,725 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-02-02 09:49:03,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:03,729 INFO L225 Difference]: With dead ends: 66 [2018-02-02 09:49:03,730 INFO L226 Difference]: Without dead ends: 66 [2018-02-02 09:49:03,730 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:49:03,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-02-02 09:49:03,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 50. [2018-02-02 09:49:03,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-02-02 09:49:03,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 55 transitions. [2018-02-02 09:49:03,736 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 55 transitions. Word has length 24 [2018-02-02 09:49:03,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:03,736 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 55 transitions. [2018-02-02 09:49:03,736 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:49:03,736 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 55 transitions. [2018-02-02 09:49:03,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-02 09:49:03,737 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:03,737 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:03,737 INFO L371 AbstractCegarLoop]: === Iteration 12 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:03,738 INFO L82 PathProgramCache]: Analyzing trace with hash -1126584510, now seen corresponding path program 1 times [2018-02-02 09:49:03,738 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:03,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:03,747 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:03,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,895 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:03,895 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:49:03,895 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:03,895 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,896 INFO L182 omatonBuilderFactory]: Interpolants [1217#true, 1218#false, 1219#(= 1 (select |#valid| main_~nondetString2~0.base)), 1220#(= 1 (select |#valid| |cstrcat_#in~s.base|)), 1221#(= 1 (select |#valid| cstrcat_~s.base)), 1222#(= 1 (select |#valid| |cstrcat_#t~post2.base|))] [2018-02-02 09:49:03,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:03,896 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:49:03,896 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:49:03,896 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:49:03,896 INFO L87 Difference]: Start difference. First operand 50 states and 55 transitions. Second operand 6 states. [2018-02-02 09:49:03,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:03,943 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-02-02 09:49:03,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:49:03,944 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-02-02 09:49:03,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:03,944 INFO L225 Difference]: With dead ends: 49 [2018-02-02 09:49:03,944 INFO L226 Difference]: Without dead ends: 49 [2018-02-02 09:49:03,944 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:49:03,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-02-02 09:49:03,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-02-02 09:49:03,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-02-02 09:49:03,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 54 transitions. [2018-02-02 09:49:03,946 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 54 transitions. Word has length 25 [2018-02-02 09:49:03,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:03,947 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 54 transitions. [2018-02-02 09:49:03,947 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:49:03,947 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 54 transitions. [2018-02-02 09:49:03,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-02 09:49:03,947 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:03,947 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:03,947 INFO L371 AbstractCegarLoop]: === Iteration 13 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:03,948 INFO L82 PathProgramCache]: Analyzing trace with hash -1126584509, now seen corresponding path program 1 times [2018-02-02 09:49:03,948 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:03,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:03,957 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:04,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,024 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:04,024 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 09:49:04,024 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:04,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,024 INFO L182 omatonBuilderFactory]: Interpolants [1328#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 1329#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 1330#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|))), 1331#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 1332#(and (<= 0 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 2) (select |#length| |cstrcat_#t~post2.base|))), 1325#true, 1326#false, 1327#(<= 2 main_~length2~0)] [2018-02-02 09:49:04,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,025 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:49:04,025 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:49:04,025 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:49:04,025 INFO L87 Difference]: Start difference. First operand 49 states and 54 transitions. Second operand 8 states. [2018-02-02 09:49:04,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:04,102 INFO L93 Difference]: Finished difference Result 54 states and 60 transitions. [2018-02-02 09:49:04,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 09:49:04,102 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 25 [2018-02-02 09:49:04,103 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:04,103 INFO L225 Difference]: With dead ends: 54 [2018-02-02 09:49:04,103 INFO L226 Difference]: Without dead ends: 54 [2018-02-02 09:49:04,103 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:49:04,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-02-02 09:49:04,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 53. [2018-02-02 09:49:04,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-02-02 09:49:04,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-02-02 09:49:04,106 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 25 [2018-02-02 09:49:04,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:04,106 INFO L432 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-02-02 09:49:04,106 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:49:04,106 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-02-02 09:49:04,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 09:49:04,107 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:04,107 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:04,107 INFO L371 AbstractCegarLoop]: === Iteration 14 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:04,107 INFO L82 PathProgramCache]: Analyzing trace with hash 718500024, now seen corresponding path program 2 times [2018-02-02 09:49:04,108 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:04,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:04,118 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:04,190 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:49:04,191 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:04,191 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-02 09:49:04,191 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:04,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,191 INFO L182 omatonBuilderFactory]: Interpolants [1456#(= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)), 1457#(= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)), 1458#(= |cstrcat_#t~mem1| 0), 1450#true, 1451#false, 1452#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1453#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1454#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1455#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)))] [2018-02-02 09:49:04,191 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:49:04,191 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:49:04,192 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:49:04,192 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:49:04,192 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 9 states. [2018-02-02 09:49:04,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:04,251 INFO L93 Difference]: Finished difference Result 76 states and 81 transitions. [2018-02-02 09:49:04,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:49:04,252 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-02-02 09:49:04,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:04,252 INFO L225 Difference]: With dead ends: 76 [2018-02-02 09:49:04,252 INFO L226 Difference]: Without dead ends: 76 [2018-02-02 09:49:04,252 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:49:04,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-02-02 09:49:04,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 65. [2018-02-02 09:49:04,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-02-02 09:49:04,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 71 transitions. [2018-02-02 09:49:04,256 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 71 transitions. Word has length 28 [2018-02-02 09:49:04,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:04,256 INFO L432 AbstractCegarLoop]: Abstraction has 65 states and 71 transitions. [2018-02-02 09:49:04,256 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:49:04,257 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 71 transitions. [2018-02-02 09:49:04,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 09:49:04,258 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:04,258 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:04,258 INFO L371 AbstractCegarLoop]: === Iteration 15 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:04,258 INFO L82 PathProgramCache]: Analyzing trace with hash -99148426, now seen corresponding path program 1 times [2018-02-02 09:49:04,259 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:04,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:04,267 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:04,358 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:49:04,358 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:04,358 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-02-02 09:49:04,358 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:04,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,359 INFO L182 omatonBuilderFactory]: Interpolants [1616#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 1617#(= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)), 1618#(= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)), 1619#(= |cstrcat_#t~mem1| 0), 1608#true, 1609#false, 1610#(<= 1 main_~length1~0), 1611#(<= main_~length2~0 (+ main_~length1~0 1)), 1612#(and (<= main_~length2~0 (+ main_~length1~0 1)) (<= 1 main_~length3~0)), 1613#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1614#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1615#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1))] [2018-02-02 09:49:04,359 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:49:04,359 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 09:49:04,359 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 09:49:04,359 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:49:04,359 INFO L87 Difference]: Start difference. First operand 65 states and 71 transitions. Second operand 12 states. [2018-02-02 09:49:04,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:04,525 INFO L93 Difference]: Finished difference Result 104 states and 111 transitions. [2018-02-02 09:49:04,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:49:04,526 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 28 [2018-02-02 09:49:04,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:04,526 INFO L225 Difference]: With dead ends: 104 [2018-02-02 09:49:04,526 INFO L226 Difference]: Without dead ends: 104 [2018-02-02 09:49:04,527 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=150, Invalid=500, Unknown=0, NotChecked=0, Total=650 [2018-02-02 09:49:04,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-02-02 09:49:04,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 66. [2018-02-02 09:49:04,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-02-02 09:49:04,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 73 transitions. [2018-02-02 09:49:04,530 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 73 transitions. Word has length 28 [2018-02-02 09:49:04,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:04,530 INFO L432 AbstractCegarLoop]: Abstraction has 66 states and 73 transitions. [2018-02-02 09:49:04,530 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 09:49:04,530 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 73 transitions. [2018-02-02 09:49:04,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 09:49:04,531 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:04,531 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:04,531 INFO L371 AbstractCegarLoop]: === Iteration 16 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:04,531 INFO L82 PathProgramCache]: Analyzing trace with hash 323553400, now seen corresponding path program 1 times [2018-02-02 09:49:04,532 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:04,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:04,540 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:04,726 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,726 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:04,726 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 09:49:04,727 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:04,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,727 INFO L182 omatonBuilderFactory]: Interpolants [1824#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))), 1825#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 1826#(and (= 0 |cstrcat_#in~s.offset|) (or (<= 3 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)))), 1827#(and (= cstrcat_~s.offset 0) (or (<= 3 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 1828#(and (= cstrcat_~s.offset 0) (or (<= 3 (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 1829#(and (<= 3 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 1830#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 1831#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 1818#true, 1819#false, 1820#(<= 1 main_~length1~0), 1821#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 1822#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 1823#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0))] [2018-02-02 09:49:04,727 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:04,727 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 09:49:04,727 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 09:49:04,728 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:49:04,728 INFO L87 Difference]: Start difference. First operand 66 states and 73 transitions. Second operand 14 states. [2018-02-02 09:49:05,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:05,094 INFO L93 Difference]: Finished difference Result 87 states and 97 transitions. [2018-02-02 09:49:05,094 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 09:49:05,094 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 28 [2018-02-02 09:49:05,094 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:05,095 INFO L225 Difference]: With dead ends: 87 [2018-02-02 09:49:05,095 INFO L226 Difference]: Without dead ends: 87 [2018-02-02 09:49:05,096 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=95, Invalid=457, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:49:05,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-02-02 09:49:05,100 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 78. [2018-02-02 09:49:05,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-02-02 09:49:05,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 88 transitions. [2018-02-02 09:49:05,101 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 88 transitions. Word has length 28 [2018-02-02 09:49:05,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:05,102 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 88 transitions. [2018-02-02 09:49:05,102 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 09:49:05,102 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 88 transitions. [2018-02-02 09:49:05,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:49:05,102 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:05,103 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:05,103 INFO L371 AbstractCegarLoop]: === Iteration 17 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:05,103 INFO L82 PathProgramCache]: Analyzing trace with hash 1309566295, now seen corresponding path program 1 times [2018-02-02 09:49:05,104 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:05,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:05,117 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:05,266 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:05,266 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:05,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-02-02 09:49:05,267 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:05,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:05,267 INFO L182 omatonBuilderFactory]: Interpolants [2017#true, 2018#false, 2019#(<= 1 main_~length1~0), 2020#(and (<= 1 main_~length1~0) (<= main_~length2~0 2)), 2021#(and (<= main_~length2~0 (+ main_~length3~0 1)) (<= 1 main_~length1~0)), 2022#(and (<= 1 main_~length1~0) (<= main_~length1~0 1)), 2023#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1) (<= main_~length1~0 1)), 2024#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2025#(and (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2026#(and (<= 1 main_~length1~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2027#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2028#(= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) |cstrcat_#in~append.offset|)), 2029#(= 0 (select (select |#memory_int| cstrcat_~append.base) cstrcat_~append.offset)), 2030#(= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 2031#(= |cstrcat_#t~mem5| 0)] [2018-02-02 09:49:05,267 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:05,267 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 09:49:05,267 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 09:49:05,267 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:49:05,267 INFO L87 Difference]: Start difference. First operand 78 states and 88 transitions. Second operand 15 states. [2018-02-02 09:49:05,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:05,589 INFO L93 Difference]: Finished difference Result 161 states and 178 transitions. [2018-02-02 09:49:05,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:49:05,590 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 29 [2018-02-02 09:49:05,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:05,591 INFO L225 Difference]: With dead ends: 161 [2018-02-02 09:49:05,591 INFO L226 Difference]: Without dead ends: 161 [2018-02-02 09:49:05,591 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=233, Invalid=889, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:49:05,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-02-02 09:49:05,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 135. [2018-02-02 09:49:05,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-02 09:49:05,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 154 transitions. [2018-02-02 09:49:05,595 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 154 transitions. Word has length 29 [2018-02-02 09:49:05,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:05,595 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 154 transitions. [2018-02-02 09:49:05,595 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 09:49:05,595 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 154 transitions. [2018-02-02 09:49:05,596 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:49:05,596 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:05,596 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:05,597 INFO L371 AbstractCegarLoop]: === Iteration 18 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:05,597 INFO L82 PathProgramCache]: Analyzing trace with hash 1528421013, now seen corresponding path program 1 times [2018-02-02 09:49:05,597 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:05,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:05,607 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:05,763 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:05,763 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:05,763 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 09:49:05,764 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:05,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:05,764 INFO L182 omatonBuilderFactory]: Interpolants [2368#(<= 1 main_~length1~0), 2369#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 2370#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (= (select |#valid| main_~nondetString1~0.base) 1)) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2371#(and (<= 1 main_~length1~0) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base |main_#t~malloc10.base|))) (= main_~nondetString1~0.offset 0)), 2372#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2373#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 2 (select |#length| main_~nondetString1~0.base)))), 2374#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) |cstrcat_#in~append.offset|)) (<= 2 (select |#length| |cstrcat_#in~append.base|))) (= 0 |cstrcat_#in~append.offset|)), 2375#(and (or (= 0 (select (select |#memory_int| cstrcat_~append.base) cstrcat_~append.offset)) (<= 2 (select |#length| cstrcat_~append.base))) (= 0 cstrcat_~append.offset)), 2376#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (or (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (<= (+ cstrcat_~append.offset 1) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset)))), 2377#(or (and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)) (= |cstrcat_#t~mem5| 0)), 2378#(and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)), 2379#(and (<= 1 |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|))), 2366#true, 2367#false] [2018-02-02 09:49:05,764 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:05,764 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 09:49:05,764 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 09:49:05,764 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=152, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:49:05,765 INFO L87 Difference]: Start difference. First operand 135 states and 154 transitions. Second operand 14 states. [2018-02-02 09:49:06,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:06,032 INFO L93 Difference]: Finished difference Result 144 states and 165 transitions. [2018-02-02 09:49:06,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:49:06,032 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-02-02 09:49:06,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:06,034 INFO L225 Difference]: With dead ends: 144 [2018-02-02 09:49:06,034 INFO L226 Difference]: Without dead ends: 144 [2018-02-02 09:49:06,034 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=418, Unknown=0, NotChecked=0, Total=506 [2018-02-02 09:49:06,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-02 09:49:06,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 140. [2018-02-02 09:49:06,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-02-02 09:49:06,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 161 transitions. [2018-02-02 09:49:06,039 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 161 transitions. Word has length 29 [2018-02-02 09:49:06,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:06,039 INFO L432 AbstractCegarLoop]: Abstraction has 140 states and 161 transitions. [2018-02-02 09:49:06,039 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 09:49:06,040 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 161 transitions. [2018-02-02 09:49:06,040 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 09:49:06,040 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:06,041 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:06,041 INFO L371 AbstractCegarLoop]: === Iteration 19 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:06,041 INFO L82 PathProgramCache]: Analyzing trace with hash 1438570336, now seen corresponding path program 1 times [2018-02-02 09:49:06,041 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:06,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:06,047 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:06,119 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:06,120 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:06,120 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 09:49:06,120 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:06,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:06,120 INFO L182 omatonBuilderFactory]: Interpolants [2688#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 2689#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 2690#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 2682#true, 2683#false, 2684#(<= 2 main_~length2~0), 2685#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 2686#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 2687#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|)))] [2018-02-02 09:49:06,120 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:06,120 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 09:49:06,121 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 09:49:06,121 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-02-02 09:49:06,121 INFO L87 Difference]: Start difference. First operand 140 states and 161 transitions. Second operand 9 states. [2018-02-02 09:49:06,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:06,233 INFO L93 Difference]: Finished difference Result 153 states and 175 transitions. [2018-02-02 09:49:06,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:49:06,233 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-02-02 09:49:06,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:06,234 INFO L225 Difference]: With dead ends: 153 [2018-02-02 09:49:06,234 INFO L226 Difference]: Without dead ends: 153 [2018-02-02 09:49:06,234 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2018-02-02 09:49:06,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-02-02 09:49:06,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 145. [2018-02-02 09:49:06,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-02-02 09:49:06,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 165 transitions. [2018-02-02 09:49:06,238 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 165 transitions. Word has length 29 [2018-02-02 09:49:06,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:06,239 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 165 transitions. [2018-02-02 09:49:06,239 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 09:49:06,239 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 165 transitions. [2018-02-02 09:49:06,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-02 09:49:06,239 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:06,239 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:06,239 INFO L371 AbstractCegarLoop]: === Iteration 20 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:06,239 INFO L82 PathProgramCache]: Analyzing trace with hash -1106610309, now seen corresponding path program 2 times [2018-02-02 09:49:06,240 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:06,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:06,250 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:06,696 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:06,697 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:06,697 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 09:49:06,697 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:06,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:06,697 INFO L182 omatonBuilderFactory]: Interpolants [3008#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 3009#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (or (not (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (= main_~nondetString1~0.offset 0)), 3010#(and (or (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (or (not (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))) (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) (* 2 main_~nondetString1~0.offset)))) (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 3011#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (or (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))) (= main_~nondetString1~0.offset 0)), 3012#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 3 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1))) (<= 4 (select |#length| |cstrcat_#in~s.base|)))), 3013#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= 4 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 3 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 3014#(and (= cstrcat_~s.offset 0) (or (<= 4 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 3 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 3015#(and (or (<= 4 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 3 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 3016#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 3017#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 3018#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 3019#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 3020#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 3021#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 3001#true, 3002#false, 3003#(<= 1 main_~length1~0), 3004#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3005#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3006#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3007#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:49:06,697 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:06,698 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 09:49:06,698 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 09:49:06,698 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=356, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:49:06,698 INFO L87 Difference]: Start difference. First operand 145 states and 165 transitions. Second operand 21 states. [2018-02-02 09:49:07,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:07,205 INFO L93 Difference]: Finished difference Result 181 states and 206 transitions. [2018-02-02 09:49:07,205 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:49:07,205 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2018-02-02 09:49:07,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:07,205 INFO L225 Difference]: With dead ends: 181 [2018-02-02 09:49:07,206 INFO L226 Difference]: Without dead ends: 181 [2018-02-02 09:49:07,206 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=195, Invalid=995, Unknown=0, NotChecked=0, Total=1190 [2018-02-02 09:49:07,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-02-02 09:49:07,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 157. [2018-02-02 09:49:07,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-02-02 09:49:07,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 180 transitions. [2018-02-02 09:49:07,211 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 180 transitions. Word has length 32 [2018-02-02 09:49:07,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:07,211 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 180 transitions. [2018-02-02 09:49:07,211 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 09:49:07,211 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 180 transitions. [2018-02-02 09:49:07,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-02 09:49:07,212 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:07,212 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:07,212 INFO L371 AbstractCegarLoop]: === Iteration 21 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:07,212 INFO L82 PathProgramCache]: Analyzing trace with hash 53168317, now seen corresponding path program 2 times [2018-02-02 09:49:07,213 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:07,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:07,220 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:07,279 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:07,279 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:07,279 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 09:49:07,279 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:07,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:07,280 INFO L182 omatonBuilderFactory]: Interpolants [3392#(= 0 |cstrcat_#in~s.offset|), 3393#(= cstrcat_~s.offset 0), 3394#(<= 1 cstrcat_~s.offset), 3395#(<= 2 cstrcat_~s.offset), 3396#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 3397#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 3388#true, 3389#false, 3390#(= 0 |main_#t~malloc10.offset|), 3391#(= 0 main_~nondetString2~0.offset)] [2018-02-02 09:49:07,280 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:07,280 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:49:07,280 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:49:07,280 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:49:07,280 INFO L87 Difference]: Start difference. First operand 157 states and 180 transitions. Second operand 10 states. [2018-02-02 09:49:07,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:07,375 INFO L93 Difference]: Finished difference Result 162 states and 184 transitions. [2018-02-02 09:49:07,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 09:49:07,375 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 33 [2018-02-02 09:49:07,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:07,376 INFO L225 Difference]: With dead ends: 162 [2018-02-02 09:49:07,376 INFO L226 Difference]: Without dead ends: 162 [2018-02-02 09:49:07,376 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=186, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:49:07,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-02 09:49:07,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 149. [2018-02-02 09:49:07,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-02-02 09:49:07,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 169 transitions. [2018-02-02 09:49:07,381 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 169 transitions. Word has length 33 [2018-02-02 09:49:07,381 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:07,381 INFO L432 AbstractCegarLoop]: Abstraction has 149 states and 169 transitions. [2018-02-02 09:49:07,381 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:49:07,381 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 169 transitions. [2018-02-02 09:49:07,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-02 09:49:07,382 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:07,382 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:07,382 INFO L371 AbstractCegarLoop]: === Iteration 22 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:07,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1452172801, now seen corresponding path program 2 times [2018-02-02 09:49:07,383 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:07,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:07,400 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:07,772 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:07,772 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:07,773 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:49:07,773 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:07,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:07,773 INFO L182 omatonBuilderFactory]: Interpolants [3721#true, 3722#false, 3723#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 3724#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 3725#(and (or (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (not (= (+ main_~nondetString1~0.offset main_~length1~0) 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 3726#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 3727#(and (or (<= 3 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) 1)))) (= main_~nondetString1~0.offset 0)), 3728#(and (or (<= (select |#length| |cstrcat_#in~append.base|) 1) (and (= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) 1)) (not (= |cstrcat_#in~append.base| |cstrcat_#in~s.base|))) (<= 3 (select |#length| |cstrcat_#in~append.base|))) (= 0 |cstrcat_#in~append.offset|)), 3729#(and (or (and (not (= cstrcat_~append.base cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~append.base) 1))) (<= (select |#length| cstrcat_~append.base) 1) (<= 3 (select |#length| cstrcat_~append.base))) (= 0 cstrcat_~append.offset)), 3730#(and (or (<= (+ cstrcat_~append.offset 2) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (= 0 (select (select |#memory_int| cstrcat_~append.base) 1)) (<= cstrcat_~append.offset (+ |cstrcat_#t~post3.offset| 1)) (not (= |cstrcat_#t~post2.base| cstrcat_~append.base))) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset)), 3731#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~append.offset 2) (select |#length| cstrcat_~append.base)) (and (= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~append.base) 1)) (<= cstrcat_~append.offset 1))) (<= 1 cstrcat_~append.offset)), 3732#(and (or (and (<= cstrcat_~append.offset 1) (= 0 (select (select |#memory_int| cstrcat_~append.base) 1))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~append.offset 2) (select |#length| cstrcat_~append.base))) (<= 1 cstrcat_~append.offset)), 3733#(and (<= 2 cstrcat_~append.offset) (or (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (and (= 1 |cstrcat_#t~post3.offset|) (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))), 3734#(and (<= 2 cstrcat_~append.offset) (or (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (= |cstrcat_#t~mem5| 0))), 3735#(and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 2 cstrcat_~append.offset)), 3736#(and (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)) (<= 2 |cstrcat_#t~post3.offset|))] [2018-02-02 09:49:07,773 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:07,773 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:49:07,774 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:49:07,774 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:49:07,774 INFO L87 Difference]: Start difference. First operand 149 states and 169 transitions. Second operand 16 states. [2018-02-02 09:49:08,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:08,165 INFO L93 Difference]: Finished difference Result 161 states and 184 transitions. [2018-02-02 09:49:08,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:49:08,166 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-02-02 09:49:08,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:08,166 INFO L225 Difference]: With dead ends: 161 [2018-02-02 09:49:08,166 INFO L226 Difference]: Without dead ends: 161 [2018-02-02 09:49:08,167 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=82, Invalid=470, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:49:08,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-02-02 09:49:08,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 154. [2018-02-02 09:49:08,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-02-02 09:49:08,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 176 transitions. [2018-02-02 09:49:08,169 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 176 transitions. Word has length 34 [2018-02-02 09:49:08,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:08,169 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 176 transitions. [2018-02-02 09:49:08,169 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:49:08,169 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 176 transitions. [2018-02-02 09:49:08,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-02 09:49:08,169 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:08,169 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:08,169 INFO L371 AbstractCegarLoop]: === Iteration 23 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:08,170 INFO L82 PathProgramCache]: Analyzing trace with hash 357476204, now seen corresponding path program 1 times [2018-02-02 09:49:08,170 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:08,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:08,176 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:08,358 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:08,358 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:08,358 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:49:08,358 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:08,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:08,359 INFO L182 omatonBuilderFactory]: Interpolants [4068#true, 4069#false, 4070#(<= 1 main_~length3~0), 4071#(<= (+ main_~length1~0 1) main_~length2~0), 4072#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4073#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 4074#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc10.base|))), 4075#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 4076#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 4077#(and (= 0 |cstrcat_#in~s.offset|) (<= (+ (select |#length| |cstrcat_#in~append.base|) 1) (select |#length| |cstrcat_#in~s.base|)) (= 0 |cstrcat_#in~append.offset|)), 4078#(and (<= (+ (select |#length| cstrcat_~append.base) 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 4079#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 4080#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 2 cstrcat_~s.offset)), 4081#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 2 cstrcat_~s.offset)), 4082#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 2 |cstrcat_#t~post2.offset|)), 4083#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:49:08,359 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:08,359 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:49:08,359 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:49:08,360 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:49:08,360 INFO L87 Difference]: Start difference. First operand 154 states and 176 transitions. Second operand 16 states. [2018-02-02 09:49:08,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:08,717 INFO L93 Difference]: Finished difference Result 187 states and 212 transitions. [2018-02-02 09:49:08,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:49:08,717 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-02-02 09:49:08,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:08,718 INFO L225 Difference]: With dead ends: 187 [2018-02-02 09:49:08,718 INFO L226 Difference]: Without dead ends: 187 [2018-02-02 09:49:08,718 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=124, Invalid=688, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:49:08,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-02-02 09:49:08,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 172. [2018-02-02 09:49:08,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-02-02 09:49:08,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 198 transitions. [2018-02-02 09:49:08,721 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 198 transitions. Word has length 34 [2018-02-02 09:49:08,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:08,721 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 198 transitions. [2018-02-02 09:49:08,721 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:49:08,721 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 198 transitions. [2018-02-02 09:49:08,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:49:08,721 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:08,721 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:08,721 INFO L371 AbstractCegarLoop]: === Iteration 24 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:08,722 INFO L82 PathProgramCache]: Analyzing trace with hash -679902947, now seen corresponding path program 1 times [2018-02-02 09:49:08,722 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:08,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:08,726 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:08,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:08,765 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:49:08,765 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:49:08,765 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:08,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:08,765 INFO L182 omatonBuilderFactory]: Interpolants [4469#true, 4470#false, 4471#(= |#valid| |old(#valid)|), 4472#(and (= (store |#valid| |main_#t~malloc9.base| 0) |old(#valid)|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4473#(and (= (store (store |#valid| |main_#t~malloc9.base| 0) |main_#t~malloc10.base| 0) |old(#valid)|) (not (= |main_#t~malloc9.base| |main_#t~malloc10.base|))), 4474#(= |old(#valid)| (store |#valid| |main_#t~malloc10.base| 0))] [2018-02-02 09:49:08,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:08,765 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:49:08,765 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:49:08,766 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:49:08,766 INFO L87 Difference]: Start difference. First operand 172 states and 198 transitions. Second operand 6 states. [2018-02-02 09:49:08,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:08,842 INFO L93 Difference]: Finished difference Result 171 states and 197 transitions. [2018-02-02 09:49:08,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:49:08,843 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-02 09:49:08,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:08,843 INFO L225 Difference]: With dead ends: 171 [2018-02-02 09:49:08,843 INFO L226 Difference]: Without dead ends: 130 [2018-02-02 09:49:08,844 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:49:08,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-02-02 09:49:08,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 125. [2018-02-02 09:49:08,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-02 09:49:08,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 134 transitions. [2018-02-02 09:49:08,846 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 134 transitions. Word has length 35 [2018-02-02 09:49:08,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:08,846 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 134 transitions. [2018-02-02 09:49:08,846 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:49:08,846 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 134 transitions. [2018-02-02 09:49:08,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:49:08,847 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:08,847 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:08,847 INFO L371 AbstractCegarLoop]: === Iteration 25 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:08,847 INFO L82 PathProgramCache]: Analyzing trace with hash -2067683903, now seen corresponding path program 1 times [2018-02-02 09:49:08,848 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:08,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:08,857 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:09,056 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:09,057 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:09,057 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:49:09,057 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:09,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:09,057 INFO L182 omatonBuilderFactory]: Interpolants [4775#true, 4776#false, 4777#(<= 1 main_~length3~0), 4778#(<= (+ main_~length1~0 1) main_~length2~0), 4779#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4780#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 4781#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc10.base|))), 4782#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 4783#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 4784#(and (= 0 |cstrcat_#in~s.offset|) (<= (+ (select |#length| |cstrcat_#in~append.base|) 1) (select |#length| |cstrcat_#in~s.base|)) (= 0 |cstrcat_#in~append.offset|)), 4785#(and (<= (+ (select |#length| cstrcat_~append.base) 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 4786#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 4787#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 4788#(and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 4789#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 2 cstrcat_~s.offset)), 4790#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset| 1) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 2 |cstrcat_#t~post2.offset|)), 4791#(and (<= (+ |cstrcat_#t~post2.offset| 2) (select |#length| |cstrcat_#t~post2.base|)) (<= 2 |cstrcat_#t~post2.offset|))] [2018-02-02 09:49:09,057 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:09,057 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:49:09,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:49:09,057 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:49:09,058 INFO L87 Difference]: Start difference. First operand 125 states and 134 transitions. Second operand 17 states. [2018-02-02 09:49:09,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:09,366 INFO L93 Difference]: Finished difference Result 135 states and 144 transitions. [2018-02-02 09:49:09,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 09:49:09,366 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 35 [2018-02-02 09:49:09,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:09,367 INFO L225 Difference]: With dead ends: 135 [2018-02-02 09:49:09,367 INFO L226 Difference]: Without dead ends: 135 [2018-02-02 09:49:09,367 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=128, Invalid=684, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:49:09,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-02-02 09:49:09,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 116. [2018-02-02 09:49:09,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-02-02 09:49:09,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 125 transitions. [2018-02-02 09:49:09,369 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 125 transitions. Word has length 35 [2018-02-02 09:49:09,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:09,369 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 125 transitions. [2018-02-02 09:49:09,370 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:49:09,370 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 125 transitions. [2018-02-02 09:49:09,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 09:49:09,370 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:09,370 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:09,370 INFO L371 AbstractCegarLoop]: === Iteration 26 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:09,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1017556222, now seen corresponding path program 3 times [2018-02-02 09:49:09,371 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:09,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:09,382 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:09,799 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:09,799 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:09,799 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-02 09:49:09,799 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:09,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:09,800 INFO L182 omatonBuilderFactory]: Interpolants [5088#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset)), 5089#(and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 5067#true, 5068#false, 5069#(<= 1 main_~length1~0), 5070#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5071#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5072#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5073#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 5074#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 5075#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 5076#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 5077#(and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= 0 main_~nondetString2~0.offset) (= main_~nondetString1~0.offset 0)), 5078#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (<= 5 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1))))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 5079#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrcat_~s.base))))), 5080#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0) (and (or (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 5081#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrcat_~s.base))))), 5082#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 5083#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0))), 5084#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 5085#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= 2 cstrcat_~s.offset)), 5086#(and (<= 2 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 5087#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))] [2018-02-02 09:49:09,800 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:09,800 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-02 09:49:09,800 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-02 09:49:09,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=445, Unknown=0, NotChecked=0, Total=506 [2018-02-02 09:49:09,800 INFO L87 Difference]: Start difference. First operand 116 states and 125 transitions. Second operand 23 states. [2018-02-02 09:49:10,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:10,418 INFO L93 Difference]: Finished difference Result 141 states and 152 transitions. [2018-02-02 09:49:10,418 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:49:10,418 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 36 [2018-02-02 09:49:10,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:10,418 INFO L225 Difference]: With dead ends: 141 [2018-02-02 09:49:10,418 INFO L226 Difference]: Without dead ends: 141 [2018-02-02 09:49:10,419 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 289 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=165, Invalid=1241, Unknown=0, NotChecked=0, Total=1406 [2018-02-02 09:49:10,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-02-02 09:49:10,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 124. [2018-02-02 09:49:10,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-02 09:49:10,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 134 transitions. [2018-02-02 09:49:10,421 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 134 transitions. Word has length 36 [2018-02-02 09:49:10,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:10,422 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 134 transitions. [2018-02-02 09:49:10,422 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-02 09:49:10,422 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 134 transitions. [2018-02-02 09:49:10,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 09:49:10,422 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:10,422 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:10,423 INFO L371 AbstractCegarLoop]: === Iteration 27 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:10,423 INFO L82 PathProgramCache]: Analyzing trace with hash 1572046895, now seen corresponding path program 2 times [2018-02-02 09:49:10,424 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:10,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:10,436 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:10,687 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:10,688 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:10,688 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-02 09:49:10,688 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:10,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:10,688 INFO L182 omatonBuilderFactory]: Interpolants [5385#true, 5386#false, 5387#(<= 1 main_~length3~0), 5388#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 5389#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 5390#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 5391#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 5392#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))), 5393#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)), 5394#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 5395#(and (= 0 |cstrcat_#in~s.offset|) (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= (+ (select |#length| |cstrcat_#in~append.base|) 2) (select |#length| |cstrcat_#in~s.base|)))), 5396#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (<= (+ (select |#length| cstrcat_~append.base) 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 5397#(and (or (<= (+ (select |#length| cstrcat_~append.base) 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 5398#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (<= (+ (select |#length| cstrcat_~append.base) 2) (select |#length| cstrcat_~s.base))), 5399#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 5400#(and (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 5401#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 3 cstrcat_~s.offset)), 5402#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 3 cstrcat_~s.offset)), 5403#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 3 |cstrcat_#t~post2.offset|)), 5404#(and (<= 3 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:49:10,689 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:10,689 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-02 09:49:10,689 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-02 09:49:10,689 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=331, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:49:10,689 INFO L87 Difference]: Start difference. First operand 124 states and 134 transitions. Second operand 20 states. [2018-02-02 09:49:11,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:11,072 INFO L93 Difference]: Finished difference Result 145 states and 155 transitions. [2018-02-02 09:49:11,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 09:49:11,072 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 38 [2018-02-02 09:49:11,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:11,073 INFO L225 Difference]: With dead ends: 145 [2018-02-02 09:49:11,073 INFO L226 Difference]: Without dead ends: 145 [2018-02-02 09:49:11,073 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 205 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=128, Invalid=864, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:49:11,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-02 09:49:11,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 124. [2018-02-02 09:49:11,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-02 09:49:11,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 134 transitions. [2018-02-02 09:49:11,076 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 134 transitions. Word has length 38 [2018-02-02 09:49:11,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:11,076 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 134 transitions. [2018-02-02 09:49:11,076 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-02 09:49:11,076 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 134 transitions. [2018-02-02 09:49:11,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 09:49:11,077 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:11,077 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:11,077 INFO L371 AbstractCegarLoop]: === Iteration 28 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:11,077 INFO L82 PathProgramCache]: Analyzing trace with hash 1543171285, now seen corresponding path program 3 times [2018-02-02 09:49:11,078 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:11,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:11,087 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:11,328 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:49:11,341 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:11,341 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 09:49:11,341 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:11,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:11,341 INFO L182 omatonBuilderFactory]: Interpolants [5698#true, 5699#false, 5700#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 5701#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 5702#(and (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 5703#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5704#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5705#(and (= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1)))) (not (= |cstrcat_#in~append.base| |cstrcat_#in~s.base|))), 5706#(and (not (= cstrcat_~append.base cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1))))), 5707#(and (not (= cstrcat_~append.base cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| |cstrcat_#t~post3.base|) (- 1)))) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (not (= |cstrcat_#t~post2.base| cstrcat_~append.base))), 5708#(and (= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (not (= cstrcat_~append.base cstrcat_~s.base))), 5709#(and (= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (not (= |cstrcat_#t~post2.base| cstrcat_~append.base))), 5710#(= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))), 5711#(= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))), 5712#(or (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (or (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset))), 5713#(or (and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)) (= |cstrcat_#t~mem5| 0)), 5714#(and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)), 5715#(and (<= 1 |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)))] [2018-02-02 09:49:11,341 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 09:49:11,341 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 09:49:11,342 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 09:49:11,342 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:49:11,342 INFO L87 Difference]: Start difference. First operand 124 states and 134 transitions. Second operand 18 states. [2018-02-02 09:49:11,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:11,672 INFO L93 Difference]: Finished difference Result 123 states and 132 transitions. [2018-02-02 09:49:11,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 09:49:11,673 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-02-02 09:49:11,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:11,673 INFO L225 Difference]: With dead ends: 123 [2018-02-02 09:49:11,673 INFO L226 Difference]: Without dead ends: 93 [2018-02-02 09:49:11,673 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=140, Invalid=672, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:49:11,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-02-02 09:49:11,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 84. [2018-02-02 09:49:11,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-02-02 09:49:11,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 88 transitions. [2018-02-02 09:49:11,675 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 88 transitions. Word has length 39 [2018-02-02 09:49:11,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:11,675 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 88 transitions. [2018-02-02 09:49:11,675 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 09:49:11,675 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 88 transitions. [2018-02-02 09:49:11,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-02 09:49:11,675 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:11,675 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:11,675 INFO L371 AbstractCegarLoop]: === Iteration 29 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:11,675 INFO L82 PathProgramCache]: Analyzing trace with hash -11114239, now seen corresponding path program 4 times [2018-02-02 09:49:11,676 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:11,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:11,688 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:12,279 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:12,280 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:12,280 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:49:12,280 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:12,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:12,280 INFO L182 omatonBuilderFactory]: Interpolants [5952#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 5953#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 5954#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 5955#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (or (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 5956#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (<= 5 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 5957#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (<= 5 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= cstrcat_~s.offset 0)), 5958#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (<= 5 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0)) (= cstrcat_~s.offset 0)), 5959#(and (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (<= 5 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 5960#(and (= cstrcat_~s.offset 1) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 5961#(and (= cstrcat_~s.offset 1) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0))), 5962#(and (= cstrcat_~s.offset 1) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 5963#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 5964#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 5965#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 5966#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 5967#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 5968#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 5969#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 5970#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 5971#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 5945#true, 5946#false, 5947#(<= 1 main_~length1~0), 5948#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5949#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5950#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5951#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:49:12,280 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:12,280 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:49:12,280 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:49:12,281 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=610, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:49:12,281 INFO L87 Difference]: Start difference. First operand 84 states and 88 transitions. Second operand 27 states. [2018-02-02 09:49:13,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:13,088 INFO L93 Difference]: Finished difference Result 107 states and 113 transitions. [2018-02-02 09:49:13,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:49:13,088 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 40 [2018-02-02 09:49:13,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:13,089 INFO L225 Difference]: With dead ends: 107 [2018-02-02 09:49:13,089 INFO L226 Difference]: Without dead ends: 107 [2018-02-02 09:49:13,089 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 462 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=284, Invalid=1696, Unknown=0, NotChecked=0, Total=1980 [2018-02-02 09:49:13,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-02-02 09:49:13,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 92. [2018-02-02 09:49:13,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-02-02 09:49:13,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 97 transitions. [2018-02-02 09:49:13,092 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 97 transitions. Word has length 40 [2018-02-02 09:49:13,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:13,092 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 97 transitions. [2018-02-02 09:49:13,092 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:49:13,092 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 97 transitions. [2018-02-02 09:49:13,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 09:49:13,093 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:13,093 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:13,093 INFO L371 AbstractCegarLoop]: === Iteration 30 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:13,093 INFO L82 PathProgramCache]: Analyzing trace with hash 862211954, now seen corresponding path program 3 times [2018-02-02 09:49:13,094 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:13,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:13,103 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:13,609 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:13,609 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:13,609 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:49:13,609 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:13,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:13,609 INFO L182 omatonBuilderFactory]: Interpolants [6208#false, 6209#(<= 1 main_~length3~0), 6210#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 6211#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 6212#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 6213#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 6214#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 6215#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 6216#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 6217#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 6218#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset))) (= cstrcat_~s.offset 0)), 6219#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (= |cstrcat_#t~mem1| 0) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 6220#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))), 6221#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 6222#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= |cstrcat_#t~mem1| 0))), 6223#(and (<= cstrcat_~s.offset 1) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (< 0 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 6224#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 6225#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 6226#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (and (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset))), 6227#(or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (and (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset))), 6228#(or (and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset)), 6229#(or (and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 6230#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 6207#true] [2018-02-02 09:49:13,610 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:13,610 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:49:13,610 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:49:13,610 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=488, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:49:13,610 INFO L87 Difference]: Start difference. First operand 92 states and 97 transitions. Second operand 24 states. [2018-02-02 09:49:14,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:14,204 INFO L93 Difference]: Finished difference Result 102 states and 107 transitions. [2018-02-02 09:49:14,204 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-02 09:49:14,205 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 42 [2018-02-02 09:49:14,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:14,205 INFO L225 Difference]: With dead ends: 102 [2018-02-02 09:49:14,205 INFO L226 Difference]: Without dead ends: 102 [2018-02-02 09:49:14,206 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=165, Invalid=1241, Unknown=0, NotChecked=0, Total=1406 [2018-02-02 09:49:14,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-02-02 09:49:14,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 97. [2018-02-02 09:49:14,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-02 09:49:14,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 102 transitions. [2018-02-02 09:49:14,208 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 102 transitions. Word has length 42 [2018-02-02 09:49:14,208 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:14,208 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 102 transitions. [2018-02-02 09:49:14,208 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:49:14,208 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 102 transitions. [2018-02-02 09:49:14,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 09:49:14,209 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:14,209 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:14,209 INFO L371 AbstractCegarLoop]: === Iteration 31 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:14,209 INFO L82 PathProgramCache]: Analyzing trace with hash 737307524, now seen corresponding path program 5 times [2018-02-02 09:49:14,210 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:14,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:14,222 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:15,140 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:15,140 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:15,140 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-02 09:49:15,140 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:15,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:15,141 INFO L182 omatonBuilderFactory]: Interpolants [6464#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 6465#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 6466#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 6467#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 6468#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ main_~nondetString1~0.offset (+ (select |#length| main_~nondetString2~0.base) (- 1))) (- 1)))))) (and (or (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 6469#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (<= 5 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 6470#(and (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= 6 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 6471#(and (= cstrcat_~s.offset 0) (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= 6 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 6472#(and (= cstrcat_~s.offset 0) (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= 6 (select |#length| cstrcat_~s.base))))), 6473#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 6474#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 6475#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 6476#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 6477#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 6478#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 6479#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 6480#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 6481#(and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 6482#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 6483#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= 0 cstrcat_~s.offset)), 6484#(and (<= 0 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 6485#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 6486#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 6458#true, 6459#false, 6460#(<= 1 main_~length1~0), 6461#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6462#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6463#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0))] [2018-02-02 09:49:15,141 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:15,141 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-02 09:49:15,141 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-02 09:49:15,142 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=710, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:49:15,142 INFO L87 Difference]: Start difference. First operand 97 states and 102 transitions. Second operand 29 states. [2018-02-02 09:49:16,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:16,456 INFO L93 Difference]: Finished difference Result 124 states and 131 transitions. [2018-02-02 09:49:16,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 09:49:16,456 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 44 [2018-02-02 09:49:16,456 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:16,457 INFO L225 Difference]: With dead ends: 124 [2018-02-02 09:49:16,457 INFO L226 Difference]: Without dead ends: 124 [2018-02-02 09:49:16,457 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 592 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=335, Invalid=2115, Unknown=0, NotChecked=0, Total=2450 [2018-02-02 09:49:16,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-02-02 09:49:16,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 105. [2018-02-02 09:49:16,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-02-02 09:49:16,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 111 transitions. [2018-02-02 09:49:16,459 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 111 transitions. Word has length 44 [2018-02-02 09:49:16,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:16,459 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 111 transitions. [2018-02-02 09:49:16,459 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-02 09:49:16,459 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 111 transitions. [2018-02-02 09:49:16,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 09:49:16,460 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:16,460 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:16,460 INFO L371 AbstractCegarLoop]: === Iteration 32 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:16,460 INFO L82 PathProgramCache]: Analyzing trace with hash -1458979531, now seen corresponding path program 4 times [2018-02-02 09:49:16,460 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:16,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:16,468 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:17,479 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:17,479 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:17,479 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:49:17,479 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:17,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:17,480 INFO L182 omatonBuilderFactory]: Interpolants [6784#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 6758#true, 6759#false, 6760#(<= 1 main_~length3~0), 6761#(and (<= 1 main_~length3~0) (or (= main_~length2~0 (+ main_~length3~0 main_~length1~0)) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0) 1) (* 2 main_~length2~0)))), 6762#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length3~0) (or (= main_~length2~0 (+ main_~length3~0 main_~length1~0)) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0) 1) (* 2 main_~length2~0))) (= (select |#valid| |main_#t~malloc9.base|) 1)), 6763#(and (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= main_~length3~0 (div (+ main_~length2~0 (+ main_~nondetString1~0.offset (- 2))) 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 6764#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (<= main_~length3~0 (div (+ (select |#length| |main_#t~malloc10.base|) (+ main_~nondetString1~0.offset (- 2))) 2))) (= main_~nondetString1~0.offset 0)), 6765#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (= (+ main_~length1~0 1) (+ main_~nondetString2~0.offset main_~length3~0)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString1~0.offset (* 2 main_~length1~0)) (select |#length| main_~nondetString2~0.base))) (<= main_~length3~0 (div (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 2))) 2)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~length3~0 1))) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~length3~0 1))))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 6766#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (select |#length| main_~nondetString1~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (= (+ main_~nondetString2~0.offset main_~length3~0) (+ (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2) 1)) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (<= (+ (* 2 main_~length3~0) 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 6767#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (select |#length| main_~nondetString1~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (<= 6 (+ (* 2 main_~nondetString2~0.offset) (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 6768#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (and (or (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 2) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (div (select |#length| |cstrcat_#in~s.base|) 2)))) (<= (select |#length| |cstrcat_#in~append.base|) (div (select |#length| |cstrcat_#in~s.base|) 2))) (<= 2 (div (+ (select |#length| |cstrcat_#in~s.base|) (- 2)) 2))) (= 0 |cstrcat_#in~append.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 6769#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 cstrcat_~append.offset) (or (and (<= (select |#length| cstrcat_~append.base) (div (select |#length| cstrcat_~s.base) 2)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (select |#length| cstrcat_~s.base) 2))) (<= (+ (select |#length| cstrcat_~append.base) 1) (div (select |#length| cstrcat_~s.base) 2)))) (<= 6 (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 6770#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (and (<= (select |#length| cstrcat_~append.base) (div (select |#length| cstrcat_~s.base) 2)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (select |#length| cstrcat_~s.base) 2))) (<= (+ (select |#length| cstrcat_~append.base) 1) (div (select |#length| cstrcat_~s.base) 2)))) (<= 6 (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)) (= cstrcat_~s.offset 0)), 6771#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (and (<= (select |#length| cstrcat_~append.base) (div (select |#length| cstrcat_~s.base) 2)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (select |#length| cstrcat_~s.base) 2))) (<= (+ (select |#length| cstrcat_~append.base) 1) (div (select |#length| cstrcat_~s.base) 2)))) (<= 6 (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 6772#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)))))) (= 0 cstrcat_~append.offset)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 6773#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)))))) (= 0 cstrcat_~append.offset))), 6774#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)))))) (= 0 cstrcat_~append.offset)), 6775#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 6776#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 6777#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 6778#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 6779#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 6780#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset) (or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 6781#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 6782#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 6783#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))))] [2018-02-02 09:49:17,480 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:17,480 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:49:17,480 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:49:17,480 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=630, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:49:17,480 INFO L87 Difference]: Start difference. First operand 105 states and 111 transitions. Second operand 27 states. [2018-02-02 09:49:18,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:18,528 INFO L93 Difference]: Finished difference Result 119 states and 125 transitions. [2018-02-02 09:49:18,528 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:49:18,528 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 46 [2018-02-02 09:49:18,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:18,528 INFO L225 Difference]: With dead ends: 119 [2018-02-02 09:49:18,528 INFO L226 Difference]: Without dead ends: 119 [2018-02-02 09:49:18,529 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=196, Invalid=1696, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 09:49:18,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-02 09:49:18,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 105. [2018-02-02 09:49:18,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-02-02 09:49:18,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 111 transitions. [2018-02-02 09:49:18,530 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 111 transitions. Word has length 46 [2018-02-02 09:49:18,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:18,530 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 111 transitions. [2018-02-02 09:49:18,531 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:49:18,531 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 111 transitions. [2018-02-02 09:49:18,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 09:49:18,531 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:18,531 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:18,531 INFO L371 AbstractCegarLoop]: === Iteration 33 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:18,531 INFO L82 PathProgramCache]: Analyzing trace with hash -620008806, now seen corresponding path program 5 times [2018-02-02 09:49:18,532 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:18,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:18,542 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:19,069 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:19,070 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:19,070 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:49:19,070 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:19,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:19,070 INFO L182 omatonBuilderFactory]: Interpolants [7043#true, 7044#false, 7045#(<= 1 main_~length3~0), 7046#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7047#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7048#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 7049#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 7050#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 7051#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 7052#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7053#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 7054#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset))) (= cstrcat_~s.offset 0)), 7055#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (= |cstrcat_#t~mem1| 0) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 7056#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))), 7057#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 7058#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= |cstrcat_#t~mem1| 0))), 7059#(and (<= cstrcat_~s.offset 1) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (< 0 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7060#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7061#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset)), 7062#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (<= 4 cstrcat_~s.offset) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 7063#(and (<= 4 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 7064#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 5 cstrcat_~s.offset)), 7065#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 5 |cstrcat_#t~post2.offset|)), 7066#(and (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)) (<= 5 |cstrcat_#t~post2.offset|))] [2018-02-02 09:49:19,070 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:19,070 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:49:19,070 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:49:19,071 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:49:19,071 INFO L87 Difference]: Start difference. First operand 105 states and 111 transitions. Second operand 24 states. [2018-02-02 09:49:19,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:19,619 INFO L93 Difference]: Finished difference Result 124 states and 130 transitions. [2018-02-02 09:49:19,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 09:49:19,620 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 47 [2018-02-02 09:49:19,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:19,620 INFO L225 Difference]: With dead ends: 124 [2018-02-02 09:49:19,620 INFO L226 Difference]: Without dead ends: 109 [2018-02-02 09:49:19,621 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=159, Invalid=1323, Unknown=0, NotChecked=0, Total=1482 [2018-02-02 09:49:19,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-02-02 09:49:19,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 105. [2018-02-02 09:49:19,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-02-02 09:49:19,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 110 transitions. [2018-02-02 09:49:19,623 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 110 transitions. Word has length 47 [2018-02-02 09:49:19,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:19,623 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 110 transitions. [2018-02-02 09:49:19,623 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:49:19,624 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 110 transitions. [2018-02-02 09:49:19,624 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 09:49:19,624 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:19,624 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:19,624 INFO L371 AbstractCegarLoop]: === Iteration 34 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:19,624 INFO L82 PathProgramCache]: Analyzing trace with hash -839682937, now seen corresponding path program 6 times [2018-02-02 09:49:19,625 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:19,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:19,640 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:20,982 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:20,983 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:20,983 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-02 09:49:20,983 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:20,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:20,983 INFO L182 omatonBuilderFactory]: Interpolants [7326#true, 7327#false, 7328#(<= 1 main_~length1~0), 7329#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7330#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7331#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7332#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 7333#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7334#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 7335#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 7336#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 7337#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1))))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 7338#(and (or (and (<= 7 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))))) (= cstrcat_~s.offset 0)), 7339#(and (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0))), 7340#(and (or (and (<= 7 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))))) (= cstrcat_~s.offset 0)), 7341#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 7342#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 7343#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 7344#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 7345#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 7346#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 7347#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7348#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 7349#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7350#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 7351#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 7352#(and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7353#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 7354#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 7355#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 7356#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 7357#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 7358#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-02 09:49:20,983 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:20,984 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-02 09:49:20,984 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-02 09:49:20,984 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=145, Invalid=911, Unknown=0, NotChecked=0, Total=1056 [2018-02-02 09:49:20,984 INFO L87 Difference]: Start difference. First operand 105 states and 110 transitions. Second operand 33 states. [2018-02-02 09:49:22,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:22,618 INFO L93 Difference]: Finished difference Result 132 states and 139 transitions. [2018-02-02 09:49:22,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 09:49:22,620 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 48 [2018-02-02 09:49:22,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:22,620 INFO L225 Difference]: With dead ends: 132 [2018-02-02 09:49:22,620 INFO L226 Difference]: Without dead ends: 132 [2018-02-02 09:49:22,621 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 808 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=481, Invalid=2711, Unknown=0, NotChecked=0, Total=3192 [2018-02-02 09:49:22,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-02-02 09:49:22,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 113. [2018-02-02 09:49:22,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-02 09:49:22,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 119 transitions. [2018-02-02 09:49:22,623 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 119 transitions. Word has length 48 [2018-02-02 09:49:22,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:22,623 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 119 transitions. [2018-02-02 09:49:22,623 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-02 09:49:22,623 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 119 transitions. [2018-02-02 09:49:22,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 09:49:22,623 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:22,623 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:22,623 INFO L371 AbstractCegarLoop]: === Iteration 35 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:22,623 INFO L82 PathProgramCache]: Analyzing trace with hash -823357064, now seen corresponding path program 6 times [2018-02-02 09:49:22,624 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:22,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:22,637 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:23,172 WARN L146 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 105 DAG size of output 32 [2018-02-02 09:49:23,302 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 117 DAG size of output 62 [2018-02-02 09:49:24,447 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 0 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:24,447 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:24,447 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-02 09:49:24,448 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:24,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:24,449 INFO L182 omatonBuilderFactory]: Interpolants [7680#(and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 7652#true, 7653#false, 7654#(<= 1 main_~length3~0), 7655#(and (<= 1 main_~length3~0) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0)) (* 2 main_~length2~0))), 7656#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length3~0) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0)) (* 2 main_~length2~0)) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7657#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 7658#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7659#(and (or (and (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= 0 main_~nondetString2~0.offset)), 7660#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 3) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ (* 2 main_~length3~0) 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)))), 7661#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) 1) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ (* 2 main_~nondetString2~0.offset) (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) 2)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base))) (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (or (<= 3 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base)))))) (= main_~nondetString1~0.offset 0)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7662#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (div (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 2) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~append.base|) 2) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 3) (select |#length| |cstrcat_#in~s.base|))))) (<= (select |#length| |cstrcat_#in~append.base|) (div (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) 2))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (select |#length| |cstrcat_#in~append.base|))) (<= 3 (select |#length| |cstrcat_#in~append.base|))) (<= (* 2 (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1))))) (<= 7 (select |#length| |cstrcat_#in~s.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 7663#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (<= 7 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (<= 3 (select |#length| cstrcat_~append.base))) (<= (* 2 (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1))))))) (<= (select |#length| cstrcat_~append.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 7664#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (<= 7 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (<= 3 (select |#length| cstrcat_~append.base))) (<= (* 2 (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1))))))) (<= (select |#length| cstrcat_~append.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (= |cstrcat_#t~mem1| 0))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 7665#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (<= 7 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (<= 3 (select |#length| cstrcat_~append.base))) (<= (* 2 (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1))))))) (<= (select |#length| cstrcat_~append.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2)))))) (= cstrcat_~s.offset 0)), 7666#(or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1)) (or (<= 3 (select |#length| cstrcat_~append.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2) 1))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 7667#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1)) (or (<= 3 (select |#length| cstrcat_~append.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2) 1))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset))), 7668#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1)) (or (<= 3 (select |#length| cstrcat_~append.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2) 1))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7669#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))))), 7670#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)))), 7671#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 7672#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 7673#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= 3 cstrcat_~s.offset))), 7674#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7675#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 7676#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset))), 7677#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (and (<= 6 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 7678#(or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (and (<= 6 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 7679#(or (and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))] [2018-02-02 09:49:24,449 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 0 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:24,449 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-02 09:49:24,449 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-02 09:49:24,450 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=738, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:49:24,450 INFO L87 Difference]: Start difference. First operand 113 states and 119 transitions. Second operand 29 states. [2018-02-02 09:49:25,113 WARN L146 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 102 DAG size of output 101 [2018-02-02 09:49:25,494 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 111 DAG size of output 110 [2018-02-02 09:49:26,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:26,386 INFO L93 Difference]: Finished difference Result 127 states and 133 transitions. [2018-02-02 09:49:26,387 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 09:49:26,387 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 50 [2018-02-02 09:49:26,387 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:26,387 INFO L225 Difference]: With dead ends: 127 [2018-02-02 09:49:26,387 INFO L226 Difference]: Without dead ends: 127 [2018-02-02 09:49:26,388 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=197, Invalid=2059, Unknown=0, NotChecked=0, Total=2256 [2018-02-02 09:49:26,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-02-02 09:49:26,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 113. [2018-02-02 09:49:26,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-02 09:49:26,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 119 transitions. [2018-02-02 09:49:26,390 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 119 transitions. Word has length 50 [2018-02-02 09:49:26,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:26,390 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 119 transitions. [2018-02-02 09:49:26,390 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-02 09:49:26,390 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 119 transitions. [2018-02-02 09:49:26,390 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-02 09:49:26,391 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:26,391 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:26,391 INFO L371 AbstractCegarLoop]: === Iteration 36 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:26,391 INFO L82 PathProgramCache]: Analyzing trace with hash 1904418487, now seen corresponding path program 7 times [2018-02-02 09:49:26,391 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:26,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:26,403 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:27,345 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:27,345 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:27,345 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-02 09:49:27,345 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:27,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:27,346 INFO L182 omatonBuilderFactory]: Interpolants [7959#true, 7960#false, 7961#(<= 1 main_~length3~0), 7962#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7963#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7964#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 7965#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7966#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))), 7967#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)), 7968#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7969#(and (= 0 |cstrcat_#in~s.offset|) (= 0 |cstrcat_#in~append.offset|) (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 7970#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 7971#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 7972#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 7973#(and (or (and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))) (= 0 cstrcat_~append.offset)), 7974#(and (= 0 cstrcat_~append.offset) (or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))))), 7975#(and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 7976#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 2))), 7977#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2) (= |cstrcat_#t~mem1| 0)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7978#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 7979#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 7980#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))), 7981#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 1))) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset 1)) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= 5 cstrcat_~s.offset)), 7982#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) (* 2 cstrcat_~append.offset) 2))) (<= 5 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset 1))), 7983#(and (<= 6 cstrcat_~s.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) (* 2 cstrcat_~append.offset) 1)) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset 1))), 7984#(and (<= 6 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 7985#(and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:49:27,346 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:27,346 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-02 09:49:27,346 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-02 09:49:27,346 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=634, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:49:27,346 INFO L87 Difference]: Start difference. First operand 113 states and 119 transitions. Second operand 27 states. [2018-02-02 09:49:28,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:28,150 INFO L93 Difference]: Finished difference Result 132 states and 138 transitions. [2018-02-02 09:49:28,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-02 09:49:28,150 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 51 [2018-02-02 09:49:28,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:28,151 INFO L225 Difference]: With dead ends: 132 [2018-02-02 09:49:28,151 INFO L226 Difference]: Without dead ends: 132 [2018-02-02 09:49:28,151 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=173, Invalid=1633, Unknown=0, NotChecked=0, Total=1806 [2018-02-02 09:49:28,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-02-02 09:49:28,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 118. [2018-02-02 09:49:28,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-02 09:49:28,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 124 transitions. [2018-02-02 09:49:28,153 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 124 transitions. Word has length 51 [2018-02-02 09:49:28,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:28,153 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 124 transitions. [2018-02-02 09:49:28,153 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-02 09:49:28,153 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 124 transitions. [2018-02-02 09:49:28,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-02 09:49:28,153 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:28,153 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:28,153 INFO L371 AbstractCegarLoop]: === Iteration 37 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:28,154 INFO L82 PathProgramCache]: Analyzing trace with hash 108151818, now seen corresponding path program 7 times [2018-02-02 09:49:28,154 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:28,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:28,169 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:28,633 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 125 DAG size of output 62 [2018-02-02 09:49:30,153 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:30,153 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:30,153 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-02-02 09:49:30,153 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:30,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:30,154 INFO L182 omatonBuilderFactory]: Interpolants [8268#true, 8269#false, 8270#(<= 1 main_~length1~0), 8271#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8272#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8273#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8274#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 8275#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 8276#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8277#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8278#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (- 1))))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 8279#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (<= 7 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (or (<= 9 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 8280#(and (= cstrcat_~s.offset 0) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 8 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1))))))), 8281#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 8 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 8282#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 8 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 8283#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 8284#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 8285#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 8286#(or (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8287#(or (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 8288#(and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 8289#(or (and (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (<= 3 cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8290#(or (and (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (<= 3 cstrcat_~s.offset)) (= |cstrcat_#t~mem1| 0)), 8291#(and (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (<= 3 cstrcat_~s.offset)), 8292#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 4 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))))), 8293#(or (and (<= 4 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 8294#(and (<= 4 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 8295#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8296#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset)) (= |cstrcat_#t~mem1| 0)), 8297#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset)), 8298#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 6 cstrcat_~s.offset)), 8299#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 6 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 8300#(and (<= 6 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 8301#(and (<= 7 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 8302#(and (<= 8 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-02 09:49:30,154 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:30,154 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-02-02 09:49:30,154 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-02-02 09:49:30,155 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=1097, Unknown=0, NotChecked=0, Total=1190 [2018-02-02 09:49:30,155 INFO L87 Difference]: Start difference. First operand 118 states and 124 transitions. Second operand 35 states. [2018-02-02 09:49:31,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:31,993 INFO L93 Difference]: Finished difference Result 149 states and 157 transitions. [2018-02-02 09:49:31,993 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-02 09:49:31,993 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 52 [2018-02-02 09:49:31,993 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:31,993 INFO L225 Difference]: With dead ends: 149 [2018-02-02 09:49:31,993 INFO L226 Difference]: Without dead ends: 149 [2018-02-02 09:49:31,994 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 853 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=269, Invalid=3513, Unknown=0, NotChecked=0, Total=3782 [2018-02-02 09:49:31,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-02-02 09:49:31,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 126. [2018-02-02 09:49:31,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-02 09:49:31,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 133 transitions. [2018-02-02 09:49:31,996 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 133 transitions. Word has length 52 [2018-02-02 09:49:31,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:31,996 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 133 transitions. [2018-02-02 09:49:31,996 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-02-02 09:49:31,996 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 133 transitions. [2018-02-02 09:49:31,996 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-02 09:49:31,996 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:31,997 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:31,997 INFO L371 AbstractCegarLoop]: === Iteration 38 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:31,997 INFO L82 PathProgramCache]: Analyzing trace with hash -487224261, now seen corresponding path program 8 times [2018-02-02 09:49:31,998 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:32,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:32,014 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:33,334 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 0 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:33,334 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:33,334 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-02 09:49:33,334 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:33,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:33,335 INFO L182 omatonBuilderFactory]: Interpolants [8640#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))), 8641#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 4) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 3) (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 8642#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|)))) (= 0 |cstrcat_#in~append.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 8643#(and (= cstrcat_~s.offset 0) (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8644#(and (= cstrcat_~s.offset 0) (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 8645#(and (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1))) (= cstrcat_~s.offset 0)), 8646#(or (and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8647#(or (and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0))), 8648#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 8649#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8650#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))))) (= |cstrcat_#t~mem1| 0)), 8651#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))))), 8652#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8653#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)), 8654#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 8655#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 8656#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 8657#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 8658#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset))), 8659#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 6 cstrcat_~s.offset))), 8660#(or (and (<= 7 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset))), 8661#(or (and (<= 7 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset)), 8662#(or (and (<= 7 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 8663#(and (<= 7 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 8632#true, 8633#false, 8634#(<= 1 main_~length3~0), 8635#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8636#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 8637#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 8638#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 8639#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-02-02 09:49:33,335 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 0 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:33,335 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-02 09:49:33,335 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-02 09:49:33,335 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=910, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:49:33,336 INFO L87 Difference]: Start difference. First operand 126 states and 133 transitions. Second operand 32 states. [2018-02-02 09:49:34,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:34,865 INFO L93 Difference]: Finished difference Result 144 states and 151 transitions. [2018-02-02 09:49:34,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 09:49:34,866 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 54 [2018-02-02 09:49:34,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:34,866 INFO L225 Difference]: With dead ends: 144 [2018-02-02 09:49:34,866 INFO L226 Difference]: Without dead ends: 144 [2018-02-02 09:49:34,867 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 669 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=223, Invalid=2639, Unknown=0, NotChecked=0, Total=2862 [2018-02-02 09:49:34,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-02 09:49:34,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 126. [2018-02-02 09:49:34,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-02 09:49:34,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 133 transitions. [2018-02-02 09:49:34,868 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 133 transitions. Word has length 54 [2018-02-02 09:49:34,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:34,869 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 133 transitions. [2018-02-02 09:49:34,869 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-02 09:49:34,869 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 133 transitions. [2018-02-02 09:49:34,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-02-02 09:49:34,869 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:34,870 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:34,870 INFO L371 AbstractCegarLoop]: === Iteration 39 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:34,870 INFO L82 PathProgramCache]: Analyzing trace with hash -560366508, now seen corresponding path program 9 times [2018-02-02 09:49:34,870 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:34,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:34,884 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:36,135 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:36,135 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:36,135 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-02-02 09:49:36,135 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:36,135 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:36,136 INFO L182 omatonBuilderFactory]: Interpolants [8978#true, 8979#false, 8980#(<= 1 main_~length3~0), 8981#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8982#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 8983#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 8984#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 8985#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 8986#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2))), 8987#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (not (= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ (select |#length| main_~nondetString1~0.base) 1))) (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 8988#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (select |#length| |cstrcat_#in~append.base|))) (not (= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (+ (select |#length| |cstrcat_#in~append.base|) 1))) (- 1)))))) (= 0 |cstrcat_#in~append.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 8989#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (+ (select |#length| cstrcat_~append.base) 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8990#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (+ (select |#length| cstrcat_~append.base) 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 8991#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (+ (select |#length| cstrcat_~append.base) 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 8992#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (or (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (- 1)))) (- 1)))))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8993#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (or (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (- 1)))) (- 1)))))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0))), 8994#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (or (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (- 1)))) (- 1)))))))), 8995#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))))) (not (= (select |#length| cstrcat_~append.base) 3)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8996#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))))) (not (= (select |#length| cstrcat_~append.base) 3)))) (= |cstrcat_#t~mem1| 0)), 8997#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))))) (not (= (select |#length| cstrcat_~append.base) 3)))), 8998#(or (and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 2))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))), 8999#(or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (or (<= (select |#length| cstrcat_~append.base) 2) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset))), 9000#(or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 2))), 9001#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 9002#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 9003#(or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (and (<= (select |#length| |cstrcat_#t~post3.base|) 2) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset))), 9004#(or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))), 9005#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 9006#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 9007#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 9008#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:49:36,136 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:36,136 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-02 09:49:36,136 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-02 09:49:36,136 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=832, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:49:36,136 INFO L87 Difference]: Start difference. First operand 126 states and 133 transitions. Second operand 31 states. [2018-02-02 09:49:37,081 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 98 DAG size of output 92 [2018-02-02 09:49:37,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:37,612 INFO L93 Difference]: Finished difference Result 154 states and 161 transitions. [2018-02-02 09:49:37,612 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 09:49:37,612 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 55 [2018-02-02 09:49:37,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:37,613 INFO L225 Difference]: With dead ends: 154 [2018-02-02 09:49:37,613 INFO L226 Difference]: Without dead ends: 154 [2018-02-02 09:49:37,614 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 639 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=289, Invalid=2261, Unknown=0, NotChecked=0, Total=2550 [2018-02-02 09:49:37,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-02 09:49:37,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 126. [2018-02-02 09:49:37,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-02 09:49:37,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 133 transitions. [2018-02-02 09:49:37,615 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 133 transitions. Word has length 55 [2018-02-02 09:49:37,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:37,615 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 133 transitions. [2018-02-02 09:49:37,615 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-02 09:49:37,615 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 133 transitions. [2018-02-02 09:49:37,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 09:49:37,616 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:37,616 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:37,616 INFO L371 AbstractCegarLoop]: === Iteration 40 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:37,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1888771701, now seen corresponding path program 10 times [2018-02-02 09:49:37,617 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:37,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:37,624 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:38,242 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:38,242 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:38,242 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-02 09:49:38,242 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:38,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:38,242 INFO L182 omatonBuilderFactory]: Interpolants [9344#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 9345#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 9346#(and (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 9347#(and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset)), 9348#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 9349#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 9350#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 9351#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 2)) (= |cstrcat_#t~post3.offset| 0)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 9352#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 2))), 9353#(or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))), 9354#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 9355#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 9356#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 9357#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 9329#true, 9330#false, 9331#(<= 1 main_~length3~0), 9332#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 9333#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 9334#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 9335#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 9336#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 9337#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)))), 9338#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 9339#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 9340#(and (or (and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1))) (= cstrcat_~s.offset 0)), 9341#(and (= cstrcat_~s.offset 0) (or (and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 9342#(and (or (and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1))) (= cstrcat_~s.offset 0)), 9343#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))))] [2018-02-02 09:49:38,243 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:38,243 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-02 09:49:38,243 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-02 09:49:38,243 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=724, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:49:38,243 INFO L87 Difference]: Start difference. First operand 126 states and 133 transitions. Second operand 29 states. [2018-02-02 09:49:39,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:39,267 INFO L93 Difference]: Finished difference Result 154 states and 161 transitions. [2018-02-02 09:49:39,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 09:49:39,268 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 56 [2018-02-02 09:49:39,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:39,268 INFO L225 Difference]: With dead ends: 154 [2018-02-02 09:49:39,268 INFO L226 Difference]: Without dead ends: 154 [2018-02-02 09:49:39,269 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 653 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=281, Invalid=2371, Unknown=0, NotChecked=0, Total=2652 [2018-02-02 09:49:39,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-02 09:49:39,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 131. [2018-02-02 09:49:39,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-02-02 09:49:39,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 138 transitions. [2018-02-02 09:49:39,270 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 138 transitions. Word has length 56 [2018-02-02 09:49:39,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:39,270 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 138 transitions. [2018-02-02 09:49:39,270 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-02 09:49:39,270 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 138 transitions. [2018-02-02 09:49:39,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 09:49:39,271 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:39,271 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:39,271 INFO L371 AbstractCegarLoop]: === Iteration 41 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:39,271 INFO L82 PathProgramCache]: Analyzing trace with hash 1009228301, now seen corresponding path program 8 times [2018-02-02 09:49:39,272 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:39,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:39,286 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:39,897 WARN L146 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 171 DAG size of output 69 [2018-02-02 09:49:40,016 WARN L146 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 133 DAG size of output 59 [2018-02-02 09:49:40,171 WARN L146 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 133 DAG size of output 59 [2018-02-02 09:49:40,360 WARN L146 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 135 DAG size of output 59 [2018-02-02 09:49:40,540 WARN L146 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 133 DAG size of output 57 [2018-02-02 09:49:40,713 WARN L146 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 149 DAG size of output 67 [2018-02-02 09:49:40,904 WARN L146 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 151 DAG size of output 67 [2018-02-02 09:49:41,075 WARN L146 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 149 DAG size of output 65 [2018-02-02 09:49:42,216 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:42,239 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:42,239 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38] total 38 [2018-02-02 09:49:42,239 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:42,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:42,240 INFO L182 omatonBuilderFactory]: Interpolants [9689#true, 9690#false, 9691#(<= 1 main_~length1~0), 9692#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9693#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9694#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9695#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 9696#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 9697#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 9698#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 9699#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1))))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 9700#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (<= 10 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1))))) (<= 9 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 9701#(and (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))))), 9702#(and (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0))), 9703#(and (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))))) (= cstrcat_~s.offset 0)), 9704#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 9705#(and (or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 9706#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 9707#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 9708#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 9709#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 9710#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 9711#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 9712#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 9713#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 9714#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 9715#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 9716#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 9717#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 9718#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 9719#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 9720#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 9721#(and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 9722#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 9723#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 9724#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 9725#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 9726#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 9727#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-02 09:49:42,240 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:42,240 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-02-02 09:49:42,240 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-02-02 09:49:42,241 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=218, Invalid=1264, Unknown=0, NotChecked=0, Total=1482 [2018-02-02 09:49:42,241 INFO L87 Difference]: Start difference. First operand 131 states and 138 transitions. Second operand 39 states. [2018-02-02 09:49:42,984 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 118 DAG size of output 117 [2018-02-02 09:49:43,310 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 112 DAG size of output 109 [2018-02-02 09:49:43,665 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 105 DAG size of output 102 [2018-02-02 09:49:45,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:45,053 INFO L93 Difference]: Finished difference Result 172 states and 181 transitions. [2018-02-02 09:49:45,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-02 09:49:45,054 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 56 [2018-02-02 09:49:45,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:45,054 INFO L225 Difference]: With dead ends: 172 [2018-02-02 09:49:45,054 INFO L226 Difference]: Without dead ends: 172 [2018-02-02 09:49:45,055 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1247 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=746, Invalid=3946, Unknown=0, NotChecked=0, Total=4692 [2018-02-02 09:49:45,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-02 09:49:45,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 139. [2018-02-02 09:49:45,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-02 09:49:45,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-02 09:49:45,058 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 56 [2018-02-02 09:49:45,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:45,058 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-02 09:49:45,058 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-02-02 09:49:45,058 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-02 09:49:45,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-02 09:49:45,059 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:45,059 INFO L351 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:45,059 INFO L371 AbstractCegarLoop]: === Iteration 42 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:45,059 INFO L82 PathProgramCache]: Analyzing trace with hash -2136117890, now seen corresponding path program 11 times [2018-02-02 09:49:45,060 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:45,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:45,086 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:45,757 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 49 DAG size of output 26 [2018-02-02 09:49:46,163 WARN L146 SmtUtils]: Spent 301ms on a formula simplification. DAG size of input: 154 DAG size of output 103 [2018-02-02 09:49:46,355 WARN L146 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 127 DAG size of output 84 [2018-02-02 09:49:46,572 WARN L146 SmtUtils]: Spent 198ms on a formula simplification. DAG size of input: 127 DAG size of output 84 [2018-02-02 09:49:46,791 WARN L146 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 129 DAG size of output 84 [2018-02-02 09:49:47,000 WARN L146 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 127 DAG size of output 82 [2018-02-02 09:49:47,239 WARN L146 SmtUtils]: Spent 197ms on a formula simplification. DAG size of input: 150 DAG size of output 93 [2018-02-02 09:49:47,464 WARN L146 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 152 DAG size of output 93 [2018-02-02 09:49:47,705 WARN L146 SmtUtils]: Spent 201ms on a formula simplification. DAG size of input: 150 DAG size of output 90 [2018-02-02 09:49:48,769 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:48,769 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:48,769 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-02 09:49:48,770 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:48,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:48,770 INFO L182 omatonBuilderFactory]: Interpolants [10112#(and (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (and (<= 3 (div (select |#length| cstrcat_~s.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (select |#length| cstrcat_~s.base) 2) (- 1))))) (<= 9 (select |#length| cstrcat_~s.base)) (and (<= 3 (div (+ (select |#length| cstrcat_~s.base) (- 2)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 10113#(and (= cstrcat_~s.offset 1) (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset 2)) (- 1)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2) (- 1)))) (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2))))), 10114#(and (= cstrcat_~s.offset 1) (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset 2)) (- 1)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2) (- 1)))) (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2))) (= |cstrcat_#t~mem1| 0))), 10115#(and (= cstrcat_~s.offset 1) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset 2)) (- 1)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2) (- 1)))) (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2)))) (= 0 cstrcat_~append.offset)), 10116#(and (= 0 cstrcat_~append.offset) (or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (<= (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (<= cstrcat_~s.offset 2)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 10117#(and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (or (not (= cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (<= (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (<= cstrcat_~s.offset 2)))), 10118#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (not (= cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (<= (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (<= cstrcat_~s.offset 2))) (= 0 cstrcat_~append.offset)), 10119#(or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 10120#(or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 10121#(and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 10122#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= 0 cstrcat_~append.offset)), 10123#(and (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (= |cstrcat_#t~mem1| 0))), 10124#(and (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))))), 10125#(and (or (and (or (<= (select |#length| cstrcat_~append.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset)), 10126#(and (or (and (or (<= (select |#length| cstrcat_~append.base) 1) (= |cstrcat_#t~mem1| 0)) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset)), 10127#(and (= 0 cstrcat_~append.offset) (or (<= (select |#length| cstrcat_~append.base) 1) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 10128#(and (or (<= (select |#length| cstrcat_~append.base) 1) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset)), 10129#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 cstrcat_~append.offset)), 10130#(and (or (< 1 (select |#length| |cstrcat_#t~post3.base|)) (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset))) (or (<= (select |#length| |cstrcat_#t~post3.base|) 1) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 10131#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 10132#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 10133#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 10134#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 10099#true, 10100#false, 10101#(<= 1 main_~length3~0), 10102#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10103#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 10104#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10105#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 10106#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)))) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 10107#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 1 main_~length3~0) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~nondetString2~0.offset main_~length3~0) (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 10108#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 3 (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString1~0.offset) (- 2)))) 2) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString1~0.offset) 3) (+ main_~nondetString1~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 9 (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (<= 3 (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset))) 2) (+ main_~nondetString1~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) 3)))) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (or (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (+ (select |#length| main_~nondetString2~0.base) (- 1))) (+ main_~nondetString2~0.offset (- 1)))))) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))))))) (= main_~nondetString1~0.offset 0)), 10109#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 3 (div (+ (select |#length| |cstrcat_#in~s.base|) (- 2)) 2))) (and (or (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 5) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (+ (select |#length| |cstrcat_#in~s.base|) (- 1))) (- 1))))) (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|)))))) (<= 9 (select |#length| |cstrcat_#in~s.base|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 3)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (div (select |#length| |cstrcat_#in~s.base|) 2) (- 1)))) (<= 3 (div (select |#length| |cstrcat_#in~s.base|) 2))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1))) (= 0 |cstrcat_#in~append.offset|)), 10110#(and (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (and (<= 3 (div (select |#length| cstrcat_~s.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (select |#length| cstrcat_~s.base) 2) (- 1))))) (<= 9 (select |#length| cstrcat_~s.base)) (and (<= 3 (div (+ (select |#length| cstrcat_~s.base) (- 2)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 10111#(and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (and (<= 3 (div (select |#length| cstrcat_~s.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (select |#length| cstrcat_~s.base) 2) (- 1))))) (<= 9 (select |#length| cstrcat_~s.base)) (and (<= 3 (div (+ (select |#length| cstrcat_~s.base) (- 2)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (= cstrcat_~s.offset 0))] [2018-02-02 09:49:48,770 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:48,771 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-02 09:49:48,771 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-02 09:49:48,771 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=1122, Unknown=0, NotChecked=0, Total=1260 [2018-02-02 09:49:48,771 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 36 states. [2018-02-02 09:49:49,134 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 133 DAG size of output 131 [2018-02-02 09:49:49,452 WARN L143 SmtUtils]: Spent 114ms on a formula simplification that was a NOOP. DAG size: 154 [2018-02-02 09:49:50,005 WARN L146 SmtUtils]: Spent 226ms on a formula simplification. DAG size of input: 172 DAG size of output 171 [2018-02-02 09:49:50,358 WARN L146 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 159 DAG size of output 157 [2018-02-02 09:49:50,617 WARN L146 SmtUtils]: Spent 217ms on a formula simplification. DAG size of input: 169 DAG size of output 164 [2018-02-02 09:49:50,868 WARN L146 SmtUtils]: Spent 213ms on a formula simplification. DAG size of input: 155 DAG size of output 154 [2018-02-02 09:49:51,052 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 130 DAG size of output 125 [2018-02-02 09:49:51,239 WARN L146 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 137 DAG size of output 129 [2018-02-02 09:49:51,483 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 115 DAG size of output 113 [2018-02-02 09:49:51,671 WARN L146 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 121 DAG size of output 116 [2018-02-02 09:49:52,095 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 109 DAG size of output 108 [2018-02-02 09:49:52,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:49:52,474 INFO L93 Difference]: Finished difference Result 172 states and 180 transitions. [2018-02-02 09:49:52,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-02 09:49:52,474 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 58 [2018-02-02 09:49:52,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:49:52,475 INFO L225 Difference]: With dead ends: 172 [2018-02-02 09:49:52,475 INFO L226 Difference]: Without dead ends: 172 [2018-02-02 09:49:52,476 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 998 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=457, Invalid=3325, Unknown=0, NotChecked=0, Total=3782 [2018-02-02 09:49:52,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-02 09:49:52,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 139. [2018-02-02 09:49:52,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-02 09:49:52,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-02 09:49:52,477 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 58 [2018-02-02 09:49:52,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:49:52,477 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-02 09:49:52,477 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-02 09:49:52,477 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-02 09:49:52,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 09:49:52,478 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:49:52,478 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:49:52,478 INFO L371 AbstractCegarLoop]: === Iteration 43 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-02 09:49:52,478 INFO L82 PathProgramCache]: Analyzing trace with hash -136461455, now seen corresponding path program 12 times [2018-02-02 09:49:52,478 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:49:52,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:49:52,487 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:49:53,055 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 197 DAG size of output 87 [2018-02-02 09:49:53,178 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 130 DAG size of output 69 [2018-02-02 09:49:54,548 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:54,548 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:49:54,548 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-02 09:49:54,548 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:49:54,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:54,549 INFO L182 omatonBuilderFactory]: Interpolants [10498#true, 10499#false, 10500#(<= 1 main_~length3~0), 10501#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10502#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 10503#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10504#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 10505#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10506#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 10507#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) 1))) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset 1))) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (+ (- main_~nondetString2~0.offset) 3)) (+ (select |#length| main_~nondetString2~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset 2))) (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (+ (- (+ (- main_~nondetString2~0.offset) 3)) (select |#length| main_~nondetString2~0.base))) (select |#length| main_~nondetString2~0.base)) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= main_~nondetString1~0.offset 0)), 10508#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 3 1) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~append.base|) 1) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= 9 (select |#length| |cstrcat_#in~s.base|)) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- 3) (+ (select |#length| |cstrcat_#in~s.base|) (- 1))) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (+ (- 3) (select |#length| |cstrcat_#in~s.base|))) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 2) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~append.base|) 2) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 3) (select |#length| |cstrcat_#in~s.base|))))) (= 0 |cstrcat_#in~append.offset|)), 10509#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s.base))) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1))))))), 10510#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s.base))) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1))))) (= |cstrcat_#t~mem1| 0))), 10511#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s.base))) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1))))))), 10512#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))))) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 1) (- 1))))))), 10513#(and (<= 1 cstrcat_~s.offset) (or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))))) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 1) (- 1)))))) (= 0 cstrcat_~append.offset)), 10514#(and (<= 1 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))))) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 1) (- 1)))))) (= 0 cstrcat_~append.offset)), 10515#(and (or (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 2) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 10516#(and (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 2) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))) (= |cstrcat_#t~mem1| 0) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 10517#(and (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 2) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 10518#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 2) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset)), 10519#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (select |#length| cstrcat_~append.base) 2) (= |cstrcat_#t~mem1| 0) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset)), 10520#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (select |#length| cstrcat_~append.base) 2) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 3 cstrcat_~s.offset)), 10521#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (select |#length| cstrcat_~append.base) 2))), 10522#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 2)) (= |cstrcat_#t~mem1| 0))) (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 10523#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 10524#(and (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2)) (<= 5 cstrcat_~s.offset)), 10525#(and (<= 6 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 10526#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 1))) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= 7 cstrcat_~s.offset)), 10527#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))) (<= 7 cstrcat_~s.offset)), 10528#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= 8 cstrcat_~s.offset)), 10529#(and (<= 8 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 10530#(and (<= 8 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-02 09:49:54,549 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:49:54,549 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-02 09:49:54,549 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-02 09:49:54,550 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=972, Unknown=0, NotChecked=0, Total=1056 [2018-02-02 09:49:54,550 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 33 states. [2018-02-02 09:49:55,302 WARN L146 SmtUtils]: Spent 146ms on a formula simplification. DAG size of input: 142 DAG size of output 141 Received shutdown request... [2018-02-02 09:49:55,324 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 09:49:55,325 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 09:49:55,328 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 09:49:55,328 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 09:49:55 BoogieIcfgContainer [2018-02-02 09:49:55,328 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 09:49:55,329 INFO L168 Benchmark]: Toolchain (without parser) took 54534.42 ms. Allocated memory was 392.2 MB in the beginning and 1.1 GB in the end (delta: 701.5 MB). Free memory was 349.0 MB in the beginning and 370.4 MB in the end (delta: -21.4 MB). Peak memory consumption was 680.1 MB. Max. memory is 5.3 GB. [2018-02-02 09:49:55,329 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 392.2 MB. Free memory is still 354.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 09:49:55,330 INFO L168 Benchmark]: CACSL2BoogieTranslator took 166.25 ms. Allocated memory is still 392.2 MB. Free memory was 349.0 MB in the beginning and 338.5 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:49:55,330 INFO L168 Benchmark]: Boogie Preprocessor took 22.64 ms. Allocated memory is still 392.2 MB. Free memory was 338.5 MB in the beginning and 335.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:49:55,330 INFO L168 Benchmark]: RCFGBuilder took 201.33 ms. Allocated memory is still 392.2 MB. Free memory was 335.8 MB in the beginning and 316.5 MB in the end (delta: 19.3 MB). Peak memory consumption was 19.3 MB. Max. memory is 5.3 GB. [2018-02-02 09:49:55,330 INFO L168 Benchmark]: TraceAbstraction took 54141.31 ms. Allocated memory was 392.2 MB in the beginning and 1.1 GB in the end (delta: 701.5 MB). Free memory was 316.5 MB in the beginning and 370.4 MB in the end (delta: -53.9 MB). Peak memory consumption was 647.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:49:55,332 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 392.2 MB. Free memory is still 354.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 166.25 ms. Allocated memory is still 392.2 MB. Free memory was 349.0 MB in the beginning and 338.5 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 22.64 ms. Allocated memory is still 392.2 MB. Free memory was 338.5 MB in the beginning and 335.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 201.33 ms. Allocated memory is still 392.2 MB. Free memory was 335.8 MB in the beginning and 316.5 MB in the end (delta: 19.3 MB). Peak memory consumption was 19.3 MB. Max. memory is 5.3 GB. * TraceAbstraction took 54141.31 ms. Allocated memory was 392.2 MB in the beginning and 1.1 GB in the end (delta: 701.5 MB). Free memory was 316.5 MB in the beginning and 370.4 MB in the end (delta: -53.9 MB). Peak memory consumption was 647.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 544). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 544). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 564). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 564). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - TimeoutResultAtElement [Line: 548]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 548). Cancelled while BasicCegarLoop was constructing difference of abstraction (139states) and interpolant automaton (currently 15 states, 33 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 42 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 50 locations, 11 error locations. TIMEOUT Result, 54.1s OverallTime, 43 OverallIterations, 10 TraceHistogramMax, 27.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1302 SDtfs, 2691 SDslu, 9484 SDs, 0 SdLazy, 11983 SolverSat, 980 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1218 GetRequests, 53 SyntacticMatches, 6 SemanticMatches, 1158 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10914 ImplicationChecksByTransitivity, 41.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=172occurred in iteration=23, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 31/1294 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 42 MinimizatonAttempts, 528 StatesRemovedByMinimization, 35 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 25.3s InterpolantComputationTime, 1496 NumberOfCodeBlocks, 1496 NumberOfCodeBlocksAsserted, 43 NumberOfCheckSat, 1453 ConstructedInterpolants, 0 QuantifiedInterpolants, 1666962 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 43 InterpolantComputations, 16 PerfectInterpolantSequences, 31/1294 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_09-49-55-337.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_09-49-55-337.csv Completed graceful shutdown