java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-26d9e06-m [2018-02-02 09:50:00,820 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 09:50:00,821 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 09:50:00,831 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 09:50:00,831 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 09:50:00,832 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 09:50:00,832 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 09:50:00,833 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 09:50:00,835 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 09:50:00,835 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 09:50:00,836 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 09:50:00,836 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 09:50:00,837 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 09:50:00,838 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 09:50:00,839 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 09:50:00,841 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 09:50:00,843 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 09:50:00,844 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 09:50:00,845 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 09:50:00,846 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 09:50:00,848 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-02-02 09:50:00,852 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-02 09:50:00,853 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-02 09:50:00,853 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cav18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 09:50:00,863 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 09:50:00,863 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 09:50:00,865 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 09:50:00,865 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 09:50:00,865 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 09:50:00,865 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 09:50:00,865 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 09:50:00,866 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 09:50:00,866 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 09:50:00,866 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 09:50:00,866 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 09:50:00,866 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 09:50:00,867 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 09:50:00,867 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 09:50:00,867 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 09:50:00,867 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 09:50:00,867 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 09:50:00,868 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 09:50:00,868 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 09:50:00,868 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 09:50:00,868 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:50:00,868 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 09:50:00,868 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 09:50:00,898 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 09:50:00,911 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 09:50:00,914 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 09:50:00,915 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 09:50:00,916 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 09:50:00,916 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:50:01,046 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 09:50:01,047 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 09:50:01,048 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 09:50:01,048 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 09:50:01,053 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 09:50:01,054 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,056 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@fdaeb63 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01, skipping insertion in model container [2018-02-02 09:50:01,056 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,069 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:50:01,096 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 09:50:01,187 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:50:01,199 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 09:50:01,204 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01 WrapperNode [2018-02-02 09:50:01,204 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 09:50:01,205 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 09:50:01,205 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 09:50:01,205 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 09:50:01,214 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,214 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,222 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,222 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,231 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,233 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,233 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... [2018-02-02 09:50:01,234 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 09:50:01,235 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 09:50:01,235 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 09:50:01,235 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 09:50:01,236 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 09:50:01,273 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 09:50:01,273 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 09:50:01,274 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrncat [2018-02-02 09:50:01,274 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure cstrncat [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 09:50:01,274 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 09:50:01,275 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 09:50:01,461 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 09:50:01,462 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:50:01 BoogieIcfgContainer [2018-02-02 09:50:01,462 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 09:50:01,462 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 09:50:01,462 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 09:50:01,464 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 09:50:01,464 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 09:50:01" (1/3) ... [2018-02-02 09:50:01,465 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@368851e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:50:01, skipping insertion in model container [2018-02-02 09:50:01,465 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 09:50:01" (2/3) ... [2018-02-02 09:50:01,465 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@368851e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 09:50:01, skipping insertion in model container [2018-02-02 09:50:01,465 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 09:50:01" (3/3) ... [2018-02-02 09:50:01,466 INFO L107 eAbstractionObserver]: Analyzing ICFG openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-02-02 09:50:01,472 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 09:50:01,477 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 13 error locations. [2018-02-02 09:50:01,511 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 09:50:01,511 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 09:50:01,511 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 09:50:01,512 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 09:50:01,512 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 09:50:01,512 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 09:50:01,512 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 09:50:01,512 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 09:50:01,513 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 09:50:01,525 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states. [2018-02-02 09:50:01,534 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-02-02 09:50:01,534 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:01,535 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:01,536 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:01,540 INFO L82 PathProgramCache]: Analyzing trace with hash 2055638365, now seen corresponding path program 1 times [2018-02-02 09:50:01,589 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:01,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:01,623 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:01,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:01,670 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:01,670 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 09:50:01,672 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:01,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:01,672 INFO L182 omatonBuilderFactory]: Interpolants [57#true, 58#false, 59#(= |#valid| |old(#valid)|)] [2018-02-02 09:50:01,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:01,674 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 09:50:01,682 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 09:50:01,683 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:50:01,685 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 3 states. [2018-02-02 09:50:01,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:01,790 INFO L93 Difference]: Finished difference Result 55 states and 62 transitions. [2018-02-02 09:50:01,790 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 09:50:01,844 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-02-02 09:50:01,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:01,854 INFO L225 Difference]: With dead ends: 55 [2018-02-02 09:50:01,854 INFO L226 Difference]: Without dead ends: 51 [2018-02-02 09:50:01,856 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 09:50:01,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-02-02 09:50:01,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-02-02 09:50:01,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-02 09:50:01,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 57 transitions. [2018-02-02 09:50:01,879 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 57 transitions. Word has length 11 [2018-02-02 09:50:01,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:01,879 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 57 transitions. [2018-02-02 09:50:01,879 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 09:50:01,879 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 57 transitions. [2018-02-02 09:50:01,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:50:01,879 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:01,880 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:01,880 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:01,880 INFO L82 PathProgramCache]: Analyzing trace with hash -1872133330, now seen corresponding path program 1 times [2018-02-02 09:50:01,881 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:01,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:01,891 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:01,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:01,961 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:01,961 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:50:01,961 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:01,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:01,962 INFO L182 omatonBuilderFactory]: Interpolants [166#true, 167#false, 168#(<= main_~length1~0 1), 169#(<= main_~length1~0 main_~length2~0), 170#(<= (+ main_~length1~0 1) (+ main_~n~0 main_~length2~0))] [2018-02-02 09:50:01,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:01,963 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:50:01,963 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:50:01,963 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:50:01,963 INFO L87 Difference]: Start difference. First operand 51 states and 57 transitions. Second operand 5 states. [2018-02-02 09:50:02,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:02,048 INFO L93 Difference]: Finished difference Result 54 states and 61 transitions. [2018-02-02 09:50:02,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:50:02,049 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 15 [2018-02-02 09:50:02,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:02,050 INFO L225 Difference]: With dead ends: 54 [2018-02-02 09:50:02,050 INFO L226 Difference]: Without dead ends: 51 [2018-02-02 09:50:02,051 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:50:02,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-02-02 09:50:02,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-02-02 09:50:02,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-02 09:50:02,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 56 transitions. [2018-02-02 09:50:02,055 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 56 transitions. Word has length 15 [2018-02-02 09:50:02,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:02,055 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 56 transitions. [2018-02-02 09:50:02,056 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:50:02,056 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 56 transitions. [2018-02-02 09:50:02,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:50:02,056 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:02,056 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:02,056 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:02,057 INFO L82 PathProgramCache]: Analyzing trace with hash -1192074960, now seen corresponding path program 1 times [2018-02-02 09:50:02,058 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:02,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:02,074 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:02,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,145 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:02,145 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:50:02,146 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:02,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,146 INFO L182 omatonBuilderFactory]: Interpolants [280#true, 281#false, 282#(= 1 (select |#valid| |main_#t~malloc11.base|)), 283#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-02-02 09:50:02,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,147 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:50:02,147 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:50:02,147 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:50:02,147 INFO L87 Difference]: Start difference. First operand 51 states and 56 transitions. Second operand 4 states. [2018-02-02 09:50:02,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:02,316 INFO L93 Difference]: Finished difference Result 50 states and 55 transitions. [2018-02-02 09:50:02,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:50:02,317 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-02-02 09:50:02,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:02,318 INFO L225 Difference]: With dead ends: 50 [2018-02-02 09:50:02,318 INFO L226 Difference]: Without dead ends: 50 [2018-02-02 09:50:02,319 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:50:02,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-02-02 09:50:02,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-02-02 09:50:02,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-02-02 09:50:02,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 55 transitions. [2018-02-02 09:50:02,323 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 55 transitions. Word has length 15 [2018-02-02 09:50:02,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:02,323 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 55 transitions. [2018-02-02 09:50:02,324 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:50:02,324 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 55 transitions. [2018-02-02 09:50:02,324 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-02 09:50:02,324 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:02,324 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:02,325 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:02,325 INFO L82 PathProgramCache]: Analyzing trace with hash -1192074959, now seen corresponding path program 1 times [2018-02-02 09:50:02,326 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:02,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:02,339 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:02,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,439 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:02,439 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 09:50:02,439 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:02,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,439 INFO L182 omatonBuilderFactory]: Interpolants [386#true, 387#false, 388#(<= 1 main_~length2~0), 389#(and (<= 1 main_~length2~0) (<= 1 main_~n~0)), 390#(and (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0)), 391#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0)), 392#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 393#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0))] [2018-02-02 09:50:02,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,440 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 09:50:02,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 09:50:02,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:50:02,440 INFO L87 Difference]: Start difference. First operand 50 states and 55 transitions. Second operand 8 states. [2018-02-02 09:50:02,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:02,537 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-02-02 09:50:02,538 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:50:02,538 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 15 [2018-02-02 09:50:02,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:02,539 INFO L225 Difference]: With dead ends: 49 [2018-02-02 09:50:02,539 INFO L226 Difference]: Without dead ends: 49 [2018-02-02 09:50:02,539 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=84, Unknown=0, NotChecked=0, Total=132 [2018-02-02 09:50:02,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-02-02 09:50:02,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-02-02 09:50:02,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-02-02 09:50:02,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 54 transitions. [2018-02-02 09:50:02,543 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 54 transitions. Word has length 15 [2018-02-02 09:50:02,543 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:02,543 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 54 transitions. [2018-02-02 09:50:02,544 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 09:50:02,544 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 54 transitions. [2018-02-02 09:50:02,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:50:02,544 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:02,544 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:02,544 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:02,545 INFO L82 PathProgramCache]: Analyzing trace with hash 1700381909, now seen corresponding path program 1 times [2018-02-02 09:50:02,545 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:02,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:02,555 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:02,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,574 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:02,574 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-02 09:50:02,574 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:02,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,575 INFO L182 omatonBuilderFactory]: Interpolants [500#true, 501#false, 502#(= 1 (select |#valid| |main_#t~malloc12.base|)), 503#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-02-02 09:50:02,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,575 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 09:50:02,575 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 09:50:02,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 09:50:02,575 INFO L87 Difference]: Start difference. First operand 49 states and 54 transitions. Second operand 4 states. [2018-02-02 09:50:02,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:02,604 INFO L93 Difference]: Finished difference Result 48 states and 53 transitions. [2018-02-02 09:50:02,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 09:50:02,605 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-02-02 09:50:02,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:02,606 INFO L225 Difference]: With dead ends: 48 [2018-02-02 09:50:02,606 INFO L226 Difference]: Without dead ends: 48 [2018-02-02 09:50:02,606 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:50:02,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-02-02 09:50:02,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-02-02 09:50:02,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-02-02 09:50:02,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 53 transitions. [2018-02-02 09:50:02,609 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 53 transitions. Word has length 16 [2018-02-02 09:50:02,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:02,609 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 53 transitions. [2018-02-02 09:50:02,609 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 09:50:02,609 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 53 transitions. [2018-02-02 09:50:02,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-02 09:50:02,609 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:02,609 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:02,610 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:02,610 INFO L82 PathProgramCache]: Analyzing trace with hash 1700381910, now seen corresponding path program 1 times [2018-02-02 09:50:02,611 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:02,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:02,618 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:02,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,673 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:02,673 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 09:50:02,673 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:02,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,673 INFO L182 omatonBuilderFactory]: Interpolants [602#true, 603#false, 604#(<= 1 main_~length2~0), 605#(and (= 0 |main_#t~malloc12.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 606#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))] [2018-02-02 09:50:02,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,674 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:50:02,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:50:02,674 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:50:02,674 INFO L87 Difference]: Start difference. First operand 48 states and 53 transitions. Second operand 5 states. [2018-02-02 09:50:02,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:02,697 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-02-02 09:50:02,697 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:50:02,698 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-02-02 09:50:02,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:02,698 INFO L225 Difference]: With dead ends: 47 [2018-02-02 09:50:02,698 INFO L226 Difference]: Without dead ends: 47 [2018-02-02 09:50:02,698 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:50:02,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-02 09:50:02,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-02-02 09:50:02,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-02-02 09:50:02,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-02-02 09:50:02,701 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 16 [2018-02-02 09:50:02,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:02,701 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-02-02 09:50:02,701 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:50:02,701 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-02-02 09:50:02,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 09:50:02,701 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:02,701 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:02,701 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:02,701 INFO L82 PathProgramCache]: Analyzing trace with hash -275307336, now seen corresponding path program 1 times [2018-02-02 09:50:02,702 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:02,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:02,710 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:02,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,749 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:02,749 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:50:02,749 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:02,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,750 INFO L182 omatonBuilderFactory]: Interpolants [704#false, 705#(= 1 (select |#valid| main_~nondetString1~0.base)), 706#(= 1 (select |#valid| |cstrncat_#in~dst.base|)), 707#(= 1 (select |#valid| cstrncat_~dst.base)), 708#(= 1 (select |#valid| cstrncat_~d~0.base)), 703#true] [2018-02-02 09:50:02,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:02,750 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:50:02,750 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:50:02,750 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:50:02,751 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 6 states. [2018-02-02 09:50:02,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:02,887 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-02-02 09:50:02,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 09:50:02,887 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-02 09:50:02,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:02,889 INFO L225 Difference]: With dead ends: 47 [2018-02-02 09:50:02,890 INFO L226 Difference]: Without dead ends: 47 [2018-02-02 09:50:02,890 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:50:02,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-02 09:50:02,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 44. [2018-02-02 09:50:02,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-02 09:50:02,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 49 transitions. [2018-02-02 09:50:02,893 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 49 transitions. Word has length 21 [2018-02-02 09:50:02,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:02,893 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 49 transitions. [2018-02-02 09:50:02,893 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:50:02,893 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 49 transitions. [2018-02-02 09:50:02,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 09:50:02,894 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:02,894 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:02,894 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:02,894 INFO L82 PathProgramCache]: Analyzing trace with hash -275307335, now seen corresponding path program 1 times [2018-02-02 09:50:02,895 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:02,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:02,908 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:03,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,015 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:03,015 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-02 09:50:03,015 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:03,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,015 INFO L182 omatonBuilderFactory]: Interpolants [804#true, 805#false, 806#(<= 1 main_~length2~0), 807#(<= (+ main_~n~0 1) main_~length1~0), 808#(and (= 0 |main_#t~malloc11.offset|) (<= (+ main_~n~0 1) main_~length1~0)), 809#(and (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 810#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 811#(and (<= 1 (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 812#(and (= 0 cstrncat_~dst.offset) (<= 1 (select |#length| cstrncat_~dst.base))), 813#(and (<= 1 (select |#length| cstrncat_~d~0.base)) (= cstrncat_~d~0.offset 0))] [2018-02-02 09:50:03,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,016 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:50:03,016 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:50:03,016 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:50:03,016 INFO L87 Difference]: Start difference. First operand 44 states and 49 transitions. Second operand 10 states. [2018-02-02 09:50:03,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:03,181 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2018-02-02 09:50:03,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 09:50:03,181 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 21 [2018-02-02 09:50:03,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:03,181 INFO L225 Difference]: With dead ends: 57 [2018-02-02 09:50:03,181 INFO L226 Difference]: Without dead ends: 57 [2018-02-02 09:50:03,182 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=65, Invalid=207, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:50:03,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-02-02 09:50:03,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 52. [2018-02-02 09:50:03,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-02-02 09:50:03,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 61 transitions. [2018-02-02 09:50:03,184 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 61 transitions. Word has length 21 [2018-02-02 09:50:03,184 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:03,184 INFO L432 AbstractCegarLoop]: Abstraction has 52 states and 61 transitions. [2018-02-02 09:50:03,184 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:50:03,184 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 61 transitions. [2018-02-02 09:50:03,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:50:03,184 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:03,184 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:03,184 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:03,185 INFO L82 PathProgramCache]: Analyzing trace with hash 1706718631, now seen corresponding path program 1 times [2018-02-02 09:50:03,185 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:03,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:03,195 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:03,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,240 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:03,241 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 09:50:03,241 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:03,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,241 INFO L182 omatonBuilderFactory]: Interpolants [937#true, 938#false, 939#(= 1 (select |#valid| main_~nondetString2~0.base)), 940#(= 1 (select |#valid| |cstrncat_#in~src.base|)), 941#(= 1 (select |#valid| cstrncat_~src.base)), 942#(= 1 (select |#valid| cstrncat_~s~0.base)), 943#(= 1 (select |#valid| |cstrncat_#t~post3.base|))] [2018-02-02 09:50:03,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,242 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:50:03,242 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:50:03,242 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:50:03,242 INFO L87 Difference]: Start difference. First operand 52 states and 61 transitions. Second operand 7 states. [2018-02-02 09:50:03,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:03,353 INFO L93 Difference]: Finished difference Result 54 states and 62 transitions. [2018-02-02 09:50:03,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:50:03,354 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 24 [2018-02-02 09:50:03,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:03,354 INFO L225 Difference]: With dead ends: 54 [2018-02-02 09:50:03,354 INFO L226 Difference]: Without dead ends: 54 [2018-02-02 09:50:03,355 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:50:03,355 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-02-02 09:50:03,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 51. [2018-02-02 09:50:03,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-02 09:50:03,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 59 transitions. [2018-02-02 09:50:03,358 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 59 transitions. Word has length 24 [2018-02-02 09:50:03,358 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:03,358 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 59 transitions. [2018-02-02 09:50:03,358 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:50:03,358 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 59 transitions. [2018-02-02 09:50:03,359 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:50:03,359 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:03,359 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:03,359 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:03,359 INFO L82 PathProgramCache]: Analyzing trace with hash 1706718632, now seen corresponding path program 1 times [2018-02-02 09:50:03,360 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:03,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:03,369 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:03,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,585 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:03,585 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-02 09:50:03,585 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:03,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,585 INFO L182 omatonBuilderFactory]: Interpolants [1056#false, 1057#(<= 1 main_~length2~0), 1058#(and (= 0 |main_#t~malloc12.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 1059#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 1060#(and (= 0 main_~nondetString2~0.offset) (<= 1 (select |#length| main_~nondetString2~0.base))), 1061#(and (<= 1 (select |#length| |cstrncat_#in~src.base|)) (= 0 |cstrncat_#in~src.offset|)), 1062#(and (= 0 cstrncat_~src.offset) (<= 1 (select |#length| cstrncat_~src.base))), 1063#(and (= 0 cstrncat_~s~0.offset) (<= 1 (select |#length| cstrncat_~s~0.base))), 1064#(and (<= 1 (select |#length| |cstrncat_#t~post3.base|)) (= |cstrncat_#t~post3.offset| 0)), 1055#true] [2018-02-02 09:50:03,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:03,585 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 09:50:03,585 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 09:50:03,585 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:50:03,586 INFO L87 Difference]: Start difference. First operand 51 states and 59 transitions. Second operand 10 states. [2018-02-02 09:50:03,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:03,852 INFO L93 Difference]: Finished difference Result 56 states and 64 transitions. [2018-02-02 09:50:03,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 09:50:03,852 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 24 [2018-02-02 09:50:03,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:03,853 INFO L225 Difference]: With dead ends: 56 [2018-02-02 09:50:03,853 INFO L226 Difference]: Without dead ends: 56 [2018-02-02 09:50:03,853 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:50:03,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-02-02 09:50:03,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 53. [2018-02-02 09:50:03,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-02-02 09:50:03,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 60 transitions. [2018-02-02 09:50:03,857 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 60 transitions. Word has length 24 [2018-02-02 09:50:03,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:03,857 INFO L432 AbstractCegarLoop]: Abstraction has 53 states and 60 transitions. [2018-02-02 09:50:03,857 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 09:50:03,857 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 60 transitions. [2018-02-02 09:50:03,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 09:50:03,858 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:03,858 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:03,858 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:03,859 INFO L82 PathProgramCache]: Analyzing trace with hash 1706720075, now seen corresponding path program 1 times [2018-02-02 09:50:03,859 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:03,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:03,874 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:04,035 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,036 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:04,036 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 09:50:04,036 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:04,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,037 INFO L182 omatonBuilderFactory]: Interpolants [1184#(<= 1 main_~length2~0), 1185#(<= 2 (+ main_~n~0 main_~length2~0)), 1186#(<= 2 main_~length1~0), 1187#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 2 main_~length1~0)), 1188#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 2 main_~length1~0)), 1189#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 2 main_~length1~0)), 1190#(and (= 0 main_~nondetString1~0.offset) (<= 2 (select |#length| main_~nondetString1~0.base))), 1191#(and (<= 2 (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 1192#(and (= 0 cstrncat_~dst.offset) (<= 2 (select |#length| cstrncat_~dst.base))), 1193#(and (<= 2 (select |#length| cstrncat_~d~0.base)) (= cstrncat_~d~0.offset 0)), 1194#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 1182#true, 1183#false] [2018-02-02 09:50:04,037 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,037 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 09:50:04,037 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 09:50:04,037 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:50:04,037 INFO L87 Difference]: Start difference. First operand 53 states and 60 transitions. Second operand 13 states. [2018-02-02 09:50:04,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:04,224 INFO L93 Difference]: Finished difference Result 72 states and 82 transitions. [2018-02-02 09:50:04,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 09:50:04,227 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 24 [2018-02-02 09:50:04,230 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:04,230 INFO L225 Difference]: With dead ends: 72 [2018-02-02 09:50:04,231 INFO L226 Difference]: Without dead ends: 72 [2018-02-02 09:50:04,231 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=85, Invalid=335, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:50:04,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-02-02 09:50:04,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 64. [2018-02-02 09:50:04,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-02-02 09:50:04,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 75 transitions. [2018-02-02 09:50:04,235 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 75 transitions. Word has length 24 [2018-02-02 09:50:04,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:04,236 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 75 transitions. [2018-02-02 09:50:04,236 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 09:50:04,236 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 75 transitions. [2018-02-02 09:50:04,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-02 09:50:04,236 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:04,236 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:04,237 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:04,237 INFO L82 PathProgramCache]: Analyzing trace with hash 1074905977, now seen corresponding path program 2 times [2018-02-02 09:50:04,238 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:04,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:04,251 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:04,509 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,509 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:04,509 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 09:50:04,509 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:04,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,510 INFO L182 omatonBuilderFactory]: Interpolants [1347#true, 1348#false, 1349#(<= 1 main_~n~0), 1350#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 1351#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1352#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1353#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1354#(and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (<= 3 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 1355#(and (or (<= 3 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 1356#(and (or (<= 3 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))) (= 0 cstrncat_~dst.offset)), 1357#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= 3 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 1358#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= 3 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 1359#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 1360#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:04,510 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,510 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 09:50:04,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 09:50:04,510 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=155, Unknown=0, NotChecked=0, Total=182 [2018-02-02 09:50:04,510 INFO L87 Difference]: Start difference. First operand 64 states and 75 transitions. Second operand 14 states. [2018-02-02 09:50:04,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:04,929 INFO L93 Difference]: Finished difference Result 105 states and 120 transitions. [2018-02-02 09:50:04,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:50:04,929 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 27 [2018-02-02 09:50:04,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:04,929 INFO L225 Difference]: With dead ends: 105 [2018-02-02 09:50:04,930 INFO L226 Difference]: Without dead ends: 105 [2018-02-02 09:50:04,930 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=120, Invalid=582, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:50:04,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-02-02 09:50:04,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 67. [2018-02-02 09:50:04,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-02-02 09:50:04,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 79 transitions. [2018-02-02 09:50:04,933 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 79 transitions. Word has length 27 [2018-02-02 09:50:04,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:04,933 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 79 transitions. [2018-02-02 09:50:04,933 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 09:50:04,934 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 79 transitions. [2018-02-02 09:50:04,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 09:50:04,934 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:04,934 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:04,934 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:04,935 INFO L82 PathProgramCache]: Analyzing trace with hash 94248296, now seen corresponding path program 1 times [2018-02-02 09:50:04,935 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:04,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:04,943 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:04,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,986 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:04,986 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:50:04,986 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:04,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,987 INFO L182 omatonBuilderFactory]: Interpolants [1559#true, 1560#false, 1561#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 1562#(and (or (<= cstrncat_~n |cstrncat_#in~n|) (<= (div cstrncat_~n 4294967296) 0)) (or (< 0 (div cstrncat_~n 4294967296)) (<= |cstrncat_#in~n| cstrncat_~n))), 1563#(or (<= 4294967296 |cstrncat_#in~n|) (<= |cstrncat_#in~n| 0))] [2018-02-02 09:50:04,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:04,987 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 09:50:04,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 09:50:04,987 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 09:50:04,987 INFO L87 Difference]: Start difference. First operand 67 states and 79 transitions. Second operand 5 states. [2018-02-02 09:50:05,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:05,018 INFO L93 Difference]: Finished difference Result 97 states and 112 transitions. [2018-02-02 09:50:05,019 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 09:50:05,019 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-02-02 09:50:05,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:05,020 INFO L225 Difference]: With dead ends: 97 [2018-02-02 09:50:05,020 INFO L226 Difference]: Without dead ends: 97 [2018-02-02 09:50:05,021 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:50:05,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-02-02 09:50:05,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 78. [2018-02-02 09:50:05,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-02-02 09:50:05,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 91 transitions. [2018-02-02 09:50:05,030 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 91 transitions. Word has length 28 [2018-02-02 09:50:05,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:05,030 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 91 transitions. [2018-02-02 09:50:05,030 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 09:50:05,030 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 91 transitions. [2018-02-02 09:50:05,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 09:50:05,031 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:05,031 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:05,031 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:05,031 INFO L82 PathProgramCache]: Analyzing trace with hash -723400154, now seen corresponding path program 1 times [2018-02-02 09:50:05,032 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:05,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:05,046 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:05,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,118 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:05,118 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 09:50:05,118 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:05,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,119 INFO L182 omatonBuilderFactory]: Interpolants [1744#(and (= |old(#valid)| (store |#valid| |main_#t~malloc11.base| 0)) (= (select |#valid| |main_#t~malloc11.base|) 1)), 1745#(and (not (= |main_#t~malloc11.base| |main_#t~malloc12.base|)) (= (store (store |#valid| |main_#t~malloc11.base| (select (store |#valid| |main_#t~malloc11.base| 0) |main_#t~malloc11.base|)) |main_#t~malloc12.base| 0) |old(#valid)|)), 1746#(= |old(#valid)| (store |#valid| |main_#t~malloc12.base| (select (store |#valid| |main_#t~malloc12.base| 0) |main_#t~malloc12.base|))), 1741#true, 1742#false, 1743#(= |#valid| |old(#valid)|)] [2018-02-02 09:50:05,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,119 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 09:50:05,119 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 09:50:05,120 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 09:50:05,120 INFO L87 Difference]: Start difference. First operand 78 states and 91 transitions. Second operand 6 states. [2018-02-02 09:50:05,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:05,223 INFO L93 Difference]: Finished difference Result 77 states and 90 transitions. [2018-02-02 09:50:05,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 09:50:05,225 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-02 09:50:05,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:05,225 INFO L225 Difference]: With dead ends: 77 [2018-02-02 09:50:05,226 INFO L226 Difference]: Without dead ends: 64 [2018-02-02 09:50:05,226 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-02 09:50:05,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-02-02 09:50:05,228 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 56. [2018-02-02 09:50:05,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-02-02 09:50:05,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 64 transitions. [2018-02-02 09:50:05,229 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 64 transitions. Word has length 28 [2018-02-02 09:50:05,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:05,229 INFO L432 AbstractCegarLoop]: Abstraction has 56 states and 64 transitions. [2018-02-02 09:50:05,229 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 09:50:05,229 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 64 transitions. [2018-02-02 09:50:05,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-02 09:50:05,230 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:05,230 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:05,230 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:05,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1208652779, now seen corresponding path program 1 times [2018-02-02 09:50:05,235 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:05,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:05,248 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:05,361 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,362 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 09:50:05,362 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 09:50:05,362 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:05,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,362 INFO L182 omatonBuilderFactory]: Interpolants [1888#(and (or (<= cstrncat_~n (* 4294967296 (div cstrncat_~n 4294967296))) (<= cstrncat_~n 1)) (< 0 (+ (div cstrncat_~n 4294967296) 1))), 1889#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 1)), 1890#(<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))), 1884#true, 1885#false, 1886#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 1887#(and (<= |cstrncat_#in~n| 1) (<= 1 |cstrncat_#in~n|))] [2018-02-02 09:50:05,362 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,362 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 09:50:05,363 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 09:50:05,363 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-02 09:50:05,363 INFO L87 Difference]: Start difference. First operand 56 states and 64 transitions. Second operand 7 states. [2018-02-02 09:50:05,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:05,427 INFO L93 Difference]: Finished difference Result 100 states and 110 transitions. [2018-02-02 09:50:05,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 09:50:05,427 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 30 [2018-02-02 09:50:05,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:05,427 INFO L225 Difference]: With dead ends: 100 [2018-02-02 09:50:05,427 INFO L226 Difference]: Without dead ends: 94 [2018-02-02 09:50:05,427 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-02-02 09:50:05,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-02-02 09:50:05,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 88. [2018-02-02 09:50:05,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-02-02 09:50:05,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 101 transitions. [2018-02-02 09:50:05,429 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 101 transitions. Word has length 30 [2018-02-02 09:50:05,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:05,429 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 101 transitions. [2018-02-02 09:50:05,429 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 09:50:05,429 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 101 transitions. [2018-02-02 09:50:05,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-02 09:50:05,430 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:05,430 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:05,430 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:05,430 INFO L82 PathProgramCache]: Analyzing trace with hash -752196469, now seen corresponding path program 3 times [2018-02-02 09:50:05,431 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:05,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:05,438 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:05,764 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,764 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:05,764 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 09:50:05,764 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:05,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,765 INFO L182 omatonBuilderFactory]: Interpolants [2085#true, 2086#false, 2087#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 2088#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= main_~n~0 1)), 2089#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 2090#(and (= 0 main_~nondetString1~0.offset) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base |main_#t~malloc12.base|))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 2091#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 2092#(and (= 0 main_~nondetString1~0.offset) (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 2))), 2093#(and (or (<= (select |#length| |cstrncat_#in~dst.base|) 2) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 |cstrncat_#in~dst.offset|)), 2094#(and (or (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (<= (select |#length| cstrncat_~dst.base) 2)) (= 0 cstrncat_~dst.offset)), 2095#(and (or (<= (select |#length| cstrncat_~d~0.base) 2) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (<= 4 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 2096#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 2097#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1))), 2098#(or (<= (select |#length| cstrncat_~d~0.base) cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 2099#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 2100#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:05,765 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:05,765 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 09:50:05,765 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 09:50:05,766 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2018-02-02 09:50:05,766 INFO L87 Difference]: Start difference. First operand 88 states and 101 transitions. Second operand 16 states. [2018-02-02 09:50:06,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:06,337 INFO L93 Difference]: Finished difference Result 100 states and 112 transitions. [2018-02-02 09:50:06,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:50:06,337 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 30 [2018-02-02 09:50:06,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:06,338 INFO L225 Difference]: With dead ends: 100 [2018-02-02 09:50:06,338 INFO L226 Difference]: Without dead ends: 93 [2018-02-02 09:50:06,339 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=108, Invalid=594, Unknown=0, NotChecked=0, Total=702 [2018-02-02 09:50:06,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-02-02 09:50:06,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 91. [2018-02-02 09:50:06,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-02-02 09:50:06,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 104 transitions. [2018-02-02 09:50:06,342 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 104 transitions. Word has length 30 [2018-02-02 09:50:06,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:06,342 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 104 transitions. [2018-02-02 09:50:06,342 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 09:50:06,342 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 104 transitions. [2018-02-02 09:50:06,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-02 09:50:06,342 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:06,343 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:06,343 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:06,343 INFO L82 PathProgramCache]: Analyzing trace with hash -989798061, now seen corresponding path program 1 times [2018-02-02 09:50:06,343 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:06,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:06,355 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:06,514 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:06,514 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:06,514 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 09:50:06,514 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:06,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:06,515 INFO L182 omatonBuilderFactory]: Interpolants [2314#true, 2315#false, 2316#(<= 1 main_~length2~0), 2317#(and (= 0 |main_#t~malloc12.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 2318#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length2~0) 1) (and (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))))), 2319#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 2 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 2320#(and (or (= 0 (select (select |#memory_int| |cstrncat_#in~src.base|) |cstrncat_#in~src.offset|)) (<= 2 (select |#length| |cstrncat_#in~src.base|))) (= 0 |cstrncat_#in~src.offset|)), 2321#(and (or (= 0 (select (select |#memory_int| cstrncat_~src.base) cstrncat_~src.offset)) (<= 2 (select |#length| cstrncat_~src.base))) (= 0 cstrncat_~src.offset)), 2322#(and (= 0 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= 2 (select |#length| cstrncat_~s~0.base)))), 2323#(and (or (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|)))) (= |cstrncat_#t~post3.offset| 0)), 2324#(or (= 0 |cstrncat_#t~mem5|) (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 2325#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 2326#(and (<= 1 |cstrncat_#t~post3.offset|) (<= (+ |cstrncat_#t~post3.offset| 1) (select |#length| |cstrncat_#t~post3.base|)))] [2018-02-02 09:50:06,515 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:06,515 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 09:50:06,515 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 09:50:06,515 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2018-02-02 09:50:06,515 INFO L87 Difference]: Start difference. First operand 91 states and 104 transitions. Second operand 13 states. [2018-02-02 09:50:06,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:06,723 INFO L93 Difference]: Finished difference Result 105 states and 119 transitions. [2018-02-02 09:50:06,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-02 09:50:06,723 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 30 [2018-02-02 09:50:06,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:06,724 INFO L225 Difference]: With dead ends: 105 [2018-02-02 09:50:06,724 INFO L226 Difference]: Without dead ends: 105 [2018-02-02 09:50:06,724 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=67, Invalid=313, Unknown=0, NotChecked=0, Total=380 [2018-02-02 09:50:06,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-02-02 09:50:06,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 99. [2018-02-02 09:50:06,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-02-02 09:50:06,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 114 transitions. [2018-02-02 09:50:06,728 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 114 transitions. Word has length 30 [2018-02-02 09:50:06,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:06,728 INFO L432 AbstractCegarLoop]: Abstraction has 99 states and 114 transitions. [2018-02-02 09:50:06,728 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 09:50:06,728 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 114 transitions. [2018-02-02 09:50:06,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-02 09:50:06,729 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:06,729 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:06,729 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:06,729 INFO L82 PathProgramCache]: Analyzing trace with hash -533341751, now seen corresponding path program 1 times [2018-02-02 09:50:06,730 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:06,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:06,742 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:07,032 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:07,032 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:07,033 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:50:07,033 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:07,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:07,033 INFO L182 omatonBuilderFactory]: Interpolants [2560#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 2561#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 2545#true, 2546#false, 2547#(<= 1 main_~n~0), 2548#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 2549#(and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 2550#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 2551#(and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2552#(and (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2553#(and (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (<= 4 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 2554#(and (= 0 cstrncat_~dst.offset) (or (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 2555#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (<= 4 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 2556#(and (= cstrncat_~d~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (<= 4 (select |#length| cstrncat_~d~0.base)))), 2557#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 2558#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 2559#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))] [2018-02-02 09:50:07,033 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:07,033 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:50:07,034 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:50:07,034 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:50:07,034 INFO L87 Difference]: Start difference. First operand 99 states and 114 transitions. Second operand 17 states. [2018-02-02 09:50:07,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:07,473 INFO L93 Difference]: Finished difference Result 117 states and 134 transitions. [2018-02-02 09:50:07,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 09:50:07,473 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 30 [2018-02-02 09:50:07,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:07,474 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:50:07,474 INFO L226 Difference]: Without dead ends: 116 [2018-02-02 09:50:07,474 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=119, Invalid=693, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:50:07,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-02-02 09:50:07,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 102. [2018-02-02 09:50:07,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-02-02 09:50:07,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 118 transitions. [2018-02-02 09:50:07,477 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 118 transitions. Word has length 30 [2018-02-02 09:50:07,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:07,477 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 118 transitions. [2018-02-02 09:50:07,477 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:50:07,477 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 118 transitions. [2018-02-02 09:50:07,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-02 09:50:07,478 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:07,478 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:07,478 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:07,478 INFO L82 PathProgramCache]: Analyzing trace with hash -1840623047, now seen corresponding path program 4 times [2018-02-02 09:50:07,478 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:07,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:07,487 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:07,722 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:07,722 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:07,722 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:50:07,722 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:07,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:07,723 INFO L182 omatonBuilderFactory]: Interpolants [2816#(and (<= 1 cstrncat_~d~0.offset) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))), 2817#(and (or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1))) (<= 2 cstrncat_~d~0.offset)), 2818#(and (or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1))) (<= 2 cstrncat_~d~0.offset)), 2819#(and (<= 3 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~d~0.base) cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)))), 2820#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 2821#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 2805#true, 2806#false, 2807#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 2808#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= main_~n~0 1)), 2809#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2810#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2811#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2812#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ main_~n~0 (- 1))) (+ main_~nondetString1~0.offset (+ (- main_~n~0) (- 1)))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2813#(and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (= 0 |cstrncat_#in~dst.offset|)), 2814#(and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)))) (= 0 cstrncat_~dst.offset)), 2815#(and (= cstrncat_~d~0.offset 0) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))] [2018-02-02 09:50:07,723 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:07,723 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:50:07,723 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:50:07,723 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:50:07,723 INFO L87 Difference]: Start difference. First operand 102 states and 118 transitions. Second operand 17 states. [2018-02-02 09:50:08,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:08,139 INFO L93 Difference]: Finished difference Result 104 states and 116 transitions. [2018-02-02 09:50:08,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:50:08,139 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 33 [2018-02-02 09:50:08,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:08,140 INFO L225 Difference]: With dead ends: 104 [2018-02-02 09:50:08,140 INFO L226 Difference]: Without dead ends: 67 [2018-02-02 09:50:08,140 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 178 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=179, Invalid=813, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:50:08,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-02-02 09:50:08,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-02-02 09:50:08,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-02-02 09:50:08,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 77 transitions. [2018-02-02 09:50:08,142 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 77 transitions. Word has length 33 [2018-02-02 09:50:08,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:08,142 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 77 transitions. [2018-02-02 09:50:08,142 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:50:08,142 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 77 transitions. [2018-02-02 09:50:08,142 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-02 09:50:08,142 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:08,142 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:08,142 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:08,142 INFO L82 PathProgramCache]: Analyzing trace with hash -1700074437, now seen corresponding path program 2 times [2018-02-02 09:50:08,143 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:08,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:08,156 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:08,513 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:08,513 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:08,513 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 09:50:08,513 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:08,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:08,514 INFO L182 omatonBuilderFactory]: Interpolants [3040#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 3023#true, 3024#false, 3025#(<= 1 main_~n~0), 3026#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 3027#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3028#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3029#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 3030#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))))) (= main_~nondetString1~0.offset 0)), 3031#(and (or (and (or (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 3032#(and (= 0 cstrncat_~dst.offset) (or (and (<= 4 (select |#length| cstrncat_~dst.base)) (or (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 3033#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (or (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))) (= cstrncat_~d~0.offset 0)), 3034#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (or (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))) (= cstrncat_~d~0.offset 0)), 3035#(and (<= 1 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))))), 3036#(and (<= 1 cstrncat_~d~0.offset) (or (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 3037#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 2 cstrncat_~d~0.offset))), 3038#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 2 cstrncat_~d~0.offset))), 3039#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:08,514 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:08,514 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 09:50:08,514 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 09:50:08,514 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-02-02 09:50:08,514 INFO L87 Difference]: Start difference. First operand 67 states and 77 transitions. Second operand 18 states. [2018-02-02 09:50:09,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:09,034 INFO L93 Difference]: Finished difference Result 100 states and 114 transitions. [2018-02-02 09:50:09,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-02 09:50:09,035 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 33 [2018-02-02 09:50:09,035 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:09,035 INFO L225 Difference]: With dead ends: 100 [2018-02-02 09:50:09,035 INFO L226 Difference]: Without dead ends: 99 [2018-02-02 09:50:09,035 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=130, Invalid=800, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:50:09,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-02-02 09:50:09,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 70. [2018-02-02 09:50:09,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-02-02 09:50:09,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 81 transitions. [2018-02-02 09:50:09,037 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 81 transitions. Word has length 33 [2018-02-02 09:50:09,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:09,038 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 81 transitions. [2018-02-02 09:50:09,038 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 09:50:09,038 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 81 transitions. [2018-02-02 09:50:09,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-02 09:50:09,038 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:09,038 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:09,038 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:09,038 INFO L82 PathProgramCache]: Analyzing trace with hash -608695935, now seen corresponding path program 1 times [2018-02-02 09:50:09,039 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:09,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:09,045 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:09,246 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:09,246 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:09,246 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-02 09:50:09,246 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:09,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:09,246 INFO L182 omatonBuilderFactory]: Interpolants [3237#true, 3238#false, 3239#(<= 1 main_~n~0), 3240#(<= (+ main_~length2~0 1) main_~length1~0), 3241#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|)), 3242#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| main_~nondetString1~0.base) 1)), 3243#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 3244#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 3245#(and (<= (+ main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 3246#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))), 3247#(and (= 0 |cstrncat_#in~src.offset|) (<= (+ (select |#length| |cstrncat_#in~src.base|) 1) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 3248#(and (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset) (<= (+ (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base))), 3249#(and (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (select |#length| cstrncat_~d~0.base))), 3250#(and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset| 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (= cstrncat_~d~0.offset 0) (= |cstrncat_#t~post3.offset| 0)), 3251#(and (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3252#(and (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3253#(and (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|))), 3254#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 3255#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:09,247 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:09,247 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-02 09:50:09,247 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-02 09:50:09,247 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=299, Unknown=0, NotChecked=0, Total=342 [2018-02-02 09:50:09,247 INFO L87 Difference]: Start difference. First operand 70 states and 81 transitions. Second operand 19 states. [2018-02-02 09:50:09,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:09,579 INFO L93 Difference]: Finished difference Result 88 states and 100 transitions. [2018-02-02 09:50:09,580 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 09:50:09,580 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 35 [2018-02-02 09:50:09,580 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:09,580 INFO L225 Difference]: With dead ends: 88 [2018-02-02 09:50:09,580 INFO L226 Difference]: Without dead ends: 87 [2018-02-02 09:50:09,581 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 141 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=132, Invalid=798, Unknown=0, NotChecked=0, Total=930 [2018-02-02 09:50:09,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-02-02 09:50:09,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 84. [2018-02-02 09:50:09,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-02-02 09:50:09,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2018-02-02 09:50:09,582 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 96 transitions. Word has length 35 [2018-02-02 09:50:09,582 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:09,582 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 96 transitions. [2018-02-02 09:50:09,582 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-02 09:50:09,582 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 96 transitions. [2018-02-02 09:50:09,582 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 09:50:09,582 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:09,583 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:09,583 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:09,583 INFO L82 PathProgramCache]: Analyzing trace with hash -1689703552, now seen corresponding path program 2 times [2018-02-02 09:50:09,583 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:09,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:09,591 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:09,853 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:09,854 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:09,854 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:50:09,854 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:09,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:09,854 INFO L182 omatonBuilderFactory]: Interpolants [3456#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 3457#(and (= 0 main_~nondetString2~0.offset) (or (not (= (+ main_~nondetString2~0.offset main_~length2~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 3458#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)) 1) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 3459#(and (= 0 |cstrncat_#in~src.offset|) (or (and (not (= |cstrncat_#in~dst.base| |cstrncat_#in~src.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~src.base|) 1))) (<= 3 (select |#length| |cstrncat_#in~src.base|)) (<= (select |#length| |cstrncat_#in~src.base|) 1))), 3460#(and (or (<= (select |#length| cstrncat_~src.base) 1) (<= 3 (select |#length| cstrncat_~src.base)) (and (not (= cstrncat_~dst.base cstrncat_~src.base)) (= 0 (select (select |#memory_int| cstrncat_~src.base) 1)))) (= 0 cstrncat_~src.offset)), 3461#(and (or (<= 3 (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) 1) (and (not (= cstrncat_~d~0.base cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 3462#(and (or (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|)) (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) cstrncat_~s~0.offset))) (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (= |cstrncat_#t~post3.base| cstrncat_~s~0.base) (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) 1)) (<= cstrncat_~s~0.offset (+ |cstrncat_#t~post3.offset| 1)) (not (= |cstrncat_#t~post3.base| cstrncat_~d~0.base)))) (= |cstrncat_#t~post3.offset| 0)), 3463#(or (and (<= 1 cstrncat_~s~0.offset) (= 0 (select (select (store |#memory_int| cstrncat_~d~0.base (store (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset |cstrncat_#t~mem5|)) cstrncat_~s~0.base) 1)) (<= cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 3464#(or (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~s~0.offset) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= cstrncat_~s~0.offset 1))), 3465#(or (and (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (= 1 |cstrncat_#t~post3.offset|)) (and (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (<= 2 cstrncat_~s~0.offset))), 3466#(or (= 0 |cstrncat_#t~mem5|) (and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))), 3467#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 3468#(and (<= (+ |cstrncat_#t~post3.offset| 1) (select |#length| |cstrncat_#t~post3.base|)) (<= 2 |cstrncat_#t~post3.offset|)), 3452#true, 3453#false, 3454#(= (select |#valid| |main_#t~malloc11.base|) 1), 3455#(= (select |#valid| main_~nondetString1~0.base) 1)] [2018-02-02 09:50:09,854 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:09,854 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:50:09,855 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:50:09,855 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:50:09,855 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. Second operand 17 states. [2018-02-02 09:50:10,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:10,237 INFO L93 Difference]: Finished difference Result 101 states and 112 transitions. [2018-02-02 09:50:10,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:50:10,237 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 36 [2018-02-02 09:50:10,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:10,238 INFO L225 Difference]: With dead ends: 101 [2018-02-02 09:50:10,238 INFO L226 Difference]: Without dead ends: 101 [2018-02-02 09:50:10,238 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2018-02-02 09:50:10,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-02-02 09:50:10,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 92. [2018-02-02 09:50:10,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-02-02 09:50:10,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 106 transitions. [2018-02-02 09:50:10,240 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 106 transitions. Word has length 36 [2018-02-02 09:50:10,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:10,240 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 106 transitions. [2018-02-02 09:50:10,240 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:50:10,240 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 106 transitions. [2018-02-02 09:50:10,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 09:50:10,240 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:10,240 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:10,240 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:10,241 INFO L82 PathProgramCache]: Analyzing trace with hash -663196535, now seen corresponding path program 3 times [2018-02-02 09:50:10,241 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:10,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:10,255 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:10,786 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:10,786 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:10,786 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 09:50:10,787 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:10,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:10,787 INFO L182 omatonBuilderFactory]: Interpolants [3680#true, 3681#false, 3682#(<= 1 main_~n~0), 3683#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 3684#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3685#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3686#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 3687#(and (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 3688#(and (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 3689#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (or (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)))))) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 3690#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (or (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1))) (= cstrncat_~d~0.offset 0)), 3691#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (or (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1))) (= cstrncat_~d~0.offset 0)), 3692#(or (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 3693#(or (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 3694#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 3695#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 3696#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 3697#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 3698#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 3699#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 3700#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:10,787 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:10,787 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 09:50:10,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 09:50:10,788 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=363, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:50:10,788 INFO L87 Difference]: Start difference. First operand 92 states and 106 transitions. Second operand 21 states. [2018-02-02 09:50:11,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:11,800 INFO L93 Difference]: Finished difference Result 121 states and 137 transitions. [2018-02-02 09:50:11,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 09:50:11,800 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 36 [2018-02-02 09:50:11,801 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:11,801 INFO L225 Difference]: With dead ends: 121 [2018-02-02 09:50:11,801 INFO L226 Difference]: Without dead ends: 120 [2018-02-02 09:50:11,801 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 334 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=205, Invalid=1201, Unknown=0, NotChecked=0, Total=1406 [2018-02-02 09:50:11,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-02-02 09:50:11,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 95. [2018-02-02 09:50:11,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-02-02 09:50:11,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 110 transitions. [2018-02-02 09:50:11,803 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 110 transitions. Word has length 36 [2018-02-02 09:50:11,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:11,804 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 110 transitions. [2018-02-02 09:50:11,804 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 09:50:11,804 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 110 transitions. [2018-02-02 09:50:11,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 09:50:11,804 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:11,804 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:11,804 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:11,805 INFO L82 PathProgramCache]: Analyzing trace with hash -601444785, now seen corresponding path program 1 times [2018-02-02 09:50:11,805 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:11,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:11,813 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:12,137 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:12,137 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:12,137 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-02 09:50:12,137 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:12,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:12,138 INFO L182 omatonBuilderFactory]: Interpolants [3968#(and (or (<= (+ |cstrncat_#t~pre2| (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)), 3969#(<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)), 3970#(<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|)), 3971#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 3972#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 3973#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 3951#true, 3952#false, 3953#(<= 1 main_~n~0), 3954#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3955#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3956#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3957#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 3958#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3959#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 3960#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 3961#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 3962#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 3963#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 3964#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) 1)) (= 0 cstrncat_~s~0.offset)), 3965#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post3.offset| 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset |cstrncat_#t~post3.offset|) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3966#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3967#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset 1)))] [2018-02-02 09:50:12,138 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:12,138 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-02 09:50:12,138 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-02 09:50:12,138 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=438, Unknown=0, NotChecked=0, Total=506 [2018-02-02 09:50:12,139 INFO L87 Difference]: Start difference. First operand 95 states and 110 transitions. Second operand 23 states. [2018-02-02 09:50:12,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:12,684 INFO L93 Difference]: Finished difference Result 115 states and 129 transitions. [2018-02-02 09:50:12,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:50:12,684 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 38 [2018-02-02 09:50:12,684 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:12,684 INFO L225 Difference]: With dead ends: 115 [2018-02-02 09:50:12,685 INFO L226 Difference]: Without dead ends: 114 [2018-02-02 09:50:12,685 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 519 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=271, Invalid=1709, Unknown=0, NotChecked=0, Total=1980 [2018-02-02 09:50:12,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-02-02 09:50:12,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 95. [2018-02-02 09:50:12,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-02-02 09:50:12,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 110 transitions. [2018-02-02 09:50:12,686 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 110 transitions. Word has length 38 [2018-02-02 09:50:12,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:12,687 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 110 transitions. [2018-02-02 09:50:12,687 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-02 09:50:12,687 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 110 transitions. [2018-02-02 09:50:12,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 09:50:12,687 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:12,687 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:12,687 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:12,687 INFO L82 PathProgramCache]: Analyzing trace with hash -438410885, now seen corresponding path program 4 times [2018-02-02 09:50:12,688 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:12,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:12,701 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:13,581 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:13,581 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:13,581 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 09:50:13,581 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:13,581 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:13,582 INFO L182 omatonBuilderFactory]: Interpolants [4228#true, 4229#false, 4230#(<= 1 main_~n~0), 4231#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 4232#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1)), 4233#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset)), 4234#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4235#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4236#(and (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (or (<= 7 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1))))) (<= 6 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 4237#(and (= 0 cstrncat_~dst.offset) (or (and (<= 6 (select |#length| cstrncat_~dst.base)) (or (<= 7 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)))))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 4238#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (<= 6 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))))), 4239#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (<= 6 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (= cstrncat_~d~0.offset 0)), 4240#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 4241#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 4242#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 4243#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 4244#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 4245#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 4246#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 4247#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))), 4248#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 4249#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:13,582 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:13,582 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:50:13,582 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:50:13,582 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=400, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:50:13,583 INFO L87 Difference]: Start difference. First operand 95 states and 110 transitions. Second operand 22 states. [2018-02-02 09:50:15,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:15,060 INFO L93 Difference]: Finished difference Result 120 states and 137 transitions. [2018-02-02 09:50:15,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:50:15,060 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 39 [2018-02-02 09:50:15,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:15,061 INFO L225 Difference]: With dead ends: 120 [2018-02-02 09:50:15,061 INFO L226 Difference]: Without dead ends: 119 [2018-02-02 09:50:15,061 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 291 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=230, Invalid=1330, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 09:50:15,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-02 09:50:15,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 98. [2018-02-02 09:50:15,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-02-02 09:50:15,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 114 transitions. [2018-02-02 09:50:15,063 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 114 transitions. Word has length 39 [2018-02-02 09:50:15,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:15,063 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 114 transitions. [2018-02-02 09:50:15,063 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:50:15,063 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 114 transitions. [2018-02-02 09:50:15,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-02 09:50:15,063 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:15,063 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:15,063 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:15,064 INFO L82 PathProgramCache]: Analyzing trace with hash 1171788660, now seen corresponding path program 2 times [2018-02-02 09:50:15,064 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:15,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:15,070 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:15,267 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:50:15,267 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:15,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 09:50:15,268 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:15,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:15,268 INFO L182 omatonBuilderFactory]: Interpolants [4512#(and (<= (+ main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 4513#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))), 4514#(and (= 0 |cstrncat_#in~src.offset|) (<= (+ (select |#length| |cstrncat_#in~src.base|) 1) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 4515#(and (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset) (<= (+ (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base))), 4516#(and (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (select |#length| cstrncat_~d~0.base))), 4517#(and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset| 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (= cstrncat_~d~0.offset 0) (= |cstrncat_#t~post3.offset| 0)), 4518#(and (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 4519#(<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)), 4520#(<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)), 4521#(<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|)), 4522#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 4523#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 4524#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 4504#true, 4505#false, 4506#(<= 1 main_~n~0), 4507#(<= (+ main_~length2~0 1) main_~length1~0), 4508#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|)), 4509#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| main_~nondetString1~0.base) 1)), 4510#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 4511#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))] [2018-02-02 09:50:15,268 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:50:15,268 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 09:50:15,268 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 09:50:15,268 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=366, Unknown=0, NotChecked=0, Total=420 [2018-02-02 09:50:15,269 INFO L87 Difference]: Start difference. First operand 98 states and 114 transitions. Second operand 21 states. [2018-02-02 09:50:15,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:15,664 INFO L93 Difference]: Finished difference Result 123 states and 139 transitions. [2018-02-02 09:50:15,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:50:15,665 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 41 [2018-02-02 09:50:15,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:15,665 INFO L225 Difference]: With dead ends: 123 [2018-02-02 09:50:15,665 INFO L226 Difference]: Without dead ends: 121 [2018-02-02 09:50:15,666 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=172, Invalid=950, Unknown=0, NotChecked=0, Total=1122 [2018-02-02 09:50:15,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-02-02 09:50:15,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 118. [2018-02-02 09:50:15,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-02 09:50:15,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 135 transitions. [2018-02-02 09:50:15,667 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 135 transitions. Word has length 41 [2018-02-02 09:50:15,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:15,668 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 135 transitions. [2018-02-02 09:50:15,668 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 09:50:15,668 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 135 transitions. [2018-02-02 09:50:15,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-02 09:50:15,668 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:15,668 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:15,668 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:15,668 INFO L82 PathProgramCache]: Analyzing trace with hash 669200065, now seen corresponding path program 2 times [2018-02-02 09:50:15,669 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:15,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:15,675 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:16,411 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:16,412 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:16,412 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:50:16,412 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:16,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:16,413 INFO L182 omatonBuilderFactory]: Interpolants [4800#(and (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~length2~0 main_~nondetString1~0.offset) 1)) (<= 1 main_~n~0))) (= main_~nondetString1~0.offset 0)), 4801#(and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 1 main_~n~0) (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) 1)))) (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 4802#(and (= 0 |cstrncat_#in~src.offset|) (or (and (or (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)) (<= (select |#length| |cstrncat_#in~src.base|) 1)) (<= 1 |cstrncat_#in~n|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1))) (= 0 |cstrncat_#in~dst.offset|)), 4803#(and (= 0 cstrncat_~dst.offset) (or (and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~src.base) 1) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~dst.base)))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1))) (= 0 cstrncat_~src.offset)), 4804#(and (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 1) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))))), 4805#(and (or (and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (or (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) 1))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 1 cstrncat_~d~0.offset))) (= 0 cstrncat_~s~0.offset)), 4806#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 1 cstrncat_~d~0.offset)) (and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (or (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 4807#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 1) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset) (<= 2 cstrncat_~d~0.offset)), 4808#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) cstrncat_~s~0.offset)) (= |cstrncat_#t~post3.offset| 0) (<= 2 cstrncat_~d~0.offset)), 4809#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~d~0.offset)), 4810#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= 3 cstrncat_~d~0.offset)), 4811#(and (<= 3 cstrncat_~d~0.offset) (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)), 4812#(and (<= 3 cstrncat_~d~0.offset) (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 4813#(and (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (<= 3 cstrncat_~d~0.offset)), 4814#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 4815#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 4792#true, 4793#false, 4794#(<= 1 main_~n~0), 4795#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 4796#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 4797#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 4798#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 |main_#t~malloc12.offset|) (= main_~nondetString1~0.offset 0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 4799#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:50:16,413 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:16,413 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:50:16,413 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:50:16,413 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=499, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:50:16,414 INFO L87 Difference]: Start difference. First operand 118 states and 135 transitions. Second operand 24 states. [2018-02-02 09:50:17,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:17,388 INFO L93 Difference]: Finished difference Result 145 states and 162 transitions. [2018-02-02 09:50:17,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-02 09:50:17,388 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 41 [2018-02-02 09:50:17,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:17,388 INFO L225 Difference]: With dead ends: 145 [2018-02-02 09:50:17,388 INFO L226 Difference]: Without dead ends: 144 [2018-02-02 09:50:17,389 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=159, Invalid=1401, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 09:50:17,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-02 09:50:17,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 118. [2018-02-02 09:50:17,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-02 09:50:17,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 135 transitions. [2018-02-02 09:50:17,390 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 135 transitions. Word has length 41 [2018-02-02 09:50:17,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:17,391 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 135 transitions. [2018-02-02 09:50:17,391 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:50:17,391 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 135 transitions. [2018-02-02 09:50:17,391 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 09:50:17,391 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:17,391 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:17,391 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:17,392 INFO L82 PathProgramCache]: Analyzing trace with hash 1965711341, now seen corresponding path program 3 times [2018-02-02 09:50:17,392 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:17,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:17,405 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:17,588 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 09:50:17,588 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:17,588 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-02 09:50:17,588 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:17,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:17,588 INFO L182 omatonBuilderFactory]: Interpolants [5120#(and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (not (= cstrncat_~d~0.base cstrncat_~s~0.base))), 5121#(and (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (= |cstrncat_#t~post3.base| cstrncat_~s~0.base) (not (= cstrncat_~d~0.base |cstrncat_#t~post3.base|))), 5122#(= 0 (select (select (store |#memory_int| cstrncat_~d~0.base (store (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset |cstrncat_#t~mem5|)) cstrncat_~s~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))), 5123#(= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))), 5124#(or (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 5125#(or (= 0 |cstrncat_#t~mem5|) (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 5126#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 5127#(and (<= 1 |cstrncat_#t~post3.offset|) (<= (+ |cstrncat_#t~post3.offset| 1) (select |#length| |cstrncat_#t~post3.base|))), 5111#true, 5112#false, 5113#(= (select |#valid| |main_#t~malloc11.base|) 1), 5114#(= (select |#valid| main_~nondetString1~0.base) 1), 5115#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 5116#(and (= main_~nondetString2~0.offset 0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 5117#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5118#(and (= 0 (select (select |#memory_int| |cstrncat_#in~src.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (not (= |cstrncat_#in~dst.base| |cstrncat_#in~src.base|))), 5119#(and (not (= cstrncat_~dst.base cstrncat_~src.base)) (= 0 (select (select |#memory_int| cstrncat_~src.base) (+ (select |#length| cstrncat_~src.base) (- 1)))))] [2018-02-02 09:50:17,588 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 09:50:17,589 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-02 09:50:17,589 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-02 09:50:17,589 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-02-02 09:50:17,589 INFO L87 Difference]: Start difference. First operand 118 states and 135 transitions. Second operand 17 states. [2018-02-02 09:50:17,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:17,880 INFO L93 Difference]: Finished difference Result 120 states and 134 transitions. [2018-02-02 09:50:17,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 09:50:17,880 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 42 [2018-02-02 09:50:17,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:17,881 INFO L225 Difference]: With dead ends: 120 [2018-02-02 09:50:17,881 INFO L226 Difference]: Without dead ends: 100 [2018-02-02 09:50:17,881 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=136, Invalid=676, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:50:17,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-02-02 09:50:17,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 69. [2018-02-02 09:50:17,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-02-02 09:50:17,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 78 transitions. [2018-02-02 09:50:17,882 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 78 transitions. Word has length 42 [2018-02-02 09:50:17,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:17,882 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 78 transitions. [2018-02-02 09:50:17,882 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-02 09:50:17,883 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 78 transitions. [2018-02-02 09:50:17,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 09:50:17,883 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:17,883 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:17,883 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:17,883 INFO L82 PathProgramCache]: Analyzing trace with hash 296873801, now seen corresponding path program 5 times [2018-02-02 09:50:17,884 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:17,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:17,895 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:18,270 WARN L146 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 84 DAG size of output 69 [2018-02-02 09:50:18,423 WARN L146 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 58 DAG size of output 45 [2018-02-02 09:50:18,543 WARN L146 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 58 DAG size of output 45 [2018-02-02 09:50:18,964 WARN L146 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 74 DAG size of output 52 [2018-02-02 09:50:19,285 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:19,286 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:19,286 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-02 09:50:19,286 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:19,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:19,287 INFO L182 omatonBuilderFactory]: Interpolants [5341#true, 5342#false, 5343#(<= 1 main_~n~0), 5344#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 5345#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 5346#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 5347#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5348#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5349#(and (or (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1))))) (and (or (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 7 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 |cstrncat_#in~dst.offset|)), 5350#(and (or (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~dst.base))) (<= 7 (select |#length| cstrncat_~dst.base))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))) (= 0 cstrncat_~dst.offset)), 5351#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))))) (= cstrncat_~d~0.offset 0)), 5352#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))))) (= cstrncat_~d~0.offset 0)), 5353#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 5354#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 5355#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 5356#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 5357#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 5358#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 5359#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 5360#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 5361#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 5362#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 5363#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 5364#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 5365#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:19,287 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:19,287 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-02 09:50:19,287 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-02 09:50:19,287 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=515, Unknown=0, NotChecked=0, Total=600 [2018-02-02 09:50:19,287 INFO L87 Difference]: Start difference. First operand 69 states and 78 transitions. Second operand 25 states. [2018-02-02 09:50:21,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:21,181 INFO L93 Difference]: Finished difference Result 116 states and 127 transitions. [2018-02-02 09:50:21,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:50:21,182 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2018-02-02 09:50:21,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:21,182 INFO L225 Difference]: With dead ends: 116 [2018-02-02 09:50:21,182 INFO L226 Difference]: Without dead ends: 115 [2018-02-02 09:50:21,183 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 422 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=317, Invalid=1753, Unknown=0, NotChecked=0, Total=2070 [2018-02-02 09:50:21,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-02-02 09:50:21,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 72. [2018-02-02 09:50:21,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-02-02 09:50:21,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 82 transitions. [2018-02-02 09:50:21,185 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 82 transitions. Word has length 42 [2018-02-02 09:50:21,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:21,186 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 82 transitions. [2018-02-02 09:50:21,186 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-02 09:50:21,186 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 82 transitions. [2018-02-02 09:50:21,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 09:50:21,186 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:21,186 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:21,186 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:21,187 INFO L82 PathProgramCache]: Analyzing trace with hash -889231934, now seen corresponding path program 3 times [2018-02-02 09:50:21,187 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:21,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:21,196 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:21,494 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:21,587 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:21,587 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 09:50:21,587 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:21,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:21,587 INFO L182 omatonBuilderFactory]: Interpolants [5600#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 5601#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 5602#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 5603#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 5604#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 5605#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 5606#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 5607#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 5608#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 5609#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) 1)) (= 0 cstrncat_~s~0.offset)), 5610#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (= |cstrncat_#t~post3.offset| 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset |cstrncat_#t~post3.offset|) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5611#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5612#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset 1)) (<= 2 cstrncat_~d~0.offset)), 5613#(and (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (and (<= 0 |cstrncat_#t~pre2|) (<= (+ |cstrncat_#t~pre2| (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)))) (<= 2 cstrncat_~d~0.offset)), 5614#(and (<= 2 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5615#(and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (<= 2 cstrncat_~d~0.offset)), 5616#(and (<= 3 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5617#(and (<= 3 cstrncat_~d~0.offset) (<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|))), 5618#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 5619#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 5596#true, 5597#false, 5598#(<= 1 main_~n~0), 5599#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))] [2018-02-02 09:50:21,587 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:21,587 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 09:50:21,588 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 09:50:21,588 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2018-02-02 09:50:21,588 INFO L87 Difference]: Start difference. First operand 72 states and 82 transitions. Second operand 24 states. [2018-02-02 09:50:22,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:22,252 INFO L93 Difference]: Finished difference Result 113 states and 123 transitions. [2018-02-02 09:50:22,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 09:50:22,253 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 44 [2018-02-02 09:50:22,253 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:22,253 INFO L225 Difference]: With dead ends: 113 [2018-02-02 09:50:22,253 INFO L226 Difference]: Without dead ends: 89 [2018-02-02 09:50:22,254 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 390 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=209, Invalid=1513, Unknown=0, NotChecked=0, Total=1722 [2018-02-02 09:50:22,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-02-02 09:50:22,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 72. [2018-02-02 09:50:22,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-02-02 09:50:22,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 81 transitions. [2018-02-02 09:50:22,256 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 81 transitions. Word has length 44 [2018-02-02 09:50:22,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:22,256 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 81 transitions. [2018-02-02 09:50:22,256 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 09:50:22,256 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 81 transitions. [2018-02-02 09:50:22,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-02 09:50:22,256 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:22,256 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:22,256 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:22,256 INFO L82 PathProgramCache]: Analyzing trace with hash -1391820529, now seen corresponding path program 4 times [2018-02-02 09:50:22,257 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:22,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:22,266 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:22,668 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:50:22,668 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:22,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 09:50:22,669 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:22,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:22,669 INFO L182 omatonBuilderFactory]: Interpolants [5856#(and (<= cstrncat_~n 2147483647) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~d~0.offset cstrncat_~n)))), 5857#(and (<= cstrncat_~n 2147483646) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)) (and (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)))), 5858#(and (<= cstrncat_~n 2147483646) (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)))), 5859#(and (or (<= 2 cstrncat_~n) (and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))) (<= cstrncat_~n 2147483646)), 5860#(and (<= cstrncat_~n 2147483646) (or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~n))), 5861#(and (or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= 1 |cstrncat_#t~pre2|)) (<= (div |cstrncat_#t~pre2| 4294967296) 0)), 5862#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 5841#true, 5842#false, 5843#(<= main_~n~0 2147483647), 5844#(and (<= main_~n~0 2147483647) (<= 1 main_~n~0)), 5845#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 5846#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 5847#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 5848#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5849#(and (<= main_~n~0 2147483647) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5850#(and (<= |cstrncat_#in~n| 2147483647) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)))) (<= 1 |cstrncat_#in~n|)), 5851#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 5852#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 5853#(and (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n))) (<= cstrncat_~n 2147483647)), 5854#(and (<= cstrncat_~n 2147483647) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n)))), 5855#(and (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n))) (<= cstrncat_~n 2147483647))] [2018-02-02 09:50:22,669 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 09:50:22,669 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 09:50:22,669 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 09:50:22,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=407, Unknown=0, NotChecked=0, Total=462 [2018-02-02 09:50:22,670 INFO L87 Difference]: Start difference. First operand 72 states and 81 transitions. Second operand 22 states. [2018-02-02 09:50:23,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:23,191 INFO L93 Difference]: Finished difference Result 105 states and 115 transitions. [2018-02-02 09:50:23,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:50:23,192 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 44 [2018-02-02 09:50:23,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:23,192 INFO L225 Difference]: With dead ends: 105 [2018-02-02 09:50:23,192 INFO L226 Difference]: Without dead ends: 104 [2018-02-02 09:50:23,192 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 226 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-02-02 09:50:23,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-02-02 09:50:23,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 98. [2018-02-02 09:50:23,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-02-02 09:50:23,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 112 transitions. [2018-02-02 09:50:23,194 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 112 transitions. Word has length 44 [2018-02-02 09:50:23,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:23,194 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 112 transitions. [2018-02-02 09:50:23,194 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 09:50:23,194 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 112 transitions. [2018-02-02 09:50:23,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-02-02 09:50:23,195 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:23,195 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:23,195 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:23,195 INFO L82 PathProgramCache]: Analyzing trace with hash 829744827, now seen corresponding path program 6 times [2018-02-02 09:50:23,195 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:23,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:23,210 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:23,788 WARN L146 SmtUtils]: Spent 226ms on a formula simplification. DAG size of input: 99 DAG size of output 76 [2018-02-02 09:50:23,993 WARN L146 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 73 DAG size of output 51 [2018-02-02 09:50:24,144 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 73 DAG size of output 51 [2018-02-02 09:50:24,266 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 73 DAG size of output 51 [2018-02-02 09:50:24,397 WARN L146 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 76 DAG size of output 54 [2018-02-02 09:50:24,581 WARN L146 SmtUtils]: Spent 155ms on a formula simplification. DAG size of input: 88 DAG size of output 58 [2018-02-02 09:50:24,783 WARN L146 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 91 DAG size of output 61 [2018-02-02 09:50:24,927 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 61 DAG size of output 48 [2018-02-02 09:50:25,429 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:25,429 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:25,429 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-02-02 09:50:25,429 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:25,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:25,430 INFO L182 omatonBuilderFactory]: Interpolants [6092#true, 6093#false, 6094#(<= 1 main_~n~0), 6095#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 6096#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 6097#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 6098#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6099#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (or (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= main_~nondetString1~0.offset 0)), 6100#(and (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 9 (select |#length| |cstrncat_#in~dst.base|))) (<= 8 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 6101#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (or (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~dst.base))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 6102#(and (or (and (or (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (= cstrncat_~d~0.offset 0)), 6103#(and (or (and (or (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (= cstrncat_~d~0.offset 0)), 6104#(and (<= 1 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))))), 6105#(and (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))) (<= 1 cstrncat_~d~0.offset)), 6106#(and (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))) (<= 2 cstrncat_~d~0.offset)), 6107#(and (<= 2 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 6108#(and (<= 3 cstrncat_~d~0.offset) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 6109#(and (<= 3 cstrncat_~d~0.offset) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 6110#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))) (<= 4 cstrncat_~d~0.offset)), 6111#(and (<= 4 cstrncat_~d~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))))), 6112#(and (<= 5 cstrncat_~d~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 6113#(and (<= 5 cstrncat_~d~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 6114#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 6 cstrncat_~d~0.offset))), 6115#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 6 cstrncat_~d~0.offset))), 6116#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 7 cstrncat_~d~0.offset)), 6117#(and (<= 8 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:25,430 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:25,430 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-02-02 09:50:25,430 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-02-02 09:50:25,430 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=590, Unknown=0, NotChecked=0, Total=650 [2018-02-02 09:50:25,430 INFO L87 Difference]: Start difference. First operand 98 states and 112 transitions. Second operand 26 states. [2018-02-02 09:50:27,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:27,282 INFO L93 Difference]: Finished difference Result 134 states and 152 transitions. [2018-02-02 09:50:27,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 09:50:27,282 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 45 [2018-02-02 09:50:27,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:27,282 INFO L225 Difference]: With dead ends: 134 [2018-02-02 09:50:27,282 INFO L226 Difference]: Without dead ends: 133 [2018-02-02 09:50:27,283 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 518 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=206, Invalid=1956, Unknown=0, NotChecked=0, Total=2162 [2018-02-02 09:50:27,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-02-02 09:50:27,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 101. [2018-02-02 09:50:27,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-02-02 09:50:27,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 116 transitions. [2018-02-02 09:50:27,285 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 116 transitions. Word has length 45 [2018-02-02 09:50:27,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:27,286 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 116 transitions. [2018-02-02 09:50:27,286 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-02-02 09:50:27,286 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 116 transitions. [2018-02-02 09:50:27,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 09:50:27,286 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:27,286 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:27,286 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:27,286 INFO L82 PathProgramCache]: Analyzing trace with hash -1804660582, now seen corresponding path program 1 times [2018-02-02 09:50:27,287 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:27,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:27,296 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:27,876 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:27,876 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:27,876 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-02 09:50:27,877 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:27,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:27,877 INFO L182 omatonBuilderFactory]: Interpolants [6400#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6401#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0))) (or (and (= 0 |main_#t~malloc12.offset|) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))) (< (+ main_~n~0 2) main_~length1~0))), 6402#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (< (+ main_~n~0 2) main_~length1~0) (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6403#(or (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= main_~length2~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6404#(or (and (= 0 main_~nondetString2~0.offset) (<= (select |#length| main_~nondetString2~0.base) 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6405#(or (and (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)) (and (= 0 |cstrncat_#in~src.offset|) (<= (select |#length| |cstrncat_#in~src.base|) 2))), 6406#(or (and (<= (select |#length| cstrncat_~src.base) 2) (= 0 cstrncat_~src.offset)) (and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~dst.base)))), 6407#(or (and (<= 1 cstrncat_~n) (= cstrncat_~d~0.offset 0) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6408#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6409#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6410#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6411#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6412#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6413#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 6414#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (and (<= |cstrncat_#t~pre2| cstrncat_~n) (<= 0 |cstrncat_#t~pre2|) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6415#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)), 6416#(or (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6417#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 0 cstrncat_~d~0.offset))), 6418#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6419#(or (and (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6420#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6421#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 6422#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 6395#true, 6396#false, 6397#(or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)), 6398#(and (or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))), 6399#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0))))] [2018-02-02 09:50:27,877 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:27,877 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-02 09:50:27,878 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-02 09:50:27,878 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=675, Unknown=0, NotChecked=0, Total=756 [2018-02-02 09:50:27,878 INFO L87 Difference]: Start difference. First operand 101 states and 116 transitions. Second operand 28 states. [2018-02-02 09:50:28,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:28,939 INFO L93 Difference]: Finished difference Result 123 states and 137 transitions. [2018-02-02 09:50:28,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 09:50:28,940 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 46 [2018-02-02 09:50:28,940 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:28,940 INFO L225 Difference]: With dead ends: 123 [2018-02-02 09:50:28,940 INFO L226 Difference]: Without dead ends: 122 [2018-02-02 09:50:28,941 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 475 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=245, Invalid=1917, Unknown=0, NotChecked=0, Total=2162 [2018-02-02 09:50:28,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-02-02 09:50:28,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 103. [2018-02-02 09:50:28,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-02-02 09:50:28,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 119 transitions. [2018-02-02 09:50:28,942 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 119 transitions. Word has length 46 [2018-02-02 09:50:28,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:28,942 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 119 transitions. [2018-02-02 09:50:28,943 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-02 09:50:28,943 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 119 transitions. [2018-02-02 09:50:28,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 09:50:28,943 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:28,943 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:28,943 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:28,943 INFO L82 PathProgramCache]: Analyzing trace with hash 98715828, now seen corresponding path program 5 times [2018-02-02 09:50:28,944 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:28,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:28,950 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:29,517 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:29,517 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:29,517 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-02 09:50:29,517 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:29,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:29,518 INFO L182 omatonBuilderFactory]: Interpolants [6687#true, 6688#false, 6689#(or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)), 6690#(and (or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))), 6691#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)))), 6692#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6693#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0))) (or (and (= 0 |main_#t~malloc12.offset|) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))) (< (+ main_~n~0 2) main_~length1~0))), 6694#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (< (+ main_~n~0 2) main_~length1~0) (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6695#(or (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= main_~length2~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6696#(or (and (= 0 main_~nondetString2~0.offset) (<= (select |#length| main_~nondetString2~0.base) 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6697#(or (and (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)) (and (= 0 |cstrncat_#in~src.offset|) (<= (select |#length| |cstrncat_#in~src.base|) 2))), 6698#(or (and (<= (select |#length| cstrncat_~src.base) 2) (= 0 cstrncat_~src.offset)) (and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~dst.base)))), 6699#(or (and (<= 1 cstrncat_~n) (= cstrncat_~d~0.offset 0) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6700#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6701#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6702#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))), 6703#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 6704#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6705#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (and (<= |cstrncat_#t~pre2| cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)) (<= 0 |cstrncat_#t~pre2|))), 6706#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967296))) 4294967296)) 1) cstrncat_~n)), 6707#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967296))) 4294967296)) 1) cstrncat_~n)), 6708#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ (* 4294967296 (div (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)), 6709#(or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))), 6710#(or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6711#(or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 6712#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 6713#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 6714#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:29,518 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:29,518 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-02 09:50:29,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-02 09:50:29,519 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=675, Unknown=0, NotChecked=0, Total=756 [2018-02-02 09:50:29,519 INFO L87 Difference]: Start difference. First operand 103 states and 119 transitions. Second operand 28 states. [2018-02-02 09:50:30,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:30,672 INFO L93 Difference]: Finished difference Result 129 states and 143 transitions. [2018-02-02 09:50:30,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-02 09:50:30,672 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 47 [2018-02-02 09:50:30,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:30,672 INFO L225 Difference]: With dead ends: 129 [2018-02-02 09:50:30,672 INFO L226 Difference]: Without dead ends: 106 [2018-02-02 09:50:30,673 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 602 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=316, Invalid=2336, Unknown=0, NotChecked=0, Total=2652 [2018-02-02 09:50:30,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-02-02 09:50:30,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 103. [2018-02-02 09:50:30,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-02-02 09:50:30,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 118 transitions. [2018-02-02 09:50:30,675 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 118 transitions. Word has length 47 [2018-02-02 09:50:30,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:30,675 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 118 transitions. [2018-02-02 09:50:30,675 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-02 09:50:30,675 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 118 transitions. [2018-02-02 09:50:30,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 09:50:30,675 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:30,675 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:30,675 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:30,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1391354377, now seen corresponding path program 7 times [2018-02-02 09:50:30,676 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:30,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:30,689 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:31,533 WARN L146 SmtUtils]: Spent 445ms on a formula simplification. DAG size of input: 120 DAG size of output 85 [2018-02-02 09:50:31,739 WARN L146 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 90 DAG size of output 57 [2018-02-02 09:50:31,935 WARN L146 SmtUtils]: Spent 177ms on a formula simplification. DAG size of input: 90 DAG size of output 57 [2018-02-02 09:50:32,132 WARN L146 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 90 DAG size of output 57 [2018-02-02 09:50:32,337 WARN L146 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-02 09:50:32,580 WARN L146 SmtUtils]: Spent 214ms on a formula simplification. DAG size of input: 105 DAG size of output 63 [2018-02-02 09:50:32,806 WARN L146 SmtUtils]: Spent 193ms on a formula simplification. DAG size of input: 108 DAG size of output 66 [2018-02-02 09:50:32,968 WARN L146 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-02 09:50:33,140 WARN L146 SmtUtils]: Spent 145ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-02 09:50:33,727 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:33,728 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:33,728 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-02 09:50:33,728 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:33,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:33,728 INFO L182 omatonBuilderFactory]: Interpolants [6995#true, 6996#false, 6997#(<= 1 main_~n~0), 6998#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 6999#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 7000#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 7001#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7002#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7003#(and (or (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (or (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 7004#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))) (<= 8 (select |#length| cstrncat_~dst.base))) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (or (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 7005#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (or (<= 10 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))))), 7006#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (or (<= 10 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))))), 7007#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 7008#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7009#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7010#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7011#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7012#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7013#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7014#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7015#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7016#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7017#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7018#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7019#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 7020#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 7021#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 7022#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 7023#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:33,728 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:33,729 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-02 09:50:33,729 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-02 09:50:33,729 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=684, Unknown=0, NotChecked=0, Total=812 [2018-02-02 09:50:33,729 INFO L87 Difference]: Start difference. First operand 103 states and 118 transitions. Second operand 29 states. [2018-02-02 09:50:34,696 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 143 DAG size of output 140 [2018-02-02 09:50:34,936 WARN L146 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 141 DAG size of output 135 [2018-02-02 09:50:35,148 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 144 DAG size of output 141 [2018-02-02 09:50:35,355 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 135 DAG size of output 129 [2018-02-02 09:50:35,520 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 138 DAG size of output 135 [2018-02-02 09:50:35,710 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 128 DAG size of output 125 [2018-02-02 09:50:35,876 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 131 DAG size of output 128 [2018-02-02 09:50:36,030 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 122 DAG size of output 119 [2018-02-02 09:50:36,199 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 125 DAG size of output 122 [2018-02-02 09:50:36,336 WARN L146 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 115 DAG size of output 112 [2018-02-02 09:50:36,488 WARN L146 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 118 DAG size of output 115 [2018-02-02 09:50:36,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:36,744 INFO L93 Difference]: Finished difference Result 127 states and 144 transitions. [2018-02-02 09:50:36,745 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-02 09:50:36,745 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 48 [2018-02-02 09:50:36,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:36,745 INFO L225 Difference]: With dead ends: 127 [2018-02-02 09:50:36,745 INFO L226 Difference]: Without dead ends: 126 [2018-02-02 09:50:36,746 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 608 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=453, Invalid=2303, Unknown=0, NotChecked=0, Total=2756 [2018-02-02 09:50:36,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-02-02 09:50:36,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 106. [2018-02-02 09:50:36,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-02 09:50:36,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-02-02 09:50:36,748 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 48 [2018-02-02 09:50:36,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:36,748 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-02-02 09:50:36,748 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-02 09:50:36,748 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-02-02 09:50:36,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-02-02 09:50:36,749 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:36,749 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:36,749 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:36,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1574633716, now seen corresponding path program 2 times [2018-02-02 09:50:36,750 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:36,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:36,761 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:38,170 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:38,170 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:38,170 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 09:50:38,170 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:38,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:38,171 INFO L182 omatonBuilderFactory]: Interpolants [7305#true, 7306#false, 7307#(<= 1 main_~n~0), 7308#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7309#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7310#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7311#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 7312#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7313#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 7314#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 7315#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 7316#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 7317#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 7318#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))), 7319#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7320#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7321#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7322#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7323#(and (<= 1 cstrncat_~n) (<= 0 cstrncat_~d~0.offset) (= 0 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7324#(and (<= 1 cstrncat_~n) (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (<= 0 cstrncat_~d~0.offset) (= |cstrncat_#t~post3.offset| 0) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7325#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (<= 0 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7326#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= 1 cstrncat_~d~0.offset)), 7327#(and (<= 1 cstrncat_~s~0.offset) (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7328#(and (<= 1 cstrncat_~s~0.offset) (<= 1 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n))), 7329#(and (<= 1 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)) (<= 2 cstrncat_~s~0.offset)), 7330#(and (<= 2 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= 2 cstrncat_~s~0.offset)), 7331#(and (<= 2 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base)))) (<= 2 cstrncat_~s~0.offset)), 7332#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~d~0.offset) (<= 2 cstrncat_~s~0.offset)), 7333#(and (or (< 2 (select |#length| |cstrncat_#t~post3.base|)) (<= 2 |cstrncat_#t~post3.offset|)) (or (<= (select |#length| |cstrncat_#t~post3.base|) 2) (and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))))), 7334#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:38,171 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:38,171 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 09:50:38,171 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 09:50:38,172 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=786, Unknown=0, NotChecked=0, Total=870 [2018-02-02 09:50:38,172 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 30 states. [2018-02-02 09:50:39,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:39,182 INFO L93 Difference]: Finished difference Result 126 states and 142 transitions. [2018-02-02 09:50:39,182 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-02 09:50:39,182 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-02-02 09:50:39,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:39,182 INFO L225 Difference]: With dead ends: 126 [2018-02-02 09:50:39,183 INFO L226 Difference]: Without dead ends: 125 [2018-02-02 09:50:39,183 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 594 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=277, Invalid=2173, Unknown=0, NotChecked=0, Total=2450 [2018-02-02 09:50:39,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-02-02 09:50:39,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 106. [2018-02-02 09:50:39,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-02 09:50:39,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-02-02 09:50:39,185 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 49 [2018-02-02 09:50:39,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:39,185 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-02-02 09:50:39,185 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 09:50:39,185 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-02-02 09:50:39,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 09:50:39,186 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:39,186 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:39,186 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:39,186 INFO L82 PathProgramCache]: Analyzing trace with hash -1360385918, now seen corresponding path program 6 times [2018-02-02 09:50:39,186 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:39,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:39,198 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:39,750 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:39,751 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:39,751 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 09:50:39,751 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:39,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:39,751 INFO L182 omatonBuilderFactory]: Interpolants [7616#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 7617#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 7618#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 7619#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 7620#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))), 7621#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7622#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7623#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7624#(and (<= 1 cstrncat_~n) (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= |cstrncat_#t~post3.offset| 0)), 7625#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))), 7626#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7627#(and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)), 7628#(and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n))), 7629#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n)) (<= 2 cstrncat_~s~0.offset)), 7630#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n)) (<= 0 cstrncat_~d~0.offset) (<= 2 cstrncat_~s~0.offset)), 7631#(and (<= 1 cstrncat_~d~0.offset) (or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) 2)) (<= 2 cstrncat_~s~0.offset)), 7632#(and (<= 1 cstrncat_~d~0.offset) (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) 2) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 2 cstrncat_~s~0.offset)), 7633#(and (<= 1 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~s~0.offset)), 7634#(and (or (<= (select |#length| |cstrncat_#t~post3.base|) 2) (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)))) (or (< 2 (select |#length| |cstrncat_#t~post3.base|)) (<= 2 |cstrncat_#t~post3.offset|))), 7635#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 7636#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 7607#true, 7608#false, 7609#(<= 1 main_~n~0), 7610#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7611#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7612#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7613#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 7614#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7615#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0))] [2018-02-02 09:50:39,751 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:39,751 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 09:50:39,752 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 09:50:39,752 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=785, Unknown=0, NotChecked=0, Total=870 [2018-02-02 09:50:39,752 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 30 states. [2018-02-02 09:50:40,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:40,739 INFO L93 Difference]: Finished difference Result 130 states and 145 transitions. [2018-02-02 09:50:40,739 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-02 09:50:40,739 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 50 [2018-02-02 09:50:40,739 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:40,740 INFO L225 Difference]: With dead ends: 130 [2018-02-02 09:50:40,740 INFO L226 Difference]: Without dead ends: 107 [2018-02-02 09:50:40,740 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 658 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=315, Invalid=2441, Unknown=0, NotChecked=0, Total=2756 [2018-02-02 09:50:40,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-02-02 09:50:40,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 106. [2018-02-02 09:50:40,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-02 09:50:40,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 121 transitions. [2018-02-02 09:50:40,741 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 121 transitions. Word has length 50 [2018-02-02 09:50:40,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:40,741 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 121 transitions. [2018-02-02 09:50:40,742 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 09:50:40,742 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 121 transitions. [2018-02-02 09:50:40,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-02 09:50:40,742 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:40,742 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:40,742 INFO L371 AbstractCegarLoop]: === Iteration 38 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:40,742 INFO L82 PathProgramCache]: Analyzing trace with hash -891126789, now seen corresponding path program 8 times [2018-02-02 09:50:40,743 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:40,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:40,755 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:42,235 WARN L146 SmtUtils]: Spent 524ms on a formula simplification. DAG size of input: 141 DAG size of output 93 [2018-02-02 09:50:42,543 WARN L146 SmtUtils]: Spent 254ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-02 09:50:42,827 WARN L146 SmtUtils]: Spent 263ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-02 09:50:43,082 WARN L146 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-02 09:50:43,341 WARN L146 SmtUtils]: Spent 234ms on a formula simplification. DAG size of input: 112 DAG size of output 66 [2018-02-02 09:50:43,631 WARN L146 SmtUtils]: Spent 260ms on a formula simplification. DAG size of input: 125 DAG size of output 70 [2018-02-02 09:50:43,957 WARN L146 SmtUtils]: Spent 293ms on a formula simplification. DAG size of input: 128 DAG size of output 73 [2018-02-02 09:50:44,173 WARN L146 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-02 09:50:44,396 WARN L146 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-02 09:50:44,541 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-02 09:50:44,712 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-02 09:50:45,305 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:45,306 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:45,306 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 09:50:45,306 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:45,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:45,307 INFO L182 omatonBuilderFactory]: Interpolants [7936#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7937#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7938#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7939#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7940#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7941#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7942#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7943#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7944#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7945#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 7946#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))), 7947#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 7948#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 7919#true, 7920#false, 7921#(<= 1 main_~n~0), 7922#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 7923#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 7924#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 7925#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7926#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7927#(and (or (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (or (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 10 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 7928#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (or (<= 11 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 7929#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 10 (select |#length| cstrncat_~d~0.base)) (or (<= 11 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))), 7930#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 10 (select |#length| cstrncat_~d~0.base)) (or (<= 11 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))), 7931#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 7932#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7933#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7934#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7935#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))] [2018-02-02 09:50:45,307 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:45,307 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 09:50:45,307 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 09:50:45,307 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=726, Unknown=0, NotChecked=0, Total=870 [2018-02-02 09:50:45,307 INFO L87 Difference]: Start difference. First operand 106 states and 121 transitions. Second operand 30 states. [2018-02-02 09:50:45,957 WARN L143 SmtUtils]: Spent 109ms on a formula simplification that was a NOOP. DAG size: 160 [2018-02-02 09:50:46,119 WARN L143 SmtUtils]: Spent 101ms on a formula simplification that was a NOOP. DAG size: 167 [2018-02-02 09:50:46,343 WARN L146 SmtUtils]: Spent 195ms on a formula simplification. DAG size of input: 173 DAG size of output 172 [2018-02-02 09:50:46,559 WARN L146 SmtUtils]: Spent 171ms on a formula simplification. DAG size of input: 161 DAG size of output 158 [2018-02-02 09:50:46,808 WARN L146 SmtUtils]: Spent 206ms on a formula simplification. DAG size of input: 167 DAG size of output 161 [2018-02-02 09:50:47,009 WARN L146 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 158 DAG size of output 152 [2018-02-02 09:50:47,203 WARN L146 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 164 DAG size of output 155 [2018-02-02 09:50:47,402 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 152 DAG size of output 146 [2018-02-02 09:50:47,604 WARN L146 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 158 DAG size of output 149 [2018-02-02 09:50:47,780 WARN L146 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 146 DAG size of output 141 [2018-02-02 09:50:47,967 WARN L146 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 152 DAG size of output 143 [2018-02-02 09:50:48,170 WARN L146 SmtUtils]: Spent 134ms on a formula simplification. DAG size of input: 140 DAG size of output 134 [2018-02-02 09:50:48,360 WARN L146 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 146 DAG size of output 137 [2018-02-02 09:50:48,531 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 134 DAG size of output 128 [2018-02-02 09:50:48,718 WARN L146 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 140 DAG size of output 134 [2018-02-02 09:50:48,880 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 126 DAG size of output 123 [2018-02-02 09:50:49,042 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 131 DAG size of output 126 [2018-02-02 09:50:49,188 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 120 DAG size of output 117 [2018-02-02 09:50:49,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:49,338 INFO L93 Difference]: Finished difference Result 130 states and 147 transitions. [2018-02-02 09:50:49,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-02 09:50:49,339 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 51 [2018-02-02 09:50:49,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:49,339 INFO L225 Difference]: With dead ends: 130 [2018-02-02 09:50:49,339 INFO L226 Difference]: Without dead ends: 129 [2018-02-02 09:50:49,340 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 700 ImplicationChecksByTransitivity, 7.3s TimeCoverageRelationStatistics Valid=516, Invalid=2564, Unknown=0, NotChecked=0, Total=3080 [2018-02-02 09:50:49,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-02-02 09:50:49,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 109. [2018-02-02 09:50:49,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-02 09:50:49,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 125 transitions. [2018-02-02 09:50:49,342 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 125 transitions. Word has length 51 [2018-02-02 09:50:49,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:49,343 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 125 transitions. [2018-02-02 09:50:49,343 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 09:50:49,343 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 125 transitions. [2018-02-02 09:50:49,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-02 09:50:49,343 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:49,343 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:49,344 INFO L371 AbstractCegarLoop]: === Iteration 39 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:49,344 INFO L82 PathProgramCache]: Analyzing trace with hash 682894170, now seen corresponding path program 3 times [2018-02-02 09:50:49,344 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:49,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:49,362 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:50,169 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:50,169 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:50,169 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-02 09:50:50,169 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:50,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:50,170 INFO L182 omatonBuilderFactory]: Interpolants [8256#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8257#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8258#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8259#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8260#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0))), 8261#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 8262#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 8263#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base)) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|))), 8264#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n)), 8265#(or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8266#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 0 cstrncat_~d~0.offset))), 8267#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8268#(or (and (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8269#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8270#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 8271#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8240#true, 8241#false, 8242#(<= 1 main_~n~0), 8243#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8244#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8245#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8246#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 8247#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8248#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8249#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (or (and (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 8250#(and (or (and (or (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1))))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))))) (= 0 |cstrncat_#in~src.offset|) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 8251#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (or (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 2) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1)))))) (= 0 cstrncat_~src.offset)), 8252#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))))), 8253#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))))), 8254#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 8255#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))))] [2018-02-02 09:50:50,170 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:50,170 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-02 09:50:50,170 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-02 09:50:50,170 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=881, Unknown=0, NotChecked=0, Total=992 [2018-02-02 09:50:50,171 INFO L87 Difference]: Start difference. First operand 109 states and 125 transitions. Second operand 32 states. [2018-02-02 09:50:50,717 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 113 DAG size of output 108 [2018-02-02 09:50:50,866 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 120 DAG size of output 117 [2018-02-02 09:50:51,717 WARN L146 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 52 DAG size of output 39 [2018-02-02 09:50:51,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:51,819 INFO L93 Difference]: Finished difference Result 129 states and 145 transitions. [2018-02-02 09:50:51,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-02 09:50:51,820 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 52 [2018-02-02 09:50:51,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:51,820 INFO L225 Difference]: With dead ends: 129 [2018-02-02 09:50:51,820 INFO L226 Difference]: Without dead ends: 128 [2018-02-02 09:50:51,821 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 719 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=353, Invalid=2403, Unknown=0, NotChecked=0, Total=2756 [2018-02-02 09:50:51,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-02-02 09:50:51,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 109. [2018-02-02 09:50:51,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-02 09:50:51,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 125 transitions. [2018-02-02 09:50:51,823 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 125 transitions. Word has length 52 [2018-02-02 09:50:51,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:51,824 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 125 transitions. [2018-02-02 09:50:51,824 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-02 09:50:51,824 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 125 transitions. [2018-02-02 09:50:51,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 09:50:51,824 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:51,824 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:51,824 INFO L371 AbstractCegarLoop]: === Iteration 40 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:51,825 INFO L82 PathProgramCache]: Analyzing trace with hash -96498188, now seen corresponding path program 7 times [2018-02-02 09:50:51,825 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:51,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:51,839 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:52,477 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 09:50:52,478 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 09:50:52,478 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-02 09:50:52,478 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 09:50:52,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 09:50:52,478 INFO L182 omatonBuilderFactory]: Interpolants [8576#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8552#true, 8553#false, 8554#(<= main_~n~0 2147483647), 8555#(and (<= main_~n~0 2147483647) (<= 1 main_~n~0)), 8556#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 8557#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 8558#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 8559#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8560#(and (<= main_~n~0 2147483647) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8561#(and (<= |cstrncat_#in~n| 2147483647) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)))) (<= 1 |cstrncat_#in~n|)), 8562#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 8563#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 8564#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 2147483647) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)))), 8565#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 2147483647) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)))), 8566#(and (<= 1 cstrncat_~n) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483647)), 8567#(and (<= 1 cstrncat_~n) (or (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483647)), 8568#(and (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483646) (<= 0 |cstrncat_#t~pre2|)), 8569#(and (or (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n))) (<= cstrncat_~n 2147483646)), 8570#(and (<= cstrncat_~n 2147483646) (or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~n cstrncat_~d~0.offset)))), 8571#(and (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~n cstrncat_~d~0.offset)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= cstrncat_~n 2147483645)), 8572#(and (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~n cstrncat_~d~0.offset))) (<= cstrncat_~n 2147483645)), 8573#(and (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~n cstrncat_~d~0.offset))) (<= cstrncat_~n 2147483645) (<= 0 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8574#(and (or (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483645) (<= 1 cstrncat_~d~0.offset) (<= cstrncat_~d~0.offset (select |#length| cstrncat_~d~0.base))), 8575#(and (<= 1 cstrncat_~d~0.offset) (<= (div |cstrncat_#t~pre2| 4294967296) 0) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset)) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~d~0.offset (select |#length| cstrncat_~d~0.base)))] [2018-02-02 09:50:52,478 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 09:50:52,478 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-02 09:50:52,479 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-02 09:50:52,479 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=539, Unknown=0, NotChecked=0, Total=600 [2018-02-02 09:50:52,479 INFO L87 Difference]: Start difference. First operand 109 states and 125 transitions. Second operand 25 states. [2018-02-02 09:50:53,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 09:50:53,177 INFO L93 Difference]: Finished difference Result 117 states and 127 transitions. [2018-02-02 09:50:53,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-02 09:50:53,177 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 53 [2018-02-02 09:50:53,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 09:50:53,178 INFO L225 Difference]: With dead ends: 117 [2018-02-02 09:50:53,178 INFO L226 Difference]: Without dead ends: 97 [2018-02-02 09:50:53,178 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 412 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=212, Invalid=1768, Unknown=0, NotChecked=0, Total=1980 [2018-02-02 09:50:53,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-02-02 09:50:53,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 88. [2018-02-02 09:50:53,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-02-02 09:50:53,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 99 transitions. [2018-02-02 09:50:53,179 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 99 transitions. Word has length 53 [2018-02-02 09:50:53,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 09:50:53,179 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 99 transitions. [2018-02-02 09:50:53,179 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-02 09:50:53,180 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 99 transitions. [2018-02-02 09:50:53,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-02 09:50:53,180 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 09:50:53,180 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 09:50:53,180 INFO L371 AbstractCegarLoop]: === Iteration 41 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-02 09:50:53,180 INFO L82 PathProgramCache]: Analyzing trace with hash -365312823, now seen corresponding path program 9 times [2018-02-02 09:50:53,180 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 09:50:53,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 09:50:53,193 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 09:50:54,922 WARN L146 SmtUtils]: Spent 473ms on a formula simplification. DAG size of input: 168 DAG size of output 101 Received shutdown request... [2018-02-02 09:50:54,970 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 09:50:54,973 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 09:50:54,973 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 09:50:54 BoogieIcfgContainer [2018-02-02 09:50:54,974 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 09:50:54,974 INFO L168 Benchmark]: Toolchain (without parser) took 53928.06 ms. Allocated memory was 401.6 MB in the beginning and 1.2 GB in the end (delta: 778.0 MB). Free memory was 358.5 MB in the beginning and 632.5 MB in the end (delta: -274.0 MB). Peak memory consumption was 504.0 MB. Max. memory is 5.3 GB. [2018-02-02 09:50:54,975 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 401.6 MB. Free memory is still 365.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 09:50:54,975 INFO L168 Benchmark]: CACSL2BoogieTranslator took 157.13 ms. Allocated memory is still 401.6 MB. Free memory was 358.5 MB in the beginning and 347.9 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-02-02 09:50:54,975 INFO L168 Benchmark]: Boogie Preprocessor took 29.68 ms. Allocated memory is still 401.6 MB. Free memory was 347.9 MB in the beginning and 346.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-02 09:50:54,975 INFO L168 Benchmark]: RCFGBuilder took 226.96 ms. Allocated memory is still 401.6 MB. Free memory was 346.6 MB in the beginning and 325.9 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 5.3 GB. [2018-02-02 09:50:54,976 INFO L168 Benchmark]: TraceAbstraction took 53511.50 ms. Allocated memory was 401.6 MB in the beginning and 1.2 GB in the end (delta: 778.0 MB). Free memory was 324.6 MB in the beginning and 632.5 MB in the end (delta: -307.9 MB). Peak memory consumption was 470.1 MB. Max. memory is 5.3 GB. [2018-02-02 09:50:54,976 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 401.6 MB. Free memory is still 365.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 157.13 ms. Allocated memory is still 401.6 MB. Free memory was 358.5 MB in the beginning and 347.9 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 29.68 ms. Allocated memory is still 401.6 MB. Free memory was 347.9 MB in the beginning and 346.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 226.96 ms. Allocated memory is still 401.6 MB. Free memory was 346.6 MB in the beginning and 325.9 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 53511.50 ms. Allocated memory was 401.6 MB in the beginning and 1.2 GB in the end (delta: 778.0 MB). Free memory was 324.6 MB in the beginning and 632.5 MB in the end (delta: -307.9 MB). Peak memory consumption was 470.1 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 574). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 573). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 574). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 573). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 557]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 557). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 553). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 546). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 546). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 553). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was analyzing trace of length 55 with TraceHistMax 12, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 130. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 54 locations, 13 error locations. TIMEOUT Result, 53.4s OverallTime, 41 OverallIterations, 12 TraceHistogramMax, 28.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1230 SDtfs, 3304 SDslu, 8120 SDs, 0 SdLazy, 12903 SolverSat, 1075 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1146 GetRequests, 52 SyntacticMatches, 14 SemanticMatches, 1080 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8979 ImplicationChecksByTransitivity, 39.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=118occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 19/1017 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 40 MinimizatonAttempts, 489 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 22.4s InterpolantComputationTime, 1350 NumberOfCodeBlocks, 1350 NumberOfCodeBlocksAsserted, 40 NumberOfCheckSat, 1310 ConstructedInterpolants, 0 QuantifiedInterpolants, 1291104 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 40 InterpolantComputations, 13 PerfectInterpolantSequences, 19/1017 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_09-50-54-981.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_09-50-54-981.csv Completed graceful shutdown