java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-ccafca9-m [2018-02-04 00:45:36,151 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 00:45:36,152 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 00:45:36,164 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 00:45:36,164 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 00:45:36,165 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 00:45:36,165 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 00:45:36,167 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 00:45:36,168 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 00:45:36,169 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 00:45:36,170 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 00:45:36,170 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 00:45:36,171 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 00:45:36,171 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 00:45:36,172 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 00:45:36,174 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 00:45:36,175 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 00:45:36,177 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 00:45:36,178 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 00:45:36,179 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 00:45:36,180 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 00:45:36,180 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 00:45:36,181 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 00:45:36,181 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 00:45:36,182 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 00:45:36,183 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 00:45:36,183 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 00:45:36,183 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 00:45:36,184 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 00:45:36,184 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 00:45:36,184 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 00:45:36,184 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-02-04 00:45:36,192 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 00:45:36,192 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 00:45:36,193 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 00:45:36,193 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 00:45:36,193 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 00:45:36,193 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 00:45:36,194 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 00:45:36,195 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 00:45:36,195 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 00:45:36,195 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 00:45:36,195 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 00:45:36,195 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 00:45:36,195 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 00:45:36,195 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 00:45:36,195 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 00:45:36,196 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-02-04 00:45:36,222 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 00:45:36,230 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 00:45:36,232 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 00:45:36,233 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 00:45:36,234 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 00:45:36,234 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_true-valid-memsafety_true-termination.i [2018-02-04 00:45:36,362 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 00:45:36,363 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 00:45:36,363 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 00:45:36,364 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 00:45:36,367 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 00:45:36,368 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,370 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b275d44 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36, skipping insertion in model container [2018-02-04 00:45:36,370 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,379 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 00:45:36,414 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 00:45:36,507 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 00:45:36,529 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 00:45:36,538 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36 WrapperNode [2018-02-04 00:45:36,538 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 00:45:36,538 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 00:45:36,539 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 00:45:36,539 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 00:45:36,550 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,551 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,560 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,561 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,568 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,571 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,572 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... [2018-02-04 00:45:36,575 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 00:45:36,575 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 00:45:36,575 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 00:45:36,575 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 00:45:36,577 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-04 00:45:36,613 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_get_drvdata [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_set_drvdata [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_arvo_device_struct [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_specials [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure lvd_arvo_remove_specials [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_probe [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_remove [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 00:45:36,614 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 00:45:36,614 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 00:45:36,614 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 00:45:36,614 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 00:45:36,614 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 00:45:36,614 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 00:45:36,614 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-02-04 00:45:36,615 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-04 00:45:36,615 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_get_drvdata [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_set_drvdata [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_arvo_device_struct [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_specials [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure lvd_arvo_remove_specials [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_probe [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_remove [2018-02-04 00:45:36,616 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 00:45:36,617 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 00:45:36,617 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 00:45:36,617 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 00:45:36,971 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 00:45:36,972 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 12:45:36 BoogieIcfgContainer [2018-02-04 00:45:36,972 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 00:45:36,973 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 00:45:36,973 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 00:45:36,975 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 00:45:36,975 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 12:45:36" (1/3) ... [2018-02-04 00:45:36,976 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@29cbaa07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 12:45:36, skipping insertion in model container [2018-02-04 00:45:36,976 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 12:45:36" (2/3) ... [2018-02-04 00:45:36,976 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@29cbaa07 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 12:45:36, skipping insertion in model container [2018-02-04 00:45:36,976 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 12:45:36" (3/3) ... [2018-02-04 00:45:36,978 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test15_true-valid-memsafety_true-termination.i [2018-02-04 00:45:36,983 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 00:45:36,991 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 45 error locations. [2018-02-04 00:45:37,017 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 00:45:37,017 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 00:45:37,017 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 00:45:37,017 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 00:45:37,017 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 00:45:37,017 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 00:45:37,017 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 00:45:37,017 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 00:45:37,018 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 00:45:37,028 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states. [2018-02-04 00:45:37,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-04 00:45:37,035 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:37,036 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:37,036 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:37,038 INFO L82 PathProgramCache]: Analyzing trace with hash -26265707, now seen corresponding path program 1 times [2018-02-04 00:45:37,039 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:37,040 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:37,074 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,074 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,074 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,115 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:37,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 00:45:37,171 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:45:37,171 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 00:45:37,220 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 00:45:37,231 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 00:45:37,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 00:45:37,233 INFO L87 Difference]: Start difference. First operand 173 states. Second operand 3 states. [2018-02-04 00:45:37,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:37,408 INFO L93 Difference]: Finished difference Result 230 states and 259 transitions. [2018-02-04 00:45:37,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 00:45:37,409 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-02-04 00:45:37,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:37,418 INFO L225 Difference]: With dead ends: 230 [2018-02-04 00:45:37,418 INFO L226 Difference]: Without dead ends: 224 [2018-02-04 00:45:37,419 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 00:45:37,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-02-04 00:45:37,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 174. [2018-02-04 00:45:37,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 00:45:37,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 190 transitions. [2018-02-04 00:45:37,456 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 190 transitions. Word has length 16 [2018-02-04 00:45:37,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:37,457 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 190 transitions. [2018-02-04 00:45:37,457 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 00:45:37,457 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 190 transitions. [2018-02-04 00:45:37,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-02-04 00:45:37,458 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:37,459 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:37,459 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:37,459 INFO L82 PathProgramCache]: Analyzing trace with hash -325108585, now seen corresponding path program 1 times [2018-02-04 00:45:37,459 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:37,459 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:37,461 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,461 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,461 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:37,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 00:45:37,521 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:45:37,521 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:45:37,523 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 00:45:37,523 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 00:45:37,523 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 00:45:37,523 INFO L87 Difference]: Start difference. First operand 174 states and 190 transitions. Second operand 6 states. [2018-02-04 00:45:37,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:37,574 INFO L93 Difference]: Finished difference Result 215 states and 240 transitions. [2018-02-04 00:45:37,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 00:45:37,574 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 18 [2018-02-04 00:45:37,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:37,576 INFO L225 Difference]: With dead ends: 215 [2018-02-04 00:45:37,576 INFO L226 Difference]: Without dead ends: 215 [2018-02-04 00:45:37,577 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:45:37,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-02-04 00:45:37,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 170. [2018-02-04 00:45:37,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-02-04 00:45:37,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 183 transitions. [2018-02-04 00:45:37,586 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 183 transitions. Word has length 18 [2018-02-04 00:45:37,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:37,586 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 183 transitions. [2018-02-04 00:45:37,586 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 00:45:37,586 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 183 transitions. [2018-02-04 00:45:37,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 00:45:37,587 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:37,587 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:37,587 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:37,587 INFO L82 PathProgramCache]: Analyzing trace with hash 743711378, now seen corresponding path program 1 times [2018-02-04 00:45:37,587 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:37,587 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:37,588 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,588 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,588 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,599 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:37,634 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:37,635 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:37,635 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:37,641 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,660 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:37,682 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:37,699 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:37,699 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 8 [2018-02-04 00:45:37,699 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 00:45:37,699 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 00:45:37,700 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:45:37,700 INFO L87 Difference]: Start difference. First operand 170 states and 183 transitions. Second operand 8 states. [2018-02-04 00:45:37,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:37,720 INFO L93 Difference]: Finished difference Result 174 states and 188 transitions. [2018-02-04 00:45:37,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 00:45:37,721 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 21 [2018-02-04 00:45:37,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:37,722 INFO L225 Difference]: With dead ends: 174 [2018-02-04 00:45:37,722 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 00:45:37,722 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:45:37,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 00:45:37,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 172. [2018-02-04 00:45:37,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-02-04 00:45:37,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 186 transitions. [2018-02-04 00:45:37,730 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 186 transitions. Word has length 21 [2018-02-04 00:45:37,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:37,731 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 186 transitions. [2018-02-04 00:45:37,731 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 00:45:37,731 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 186 transitions. [2018-02-04 00:45:37,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-02-04 00:45:37,732 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:37,732 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:37,732 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:37,732 INFO L82 PathProgramCache]: Analyzing trace with hash 667479760, now seen corresponding path program 1 times [2018-02-04 00:45:37,732 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:37,732 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:37,734 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,734 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,734 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,745 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:37,783 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:37,783 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:37,783 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:37,789 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,809 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:37,822 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:37,846 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:37,846 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-02-04 00:45:37,846 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 00:45:37,846 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 00:45:37,846 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 00:45:37,847 INFO L87 Difference]: Start difference. First operand 172 states and 186 transitions. Second operand 6 states. [2018-02-04 00:45:37,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:37,870 INFO L93 Difference]: Finished difference Result 171 states and 185 transitions. [2018-02-04 00:45:37,871 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 00:45:37,871 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-02-04 00:45:37,871 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:37,872 INFO L225 Difference]: With dead ends: 171 [2018-02-04 00:45:37,872 INFO L226 Difference]: Without dead ends: 171 [2018-02-04 00:45:37,872 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 21 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:45:37,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-02-04 00:45:37,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. [2018-02-04 00:45:37,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-02-04 00:45:37,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 185 transitions. [2018-02-04 00:45:37,879 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 185 transitions. Word has length 23 [2018-02-04 00:45:37,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:37,880 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 185 transitions. [2018-02-04 00:45:37,880 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 00:45:37,880 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 185 transitions. [2018-02-04 00:45:37,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-02-04 00:45:37,880 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:37,881 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:37,881 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:37,881 INFO L82 PathProgramCache]: Analyzing trace with hash 667479761, now seen corresponding path program 1 times [2018-02-04 00:45:37,881 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:37,881 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:37,882 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,882 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,882 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:37,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,899 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:37,953 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 00:45:37,953 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:37,953 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:37,962 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:37,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:37,980 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:38,007 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:45:38,008 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:38,010 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:45:38,010 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:45:38,017 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 00:45:38,042 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:38,042 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-02-04 00:45:38,043 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:45:38,043 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:45:38,043 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:45:38,043 INFO L87 Difference]: Start difference. First operand 171 states and 185 transitions. Second operand 7 states. [2018-02-04 00:45:38,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:38,310 INFO L93 Difference]: Finished difference Result 216 states and 238 transitions. [2018-02-04 00:45:38,311 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 00:45:38,311 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-02-04 00:45:38,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:38,312 INFO L225 Difference]: With dead ends: 216 [2018-02-04 00:45:38,312 INFO L226 Difference]: Without dead ends: 216 [2018-02-04 00:45:38,312 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:45:38,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-02-04 00:45:38,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 184. [2018-02-04 00:45:38,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-02-04 00:45:38,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 211 transitions. [2018-02-04 00:45:38,318 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 211 transitions. Word has length 23 [2018-02-04 00:45:38,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:38,318 INFO L432 AbstractCegarLoop]: Abstraction has 184 states and 211 transitions. [2018-02-04 00:45:38,318 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:45:38,318 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 211 transitions. [2018-02-04 00:45:38,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-04 00:45:38,319 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:38,319 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:38,319 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:38,319 INFO L82 PathProgramCache]: Analyzing trace with hash -314305773, now seen corresponding path program 1 times [2018-02-04 00:45:38,319 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:38,319 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:38,320 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:38,320 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:38,320 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:38,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:38,329 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:38,356 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:45:38,356 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:45:38,356 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:45:38,356 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 00:45:38,356 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 00:45:38,356 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 00:45:38,356 INFO L87 Difference]: Start difference. First operand 184 states and 211 transitions. Second operand 6 states. [2018-02-04 00:45:38,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:38,412 INFO L93 Difference]: Finished difference Result 220 states and 251 transitions. [2018-02-04 00:45:38,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 00:45:38,412 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-02-04 00:45:38,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:38,413 INFO L225 Difference]: With dead ends: 220 [2018-02-04 00:45:38,413 INFO L226 Difference]: Without dead ends: 220 [2018-02-04 00:45:38,413 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:45:38,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-02-04 00:45:38,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 184. [2018-02-04 00:45:38,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-02-04 00:45:38,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 210 transitions. [2018-02-04 00:45:38,418 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 210 transitions. Word has length 25 [2018-02-04 00:45:38,418 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:38,418 INFO L432 AbstractCegarLoop]: Abstraction has 184 states and 210 transitions. [2018-02-04 00:45:38,418 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 00:45:38,418 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 210 transitions. [2018-02-04 00:45:38,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 00:45:38,418 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:38,418 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:38,418 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:38,419 INFO L82 PathProgramCache]: Analyzing trace with hash -808960356, now seen corresponding path program 1 times [2018-02-04 00:45:38,419 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:38,419 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:38,420 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:38,420 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:38,420 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:38,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:38,432 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:38,530 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:38,530 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:38,530 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:38,535 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:38,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:38,548 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:38,642 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:38,659 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:38,659 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 8] total 12 [2018-02-04 00:45:38,659 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 00:45:38,659 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 00:45:38,659 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=122, Unknown=9, NotChecked=0, Total=156 [2018-02-04 00:45:38,659 INFO L87 Difference]: Start difference. First operand 184 states and 210 transitions. Second operand 13 states. [2018-02-04 00:45:39,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:39,487 INFO L93 Difference]: Finished difference Result 220 states and 242 transitions. [2018-02-04 00:45:39,487 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 00:45:39,487 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 26 [2018-02-04 00:45:39,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:39,488 INFO L225 Difference]: With dead ends: 220 [2018-02-04 00:45:39,488 INFO L226 Difference]: Without dead ends: 216 [2018-02-04 00:45:39,489 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 24 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=50, Invalid=247, Unknown=9, NotChecked=0, Total=306 [2018-02-04 00:45:39,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-02-04 00:45:39,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 183. [2018-02-04 00:45:39,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-02-04 00:45:39,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 208 transitions. [2018-02-04 00:45:39,495 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 208 transitions. Word has length 26 [2018-02-04 00:45:39,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:39,495 INFO L432 AbstractCegarLoop]: Abstraction has 183 states and 208 transitions. [2018-02-04 00:45:39,495 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 00:45:39,495 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 208 transitions. [2018-02-04 00:45:39,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 00:45:39,496 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:39,496 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:39,496 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:39,497 INFO L82 PathProgramCache]: Analyzing trace with hash 437179314, now seen corresponding path program 1 times [2018-02-04 00:45:39,497 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:39,497 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:39,498 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:39,498 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:39,498 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:39,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:39,506 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:39,535 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 00:45:39,536 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:39,536 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:39,543 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:39,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:39,561 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:39,571 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:39,588 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:45:39,588 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 5 [2018-02-04 00:45:39,589 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 00:45:39,589 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 00:45:39,589 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 00:45:39,590 INFO L87 Difference]: Start difference. First operand 183 states and 208 transitions. Second operand 5 states. [2018-02-04 00:45:39,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:39,626 INFO L93 Difference]: Finished difference Result 173 states and 185 transitions. [2018-02-04 00:45:39,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 00:45:39,627 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-02-04 00:45:39,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:39,628 INFO L225 Difference]: With dead ends: 173 [2018-02-04 00:45:39,628 INFO L226 Difference]: Without dead ends: 171 [2018-02-04 00:45:39,629 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 27 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 00:45:39,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-02-04 00:45:39,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 171. [2018-02-04 00:45:39,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-02-04 00:45:39,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 183 transitions. [2018-02-04 00:45:39,632 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 183 transitions. Word has length 28 [2018-02-04 00:45:39,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:39,633 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 183 transitions. [2018-02-04 00:45:39,633 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 00:45:39,633 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 183 transitions. [2018-02-04 00:45:39,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-04 00:45:39,633 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:39,634 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:39,634 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:39,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1753876656, now seen corresponding path program 2 times [2018-02-04 00:45:39,634 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:39,634 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:39,635 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:39,635 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:39,635 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:39,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:39,643 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:39,677 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:45:39,678 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:39,678 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:39,685 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 00:45:39,704 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 00:45:39,704 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 00:45:39,706 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:39,712 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:45:39,712 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:39,714 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:45:39,714 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:45:39,717 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:45:39,746 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:39,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-02-04 00:45:39,747 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:45:39,747 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:45:39,747 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:45:39,748 INFO L87 Difference]: Start difference. First operand 171 states and 183 transitions. Second operand 7 states. [2018-02-04 00:45:40,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:40,063 INFO L93 Difference]: Finished difference Result 189 states and 205 transitions. [2018-02-04 00:45:40,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 00:45:40,066 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 30 [2018-02-04 00:45:40,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:40,067 INFO L225 Difference]: With dead ends: 189 [2018-02-04 00:45:40,067 INFO L226 Difference]: Without dead ends: 189 [2018-02-04 00:45:40,067 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:45:40,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-02-04 00:45:40,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 186. [2018-02-04 00:45:40,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-02-04 00:45:40,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 205 transitions. [2018-02-04 00:45:40,073 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 205 transitions. Word has length 30 [2018-02-04 00:45:40,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:40,073 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 205 transitions. [2018-02-04 00:45:40,073 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:45:40,073 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 205 transitions. [2018-02-04 00:45:40,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-04 00:45:40,074 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:40,074 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:40,074 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:40,074 INFO L82 PathProgramCache]: Analyzing trace with hash 1753876657, now seen corresponding path program 1 times [2018-02-04 00:45:40,074 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:40,074 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:40,075 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:40,075 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 00:45:40,075 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:40,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:40,085 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:40,202 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 00:45:40,202 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:40,202 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:40,208 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:40,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:40,232 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:40,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 00:45:40,247 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:40,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 00:45:40,268 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:40,276 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 00:45:40,276 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 00:45:40,351 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 00:45:40,379 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:40,379 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-02-04 00:45:40,379 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 00:45:40,379 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 00:45:40,379 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2018-02-04 00:45:40,380 INFO L87 Difference]: Start difference. First operand 186 states and 205 transitions. Second operand 13 states. [2018-02-04 00:45:40,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:40,856 INFO L93 Difference]: Finished difference Result 216 states and 240 transitions. [2018-02-04 00:45:40,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 00:45:40,856 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 30 [2018-02-04 00:45:40,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:40,857 INFO L225 Difference]: With dead ends: 216 [2018-02-04 00:45:40,857 INFO L226 Difference]: Without dead ends: 216 [2018-02-04 00:45:40,858 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-02-04 00:45:40,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-02-04 00:45:40,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 204. [2018-02-04 00:45:40,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-02-04 00:45:40,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 236 transitions. [2018-02-04 00:45:40,861 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 236 transitions. Word has length 30 [2018-02-04 00:45:40,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:40,861 INFO L432 AbstractCegarLoop]: Abstraction has 204 states and 236 transitions. [2018-02-04 00:45:40,861 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 00:45:40,861 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 236 transitions. [2018-02-04 00:45:40,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-04 00:45:40,862 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:40,862 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:40,862 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:40,862 INFO L82 PathProgramCache]: Analyzing trace with hash 1756950194, now seen corresponding path program 1 times [2018-02-04 00:45:40,862 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:40,862 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:40,864 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:40,864 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:40,864 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:40,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:40,873 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:40,942 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:45:40,942 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:40,942 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:40,947 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:40,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:40,960 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:40,963 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:45:40,963 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:40,964 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:45:40,964 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:45:40,980 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:40,981 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:40,982 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:45:40,983 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:40,986 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:45:40,986 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-02-04 00:45:41,005 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:45:41,023 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:41,024 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-02-04 00:45:41,024 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 00:45:41,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 00:45:41,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=86, Unknown=1, NotChecked=0, Total=110 [2018-02-04 00:45:41,024 INFO L87 Difference]: Start difference. First operand 204 states and 236 transitions. Second operand 11 states. [2018-02-04 00:45:41,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:41,427 INFO L93 Difference]: Finished difference Result 223 states and 255 transitions. [2018-02-04 00:45:41,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 00:45:41,427 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 32 [2018-02-04 00:45:41,428 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:41,428 INFO L225 Difference]: With dead ends: 223 [2018-02-04 00:45:41,428 INFO L226 Difference]: Without dead ends: 223 [2018-02-04 00:45:41,429 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 29 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=37, Invalid=118, Unknown=1, NotChecked=0, Total=156 [2018-02-04 00:45:41,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-02-04 00:45:41,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 210. [2018-02-04 00:45:41,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-02-04 00:45:41,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 244 transitions. [2018-02-04 00:45:41,434 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 244 transitions. Word has length 32 [2018-02-04 00:45:41,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:41,435 INFO L432 AbstractCegarLoop]: Abstraction has 210 states and 244 transitions. [2018-02-04 00:45:41,435 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 00:45:41,435 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 244 transitions. [2018-02-04 00:45:41,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-04 00:45:41,435 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:41,435 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:41,436 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:41,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1756950195, now seen corresponding path program 1 times [2018-02-04 00:45:41,436 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:41,436 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:41,437 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:41,437 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:41,437 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:41,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:41,446 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:41,584 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 00:45:41,584 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:41,584 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:41,589 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:41,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:41,601 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:41,610 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 00:45:41,610 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,621 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 00:45:41,621 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,631 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 00:45:41,631 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,632 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 00:45:41,632 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,640 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 00:45:41,641 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 00:45:41,733 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:41,734 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:41,735 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-02-04 00:45:41,735 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,766 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:41,767 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 37 [2018-02-04 00:45:41,767 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,783 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:41,783 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:41,784 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 26 [2018-02-04 00:45:41,784 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,797 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 00:45:41,797 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:41,810 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 00:45:41,810 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-02-04 00:45:41,842 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 00:45:41,859 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:41,859 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-02-04 00:45:41,859 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 00:45:41,859 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 00:45:41,859 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=261, Unknown=1, NotChecked=0, Total=306 [2018-02-04 00:45:41,859 INFO L87 Difference]: Start difference. First operand 210 states and 244 transitions. Second operand 18 states. [2018-02-04 00:45:53,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:53,891 INFO L93 Difference]: Finished difference Result 224 states and 251 transitions. [2018-02-04 00:45:53,891 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 00:45:53,891 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 32 [2018-02-04 00:45:53,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:53,892 INFO L225 Difference]: With dead ends: 224 [2018-02-04 00:45:53,892 INFO L226 Difference]: Without dead ends: 224 [2018-02-04 00:45:53,892 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=384, Unknown=1, NotChecked=0, Total=462 [2018-02-04 00:45:53,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-02-04 00:45:53,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 179. [2018-02-04 00:45:53,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-02-04 00:45:53,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 195 transitions. [2018-02-04 00:45:53,897 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 195 transitions. Word has length 32 [2018-02-04 00:45:53,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:53,897 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 195 transitions. [2018-02-04 00:45:53,897 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 00:45:53,898 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 195 transitions. [2018-02-04 00:45:53,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 00:45:53,898 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:53,898 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:53,898 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:53,898 INFO L82 PathProgramCache]: Analyzing trace with hash 860002885, now seen corresponding path program 1 times [2018-02-04 00:45:53,899 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:53,899 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:53,899 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:53,900 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:53,900 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:53,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:53,906 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:54,030 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:54,030 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:54,030 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:54,040 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:54,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:54,062 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:54,068 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:45:54,068 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:54,069 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:45:54,069 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:45:54,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:54,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:54,111 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:45:54,111 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:54,116 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:45:54,116 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 00:45:54,183 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:54,184 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 15 [2018-02-04 00:45:54,184 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:54,190 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:45:54,190 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:25, output treesize:15 [2018-02-04 00:45:54,212 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 8 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 00:45:54,239 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:54,239 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 16 [2018-02-04 00:45:54,239 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 00:45:54,239 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 00:45:54,240 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=232, Unknown=0, NotChecked=0, Total=272 [2018-02-04 00:45:54,240 INFO L87 Difference]: Start difference. First operand 179 states and 195 transitions. Second operand 17 states. [2018-02-04 00:45:54,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:54,776 INFO L93 Difference]: Finished difference Result 193 states and 213 transitions. [2018-02-04 00:45:54,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 00:45:54,777 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 35 [2018-02-04 00:45:54,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:54,777 INFO L225 Difference]: With dead ends: 193 [2018-02-04 00:45:54,777 INFO L226 Difference]: Without dead ends: 193 [2018-02-04 00:45:54,777 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 29 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=70, Invalid=392, Unknown=0, NotChecked=0, Total=462 [2018-02-04 00:45:54,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-02-04 00:45:54,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 179. [2018-02-04 00:45:54,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-02-04 00:45:54,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 195 transitions. [2018-02-04 00:45:54,780 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 195 transitions. Word has length 35 [2018-02-04 00:45:54,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:54,780 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 195 transitions. [2018-02-04 00:45:54,780 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 00:45:54,780 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 195 transitions. [2018-02-04 00:45:54,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 00:45:54,781 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:54,781 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:54,781 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:54,781 INFO L82 PathProgramCache]: Analyzing trace with hash 890317459, now seen corresponding path program 1 times [2018-02-04 00:45:54,781 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:54,781 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:54,782 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:54,782 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:54,782 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:54,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:54,786 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:54,838 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 00:45:54,839 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:45:54,839 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:45:54,839 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 00:45:54,839 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 00:45:54,839 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 00:45:54,839 INFO L87 Difference]: Start difference. First operand 179 states and 195 transitions. Second operand 6 states. [2018-02-04 00:45:54,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:54,920 INFO L93 Difference]: Finished difference Result 187 states and 203 transitions. [2018-02-04 00:45:54,920 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 00:45:54,920 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-02-04 00:45:54,921 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:54,921 INFO L225 Difference]: With dead ends: 187 [2018-02-04 00:45:54,921 INFO L226 Difference]: Without dead ends: 187 [2018-02-04 00:45:54,922 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:45:54,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-02-04 00:45:54,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 183. [2018-02-04 00:45:54,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-02-04 00:45:54,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 199 transitions. [2018-02-04 00:45:54,926 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 199 transitions. Word has length 36 [2018-02-04 00:45:54,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:54,926 INFO L432 AbstractCegarLoop]: Abstraction has 183 states and 199 transitions. [2018-02-04 00:45:54,926 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 00:45:54,926 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 199 transitions. [2018-02-04 00:45:54,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 00:45:54,929 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:54,929 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:54,929 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:54,929 INFO L82 PathProgramCache]: Analyzing trace with hash 866086568, now seen corresponding path program 1 times [2018-02-04 00:45:54,929 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:54,929 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:54,930 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:54,930 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:54,930 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:54,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:54,941 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:55,258 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 00:45:55,258 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:55,259 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:55,266 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:55,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:55,285 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:55,531 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 00:45:55,548 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:45:55,548 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 12] total 19 [2018-02-04 00:45:55,549 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 00:45:55,549 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 00:45:55,549 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=327, Unknown=10, NotChecked=0, Total=380 [2018-02-04 00:45:55,549 INFO L87 Difference]: Start difference. First operand 183 states and 199 transitions. Second operand 20 states. [2018-02-04 00:45:56,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:56,539 INFO L93 Difference]: Finished difference Result 195 states and 211 transitions. [2018-02-04 00:45:56,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 00:45:56,539 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 38 [2018-02-04 00:45:56,539 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:56,540 INFO L225 Difference]: With dead ends: 195 [2018-02-04 00:45:56,540 INFO L226 Difference]: Without dead ends: 184 [2018-02-04 00:45:56,540 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 33 SyntacticMatches, 6 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=89, Invalid=657, Unknown=10, NotChecked=0, Total=756 [2018-02-04 00:45:56,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-02-04 00:45:56,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 177. [2018-02-04 00:45:56,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-02-04 00:45:56,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 192 transitions. [2018-02-04 00:45:56,543 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 192 transitions. Word has length 38 [2018-02-04 00:45:56,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:56,544 INFO L432 AbstractCegarLoop]: Abstraction has 177 states and 192 transitions. [2018-02-04 00:45:56,544 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 00:45:56,544 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 192 transitions. [2018-02-04 00:45:56,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 00:45:56,544 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:56,544 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:56,545 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:56,545 INFO L82 PathProgramCache]: Analyzing trace with hash 499648277, now seen corresponding path program 1 times [2018-02-04 00:45:56,545 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:56,545 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:56,546 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:56,546 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:56,546 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:56,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:56,554 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:56,597 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:45:56,597 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:45:56,597 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:45:56,598 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:45:56,598 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:45:56,598 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:45:56,598 INFO L87 Difference]: Start difference. First operand 177 states and 192 transitions. Second operand 7 states. [2018-02-04 00:45:56,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:56,704 INFO L93 Difference]: Finished difference Result 176 states and 191 transitions. [2018-02-04 00:45:56,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 00:45:56,704 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 38 [2018-02-04 00:45:56,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:56,705 INFO L225 Difference]: With dead ends: 176 [2018-02-04 00:45:56,705 INFO L226 Difference]: Without dead ends: 176 [2018-02-04 00:45:56,705 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 00:45:56,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-02-04 00:45:56,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2018-02-04 00:45:56,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-02-04 00:45:56,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 191 transitions. [2018-02-04 00:45:56,708 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 191 transitions. Word has length 38 [2018-02-04 00:45:56,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:56,708 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 191 transitions. [2018-02-04 00:45:56,708 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:45:56,709 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 191 transitions. [2018-02-04 00:45:56,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 00:45:56,709 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:56,709 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:56,709 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:56,709 INFO L82 PathProgramCache]: Analyzing trace with hash 499648278, now seen corresponding path program 1 times [2018-02-04 00:45:56,709 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:56,709 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:56,710 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:56,710 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:56,711 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:56,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:56,719 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:56,836 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 00:45:56,836 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:45:56,836 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 00:45:56,837 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 00:45:56,837 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 00:45:56,837 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:45:56,837 INFO L87 Difference]: Start difference. First operand 176 states and 191 transitions. Second operand 8 states. [2018-02-04 00:45:57,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:45:57,064 INFO L93 Difference]: Finished difference Result 177 states and 192 transitions. [2018-02-04 00:45:57,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 00:45:57,065 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 38 [2018-02-04 00:45:57,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:45:57,066 INFO L225 Difference]: With dead ends: 177 [2018-02-04 00:45:57,066 INFO L226 Difference]: Without dead ends: 177 [2018-02-04 00:45:57,066 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2018-02-04 00:45:57,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-04 00:45:57,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 175. [2018-02-04 00:45:57,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-04 00:45:57,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 190 transitions. [2018-02-04 00:45:57,070 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 190 transitions. Word has length 38 [2018-02-04 00:45:57,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:45:57,070 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 190 transitions. [2018-02-04 00:45:57,071 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 00:45:57,071 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 190 transitions. [2018-02-04 00:45:57,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-04 00:45:57,072 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:45:57,072 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:45:57,072 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:45:57,072 INFO L82 PathProgramCache]: Analyzing trace with hash -874341065, now seen corresponding path program 1 times [2018-02-04 00:45:57,072 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:45:57,072 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:45:57,073 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:57,073 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:57,074 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:45:57,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:57,086 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:45:57,396 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:45:57,396 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:45:57,396 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:45:57,404 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:45:57,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:45:57,433 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:45:57,451 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 00:45:57,452 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,469 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 00:45:57,469 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,491 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 00:45:57,491 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,493 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 00:45:57,493 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,504 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 00:45:57,504 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 00:45:57,687 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,688 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,689 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 44 [2018-02-04 00:45:57,689 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,721 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,723 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 41 [2018-02-04 00:45:57,723 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,753 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 47 [2018-02-04 00:45:57,753 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,776 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,782 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 41 [2018-02-04 00:45:57,783 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:57,799 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 4 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:45:57,799 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:79, output treesize:69 [2018-02-04 00:45:57,948 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,949 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,950 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:57,950 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 46 [2018-02-04 00:45:57,951 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,041 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-02-04 00:45:58,041 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,119 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 48 [2018-02-04 00:45:58,122 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,188 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,189 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,190 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,191 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 48 [2018-02-04 00:45:58,191 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,245 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,246 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 67 [2018-02-04 00:45:58,247 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,335 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,336 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,337 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,338 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 63 [2018-02-04 00:45:58,338 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,430 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,431 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,432 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,433 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,433 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 50 [2018-02-04 00:45:58,434 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,505 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,506 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,507 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:45:58,508 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 67 [2018-02-04 00:45:58,509 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-02-04 00:45:58,584 INFO L267 ElimStorePlain]: Start of recursive call 1: 8 dim-0 vars, 8 dim-1 vars, End of recursive call: 8 dim-0 vars, and 4 xjuncts. [2018-02-04 00:45:58,584 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 16 variables, input treesize:213, output treesize:165 [2018-02-04 00:46:00,711 WARN L143 SmtUtils]: Spent 2082ms on a formula simplification that was a NOOP. DAG size: 75 [2018-02-04 00:46:00,717 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 49 [2018-02-04 00:46:00,719 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:46:00,719 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,726 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,795 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 49 [2018-02-04 00:46:00,797 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:46:00,797 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,804 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 51 [2018-02-04 00:46:00,860 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:46:00,860 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,868 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,917 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 55 [2018-02-04 00:46:00,919 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:46:00,919 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,932 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:46:00,980 INFO L267 ElimStorePlain]: Start of recursive call 1: 12 dim-0 vars, 4 dim-2 vars, End of recursive call: 8 dim-0 vars, and 4 xjuncts. [2018-02-04 00:46:00,980 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 16 variables, input treesize:217, output treesize:213 [2018-02-04 00:46:02,968 WARN L143 SmtUtils]: Spent 1944ms on a formula simplification that was a NOOP. DAG size: 80 [2018-02-04 00:46:02,981 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 57 [2018-02-04 00:46:02,983 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2018-02-04 00:46:02,984 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:02,994 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,035 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 43 [2018-02-04 00:46:03,036 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 9 [2018-02-04 00:46:03,036 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,043 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,084 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 49 [2018-02-04 00:46:03,085 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 14 [2018-02-04 00:46:03,086 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,093 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 47 [2018-02-04 00:46:03,134 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 12 [2018-02-04 00:46:03,134 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,141 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:46:03,188 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 4 dim-2 vars, End of recursive call: 16 dim-0 vars, and 4 xjuncts. [2018-02-04 00:46:03,188 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 20 variables, input treesize:213, output treesize:165 [2018-02-04 00:46:26,519 WARN L146 SmtUtils]: Spent 19261ms on a formula simplification. DAG size of input: 91 DAG size of output 71 [2018-02-04 00:46:26,548 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 13 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:46:26,565 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:46:26,565 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 16] total 26 [2018-02-04 00:46:26,565 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 00:46:26,566 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 00:46:26,566 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=611, Unknown=4, NotChecked=0, Total=702 [2018-02-04 00:46:26,566 INFO L87 Difference]: Start difference. First operand 175 states and 190 transitions. Second operand 27 states. [2018-02-04 00:46:39,012 WARN L146 SmtUtils]: Spent 1973ms on a formula simplification. DAG size of input: 85 DAG size of output 59 [2018-02-04 00:46:39,287 WARN L146 SmtUtils]: Spent 235ms on a formula simplification. DAG size of input: 114 DAG size of output 80 [2018-02-04 00:46:43,001 WARN L146 SmtUtils]: Spent 3684ms on a formula simplification. DAG size of input: 90 DAG size of output 64 [2018-02-04 00:46:45,193 WARN L146 SmtUtils]: Spent 2132ms on a formula simplification. DAG size of input: 85 DAG size of output 85 [2018-02-04 00:47:05,637 WARN L146 SmtUtils]: Spent 20381ms on a formula simplification. DAG size of input: 91 DAG size of output 91 [2018-02-04 00:47:18,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:18,242 INFO L93 Difference]: Finished difference Result 205 states and 224 transitions. [2018-02-04 00:47:18,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 00:47:18,242 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 40 [2018-02-04 00:47:18,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:18,243 INFO L225 Difference]: With dead ends: 205 [2018-02-04 00:47:18,243 INFO L226 Difference]: Without dead ends: 205 [2018-02-04 00:47:18,243 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 27 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 286 ImplicationChecksByTransitivity, 58.7s TimeCoverageRelationStatistics Valid=182, Invalid=1145, Unknown=5, NotChecked=0, Total=1332 [2018-02-04 00:47:18,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-02-04 00:47:18,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 174. [2018-02-04 00:47:18,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 00:47:18,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 189 transitions. [2018-02-04 00:47:18,246 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 189 transitions. Word has length 40 [2018-02-04 00:47:18,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:18,246 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 189 transitions. [2018-02-04 00:47:18,246 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 00:47:18,246 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 189 transitions. [2018-02-04 00:47:18,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-04 00:47:18,246 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:18,246 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:18,246 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:18,246 INFO L82 PathProgramCache]: Analyzing trace with hash -904842582, now seen corresponding path program 1 times [2018-02-04 00:47:18,247 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:18,247 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:18,247 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,247 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:18,247 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:18,251 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:18,279 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:18,279 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:18,279 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 00:47:18,279 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:47:18,280 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:47:18,280 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:47:18,280 INFO L87 Difference]: Start difference. First operand 174 states and 189 transitions. Second operand 7 states. [2018-02-04 00:47:18,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:18,338 INFO L93 Difference]: Finished difference Result 172 states and 186 transitions. [2018-02-04 00:47:18,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 00:47:18,338 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 40 [2018-02-04 00:47:18,338 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:18,339 INFO L225 Difference]: With dead ends: 172 [2018-02-04 00:47:18,339 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 00:47:18,339 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 00:47:18,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 00:47:18,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 172. [2018-02-04 00:47:18,341 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-02-04 00:47:18,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 186 transitions. [2018-02-04 00:47:18,342 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 186 transitions. Word has length 40 [2018-02-04 00:47:18,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:18,342 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 186 transitions. [2018-02-04 00:47:18,342 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:47:18,342 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 186 transitions. [2018-02-04 00:47:18,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-02-04 00:47:18,342 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:18,342 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:18,342 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:18,343 INFO L82 PathProgramCache]: Analyzing trace with hash -1596182576, now seen corresponding path program 1 times [2018-02-04 00:47:18,343 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:18,343 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:18,343 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,343 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:18,343 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:18,349 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:18,391 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:18,391 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:18,391 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:47:18,391 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:47:18,391 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:47:18,392 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:47:18,392 INFO L87 Difference]: Start difference. First operand 172 states and 186 transitions. Second operand 7 states. [2018-02-04 00:47:18,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:18,506 INFO L93 Difference]: Finished difference Result 178 states and 193 transitions. [2018-02-04 00:47:18,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 00:47:18,507 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 45 [2018-02-04 00:47:18,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:18,507 INFO L225 Difference]: With dead ends: 178 [2018-02-04 00:47:18,507 INFO L226 Difference]: Without dead ends: 178 [2018-02-04 00:47:18,508 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-04 00:47:18,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-02-04 00:47:18,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 171. [2018-02-04 00:47:18,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-02-04 00:47:18,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 185 transitions. [2018-02-04 00:47:18,511 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 185 transitions. Word has length 45 [2018-02-04 00:47:18,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:18,512 INFO L432 AbstractCegarLoop]: Abstraction has 171 states and 185 transitions. [2018-02-04 00:47:18,512 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:47:18,512 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 185 transitions. [2018-02-04 00:47:18,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-02-04 00:47:18,512 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:18,512 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:18,513 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:18,513 INFO L82 PathProgramCache]: Analyzing trace with hash -1596182575, now seen corresponding path program 1 times [2018-02-04 00:47:18,513 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:18,513 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:18,514 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,514 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:18,514 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:18,524 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:18,616 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:18,616 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:18,617 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:18,624 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:18,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:18,654 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:18,722 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:18,740 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:18,740 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [10] total 15 [2018-02-04 00:47:18,740 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 00:47:18,741 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 00:47:18,741 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-04 00:47:18,741 INFO L87 Difference]: Start difference. First operand 171 states and 185 transitions. Second operand 16 states. [2018-02-04 00:47:18,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:18,907 INFO L93 Difference]: Finished difference Result 177 states and 192 transitions. [2018-02-04 00:47:18,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 00:47:18,908 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 45 [2018-02-04 00:47:18,908 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:18,909 INFO L225 Difference]: With dead ends: 177 [2018-02-04 00:47:18,909 INFO L226 Difference]: Without dead ends: 177 [2018-02-04 00:47:18,909 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2018-02-04 00:47:18,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-04 00:47:18,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 170. [2018-02-04 00:47:18,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-02-04 00:47:18,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 184 transitions. [2018-02-04 00:47:18,912 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 184 transitions. Word has length 45 [2018-02-04 00:47:18,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:18,912 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 184 transitions. [2018-02-04 00:47:18,912 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 00:47:18,912 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 184 transitions. [2018-02-04 00:47:18,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 00:47:18,912 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:18,912 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:18,913 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:18,913 INFO L82 PathProgramCache]: Analyzing trace with hash -628127471, now seen corresponding path program 1 times [2018-02-04 00:47:18,913 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:18,913 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:18,914 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,914 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:18,914 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:18,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:18,929 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:19,079 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:19,079 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:19,079 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:19,088 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:19,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:19,119 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:19,139 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:47:19,140 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:19,141 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,142 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,145 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,146 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:11 [2018-02-04 00:47:19,227 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-02-04 00:47:19,229 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-02-04 00:47:19,229 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,230 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,231 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,231 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:5 [2018-02-04 00:47:19,234 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:19,267 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:19,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [13] total 19 [2018-02-04 00:47:19,267 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 00:47:19,267 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 00:47:19,268 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=335, Unknown=0, NotChecked=0, Total=380 [2018-02-04 00:47:19,268 INFO L87 Difference]: Start difference. First operand 170 states and 184 transitions. Second operand 20 states. [2018-02-04 00:47:19,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:19,627 INFO L93 Difference]: Finished difference Result 171 states and 185 transitions. [2018-02-04 00:47:19,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 00:47:19,628 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 47 [2018-02-04 00:47:19,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:19,628 INFO L225 Difference]: With dead ends: 171 [2018-02-04 00:47:19,628 INFO L226 Difference]: Without dead ends: 171 [2018-02-04 00:47:19,629 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 41 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=566, Unknown=0, NotChecked=0, Total=650 [2018-02-04 00:47:19,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states. [2018-02-04 00:47:19,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 169. [2018-02-04 00:47:19,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-02-04 00:47:19,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 183 transitions. [2018-02-04 00:47:19,631 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 183 transitions. Word has length 47 [2018-02-04 00:47:19,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:19,631 INFO L432 AbstractCegarLoop]: Abstraction has 169 states and 183 transitions. [2018-02-04 00:47:19,631 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 00:47:19,631 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 183 transitions. [2018-02-04 00:47:19,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 00:47:19,632 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:19,632 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:19,632 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:19,632 INFO L82 PathProgramCache]: Analyzing trace with hash -628127470, now seen corresponding path program 1 times [2018-02-04 00:47:19,632 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:19,632 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:19,633 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:19,633 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:19,633 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:19,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:19,645 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:19,876 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 11 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 00:47:19,877 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:19,877 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:19,882 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:19,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:19,901 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:19,918 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:47:19,920 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:19,920 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,922 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,929 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 00:47:19,930 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 00:47:19,930 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,932 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,937 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:19,937 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:41, output treesize:27 [2018-02-04 00:47:20,021 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 23 [2018-02-04 00:47:20,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2018-02-04 00:47:20,023 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,024 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,027 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2018-02-04 00:47:20,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 9 [2018-02-04 00:47:20,029 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,030 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,032 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,032 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:45, output treesize:9 [2018-02-04 00:47:20,060 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:20,077 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:20,077 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [18] total 26 [2018-02-04 00:47:20,077 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 00:47:20,077 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 00:47:20,077 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=636, Unknown=0, NotChecked=0, Total=702 [2018-02-04 00:47:20,078 INFO L87 Difference]: Start difference. First operand 169 states and 183 transitions. Second operand 27 states. [2018-02-04 00:47:20,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:20,482 INFO L93 Difference]: Finished difference Result 170 states and 184 transitions. [2018-02-04 00:47:20,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 00:47:20,482 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 47 [2018-02-04 00:47:20,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:20,483 INFO L225 Difference]: With dead ends: 170 [2018-02-04 00:47:20,483 INFO L226 Difference]: Without dead ends: 170 [2018-02-04 00:47:20,483 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 39 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 164 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=117, Invalid=1005, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 00:47:20,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2018-02-04 00:47:20,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 168. [2018-02-04 00:47:20,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-02-04 00:47:20,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 182 transitions. [2018-02-04 00:47:20,486 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 182 transitions. Word has length 47 [2018-02-04 00:47:20,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:20,487 INFO L432 AbstractCegarLoop]: Abstraction has 168 states and 182 transitions. [2018-02-04 00:47:20,487 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 00:47:20,487 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 182 transitions. [2018-02-04 00:47:20,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 00:47:20,487 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:20,487 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:20,487 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:20,488 INFO L82 PathProgramCache]: Analyzing trace with hash 2002884989, now seen corresponding path program 1 times [2018-02-04 00:47:20,488 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:20,488 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:20,489 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:20,489 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:20,489 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:20,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:20,503 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:20,854 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 6 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 00:47:20,854 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:20,854 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:20,859 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:20,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:20,878 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:20,880 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:47:20,880 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,881 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,881 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:47:20,972 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:20,972 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:20,973 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:47:20,973 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,976 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:20,976 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 00:47:21,017 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:21,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:21,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:21,019 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 34 [2018-02-04 00:47:21,019 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,024 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,024 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:26, output treesize:28 [2018-02-04 00:47:21,067 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:47:21,068 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:21,068 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,069 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,076 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,077 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:41, output treesize:46 [2018-02-04 00:47:21,146 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 63 [2018-02-04 00:47:21,148 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 00:47:21,148 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,151 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,174 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,174 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:83, output treesize:46 [2018-02-04 00:47:21,177 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 00:47:21,179 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 00:47:21,179 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,184 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,198 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2018-02-04 00:47:21,200 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:21,200 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,206 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,216 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,216 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:74, output treesize:100 [2018-02-04 00:47:21,420 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 75 [2018-02-04 00:47:21,421 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 75 treesize of output 56 [2018-02-04 00:47:21,421 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,425 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,434 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:21,434 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:118, output treesize:91 [2018-02-04 00:47:21,527 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 61 [2018-02-04 00:47:21,529 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 18 [2018-02-04 00:47:21,529 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:21,536 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 14 [2018-02-04 00:47:21,537 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:21,541 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:21,547 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:21,548 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:97, output treesize:28 [2018-02-04 00:47:21,595 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 00:47:21,611 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:21,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [21] imperfect sequences [22] total 41 [2018-02-04 00:47:21,612 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-02-04 00:47:21,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-02-04 00:47:21,612 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=1616, Unknown=0, NotChecked=0, Total=1722 [2018-02-04 00:47:21,612 INFO L87 Difference]: Start difference. First operand 168 states and 182 transitions. Second operand 42 states. [2018-02-04 00:47:23,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:23,609 INFO L93 Difference]: Finished difference Result 181 states and 199 transitions. [2018-02-04 00:47:23,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-04 00:47:23,609 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 48 [2018-02-04 00:47:23,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:23,610 INFO L225 Difference]: With dead ends: 181 [2018-02-04 00:47:23,610 INFO L226 Difference]: Without dead ends: 181 [2018-02-04 00:47:23,610 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 30 SyntacticMatches, 3 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 404 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=256, Invalid=3050, Unknown=0, NotChecked=0, Total=3306 [2018-02-04 00:47:23,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-02-04 00:47:23,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 167. [2018-02-04 00:47:23,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-02-04 00:47:23,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 181 transitions. [2018-02-04 00:47:23,613 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 181 transitions. Word has length 48 [2018-02-04 00:47:23,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:23,613 INFO L432 AbstractCegarLoop]: Abstraction has 167 states and 181 transitions. [2018-02-04 00:47:23,613 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-02-04 00:47:23,613 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 181 transitions. [2018-02-04 00:47:23,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 00:47:23,613 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:23,613 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:23,613 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:23,614 INFO L82 PathProgramCache]: Analyzing trace with hash 2002884990, now seen corresponding path program 1 times [2018-02-04 00:47:23,614 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:23,614 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:23,614 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:23,614 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:23,614 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:23,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:23,630 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:24,291 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 11 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 00:47:24,291 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:24,322 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:24,327 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:24,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:24,348 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:24,354 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:47:24,354 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:24,355 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:24,355 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:47:24,478 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:24,478 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:24,478 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:47:24,479 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:24,481 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:24,481 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 00:47:24,528 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 00:47:24,528 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:24,540 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 00:47:24,540 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:24,550 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:47:24,550 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:48, output treesize:46 [2018-02-04 00:47:26,664 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:26,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:26,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:26,666 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 30 [2018-02-04 00:47:26,666 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,682 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:26,682 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:26,683 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:26,683 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 28 [2018-02-04 00:47:26,683 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,699 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:47:26,699 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:73, output treesize:59 [2018-02-04 00:47:26,768 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 48 [2018-02-04 00:47:26,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:26,770 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,777 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,806 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 50 [2018-02-04 00:47:26,808 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:26,808 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,815 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,837 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 44 [2018-02-04 00:47:26,838 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:26,838 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,844 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,864 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 46 [2018-02-04 00:47:26,865 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:26,865 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,872 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:26,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:47:26,888 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 8 variables, input treesize:105, output treesize:107 [2018-02-04 00:47:27,047 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 148 treesize of output 139 [2018-02-04 00:47:27,049 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 00:47:27,049 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,060 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,102 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 78 [2018-02-04 00:47:27,103 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 00:47:27,104 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,108 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,116 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 4 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:27,116 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 7 variables, input treesize:299, output treesize:71 [2018-02-04 00:47:27,175 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 45 [2018-02-04 00:47:27,177 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 00:47:27,177 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,182 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,195 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 67 [2018-02-04 00:47:27,197 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:27,197 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,204 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,214 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:27,214 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:99, output treesize:155 [2018-02-04 00:47:27,684 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 192 treesize of output 149 [2018-02-04 00:47:27,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 78 [2018-02-04 00:47:27,686 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:27,695 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 35 [2018-02-04 00:47:27,696 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,703 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:27,712 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 42 [2018-02-04 00:47:27,714 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 26 [2018-02-04 00:47:27,714 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:27,718 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 11 [2018-02-04 00:47:27,719 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,721 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:27,726 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:27,726 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 5 variables, input treesize:197, output treesize:23 [2018-02-04 00:47:27,787 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:47:27,804 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:47:27,804 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24] total 47 [2018-02-04 00:47:27,804 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-02-04 00:47:27,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-02-04 00:47:27,805 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=2148, Unknown=1, NotChecked=0, Total=2256 [2018-02-04 00:47:27,805 INFO L87 Difference]: Start difference. First operand 167 states and 181 transitions. Second operand 48 states. [2018-02-04 00:47:29,819 WARN L146 SmtUtils]: Spent 1879ms on a formula simplification. DAG size of input: 45 DAG size of output 39 [2018-02-04 00:47:33,831 WARN L146 SmtUtils]: Spent 3662ms on a formula simplification. DAG size of input: 55 DAG size of output 48 [2018-02-04 00:47:39,962 WARN L146 SmtUtils]: Spent 6044ms on a formula simplification. DAG size of input: 87 DAG size of output 77 [2018-02-04 00:47:43,577 WARN L146 SmtUtils]: Spent 3425ms on a formula simplification. DAG size of input: 74 DAG size of output 62 [2018-02-04 00:47:44,887 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 115 DAG size of output 102 [2018-02-04 00:47:46,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:46,166 INFO L93 Difference]: Finished difference Result 180 states and 198 transitions. [2018-02-04 00:47:46,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 00:47:46,166 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 48 [2018-02-04 00:47:46,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:46,167 INFO L225 Difference]: With dead ends: 180 [2018-02-04 00:47:46,167 INFO L226 Difference]: Without dead ends: 180 [2018-02-04 00:47:46,168 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 27 SyntacticMatches, 1 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 385 ImplicationChecksByTransitivity, 20.1s TimeCoverageRelationStatistics Valid=294, Invalid=4127, Unknown=1, NotChecked=0, Total=4422 [2018-02-04 00:47:46,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-02-04 00:47:46,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 166. [2018-02-04 00:47:46,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-02-04 00:47:46,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 180 transitions. [2018-02-04 00:47:46,170 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 180 transitions. Word has length 48 [2018-02-04 00:47:46,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:46,170 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 180 transitions. [2018-02-04 00:47:46,170 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-02-04 00:47:46,170 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 180 transitions. [2018-02-04 00:47:46,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-04 00:47:46,171 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:46,171 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:46,171 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:46,171 INFO L82 PathProgramCache]: Analyzing trace with hash -411236025, now seen corresponding path program 1 times [2018-02-04 00:47:46,171 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:46,171 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:46,172 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:46,172 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:46,172 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:46,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:46,178 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:46,250 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:46,250 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:46,250 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 00:47:46,251 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 00:47:46,251 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 00:47:46,251 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-02-04 00:47:46,251 INFO L87 Difference]: Start difference. First operand 166 states and 180 transitions. Second operand 11 states. [2018-02-04 00:47:46,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:46,433 INFO L93 Difference]: Finished difference Result 182 states and 196 transitions. [2018-02-04 00:47:46,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 00:47:46,433 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 54 [2018-02-04 00:47:46,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:46,434 INFO L225 Difference]: With dead ends: 182 [2018-02-04 00:47:46,434 INFO L226 Difference]: Without dead ends: 182 [2018-02-04 00:47:46,434 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=175, Unknown=0, NotChecked=0, Total=210 [2018-02-04 00:47:46,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-02-04 00:47:46,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 174. [2018-02-04 00:47:46,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 00:47:46,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-04 00:47:46,436 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 54 [2018-02-04 00:47:46,437 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:46,437 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-04 00:47:46,437 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 00:47:46,437 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-04 00:47:46,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-04 00:47:46,438 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:46,438 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:46,438 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:46,438 INFO L82 PathProgramCache]: Analyzing trace with hash -411236024, now seen corresponding path program 1 times [2018-02-04 00:47:46,438 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:46,438 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:46,439 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:46,439 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:46,439 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:46,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:46,448 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:46,567 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:46,567 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:46,567 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:46,572 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:46,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:46,592 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:46,652 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:46,669 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:47:46,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 18 [2018-02-04 00:47:46,669 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 00:47:46,670 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 00:47:46,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=302, Unknown=0, NotChecked=0, Total=342 [2018-02-04 00:47:46,670 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 19 states. [2018-02-04 00:47:46,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:46,879 INFO L93 Difference]: Finished difference Result 181 states and 195 transitions. [2018-02-04 00:47:46,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 00:47:46,879 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 54 [2018-02-04 00:47:46,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:46,880 INFO L225 Difference]: With dead ends: 181 [2018-02-04 00:47:46,880 INFO L226 Difference]: Without dead ends: 181 [2018-02-04 00:47:46,880 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 45 SyntacticMatches, 5 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 81 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=81, Invalid=621, Unknown=0, NotChecked=0, Total=702 [2018-02-04 00:47:46,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-02-04 00:47:46,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 174. [2018-02-04 00:47:46,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 00:47:46,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 187 transitions. [2018-02-04 00:47:46,883 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 187 transitions. Word has length 54 [2018-02-04 00:47:46,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:46,883 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 187 transitions. [2018-02-04 00:47:46,883 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 00:47:46,883 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 187 transitions. [2018-02-04 00:47:46,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-04 00:47:46,884 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:46,884 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:46,884 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:46,884 INFO L82 PathProgramCache]: Analyzing trace with hash -473136990, now seen corresponding path program 1 times [2018-02-04 00:47:46,884 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:46,884 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:46,886 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:46,886 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:46,886 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:46,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:46,895 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:46,945 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:46,945 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:46,945 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 00:47:46,945 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 00:47:46,946 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 00:47:46,946 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:47:46,946 INFO L87 Difference]: Start difference. First operand 174 states and 187 transitions. Second operand 8 states. [2018-02-04 00:47:47,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:47,124 INFO L93 Difference]: Finished difference Result 172 states and 185 transitions. [2018-02-04 00:47:47,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 00:47:47,125 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 65 [2018-02-04 00:47:47,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:47,125 INFO L225 Difference]: With dead ends: 172 [2018-02-04 00:47:47,125 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 00:47:47,126 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-04 00:47:47,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 00:47:47,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 170. [2018-02-04 00:47:47,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 170 states. [2018-02-04 00:47:47,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 183 transitions. [2018-02-04 00:47:47,128 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 183 transitions. Word has length 65 [2018-02-04 00:47:47,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:47,129 INFO L432 AbstractCegarLoop]: Abstraction has 170 states and 183 transitions. [2018-02-04 00:47:47,129 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 00:47:47,129 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 183 transitions. [2018-02-04 00:47:47,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-04 00:47:47,129 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:47,129 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:47,130 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:47,130 INFO L82 PathProgramCache]: Analyzing trace with hash -473136989, now seen corresponding path program 1 times [2018-02-04 00:47:47,130 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:47,130 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:47,131 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,131 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:47,131 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:47,140 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:47,347 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:47,347 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:47,347 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 00:47:47,348 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 00:47:47,348 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 00:47:47,348 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-02-04 00:47:47,348 INFO L87 Difference]: Start difference. First operand 170 states and 183 transitions. Second operand 10 states. [2018-02-04 00:47:47,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:47,642 INFO L93 Difference]: Finished difference Result 168 states and 181 transitions. [2018-02-04 00:47:47,642 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 00:47:47,642 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-02-04 00:47:47,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:47,643 INFO L225 Difference]: With dead ends: 168 [2018-02-04 00:47:47,643 INFO L226 Difference]: Without dead ends: 168 [2018-02-04 00:47:47,643 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2018-02-04 00:47:47,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states. [2018-02-04 00:47:47,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 166. [2018-02-04 00:47:47,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 166 states. [2018-02-04 00:47:47,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166 states to 166 states and 179 transitions. [2018-02-04 00:47:47,647 INFO L78 Accepts]: Start accepts. Automaton has 166 states and 179 transitions. Word has length 65 [2018-02-04 00:47:47,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:47,647 INFO L432 AbstractCegarLoop]: Abstraction has 166 states and 179 transitions. [2018-02-04 00:47:47,647 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 00:47:47,647 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 179 transitions. [2018-02-04 00:47:47,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2018-02-04 00:47:47,648 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:47,648 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:47,648 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:47,648 INFO L82 PathProgramCache]: Analyzing trace with hash -288623325, now seen corresponding path program 1 times [2018-02-04 00:47:47,648 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:47,659 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:47,660 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,660 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:47,660 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:47,671 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:47,701 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:47,701 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:47,701 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 00:47:47,702 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 00:47:47,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 00:47:47,702 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 00:47:47,702 INFO L87 Difference]: Start difference. First operand 166 states and 179 transitions. Second operand 4 states. [2018-02-04 00:47:47,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:47,707 INFO L93 Difference]: Finished difference Result 174 states and 187 transitions. [2018-02-04 00:47:47,707 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 00:47:47,707 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 69 [2018-02-04 00:47:47,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:47,708 INFO L225 Difference]: With dead ends: 174 [2018-02-04 00:47:47,708 INFO L226 Difference]: Without dead ends: 174 [2018-02-04 00:47:47,708 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 00:47:47,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-04 00:47:47,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-04 00:47:47,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 00:47:47,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 187 transitions. [2018-02-04 00:47:47,711 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 187 transitions. Word has length 69 [2018-02-04 00:47:47,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:47,711 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 187 transitions. [2018-02-04 00:47:47,711 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 00:47:47,712 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 187 transitions. [2018-02-04 00:47:47,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-02-04 00:47:47,712 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:47,712 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:47,712 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:47,712 INFO L82 PathProgramCache]: Analyzing trace with hash -804539978, now seen corresponding path program 1 times [2018-02-04 00:47:47,712 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:47,713 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:47,713 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,713 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:47,713 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:47,722 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:47,748 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:47,749 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:47,749 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 00:47:47,749 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 00:47:47,749 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 00:47:47,749 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 00:47:47,749 INFO L87 Difference]: Start difference. First operand 174 states and 187 transitions. Second operand 5 states. [2018-02-04 00:47:47,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:47,760 INFO L93 Difference]: Finished difference Result 178 states and 191 transitions. [2018-02-04 00:47:47,762 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 00:47:47,762 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 70 [2018-02-04 00:47:47,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:47,763 INFO L225 Difference]: With dead ends: 178 [2018-02-04 00:47:47,763 INFO L226 Difference]: Without dead ends: 178 [2018-02-04 00:47:47,763 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 00:47:47,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-02-04 00:47:47,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2018-02-04 00:47:47,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-02-04 00:47:47,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 191 transitions. [2018-02-04 00:47:47,766 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 191 transitions. Word has length 70 [2018-02-04 00:47:47,766 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:47,766 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 191 transitions. [2018-02-04 00:47:47,766 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 00:47:47,766 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 191 transitions. [2018-02-04 00:47:47,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-02-04 00:47:47,767 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:47,767 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:47,767 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:47,768 INFO L82 PathProgramCache]: Analyzing trace with hash 172589229, now seen corresponding path program 1 times [2018-02-04 00:47:47,768 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:47,768 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:47,768 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,768 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:47,768 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:47,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:47,778 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:47,823 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:47,823 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:47:47,823 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 00:47:47,824 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 00:47:47,824 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 00:47:47,824 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 00:47:47,824 INFO L87 Difference]: Start difference. First operand 178 states and 191 transitions. Second operand 8 states. [2018-02-04 00:47:48,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:48,057 INFO L93 Difference]: Finished difference Result 213 states and 230 transitions. [2018-02-04 00:47:48,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 00:47:48,057 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 72 [2018-02-04 00:47:48,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:48,058 INFO L225 Difference]: With dead ends: 213 [2018-02-04 00:47:48,058 INFO L226 Difference]: Without dead ends: 213 [2018-02-04 00:47:48,058 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-02-04 00:47:48,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-02-04 00:47:48,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 199. [2018-02-04 00:47:48,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-02-04 00:47:48,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 220 transitions. [2018-02-04 00:47:48,061 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 220 transitions. Word has length 72 [2018-02-04 00:47:48,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:48,061 INFO L432 AbstractCegarLoop]: Abstraction has 199 states and 220 transitions. [2018-02-04 00:47:48,062 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 00:47:48,062 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 220 transitions. [2018-02-04 00:47:48,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-02-04 00:47:48,062 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:48,062 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:48,062 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:48,063 INFO L82 PathProgramCache]: Analyzing trace with hash 172589230, now seen corresponding path program 1 times [2018-02-04 00:47:48,063 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:48,063 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:48,063 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:48,063 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:48,064 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:48,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:48,072 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:48,262 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:48,262 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:48,287 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:48,292 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:48,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:48,363 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:48,472 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:48,501 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:48,501 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [15] total 21 [2018-02-04 00:47:48,502 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 00:47:48,502 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 00:47:48,502 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=413, Unknown=0, NotChecked=0, Total=462 [2018-02-04 00:47:48,502 INFO L87 Difference]: Start difference. First operand 199 states and 220 transitions. Second operand 22 states. [2018-02-04 00:47:49,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:49,092 INFO L93 Difference]: Finished difference Result 225 states and 240 transitions. [2018-02-04 00:47:49,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 00:47:49,092 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 72 [2018-02-04 00:47:49,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:49,093 INFO L225 Difference]: With dead ends: 225 [2018-02-04 00:47:49,093 INFO L226 Difference]: Without dead ends: 225 [2018-02-04 00:47:49,093 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 106 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=105, Invalid=887, Unknown=0, NotChecked=0, Total=992 [2018-02-04 00:47:49,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-02-04 00:47:49,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 206. [2018-02-04 00:47:49,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-02-04 00:47:49,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 227 transitions. [2018-02-04 00:47:49,096 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 227 transitions. Word has length 72 [2018-02-04 00:47:49,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:49,096 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 227 transitions. [2018-02-04 00:47:49,096 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 00:47:49,096 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 227 transitions. [2018-02-04 00:47:49,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-04 00:47:49,096 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:49,096 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:49,096 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:49,096 INFO L82 PathProgramCache]: Analyzing trace with hash -1645476210, now seen corresponding path program 1 times [2018-02-04 00:47:49,096 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:49,097 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:49,097 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:49,097 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:49,097 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:49,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:49,108 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:49,514 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:47:49,514 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:49,515 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:49,519 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:49,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:49,561 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:49,577 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:47:49,595 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:49,596 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,597 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,599 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,599 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:11 [2018-02-04 00:47:49,686 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int)) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.base))) (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_dev_set_drvdata_#in~dev.offset|))) is different from true [2018-02-04 00:47:49,703 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int)) (and (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_hid_set_drvdata_#in~hdev.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.base))))) is different from true [2018-02-04 00:47:49,781 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-02-04 00:47:49,782 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:49,783 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 29 [2018-02-04 00:47:49,783 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,786 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,789 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,789 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:28, output treesize:11 [2018-02-04 00:47:49,849 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-02-04 00:47:49,850 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-02-04 00:47:49,850 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,851 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,852 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:49,852 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:5 [2018-02-04 00:47:49,858 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:49,874 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:49,874 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [23] total 37 [2018-02-04 00:47:49,874 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-02-04 00:47:49,875 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-02-04 00:47:49,875 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1122, Unknown=17, NotChecked=138, Total=1406 [2018-02-04 00:47:49,875 INFO L87 Difference]: Start difference. First operand 206 states and 227 transitions. Second operand 38 states. [2018-02-04 00:47:51,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:51,111 INFO L93 Difference]: Finished difference Result 233 states and 252 transitions. [2018-02-04 00:47:51,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 00:47:51,112 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 74 [2018-02-04 00:47:51,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:51,112 INFO L225 Difference]: With dead ends: 233 [2018-02-04 00:47:51,112 INFO L226 Difference]: Without dead ends: 233 [2018-02-04 00:47:51,113 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 116 GetRequests, 62 SyntacticMatches, 2 SemanticMatches, 52 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 521 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=274, Invalid=2303, Unknown=83, NotChecked=202, Total=2862 [2018-02-04 00:47:51,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-02-04 00:47:51,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 206. [2018-02-04 00:47:51,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-02-04 00:47:51,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 226 transitions. [2018-02-04 00:47:51,115 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 226 transitions. Word has length 74 [2018-02-04 00:47:51,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:51,115 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 226 transitions. [2018-02-04 00:47:51,115 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-02-04 00:47:51,116 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 226 transitions. [2018-02-04 00:47:51,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-04 00:47:51,116 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:51,116 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:51,116 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:51,116 INFO L82 PathProgramCache]: Analyzing trace with hash -1645476209, now seen corresponding path program 1 times [2018-02-04 00:47:51,117 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:51,117 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:51,117 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:51,117 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:51,117 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:51,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:51,131 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:51,801 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 2 proven. 8 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 00:47:51,801 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:51,802 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:51,807 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:51,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:51,842 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:51,877 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:47:51,878 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:51,879 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:51,880 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:51,887 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 00:47:51,888 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 00:47:51,888 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:51,890 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:51,895 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:51,895 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:41, output treesize:27 [2018-02-04 00:47:52,085 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (let ((.cse0 (+ ldv_dev_set_drvdata_~dev.offset 4))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_dev_set_drvdata_#in~dev.base|) .cse0 ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base|) .cse0 ldv_dev_set_drvdata_~data.base))) (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_dev_set_drvdata_#in~dev.offset|)))) is different from true [2018-02-04 00:47:52,091 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (let ((.cse0 (+ ldv_dev_set_drvdata_~dev.offset 4))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_hid_set_drvdata_#in~hdev.base|) .cse0 ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|) (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_hid_set_drvdata_#in~hdev.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base|) .cse0 ldv_dev_set_drvdata_~data.base)))))) is different from true [2018-02-04 00:47:52,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 26 [2018-02-04 00:47:52,222 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:52,224 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 35 [2018-02-04 00:47:52,224 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,228 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,237 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 33 [2018-02-04 00:47:52,238 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:52,239 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 44 [2018-02-04 00:47:52,240 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,244 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,250 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,250 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:56, output treesize:27 [2018-02-04 00:47:52,403 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 23 [2018-02-04 00:47:52,405 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2018-02-04 00:47:52,405 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,406 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,412 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2018-02-04 00:47:52,413 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 9 [2018-02-04 00:47:52,414 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,416 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,419 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:52,419 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:45, output treesize:9 [2018-02-04 00:47:52,474 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:47:52,491 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:52,491 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [19] imperfect sequences [26] total 42 [2018-02-04 00:47:52,491 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-02-04 00:47:52,491 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-02-04 00:47:52,492 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=1487, Unknown=17, NotChecked=158, Total=1806 [2018-02-04 00:47:52,492 INFO L87 Difference]: Start difference. First operand 206 states and 226 transitions. Second operand 43 states. [2018-02-04 00:47:54,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:54,740 INFO L93 Difference]: Finished difference Result 241 states and 260 transitions. [2018-02-04 00:47:54,740 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-04 00:47:54,740 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 74 [2018-02-04 00:47:54,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:54,741 INFO L225 Difference]: With dead ends: 241 [2018-02-04 00:47:54,741 INFO L226 Difference]: Without dead ends: 241 [2018-02-04 00:47:54,741 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 63 SyntacticMatches, 2 SemanticMatches, 61 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 759 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=327, Invalid=3248, Unknown=93, NotChecked=238, Total=3906 [2018-02-04 00:47:54,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241 states. [2018-02-04 00:47:54,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241 to 206. [2018-02-04 00:47:54,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-02-04 00:47:54,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 225 transitions. [2018-02-04 00:47:54,745 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 225 transitions. Word has length 74 [2018-02-04 00:47:54,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:54,745 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 225 transitions. [2018-02-04 00:47:54,745 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-02-04 00:47:54,745 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 225 transitions. [2018-02-04 00:47:54,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-04 00:47:54,746 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:54,746 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:54,746 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:54,746 INFO L82 PathProgramCache]: Analyzing trace with hash 529845023, now seen corresponding path program 1 times [2018-02-04 00:47:54,746 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:54,747 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:54,747 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:54,747 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:54,747 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:54,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:54,763 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:47:55,750 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 6 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 00:47:55,751 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:47:55,751 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:47:55,755 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:55,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:55,786 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:47:55,788 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:47:55,788 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:55,789 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:55,789 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:47:55,920 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:55,921 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:55,921 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:47:55,921 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:55,924 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:55,924 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 00:47:55,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:55,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:55,975 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:55,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 34 [2018-02-04 00:47:55,975 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:55,981 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:55,982 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:26, output treesize:28 [2018-02-04 00:47:56,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:47:56,014 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:56,014 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,015 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,020 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,020 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:41, output treesize:46 [2018-02-04 00:47:56,096 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 63 [2018-02-04 00:47:56,097 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 00:47:56,098 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,100 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,105 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,106 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:83, output treesize:46 [2018-02-04 00:47:56,110 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 46 [2018-02-04 00:47:56,111 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:47:56,111 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,116 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,125 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 00:47:56,126 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 00:47:56,126 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,127 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,134 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,134 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:74, output treesize:100 [2018-02-04 00:47:56,278 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (let ((.cse0 (+ ldv_dev_set_drvdata_~dev.offset 4))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_dev_set_drvdata_#in~dev.base|) .cse0 ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base|) .cse0 ldv_dev_set_drvdata_~data.base))) (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_dev_set_drvdata_#in~dev.offset|)))) is different from true [2018-02-04 00:47:56,281 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (let ((.cse0 (+ ldv_dev_set_drvdata_~dev.offset 4))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_hid_set_drvdata_#in~hdev.base|) .cse0 ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|) (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_hid_set_drvdata_#in~hdev.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base|) .cse0 ldv_dev_set_drvdata_~data.base)))))) is different from true [2018-02-04 00:47:56,383 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 78 [2018-02-04 00:47:56,386 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:56,387 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 91 [2018-02-04 00:47:56,387 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,396 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,415 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 88 [2018-02-04 00:47:56,417 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:47:56,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 112 [2018-02-04 00:47:56,419 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,436 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,446 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,446 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:129, output treesize:100 [2018-02-04 00:47:56,636 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 75 [2018-02-04 00:47:56,637 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 75 treesize of output 56 [2018-02-04 00:47:56,637 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,640 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,646 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:56,646 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:118, output treesize:91 [2018-02-04 00:47:56,751 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 61 [2018-02-04 00:47:56,752 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 18 [2018-02-04 00:47:56,752 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:56,758 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 14 [2018-02-04 00:47:56,758 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:47:56,762 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:56,767 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 00:47:56,767 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:97, output treesize:28 [2018-02-04 00:47:56,821 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 00:47:56,838 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 00:47:56,838 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [32] imperfect sequences [33] total 59 [2018-02-04 00:47:56,838 INFO L409 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-02-04 00:47:56,839 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-02-04 00:47:56,839 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=3111, Unknown=13, NotChecked=226, Total=3540 [2018-02-04 00:47:56,839 INFO L87 Difference]: Start difference. First operand 206 states and 225 transitions. Second operand 60 states. [2018-02-04 00:47:59,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:47:59,820 INFO L93 Difference]: Finished difference Result 215 states and 229 transitions. [2018-02-04 00:47:59,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 00:47:59,842 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 75 [2018-02-04 00:47:59,842 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:47:59,842 INFO L225 Difference]: With dead ends: 215 [2018-02-04 00:47:59,842 INFO L226 Difference]: Without dead ends: 215 [2018-02-04 00:47:59,843 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 50 SyntacticMatches, 5 SemanticMatches, 82 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 1396 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=428, Invalid=6163, Unknown=59, NotChecked=322, Total=6972 [2018-02-04 00:47:59,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states. [2018-02-04 00:47:59,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 212. [2018-02-04 00:47:59,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-02-04 00:47:59,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 229 transitions. [2018-02-04 00:47:59,846 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 229 transitions. Word has length 75 [2018-02-04 00:47:59,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:47:59,846 INFO L432 AbstractCegarLoop]: Abstraction has 212 states and 229 transitions. [2018-02-04 00:47:59,846 INFO L433 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-02-04 00:47:59,846 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 229 transitions. [2018-02-04 00:47:59,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-04 00:47:59,847 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:47:59,847 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:47:59,847 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:47:59,847 INFO L82 PathProgramCache]: Analyzing trace with hash 529845024, now seen corresponding path program 1 times [2018-02-04 00:47:59,847 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:47:59,847 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:47:59,848 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:59,848 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:47:59,848 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:47:59,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:47:59,863 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:01,340 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 12 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:48:01,340 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:48:01,340 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:48:01,345 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:01,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:01,377 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:48:01,379 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:48:01,379 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,380 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,380 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:48:01,554 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:01,555 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:01,555 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 00:48:01,555 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,558 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,558 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:8 [2018-02-04 00:48:01,616 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:48:01,618 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:01,618 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,621 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,627 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:48:01,628 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:01,628 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,630 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,633 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,634 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:31, output treesize:20 [2018-02-04 00:48:01,895 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 67 treesize of output 59 [2018-02-04 00:48:01,900 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 1 case distinctions, treesize of input 45 treesize of output 40 [2018-02-04 00:48:01,901 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-0 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:48:01,912 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 39 [2018-02-04 00:48:01,913 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,923 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 28 [2018-02-04 00:48:01,923 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,931 INFO L267 ElimStorePlain]: Start of recursive call 2: 3 dim-1 vars, End of recursive call: 3 dim-0 vars, and 3 xjuncts. [2018-02-04 00:48:01,945 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 30 [2018-02-04 00:48:01,947 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 19 [2018-02-04 00:48:01,947 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,952 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 13 [2018-02-04 00:48:01,953 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,958 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 13 [2018-02-04 00:48:01,958 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,963 INFO L267 ElimStorePlain]: Start of recursive call 6: 3 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:48:01,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 25 [2018-02-04 00:48:01,965 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 5 [2018-02-04 00:48:01,966 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,968 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 4 [2018-02-04 00:48:01,968 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,969 INFO L267 ElimStorePlain]: Start of recursive call 10: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,973 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 1 case distinctions, treesize of input 22 treesize of output 29 [2018-02-04 00:48:01,974 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2018-02-04 00:48:01,975 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,981 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 16 [2018-02-04 00:48:01,981 INFO L267 ElimStorePlain]: Start of recursive call 15: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:01,987 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 12 [2018-02-04 00:48:01,987 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:01,992 INFO L267 ElimStorePlain]: Start of recursive call 13: 3 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:48:02,012 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 5 dim-0 vars, and 5 xjuncts. [2018-02-04 00:48:02,012 INFO L202 ElimStorePlain]: Needed 16 recursive calls to eliminate 4 variables, input treesize:73, output treesize:61 [2018-02-04 00:48:04,277 WARN L143 SmtUtils]: Spent 2004ms on a formula simplification that was a NOOP. DAG size: 29 [2018-02-04 00:48:06,354 WARN L143 SmtUtils]: Spent 2004ms on a formula simplification that was a NOOP. DAG size: 29 [2018-02-04 00:48:06,512 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 89 treesize of output 88 [2018-02-04 00:48:06,521 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:06,522 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 93 [2018-02-04 00:48:06,522 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,530 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,542 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 82 [2018-02-04 00:48:06,544 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:06,545 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 79 treesize of output 94 [2018-02-04 00:48:06,545 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,550 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,558 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,558 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:115, output treesize:86 [2018-02-04 00:48:06,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 102 [2018-02-04 00:48:06,976 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 82 treesize of output 66 [2018-02-04 00:48:06,977 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:06,982 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 19 [2018-02-04 00:48:06,982 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,986 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:06,992 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 51 [2018-02-04 00:48:06,993 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 13 [2018-02-04 00:48:06,993 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,997 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-02-04 00:48:06,997 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:06,999 INFO L267 ElimStorePlain]: Start of recursive call 5: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:07,002 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:07,002 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 4 variables, input treesize:128, output treesize:13 [2018-02-04 00:48:07,017 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 3 proven. 12 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:48:07,034 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:48:07,034 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 33] total 58 [2018-02-04 00:48:07,034 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-02-04 00:48:07,034 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-02-04 00:48:07,035 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=183, Invalid=3145, Unknown=94, NotChecked=0, Total=3422 [2018-02-04 00:48:07,035 INFO L87 Difference]: Start difference. First operand 212 states and 229 transitions. Second operand 59 states. [2018-02-04 00:48:16,416 WARN L143 SmtUtils]: Spent 2005ms on a formula simplification that was a NOOP. DAG size: 32 [2018-02-04 00:48:18,584 WARN L143 SmtUtils]: Spent 2005ms on a formula simplification that was a NOOP. DAG size: 32 [2018-02-04 00:48:21,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:21,884 INFO L93 Difference]: Finished difference Result 266 states and 287 transitions. [2018-02-04 00:48:21,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-02-04 00:48:21,884 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 75 [2018-02-04 00:48:21,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:21,885 INFO L225 Difference]: With dead ends: 266 [2018-02-04 00:48:21,885 INFO L226 Difference]: Without dead ends: 266 [2018-02-04 00:48:21,886 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 50 SyntacticMatches, 5 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1783 ImplicationChecksByTransitivity, 12.2s TimeCoverageRelationStatistics Valid=635, Invalid=8669, Unknown=202, NotChecked=0, Total=9506 [2018-02-04 00:48:21,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 266 states. [2018-02-04 00:48:21,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 266 to 212. [2018-02-04 00:48:21,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-02-04 00:48:21,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 228 transitions. [2018-02-04 00:48:21,889 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 228 transitions. Word has length 75 [2018-02-04 00:48:21,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:21,889 INFO L432 AbstractCegarLoop]: Abstraction has 212 states and 228 transitions. [2018-02-04 00:48:21,889 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-02-04 00:48:21,889 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 228 transitions. [2018-02-04 00:48:21,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-02-04 00:48:21,890 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:21,890 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:21,890 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:21,890 INFO L82 PathProgramCache]: Analyzing trace with hash -90629135, now seen corresponding path program 1 times [2018-02-04 00:48:21,891 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:21,891 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:21,891 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:21,891 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:21,891 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:21,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:21,897 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:21,916 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:48:21,916 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:48:21,916 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:48:21,916 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 00:48:21,916 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 00:48:21,916 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 00:48:21,917 INFO L87 Difference]: Start difference. First operand 212 states and 228 transitions. Second operand 6 states. [2018-02-04 00:48:21,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:21,927 INFO L93 Difference]: Finished difference Result 203 states and 216 transitions. [2018-02-04 00:48:21,927 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 00:48:21,927 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 73 [2018-02-04 00:48:21,927 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:21,927 INFO L225 Difference]: With dead ends: 203 [2018-02-04 00:48:21,927 INFO L226 Difference]: Without dead ends: 203 [2018-02-04 00:48:21,928 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:48:21,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states. [2018-02-04 00:48:21,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 203. [2018-02-04 00:48:21,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-02-04 00:48:21,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 216 transitions. [2018-02-04 00:48:21,929 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 216 transitions. Word has length 73 [2018-02-04 00:48:21,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:21,929 INFO L432 AbstractCegarLoop]: Abstraction has 203 states and 216 transitions. [2018-02-04 00:48:21,930 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 00:48:21,930 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 216 transitions. [2018-02-04 00:48:21,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-04 00:48:21,930 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:21,930 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:21,930 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:21,930 INFO L82 PathProgramCache]: Analyzing trace with hash 217510894, now seen corresponding path program 1 times [2018-02-04 00:48:21,930 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:21,930 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:21,931 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:21,931 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:21,931 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:21,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:21,936 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:21,978 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:48:21,978 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:48:21,978 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 00:48:21,979 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:48:21,979 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:48:21,979 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:48:21,979 INFO L87 Difference]: Start difference. First operand 203 states and 216 transitions. Second operand 7 states. [2018-02-04 00:48:22,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:22,114 INFO L93 Difference]: Finished difference Result 202 states and 215 transitions. [2018-02-04 00:48:22,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 00:48:22,115 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 81 [2018-02-04 00:48:22,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:22,115 INFO L225 Difference]: With dead ends: 202 [2018-02-04 00:48:22,115 INFO L226 Difference]: Without dead ends: 202 [2018-02-04 00:48:22,115 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-04 00:48:22,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-02-04 00:48:22,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 202. [2018-02-04 00:48:22,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 202 states. [2018-02-04 00:48:22,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 202 states to 202 states and 215 transitions. [2018-02-04 00:48:22,117 INFO L78 Accepts]: Start accepts. Automaton has 202 states and 215 transitions. Word has length 81 [2018-02-04 00:48:22,117 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:22,117 INFO L432 AbstractCegarLoop]: Abstraction has 202 states and 215 transitions. [2018-02-04 00:48:22,117 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:48:22,117 INFO L276 IsEmpty]: Start isEmpty. Operand 202 states and 215 transitions. [2018-02-04 00:48:22,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-04 00:48:22,118 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:22,118 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:22,118 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:22,118 INFO L82 PathProgramCache]: Analyzing trace with hash 217510895, now seen corresponding path program 1 times [2018-02-04 00:48:22,118 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:22,118 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:22,119 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:22,119 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:22,119 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:22,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:22,127 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:22,384 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:48:22,384 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:48:22,384 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:48:22,392 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:22,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:22,438 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:48:22,511 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 00:48:22,541 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:48:22,542 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15] total 20 [2018-02-04 00:48:22,542 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 00:48:22,542 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 00:48:22,542 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=378, Unknown=0, NotChecked=0, Total=420 [2018-02-04 00:48:22,543 INFO L87 Difference]: Start difference. First operand 202 states and 215 transitions. Second operand 21 states. [2018-02-04 00:48:23,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:23,191 INFO L93 Difference]: Finished difference Result 227 states and 237 transitions. [2018-02-04 00:48:23,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 00:48:23,192 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 81 [2018-02-04 00:48:23,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:23,192 INFO L225 Difference]: With dead ends: 227 [2018-02-04 00:48:23,192 INFO L226 Difference]: Without dead ends: 227 [2018-02-04 00:48:23,193 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 73 SyntacticMatches, 7 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 141 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=107, Invalid=1015, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 00:48:23,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-02-04 00:48:23,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 212. [2018-02-04 00:48:23,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-02-04 00:48:23,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 224 transitions. [2018-02-04 00:48:23,195 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 224 transitions. Word has length 81 [2018-02-04 00:48:23,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:23,196 INFO L432 AbstractCegarLoop]: Abstraction has 212 states and 224 transitions. [2018-02-04 00:48:23,196 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 00:48:23,196 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 224 transitions. [2018-02-04 00:48:23,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-02-04 00:48:23,196 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:23,197 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:23,197 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:23,197 INFO L82 PathProgramCache]: Analyzing trace with hash 790903974, now seen corresponding path program 1 times [2018-02-04 00:48:23,197 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:23,197 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:23,198 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:23,198 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:23,198 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:23,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:23,208 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:23,733 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:48:23,733 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:48:23,733 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:48:23,738 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:23,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:23,779 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:48:23,781 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:48:23,781 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,782 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,782 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:48:23,821 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:23,822 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:23,822 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:48:23,822 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,825 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,825 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 00:48:23,872 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:23,873 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:23,873 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:23,873 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-02-04 00:48:23,873 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,876 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,876 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:23, output treesize:16 [2018-02-04 00:48:23,894 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:48:23,895 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:23,895 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,896 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,902 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:48:23,902 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:23,903 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,903 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,907 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,907 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:39, output treesize:34 [2018-02-04 00:48:23,927 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2018-02-04 00:48:23,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 9 [2018-02-04 00:48:23,928 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,930 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,933 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,933 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:43, output treesize:22 [2018-02-04 00:48:23,955 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 30 [2018-02-04 00:48:23,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 1 [2018-02-04 00:48:23,964 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,967 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,971 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:23,971 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:41, output treesize:14 [2018-02-04 00:48:24,011 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 26 [2018-02-04 00:48:24,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 00:48:24,012 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,015 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,021 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:48:24,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:24,022 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,023 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,028 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,028 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:54, output treesize:34 [2018-02-04 00:48:24,145 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_dev_set_drvdata_#in~dev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|)) is different from true [2018-02-04 00:48:24,147 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_hid_set_drvdata_#in~hdev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|)) is different from true [2018-02-04 00:48:24,149 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_arvo_init_specials_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_arvo_init_specials_#in~hdev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.offset)) |c_#memory_$Pointer$.offset|)) is different from true [2018-02-04 00:48:24,151 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~dev.offset Int) (ldv_dev_set_drvdata_~data.offset Int)) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_ldv_arvo_probe_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_arvo_probe_#in~hdev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.offset)))) is different from true [2018-02-04 00:48:24,153 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-02-04 00:48:24,154 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-02-04 00:48:24,155 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,155 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,163 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 33 [2018-02-04 00:48:24,168 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 20 treesize of output 29 [2018-02-04 00:48:24,169 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 2 xjuncts. [2018-02-04 00:48:24,176 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 00:48:24,185 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:48:24,185 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:47, output treesize:35 [2018-02-04 00:48:24,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-02-04 00:48:24,245 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 3 [2018-02-04 00:48:24,245 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,246 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,247 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:24,247 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:19, output treesize:3 [2018-02-04 00:48:24,270 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:48:24,298 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:48:24,298 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 32] total 44 [2018-02-04 00:48:24,299 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-02-04 00:48:24,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-02-04 00:48:24,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1485, Unknown=4, NotChecked=324, Total=1980 [2018-02-04 00:48:24,299 INFO L87 Difference]: Start difference. First operand 212 states and 224 transitions. Second operand 45 states. [2018-02-04 00:48:25,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:25,875 INFO L93 Difference]: Finished difference Result 239 states and 250 transitions. [2018-02-04 00:48:25,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 00:48:25,875 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 82 [2018-02-04 00:48:25,875 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:25,876 INFO L225 Difference]: With dead ends: 239 [2018-02-04 00:48:25,876 INFO L226 Difference]: Without dead ends: 239 [2018-02-04 00:48:25,876 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 148 GetRequests, 61 SyntacticMatches, 13 SemanticMatches, 74 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 1353 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=508, Invalid=4580, Unknown=40, NotChecked=572, Total=5700 [2018-02-04 00:48:25,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-02-04 00:48:25,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 215. [2018-02-04 00:48:25,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-02-04 00:48:25,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 229 transitions. [2018-02-04 00:48:25,879 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 229 transitions. Word has length 82 [2018-02-04 00:48:25,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:25,879 INFO L432 AbstractCegarLoop]: Abstraction has 215 states and 229 transitions. [2018-02-04 00:48:25,879 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-02-04 00:48:25,879 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 229 transitions. [2018-02-04 00:48:25,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-02-04 00:48:25,879 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:25,879 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:25,880 INFO L371 AbstractCegarLoop]: === Iteration 42 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:25,880 INFO L82 PathProgramCache]: Analyzing trace with hash 790903975, now seen corresponding path program 1 times [2018-02-04 00:48:25,880 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:25,880 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:25,880 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:25,881 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:25,881 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:25,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:25,887 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:26,284 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 00:48:26,284 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:48:26,285 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [] total 26 [2018-02-04 00:48:26,285 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 00:48:26,285 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 00:48:26,285 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=614, Unknown=0, NotChecked=0, Total=702 [2018-02-04 00:48:26,285 INFO L87 Difference]: Start difference. First operand 215 states and 229 transitions. Second operand 27 states. [2018-02-04 00:48:27,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:27,065 INFO L93 Difference]: Finished difference Result 225 states and 241 transitions. [2018-02-04 00:48:27,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-04 00:48:27,065 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 82 [2018-02-04 00:48:27,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:27,066 INFO L225 Difference]: With dead ends: 225 [2018-02-04 00:48:27,066 INFO L226 Difference]: Without dead ends: 225 [2018-02-04 00:48:27,066 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 8 SyntacticMatches, 3 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 354 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=213, Invalid=1593, Unknown=0, NotChecked=0, Total=1806 [2018-02-04 00:48:27,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-02-04 00:48:27,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 216. [2018-02-04 00:48:27,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-02-04 00:48:27,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 230 transitions. [2018-02-04 00:48:27,068 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 230 transitions. Word has length 82 [2018-02-04 00:48:27,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:27,069 INFO L432 AbstractCegarLoop]: Abstraction has 216 states and 230 transitions. [2018-02-04 00:48:27,069 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 00:48:27,069 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 230 transitions. [2018-02-04 00:48:27,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 00:48:27,069 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:27,069 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:27,069 INFO L371 AbstractCegarLoop]: === Iteration 43 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:27,070 INFO L82 PathProgramCache]: Analyzing trace with hash -1859667754, now seen corresponding path program 1 times [2018-02-04 00:48:27,070 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:27,070 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:27,070 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:27,070 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:27,070 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:27,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:27,077 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:27,124 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:48:27,124 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:48:27,124 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 00:48:27,124 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 00:48:27,124 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 00:48:27,124 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:48:27,125 INFO L87 Difference]: Start difference. First operand 216 states and 230 transitions. Second operand 7 states. [2018-02-04 00:48:27,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:27,135 INFO L93 Difference]: Finished difference Result 223 states and 237 transitions. [2018-02-04 00:48:27,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 00:48:27,135 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 85 [2018-02-04 00:48:27,135 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:27,136 INFO L225 Difference]: With dead ends: 223 [2018-02-04 00:48:27,136 INFO L226 Difference]: Without dead ends: 223 [2018-02-04 00:48:27,136 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 00:48:27,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-02-04 00:48:27,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2018-02-04 00:48:27,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-02-04 00:48:27,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 237 transitions. [2018-02-04 00:48:27,138 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 237 transitions. Word has length 85 [2018-02-04 00:48:27,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:27,138 INFO L432 AbstractCegarLoop]: Abstraction has 223 states and 237 transitions. [2018-02-04 00:48:27,138 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 00:48:27,138 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 237 transitions. [2018-02-04 00:48:27,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 00:48:27,139 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:27,139 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:27,139 INFO L371 AbstractCegarLoop]: === Iteration 44 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:27,139 INFO L82 PathProgramCache]: Analyzing trace with hash 2141896535, now seen corresponding path program 1 times [2018-02-04 00:48:27,139 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:27,139 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:27,140 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:27,140 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:27,140 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:27,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:27,150 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:27,279 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 00:48:27,279 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 00:48:27,280 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-02-04 00:48:27,280 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 00:48:27,280 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 00:48:27,280 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-02-04 00:48:27,280 INFO L87 Difference]: Start difference. First operand 223 states and 237 transitions. Second operand 11 states. [2018-02-04 00:48:27,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 00:48:27,531 INFO L93 Difference]: Finished difference Result 232 states and 247 transitions. [2018-02-04 00:48:27,531 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 00:48:27,531 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 85 [2018-02-04 00:48:27,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 00:48:27,532 INFO L225 Difference]: With dead ends: 232 [2018-02-04 00:48:27,532 INFO L226 Difference]: Without dead ends: 224 [2018-02-04 00:48:27,532 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-02-04 00:48:27,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-02-04 00:48:27,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 224. [2018-02-04 00:48:27,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-02-04 00:48:27,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 238 transitions. [2018-02-04 00:48:27,536 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 238 transitions. Word has length 85 [2018-02-04 00:48:27,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 00:48:27,536 INFO L432 AbstractCegarLoop]: Abstraction has 224 states and 238 transitions. [2018-02-04 00:48:27,537 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 00:48:27,537 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 238 transitions. [2018-02-04 00:48:27,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-02-04 00:48:27,537 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 00:48:27,537 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 00:48:27,537 INFO L371 AbstractCegarLoop]: === Iteration 45 === [ldv_arvo_init_specialsErr1RequiresViolation, ldv_arvo_init_specialsErr3RequiresViolation, ldv_arvo_init_specialsErr7RequiresViolation, ldv_arvo_init_specialsErr2RequiresViolation, ldv_arvo_init_specialsErr4RequiresViolation, ldv_arvo_init_specialsErr0RequiresViolation, ldv_arvo_init_specialsErr6RequiresViolation, ldv_arvo_init_specialsErr5RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation]=== [2018-02-04 00:48:27,538 INFO L82 PathProgramCache]: Analyzing trace with hash -150489879, now seen corresponding path program 1 times [2018-02-04 00:48:27,538 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 00:48:27,538 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 00:48:27,538 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:27,542 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:27,542 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 00:48:27,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:27,564 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 00:48:27,999 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:48:27,999 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 00:48:28,014 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 00:48:28,019 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 00:48:28,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 00:48:28,045 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 00:48:28,047 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 00:48:28,047 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,048 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,048 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 00:48:28,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:28,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:28,079 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 00:48:28,079 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,082 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,082 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 00:48:28,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:28,136 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:28,136 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:28,137 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-02-04 00:48:28,137 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,139 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,139 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:20, output treesize:13 [2018-02-04 00:48:28,156 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 00:48:28,157 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:28,157 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,158 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,163 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,163 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:31, output treesize:30 [2018-02-04 00:48:28,209 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 52 [2018-02-04 00:48:28,210 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 00:48:28,210 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,212 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,216 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,216 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:67, output treesize:30 [2018-02-04 00:48:28,219 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 35 [2018-02-04 00:48:28,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 00:48:28,220 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,224 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,228 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:28,228 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:43, output treesize:39 [2018-02-04 00:48:28,283 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int)) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.base)))) is different from true [2018-02-04 00:48:28,285 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int)) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.base)))) is different from true [2018-02-04 00:48:28,339 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 42 [2018-02-04 00:48:28,344 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 18 treesize of output 27 [2018-02-04 00:48:28,345 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 2 xjuncts. [2018-02-04 00:48:28,353 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 00:48:28,364 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 00:48:28,364 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:52, output treesize:56 [2018-02-04 00:48:28,392 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 00:48:28,392 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:28,394 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 00:48:28,394 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:19, output treesize:14 [2018-02-04 00:48:46,429 WARN L143 SmtUtils]: Spent 2003ms on a formula simplification that was a NOOP. DAG size: 14 [2018-02-04 00:48:46,460 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 16 [2018-02-04 00:48:46,461 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 4 [2018-02-04 00:48:46,461 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:46,462 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:46,463 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 00:48:46,463 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:25, output treesize:10 [2018-02-04 00:48:46,475 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 00:48:46,475 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 29 [2018-02-04 00:48:46,476 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 00:48:46,484 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-02-04 00:48:46,484 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:46, output treesize:22 [2018-02-04 00:48:46,518 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 9 proven. 6 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 00:48:46,535 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 00:48:46,535 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 30] total 45 [2018-02-04 00:48:46,536 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-02-04 00:48:46,536 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-02-04 00:48:46,536 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=1710, Unknown=23, NotChecked=170, Total=2070 [2018-02-04 00:48:46,536 INFO L87 Difference]: Start difference. First operand 224 states and 238 transitions. Second operand 46 states. Received shutdown request... [2018-02-04 00:48:54,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 00:48:54,583 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 00:48:54,587 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 00:48:54,587 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 12:48:54 BoogieIcfgContainer [2018-02-04 00:48:54,587 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 00:48:54,587 INFO L168 Benchmark]: Toolchain (without parser) took 198224.96 ms. Allocated memory was 399.5 MB in the beginning and 775.9 MB in the end (delta: 376.4 MB). Free memory was 356.0 MB in the beginning and 488.4 MB in the end (delta: -132.4 MB). Peak memory consumption was 244.0 MB. Max. memory is 5.3 GB. [2018-02-04 00:48:54,588 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 399.5 MB. Free memory is still 362.6 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 00:48:54,588 INFO L168 Benchmark]: CACSL2BoogieTranslator took 174.74 ms. Allocated memory is still 399.5 MB. Free memory was 356.0 MB in the beginning and 341.3 MB in the end (delta: 14.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 5.3 GB. [2018-02-04 00:48:54,589 INFO L168 Benchmark]: Boogie Preprocessor took 36.49 ms. Allocated memory is still 399.5 MB. Free memory was 341.3 MB in the beginning and 338.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 5.3 GB. [2018-02-04 00:48:54,589 INFO L168 Benchmark]: RCFGBuilder took 397.06 ms. Allocated memory is still 399.5 MB. Free memory was 338.6 MB in the beginning and 294.8 MB in the end (delta: 43.8 MB). Peak memory consumption was 43.8 MB. Max. memory is 5.3 GB. [2018-02-04 00:48:54,589 INFO L168 Benchmark]: TraceAbstraction took 197614.14 ms. Allocated memory was 399.5 MB in the beginning and 775.9 MB in the end (delta: 376.4 MB). Free memory was 294.8 MB in the beginning and 488.4 MB in the end (delta: -193.6 MB). Peak memory consumption was 182.8 MB. Max. memory is 5.3 GB. [2018-02-04 00:48:54,590 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 399.5 MB. Free memory is still 362.6 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 174.74 ms. Allocated memory is still 399.5 MB. Free memory was 356.0 MB in the beginning and 341.3 MB in the end (delta: 14.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 36.49 ms. Allocated memory is still 399.5 MB. Free memory was 341.3 MB in the beginning and 338.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 5.3 GB. * RCFGBuilder took 397.06 ms. Allocated memory is still 399.5 MB. Free memory was 338.6 MB in the beginning and 294.8 MB in the end (delta: 43.8 MB). Peak memory consumption was 43.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 197614.14 ms. Allocated memory was 399.5 MB in the beginning and 775.9 MB in the end (delta: 376.4 MB). Free memory was 294.8 MB in the beginning and 488.4 MB in the end (delta: -193.6 MB). Peak memory consumption was 182.8 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1533]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1533). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (224states) and interpolant automaton (currently 4 states, 46 states before enhancement), while ReachableStatesComputation was computing reachable states (7 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 17 procedures, 173 locations, 45 error locations. TIMEOUT Result, 197.5s OverallTime, 45 OverallIterations, 3 TraceHistogramMax, 124.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 6202 SDtfs, 4389 SDslu, 41789 SDs, 0 SdLazy, 45066 SolverSat, 1307 SolverUnsat, 811 SolverUnknown, 0 SolverNotchecked, 62.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2184 GetRequests, 1076 SyntacticMatches, 81 SemanticMatches, 1027 ConstructedPredicates, 12 IntricatePredicates, 0 DeprecatedPredicates, 8734 ImplicationChecksByTransitivity, 123.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=224occurred in iteration=44, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 44 MinimizatonAttempts, 592 StatesRemovedByMinimization, 33 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.2s SsaConstructionTime, 0.7s SatisfiabilityAnalysisTime, 70.7s InterpolantComputationTime, 3585 NumberOfCodeBlocks, 3585 NumberOfCodeBlocksAsserted, 72 NumberOfCheckSat, 3514 ConstructedInterpolants, 159 QuantifiedInterpolants, 2217534 SizeOfPredicates, 310 NumberOfNonLiveVariables, 5913 ConjunctsInSsa, 1182 ConjunctsInUnsatCore, 71 InterpolantComputations, 28 PerfectInterpolantSequences, 837/1070 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_00-48-54-594.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_00-48-54-594.csv Completed graceful shutdown