java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_2_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 14:08:35,745 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 14:08:35,746 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 14:08:35,759 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 14:08:35,759 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 14:08:35,760 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 14:08:35,760 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 14:08:35,762 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 14:08:35,763 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 14:08:35,764 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 14:08:35,764 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 14:08:35,765 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 14:08:35,765 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 14:08:35,766 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 14:08:35,767 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 14:08:35,769 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 14:08:35,770 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 14:08:35,772 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 14:08:35,773 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 14:08:35,774 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 14:08:35,775 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 14:08:35,776 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 14:08:35,776 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 14:08:35,777 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 14:08:35,777 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 14:08:35,778 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 14:08:35,778 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 14:08:35,779 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 14:08:35,779 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 14:08:35,779 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 14:08:35,780 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 14:08:35,780 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-02-04 14:08:35,788 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 14:08:35,789 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 14:08:35,789 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 14:08:35,789 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 14:08:35,790 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 14:08:35,790 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 14:08:35,791 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 14:08:35,791 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 14:08:35,791 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 14:08:35,792 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-02-04 14:08:35,817 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 14:08:35,824 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 14:08:35,827 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 14:08:35,828 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 14:08:35,828 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 14:08:35,829 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_2_true-valid-memsafety_true-termination.i [2018-02-04 14:08:35,967 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 14:08:35,968 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 14:08:35,968 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 14:08:35,968 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 14:08:35,972 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 14:08:35,973 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 02:08:35" (1/1) ... [2018-02-04 14:08:35,975 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b275d44 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:35, skipping insertion in model container [2018-02-04 14:08:35,975 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 02:08:35" (1/1) ... [2018-02-04 14:08:35,985 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 14:08:36,019 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 14:08:36,117 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 14:08:36,133 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 14:08:36,139 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36 WrapperNode [2018-02-04 14:08:36,139 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 14:08:36,139 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 14:08:36,139 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 14:08:36,139 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 14:08:36,148 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,148 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,155 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,156 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,160 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,162 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,163 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... [2018-02-04 14:08:36,165 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 14:08:36,165 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 14:08:36,165 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 14:08:36,166 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 14:08:36,166 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_add_return [2018-02-04 14:08:36,201 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_get [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_get [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 14:08:36,202 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 14:08:36,202 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 14:08:36,202 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-02-04 14:08:36,203 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-04 14:08:36,203 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_add_return [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_get [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_get [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 14:08:36,204 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 14:08:36,205 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 14:08:36,397 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-04 14:08:36,508 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 14:08:36,508 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 02:08:36 BoogieIcfgContainer [2018-02-04 14:08:36,508 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 14:08:36,509 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 14:08:36,509 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 14:08:36,511 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 14:08:36,511 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 02:08:35" (1/3) ... [2018-02-04 14:08:36,511 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a2a46a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 02:08:36, skipping insertion in model container [2018-02-04 14:08:36,512 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 02:08:36" (2/3) ... [2018-02-04 14:08:36,512 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a2a46a1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 02:08:36, skipping insertion in model container [2018-02-04 14:08:36,512 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 02:08:36" (3/3) ... [2018-02-04 14:08:36,513 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test22_2_true-valid-memsafety_true-termination.i [2018-02-04 14:08:36,519 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 14:08:36,526 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2018-02-04 14:08:36,554 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 14:08:36,554 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 14:08:36,554 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 14:08:36,554 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 14:08:36,554 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 14:08:36,554 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 14:08:36,554 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 14:08:36,554 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 14:08:36,555 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 14:08:36,565 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states. [2018-02-04 14:08:36,572 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-02-04 14:08:36,573 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:36,573 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:36,573 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:36,576 INFO L82 PathProgramCache]: Analyzing trace with hash -998986606, now seen corresponding path program 1 times [2018-02-04 14:08:36,577 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:36,577 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:36,611 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:36,611 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:36,611 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:36,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:36,655 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:36,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:36,812 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:36,812 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 14:08:36,813 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 14:08:36,820 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 14:08:36,821 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 14:08:36,822 INFO L87 Difference]: Start difference. First operand 143 states. Second operand 5 states. [2018-02-04 14:08:36,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:36,862 INFO L93 Difference]: Finished difference Result 149 states and 158 transitions. [2018-02-04 14:08:36,863 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 14:08:36,864 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-02-04 14:08:36,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:36,874 INFO L225 Difference]: With dead ends: 149 [2018-02-04 14:08:36,874 INFO L226 Difference]: Without dead ends: 146 [2018-02-04 14:08:36,876 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 14:08:36,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-02-04 14:08:36,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-02-04 14:08:36,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-02-04 14:08:36,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2018-02-04 14:08:36,909 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 17 [2018-02-04 14:08:36,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:36,909 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2018-02-04 14:08:36,909 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 14:08:36,909 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2018-02-04 14:08:36,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-04 14:08:36,909 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:36,909 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:36,910 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:36,910 INFO L82 PathProgramCache]: Analyzing trace with hash -2077747980, now seen corresponding path program 1 times [2018-02-04 14:08:36,910 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:36,910 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:36,911 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:36,912 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:36,912 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:36,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:36,927 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:36,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:36,969 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:36,969 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 14:08:36,970 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 14:08:36,970 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 14:08:36,970 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 14:08:36,970 INFO L87 Difference]: Start difference. First operand 144 states and 153 transitions. Second operand 6 states. [2018-02-04 14:08:37,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:37,088 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2018-02-04 14:08:37,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 14:08:37,089 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-02-04 14:08:37,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:37,090 INFO L225 Difference]: With dead ends: 145 [2018-02-04 14:08:37,090 INFO L226 Difference]: Without dead ends: 145 [2018-02-04 14:08:37,091 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 14:08:37,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-04 14:08:37,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 143. [2018-02-04 14:08:37,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-02-04 14:08:37,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 152 transitions. [2018-02-04 14:08:37,096 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 152 transitions. Word has length 19 [2018-02-04 14:08:37,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:37,097 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 152 transitions. [2018-02-04 14:08:37,097 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 14:08:37,097 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 152 transitions. [2018-02-04 14:08:37,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-04 14:08:37,097 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:37,097 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:37,097 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:37,097 INFO L82 PathProgramCache]: Analyzing trace with hash -2077747979, now seen corresponding path program 1 times [2018-02-04 14:08:37,097 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:37,097 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:37,098 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,098 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:37,098 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:37,113 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:37,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:37,260 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:37,260 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 14:08:37,261 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 14:08:37,261 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 14:08:37,261 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 14:08:37,261 INFO L87 Difference]: Start difference. First operand 143 states and 152 transitions. Second operand 7 states. [2018-02-04 14:08:37,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:37,436 INFO L93 Difference]: Finished difference Result 144 states and 153 transitions. [2018-02-04 14:08:37,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 14:08:37,436 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-02-04 14:08:37,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:37,438 INFO L225 Difference]: With dead ends: 144 [2018-02-04 14:08:37,438 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 14:08:37,438 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-04 14:08:37,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 14:08:37,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 142. [2018-02-04 14:08:37,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-02-04 14:08:37,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 151 transitions. [2018-02-04 14:08:37,448 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 151 transitions. Word has length 19 [2018-02-04 14:08:37,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:37,448 INFO L432 AbstractCegarLoop]: Abstraction has 142 states and 151 transitions. [2018-02-04 14:08:37,448 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 14:08:37,448 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 151 transitions. [2018-02-04 14:08:37,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 14:08:37,449 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:37,449 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:37,449 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:37,450 INFO L82 PathProgramCache]: Analyzing trace with hash -471802203, now seen corresponding path program 1 times [2018-02-04 14:08:37,450 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:37,450 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:37,451 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,452 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:37,452 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:37,464 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:37,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:37,511 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:37,511 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 14:08:37,512 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 14:08:37,512 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 14:08:37,512 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 14:08:37,512 INFO L87 Difference]: Start difference. First operand 142 states and 151 transitions. Second operand 7 states. [2018-02-04 14:08:37,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:37,552 INFO L93 Difference]: Finished difference Result 159 states and 170 transitions. [2018-02-04 14:08:37,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 14:08:37,552 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 27 [2018-02-04 14:08:37,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:37,553 INFO L225 Difference]: With dead ends: 159 [2018-02-04 14:08:37,553 INFO L226 Difference]: Without dead ends: 159 [2018-02-04 14:08:37,554 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 14:08:37,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-02-04 14:08:37,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 151. [2018-02-04 14:08:37,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-02-04 14:08:37,563 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2018-02-04 14:08:37,563 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 27 [2018-02-04 14:08:37,563 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:37,563 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2018-02-04 14:08:37,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 14:08:37,563 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2018-02-04 14:08:37,564 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 14:08:37,564 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:37,564 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:37,564 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:37,564 INFO L82 PathProgramCache]: Analyzing trace with hash 131109242, now seen corresponding path program 1 times [2018-02-04 14:08:37,564 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:37,565 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:37,565 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,565 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:37,566 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:37,578 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:37,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:37,652 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:37,652 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 14:08:37,652 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 14:08:37,652 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 14:08:37,653 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 14:08:37,653 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand 10 states. [2018-02-04 14:08:37,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:37,841 INFO L93 Difference]: Finished difference Result 150 states and 159 transitions. [2018-02-04 14:08:37,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 14:08:37,841 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-02-04 14:08:37,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:37,842 INFO L225 Difference]: With dead ends: 150 [2018-02-04 14:08:37,842 INFO L226 Difference]: Without dead ends: 150 [2018-02-04 14:08:37,842 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 14:08:37,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-02-04 14:08:37,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-02-04 14:08:37,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-02-04 14:08:37,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 159 transitions. [2018-02-04 14:08:37,848 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 159 transitions. Word has length 34 [2018-02-04 14:08:37,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:37,848 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 159 transitions. [2018-02-04 14:08:37,848 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 14:08:37,849 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 159 transitions. [2018-02-04 14:08:37,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 14:08:37,849 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:37,850 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:37,850 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:37,850 INFO L82 PathProgramCache]: Analyzing trace with hash 131109243, now seen corresponding path program 1 times [2018-02-04 14:08:37,850 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:37,850 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:37,851 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,851 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:37,851 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:37,862 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:37,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:37,886 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:37,886 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 14:08:37,886 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 14:08:37,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 14:08:37,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 14:08:37,887 INFO L87 Difference]: Start difference. First operand 150 states and 159 transitions. Second operand 4 states. [2018-02-04 14:08:37,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:37,902 INFO L93 Difference]: Finished difference Result 153 states and 162 transitions. [2018-02-04 14:08:37,902 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 14:08:37,902 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-02-04 14:08:37,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:37,903 INFO L225 Difference]: With dead ends: 153 [2018-02-04 14:08:37,903 INFO L226 Difference]: Without dead ends: 151 [2018-02-04 14:08:37,903 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 14:08:37,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-02-04 14:08:37,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-02-04 14:08:37,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-02-04 14:08:37,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 160 transitions. [2018-02-04 14:08:37,909 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 160 transitions. Word has length 34 [2018-02-04 14:08:37,909 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:37,909 INFO L432 AbstractCegarLoop]: Abstraction has 151 states and 160 transitions. [2018-02-04 14:08:37,909 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 14:08:37,909 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 160 transitions. [2018-02-04 14:08:37,910 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 14:08:37,910 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:37,910 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:37,910 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:37,910 INFO L82 PathProgramCache]: Analyzing trace with hash -2110897305, now seen corresponding path program 1 times [2018-02-04 14:08:37,910 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:37,911 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:37,911 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,912 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:37,912 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:37,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:37,924 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:37,947 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:37,948 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:37,948 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:37,956 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:37,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:37,991 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:38,015 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:38,038 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:08:38,039 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-02-04 14:08:38,039 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 14:08:38,039 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 14:08:38,039 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-02-04 14:08:38,039 INFO L87 Difference]: Start difference. First operand 151 states and 160 transitions. Second operand 6 states. [2018-02-04 14:08:38,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:38,057 INFO L93 Difference]: Finished difference Result 154 states and 163 transitions. [2018-02-04 14:08:38,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 14:08:38,057 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-04 14:08:38,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:38,058 INFO L225 Difference]: With dead ends: 154 [2018-02-04 14:08:38,058 INFO L226 Difference]: Without dead ends: 152 [2018-02-04 14:08:38,059 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-02-04 14:08:38,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-02-04 14:08:38,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 152. [2018-02-04 14:08:38,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 152 states. [2018-02-04 14:08:38,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 161 transitions. [2018-02-04 14:08:38,064 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 161 transitions. Word has length 35 [2018-02-04 14:08:38,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:38,065 INFO L432 AbstractCegarLoop]: Abstraction has 152 states and 161 transitions. [2018-02-04 14:08:38,065 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 14:08:38,065 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 161 transitions. [2018-02-04 14:08:38,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 14:08:38,066 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:38,066 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:38,066 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:38,066 INFO L82 PathProgramCache]: Analyzing trace with hash 1181841647, now seen corresponding path program 1 times [2018-02-04 14:08:38,066 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:38,066 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:38,068 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:38,068 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:38,068 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:38,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:38,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:38,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:38,136 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:38,136 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 14:08:38,137 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 14:08:38,137 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 14:08:38,137 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 14:08:38,137 INFO L87 Difference]: Start difference. First operand 152 states and 161 transitions. Second operand 7 states. [2018-02-04 14:08:38,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:38,174 INFO L93 Difference]: Finished difference Result 163 states and 174 transitions. [2018-02-04 14:08:38,175 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 14:08:38,176 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-02-04 14:08:38,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:38,177 INFO L225 Difference]: With dead ends: 163 [2018-02-04 14:08:38,177 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 14:08:38,177 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 14:08:38,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 14:08:38,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 159. [2018-02-04 14:08:38,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-02-04 14:08:38,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 169 transitions. [2018-02-04 14:08:38,182 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 169 transitions. Word has length 36 [2018-02-04 14:08:38,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:38,183 INFO L432 AbstractCegarLoop]: Abstraction has 159 states and 169 transitions. [2018-02-04 14:08:38,183 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 14:08:38,183 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 169 transitions. [2018-02-04 14:08:38,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 14:08:38,184 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:38,184 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:38,184 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:38,184 INFO L82 PathProgramCache]: Analyzing trace with hash 1401343739, now seen corresponding path program 2 times [2018-02-04 14:08:38,184 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:38,185 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:38,185 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:38,185 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:38,186 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:38,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:38,197 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:38,226 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:38,226 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:38,226 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:38,235 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 14:08:38,263 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 14:08:38,263 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 14:08:38,266 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:38,294 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 14:08:38,296 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:38,315 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 14:08:38,315 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:38,330 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 14:08:38,330 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-04 14:08:38,745 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 14:08:38,762 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 14:08:38,762 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [14] imperfect sequences [6] total 19 [2018-02-04 14:08:38,762 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 14:08:38,762 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 14:08:38,762 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2018-02-04 14:08:38,763 INFO L87 Difference]: Start difference. First operand 159 states and 169 transitions. Second operand 19 states. [2018-02-04 14:08:39,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:39,655 INFO L93 Difference]: Finished difference Result 181 states and 191 transitions. [2018-02-04 14:08:39,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 14:08:39,656 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 36 [2018-02-04 14:08:39,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:39,656 INFO L225 Difference]: With dead ends: 181 [2018-02-04 14:08:39,657 INFO L226 Difference]: Without dead ends: 179 [2018-02-04 14:08:39,657 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=99, Invalid=603, Unknown=0, NotChecked=0, Total=702 [2018-02-04 14:08:39,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-02-04 14:08:39,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 159. [2018-02-04 14:08:39,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-02-04 14:08:39,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 169 transitions. [2018-02-04 14:08:39,660 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 169 transitions. Word has length 36 [2018-02-04 14:08:39,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:39,660 INFO L432 AbstractCegarLoop]: Abstraction has 159 states and 169 transitions. [2018-02-04 14:08:39,661 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 14:08:39,661 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 169 transitions. [2018-02-04 14:08:39,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 14:08:39,662 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:39,663 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:39,663 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:39,663 INFO L82 PathProgramCache]: Analyzing trace with hash -1379512829, now seen corresponding path program 1 times [2018-02-04 14:08:39,663 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:39,663 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:39,664 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:39,665 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 14:08:39,665 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:39,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:39,669 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:39,702 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 14:08:39,702 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:39,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 14:08:39,703 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 14:08:39,703 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 14:08:39,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 14:08:39,703 INFO L87 Difference]: Start difference. First operand 159 states and 169 transitions. Second operand 3 states. [2018-02-04 14:08:39,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:39,790 INFO L93 Difference]: Finished difference Result 177 states and 190 transitions. [2018-02-04 14:08:39,791 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 14:08:39,791 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2018-02-04 14:08:39,791 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:39,792 INFO L225 Difference]: With dead ends: 177 [2018-02-04 14:08:39,792 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 14:08:39,792 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 14:08:39,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 14:08:39,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 155. [2018-02-04 14:08:39,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 155 states. [2018-02-04 14:08:39,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 164 transitions. [2018-02-04 14:08:39,796 INFO L78 Accepts]: Start accepts. Automaton has 155 states and 164 transitions. Word has length 39 [2018-02-04 14:08:39,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:39,796 INFO L432 AbstractCegarLoop]: Abstraction has 155 states and 164 transitions. [2018-02-04 14:08:39,796 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 14:08:39,796 INFO L276 IsEmpty]: Start isEmpty. Operand 155 states and 164 transitions. [2018-02-04 14:08:39,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 14:08:39,796 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:39,796 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:39,796 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:39,797 INFO L82 PathProgramCache]: Analyzing trace with hash 710655878, now seen corresponding path program 1 times [2018-02-04 14:08:39,797 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:39,797 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:39,797 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:39,797 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:39,797 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:39,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:39,804 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:39,847 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 14:08:39,847 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:39,847 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 14:08:39,847 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 14:08:39,847 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 14:08:39,847 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 14:08:39,848 INFO L87 Difference]: Start difference. First operand 155 states and 164 transitions. Second operand 10 states. [2018-02-04 14:08:40,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:40,054 INFO L93 Difference]: Finished difference Result 153 states and 162 transitions. [2018-02-04 14:08:40,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 14:08:40,054 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-04 14:08:40,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:40,055 INFO L225 Difference]: With dead ends: 153 [2018-02-04 14:08:40,055 INFO L226 Difference]: Without dead ends: 153 [2018-02-04 14:08:40,055 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 14:08:40,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-02-04 14:08:40,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 153. [2018-02-04 14:08:40,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-02-04 14:08:40,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 162 transitions. [2018-02-04 14:08:40,058 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 162 transitions. Word has length 42 [2018-02-04 14:08:40,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:40,058 INFO L432 AbstractCegarLoop]: Abstraction has 153 states and 162 transitions. [2018-02-04 14:08:40,058 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 14:08:40,058 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 162 transitions. [2018-02-04 14:08:40,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 14:08:40,059 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:40,059 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:40,059 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:40,060 INFO L82 PathProgramCache]: Analyzing trace with hash 710655879, now seen corresponding path program 1 times [2018-02-04 14:08:40,060 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:40,060 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:40,061 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:40,061 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:40,061 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:40,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:40,072 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:40,099 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:40,099 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:40,099 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:40,104 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:40,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:40,127 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:40,134 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:40,150 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:08:40,151 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-02-04 14:08:40,151 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 14:08:40,151 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 14:08:40,151 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-02-04 14:08:40,151 INFO L87 Difference]: Start difference. First operand 153 states and 162 transitions. Second operand 8 states. [2018-02-04 14:08:40,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:40,164 INFO L93 Difference]: Finished difference Result 156 states and 165 transitions. [2018-02-04 14:08:40,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 14:08:40,164 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-02-04 14:08:40,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:40,165 INFO L225 Difference]: With dead ends: 156 [2018-02-04 14:08:40,165 INFO L226 Difference]: Without dead ends: 154 [2018-02-04 14:08:40,165 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-02-04 14:08:40,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-04 14:08:40,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 154. [2018-02-04 14:08:40,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-02-04 14:08:40,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 163 transitions. [2018-02-04 14:08:40,168 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 163 transitions. Word has length 42 [2018-02-04 14:08:40,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:40,168 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 163 transitions. [2018-02-04 14:08:40,168 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 14:08:40,168 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 163 transitions. [2018-02-04 14:08:40,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-04 14:08:40,169 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:40,169 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:40,169 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:40,169 INFO L82 PathProgramCache]: Analyzing trace with hash -495427355, now seen corresponding path program 1 times [2018-02-04 14:08:40,169 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:40,169 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:40,170 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:40,170 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:40,170 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:40,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:40,173 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:40,211 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 14:08:40,211 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:40,211 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 14:08:40,211 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 14:08:40,211 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 14:08:40,211 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 14:08:40,212 INFO L87 Difference]: Start difference. First operand 154 states and 163 transitions. Second operand 6 states. [2018-02-04 14:08:40,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:40,255 INFO L93 Difference]: Finished difference Result 138 states and 145 transitions. [2018-02-04 14:08:40,256 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 14:08:40,256 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 41 [2018-02-04 14:08:40,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:40,256 INFO L225 Difference]: With dead ends: 138 [2018-02-04 14:08:40,256 INFO L226 Difference]: Without dead ends: 138 [2018-02-04 14:08:40,256 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 14:08:40,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-02-04 14:08:40,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 138. [2018-02-04 14:08:40,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-02-04 14:08:40,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 145 transitions. [2018-02-04 14:08:40,259 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 145 transitions. Word has length 41 [2018-02-04 14:08:40,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:40,259 INFO L432 AbstractCegarLoop]: Abstraction has 138 states and 145 transitions. [2018-02-04 14:08:40,259 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 14:08:40,260 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 145 transitions. [2018-02-04 14:08:40,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-02-04 14:08:40,260 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:40,260 INFO L351 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:40,260 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:40,260 INFO L82 PathProgramCache]: Analyzing trace with hash -141638285, now seen corresponding path program 2 times [2018-02-04 14:08:40,261 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:40,261 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:40,262 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:40,262 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:40,262 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:40,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:40,273 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:40,300 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:40,301 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:40,301 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:40,306 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 14:08:40,320 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 14:08:40,320 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 14:08:40,322 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:40,325 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 14:08:40,325 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:40,336 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 14:08:40,337 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:40,348 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 14:08:40,348 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-04 14:08:40,798 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 14:08:40,815 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 14:08:40,885 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [8] total 22 [2018-02-04 14:08:40,885 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 14:08:40,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 14:08:40,886 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=390, Unknown=0, NotChecked=0, Total=462 [2018-02-04 14:08:40,886 INFO L87 Difference]: Start difference. First operand 138 states and 145 transitions. Second operand 22 states. [2018-02-04 14:08:43,086 WARN L143 SmtUtils]: Spent 2029ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-04 14:08:43,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:43,751 INFO L93 Difference]: Finished difference Result 139 states and 146 transitions. [2018-02-04 14:08:43,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 14:08:43,751 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 43 [2018-02-04 14:08:43,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:43,752 INFO L225 Difference]: With dead ends: 139 [2018-02-04 14:08:43,752 INFO L226 Difference]: Without dead ends: 137 [2018-02-04 14:08:43,752 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 155 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=147, Invalid=845, Unknown=0, NotChecked=0, Total=992 [2018-02-04 14:08:43,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-02-04 14:08:43,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-02-04 14:08:43,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-02-04 14:08:43,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 144 transitions. [2018-02-04 14:08:43,756 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 144 transitions. Word has length 43 [2018-02-04 14:08:43,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:43,756 INFO L432 AbstractCegarLoop]: Abstraction has 137 states and 144 transitions. [2018-02-04 14:08:43,756 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 14:08:43,756 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 144 transitions. [2018-02-04 14:08:43,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 14:08:43,757 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:43,757 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:43,757 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:43,757 INFO L82 PathProgramCache]: Analyzing trace with hash 1517747909, now seen corresponding path program 1 times [2018-02-04 14:08:43,757 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:43,757 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:43,758 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:43,758 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 14:08:43,758 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:43,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:43,766 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:43,803 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 14:08:43,803 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:43,803 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 14:08:43,803 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 14:08:43,804 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 14:08:43,804 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 14:08:43,804 INFO L87 Difference]: Start difference. First operand 137 states and 144 transitions. Second operand 8 states. [2018-02-04 14:08:43,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:43,853 INFO L93 Difference]: Finished difference Result 139 states and 145 transitions. [2018-02-04 14:08:43,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 14:08:43,867 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 47 [2018-02-04 14:08:43,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:43,867 INFO L225 Difference]: With dead ends: 139 [2018-02-04 14:08:43,868 INFO L226 Difference]: Without dead ends: 137 [2018-02-04 14:08:43,868 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-04 14:08:43,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-02-04 14:08:43,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-02-04 14:08:43,871 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-02-04 14:08:43,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 143 transitions. [2018-02-04 14:08:43,872 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 143 transitions. Word has length 47 [2018-02-04 14:08:43,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:43,872 INFO L432 AbstractCegarLoop]: Abstraction has 137 states and 143 transitions. [2018-02-04 14:08:43,872 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 14:08:43,872 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 143 transitions. [2018-02-04 14:08:43,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-04 14:08:43,873 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:43,873 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:43,873 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:43,873 INFO L82 PathProgramCache]: Analyzing trace with hash 2035822852, now seen corresponding path program 1 times [2018-02-04 14:08:43,873 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:43,873 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:43,874 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:43,874 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:43,874 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:43,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:43,882 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:43,927 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 14:08:43,927 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:43,927 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 14:08:43,927 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 14:08:43,927 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 14:08:43,928 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 14:08:43,928 INFO L87 Difference]: Start difference. First operand 137 states and 143 transitions. Second operand 10 states. [2018-02-04 14:08:43,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:43,985 INFO L93 Difference]: Finished difference Result 141 states and 146 transitions. [2018-02-04 14:08:43,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 14:08:43,985 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 52 [2018-02-04 14:08:43,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:43,986 INFO L225 Difference]: With dead ends: 141 [2018-02-04 14:08:43,986 INFO L226 Difference]: Without dead ends: 137 [2018-02-04 14:08:43,986 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 14:08:43,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-02-04 14:08:43,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-02-04 14:08:43,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-02-04 14:08:43,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 142 transitions. [2018-02-04 14:08:43,989 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 142 transitions. Word has length 52 [2018-02-04 14:08:43,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:43,989 INFO L432 AbstractCegarLoop]: Abstraction has 137 states and 142 transitions. [2018-02-04 14:08:43,989 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 14:08:43,989 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 142 transitions. [2018-02-04 14:08:43,990 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-02-04 14:08:43,990 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:43,990 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:43,990 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:43,990 INFO L82 PathProgramCache]: Analyzing trace with hash 1511828740, now seen corresponding path program 1 times [2018-02-04 14:08:43,990 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:43,991 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:43,991 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:43,991 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:43,991 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:44,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:44,003 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:44,106 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 14:08:44,107 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:44,107 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-02-04 14:08:44,107 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 14:08:44,107 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 14:08:44,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=133, Unknown=0, NotChecked=0, Total=156 [2018-02-04 14:08:44,108 INFO L87 Difference]: Start difference. First operand 137 states and 142 transitions. Second operand 13 states. [2018-02-04 14:08:44,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:44,369 INFO L93 Difference]: Finished difference Result 135 states and 140 transitions. [2018-02-04 14:08:44,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 14:08:44,369 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 63 [2018-02-04 14:08:44,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:44,369 INFO L225 Difference]: With dead ends: 135 [2018-02-04 14:08:44,370 INFO L226 Difference]: Without dead ends: 135 [2018-02-04 14:08:44,370 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-02-04 14:08:44,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-02-04 14:08:44,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-02-04 14:08:44,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-04 14:08:44,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 140 transitions. [2018-02-04 14:08:44,373 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 140 transitions. Word has length 63 [2018-02-04 14:08:44,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:44,374 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 140 transitions. [2018-02-04 14:08:44,374 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 14:08:44,374 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 140 transitions. [2018-02-04 14:08:44,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-02-04 14:08:44,374 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:44,375 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:44,375 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:44,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1511828741, now seen corresponding path program 1 times [2018-02-04 14:08:44,375 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:44,375 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:44,376 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:44,376 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:44,376 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:44,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:44,395 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:44,433 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:44,434 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:44,434 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:44,439 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:44,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:44,472 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:44,485 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:44,502 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:08:44,502 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-02-04 14:08:44,503 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 14:08:44,503 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 14:08:44,503 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-02-04 14:08:44,503 INFO L87 Difference]: Start difference. First operand 135 states and 140 transitions. Second operand 10 states. [2018-02-04 14:08:44,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:44,521 INFO L93 Difference]: Finished difference Result 138 states and 143 transitions. [2018-02-04 14:08:44,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 14:08:44,522 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 63 [2018-02-04 14:08:44,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:44,523 INFO L225 Difference]: With dead ends: 138 [2018-02-04 14:08:44,523 INFO L226 Difference]: Without dead ends: 136 [2018-02-04 14:08:44,523 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-02-04 14:08:44,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-02-04 14:08:44,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-02-04 14:08:44,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-02-04 14:08:44,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 141 transitions. [2018-02-04 14:08:44,526 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 141 transitions. Word has length 63 [2018-02-04 14:08:44,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:44,526 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 141 transitions. [2018-02-04 14:08:44,526 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 14:08:44,526 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 141 transitions. [2018-02-04 14:08:44,527 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 14:08:44,527 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:44,527 INFO L351 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:44,527 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:44,527 INFO L82 PathProgramCache]: Analyzing trace with hash 2058801817, now seen corresponding path program 2 times [2018-02-04 14:08:44,527 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:44,527 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:44,528 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:44,528 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:44,528 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:44,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:44,537 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:44,580 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:44,580 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:44,580 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:44,586 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 14:08:44,609 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 14:08:44,610 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 14:08:44,612 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:44,615 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 14:08:44,616 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:44,624 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 14:08:44,624 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:44,632 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 14:08:44,632 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-04 14:08:45,108 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 14:08:45,125 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 14:08:45,125 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [18] imperfect sequences [10] total 27 [2018-02-04 14:08:45,125 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 14:08:45,125 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 14:08:45,126 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=603, Unknown=0, NotChecked=0, Total=702 [2018-02-04 14:08:45,126 INFO L87 Difference]: Start difference. First operand 136 states and 141 transitions. Second operand 27 states. [2018-02-04 14:08:47,239 WARN L143 SmtUtils]: Spent 2016ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-04 14:08:51,178 WARN L143 SmtUtils]: Spent 3902ms on a formula simplification that was a NOOP. DAG size: 31 [2018-02-04 14:08:52,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:52,011 INFO L93 Difference]: Finished difference Result 137 states and 142 transitions. [2018-02-04 14:08:52,011 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-04 14:08:52,011 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 64 [2018-02-04 14:08:52,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:52,012 INFO L225 Difference]: With dead ends: 137 [2018-02-04 14:08:52,012 INFO L226 Difference]: Without dead ends: 135 [2018-02-04 14:08:52,012 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=213, Invalid=1347, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 14:08:52,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-02-04 14:08:52,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-02-04 14:08:52,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-04 14:08:52,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 140 transitions. [2018-02-04 14:08:52,014 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 140 transitions. Word has length 64 [2018-02-04 14:08:52,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:52,015 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 140 transitions. [2018-02-04 14:08:52,015 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 14:08:52,015 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 140 transitions. [2018-02-04 14:08:52,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-04 14:08:52,015 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:52,015 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:52,015 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:52,015 INFO L82 PathProgramCache]: Analyzing trace with hash -243629328, now seen corresponding path program 1 times [2018-02-04 14:08:52,016 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:52,016 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:52,016 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,016 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 14:08:52,016 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:52,025 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:52,086 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 14:08:52,086 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:52,086 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2018-02-04 14:08:52,086 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 14:08:52,087 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 14:08:52,087 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-02-04 14:08:52,087 INFO L87 Difference]: Start difference. First operand 135 states and 140 transitions. Second operand 11 states. [2018-02-04 14:08:52,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:52,141 INFO L93 Difference]: Finished difference Result 138 states and 142 transitions. [2018-02-04 14:08:52,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 14:08:52,142 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 74 [2018-02-04 14:08:52,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:52,142 INFO L225 Difference]: With dead ends: 138 [2018-02-04 14:08:52,142 INFO L226 Difference]: Without dead ends: 135 [2018-02-04 14:08:52,143 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-04 14:08:52,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-02-04 14:08:52,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-02-04 14:08:52,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-04 14:08:52,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 139 transitions. [2018-02-04 14:08:52,146 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 139 transitions. Word has length 74 [2018-02-04 14:08:52,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:52,146 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 139 transitions. [2018-02-04 14:08:52,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 14:08:52,146 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 139 transitions. [2018-02-04 14:08:52,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-04 14:08:52,147 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:52,147 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:52,147 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:52,147 INFO L82 PathProgramCache]: Analyzing trace with hash 254396120, now seen corresponding path program 1 times [2018-02-04 14:08:52,147 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:52,147 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:52,148 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,148 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:52,148 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:52,163 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:52,303 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 14:08:52,303 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:08:52,303 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2018-02-04 14:08:52,303 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 14:08:52,304 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 14:08:52,304 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=271, Unknown=0, NotChecked=0, Total=306 [2018-02-04 14:08:52,304 INFO L87 Difference]: Start difference. First operand 135 states and 139 transitions. Second operand 18 states. [2018-02-04 14:08:52,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:52,632 INFO L93 Difference]: Finished difference Result 163 states and 174 transitions. [2018-02-04 14:08:52,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 14:08:52,632 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 87 [2018-02-04 14:08:52,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:52,633 INFO L225 Difference]: With dead ends: 163 [2018-02-04 14:08:52,633 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 14:08:52,633 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=493, Unknown=0, NotChecked=0, Total=552 [2018-02-04 14:08:52,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 14:08:52,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 158. [2018-02-04 14:08:52,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-02-04 14:08:52,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 170 transitions. [2018-02-04 14:08:52,636 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 170 transitions. Word has length 87 [2018-02-04 14:08:52,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:52,636 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 170 transitions. [2018-02-04 14:08:52,636 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 14:08:52,636 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 170 transitions. [2018-02-04 14:08:52,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-04 14:08:52,637 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:52,637 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:52,637 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:52,637 INFO L82 PathProgramCache]: Analyzing trace with hash 254396121, now seen corresponding path program 1 times [2018-02-04 14:08:52,638 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:52,638 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:52,638 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,638 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:52,638 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:52,649 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:52,720 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:52,721 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:52,721 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:52,729 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:52,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:52,773 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:52,797 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:52,828 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:08:52,828 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-02-04 14:08:52,828 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 14:08:52,828 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 14:08:52,828 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-02-04 14:08:52,828 INFO L87 Difference]: Start difference. First operand 158 states and 170 transitions. Second operand 12 states. [2018-02-04 14:08:52,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:08:52,852 INFO L93 Difference]: Finished difference Result 161 states and 173 transitions. [2018-02-04 14:08:52,854 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 14:08:52,854 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 87 [2018-02-04 14:08:52,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:08:52,855 INFO L225 Difference]: With dead ends: 161 [2018-02-04 14:08:52,855 INFO L226 Difference]: Without dead ends: 159 [2018-02-04 14:08:52,855 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-02-04 14:08:52,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-02-04 14:08:52,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 159. [2018-02-04 14:08:52,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-02-04 14:08:52,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 171 transitions. [2018-02-04 14:08:52,857 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 171 transitions. Word has length 87 [2018-02-04 14:08:52,857 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:08:52,857 INFO L432 AbstractCegarLoop]: Abstraction has 159 states and 171 transitions. [2018-02-04 14:08:52,858 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 14:08:52,858 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 171 transitions. [2018-02-04 14:08:52,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-02-04 14:08:52,858 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:08:52,858 INFO L351 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:08:52,858 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:08:52,858 INFO L82 PathProgramCache]: Analyzing trace with hash -388927379, now seen corresponding path program 2 times [2018-02-04 14:08:52,858 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:08:52,859 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:08:52,859 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,859 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:08:52,859 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:08:52,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:08:52,869 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:08:52,929 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:08:52,930 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:08:52,930 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:08:52,939 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 14:08:52,988 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 14:08:52,988 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 14:08:52,992 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:08:53,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 14:08:53,000 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:53,011 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 14:08:53,011 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:08:53,023 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 14:08:53,023 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-04 14:08:53,780 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-04 14:08:53,797 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 14:08:53,797 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [12] total 31 [2018-02-04 14:08:53,797 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 14:08:53,797 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 14:08:53,797 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=126, Invalid=804, Unknown=0, NotChecked=0, Total=930 [2018-02-04 14:08:53,798 INFO L87 Difference]: Start difference. First operand 159 states and 171 transitions. Second operand 31 states. [2018-02-04 14:08:56,010 WARN L143 SmtUtils]: Spent 2030ms on a formula simplification that was a NOOP. DAG size: 35 [2018-02-04 14:08:58,165 WARN L143 SmtUtils]: Spent 2020ms on a formula simplification that was a NOOP. DAG size: 35 [2018-02-04 14:09:00,218 WARN L143 SmtUtils]: Spent 1946ms on a formula simplification that was a NOOP. DAG size: 36 [2018-02-04 14:09:00,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:00,955 INFO L93 Difference]: Finished difference Result 160 states and 170 transitions. [2018-02-04 14:09:00,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-04 14:09:00,955 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 88 [2018-02-04 14:09:00,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:00,956 INFO L225 Difference]: With dead ends: 160 [2018-02-04 14:09:00,956 INFO L226 Difference]: Without dead ends: 158 [2018-02-04 14:09:00,957 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 67 SyntacticMatches, 3 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 488 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=286, Invalid=1876, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 14:09:00,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2018-02-04 14:09:00,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 158. [2018-02-04 14:09:00,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 158 states. [2018-02-04 14:09:00,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 168 transitions. [2018-02-04 14:09:00,960 INFO L78 Accepts]: Start accepts. Automaton has 158 states and 168 transitions. Word has length 88 [2018-02-04 14:09:00,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:00,961 INFO L432 AbstractCegarLoop]: Abstraction has 158 states and 168 transitions. [2018-02-04 14:09:00,961 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 14:09:00,961 INFO L276 IsEmpty]: Start isEmpty. Operand 158 states and 168 transitions. [2018-02-04 14:09:00,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-04 14:09:00,962 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:00,962 INFO L351 BasicCegarLoop]: trace histogram [9, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:00,962 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:00,962 INFO L82 PathProgramCache]: Analyzing trace with hash 1868073210, now seen corresponding path program 1 times [2018-02-04 14:09:00,962 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:00,962 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:00,963 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:00,963 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 14:09:00,963 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:00,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:00,976 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:01,060 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-02-04 14:09:01,061 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:01,061 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:01,069 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:01,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:01,119 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:01,244 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 14:09:01,270 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:09:01,270 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 13] total 22 [2018-02-04 14:09:01,270 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 14:09:01,270 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 14:09:01,271 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=376, Unknown=0, NotChecked=0, Total=462 [2018-02-04 14:09:01,271 INFO L87 Difference]: Start difference. First operand 158 states and 168 transitions. Second operand 22 states. [2018-02-04 14:09:01,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:01,400 INFO L93 Difference]: Finished difference Result 162 states and 168 transitions. [2018-02-04 14:09:01,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 14:09:01,400 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 92 [2018-02-04 14:09:01,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:01,401 INFO L225 Difference]: With dead ends: 162 [2018-02-04 14:09:01,401 INFO L226 Difference]: Without dead ends: 156 [2018-02-04 14:09:01,401 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=102, Invalid=548, Unknown=0, NotChecked=0, Total=650 [2018-02-04 14:09:01,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-02-04 14:09:01,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 156. [2018-02-04 14:09:01,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-02-04 14:09:01,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 162 transitions. [2018-02-04 14:09:01,405 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 162 transitions. Word has length 92 [2018-02-04 14:09:01,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:01,405 INFO L432 AbstractCegarLoop]: Abstraction has 156 states and 162 transitions. [2018-02-04 14:09:01,405 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 14:09:01,405 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 162 transitions. [2018-02-04 14:09:01,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-02-04 14:09:01,406 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:01,406 INFO L351 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:01,406 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:01,407 INFO L82 PathProgramCache]: Analyzing trace with hash -63866368, now seen corresponding path program 1 times [2018-02-04 14:09:01,407 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:01,407 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:01,407 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:01,407 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:01,408 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:01,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:01,425 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:01,631 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 55 trivial. 0 not checked. [2018-02-04 14:09:01,631 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 14:09:01,631 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [] total 20 [2018-02-04 14:09:01,631 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 14:09:01,632 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 14:09:01,632 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=381, Unknown=0, NotChecked=0, Total=420 [2018-02-04 14:09:01,632 INFO L87 Difference]: Start difference. First operand 156 states and 162 transitions. Second operand 21 states. [2018-02-04 14:09:02,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:02,061 INFO L93 Difference]: Finished difference Result 166 states and 175 transitions. [2018-02-04 14:09:02,061 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-04 14:09:02,061 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 104 [2018-02-04 14:09:02,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:02,062 INFO L225 Difference]: With dead ends: 166 [2018-02-04 14:09:02,062 INFO L226 Difference]: Without dead ends: 166 [2018-02-04 14:09:02,062 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=75, Invalid=795, Unknown=0, NotChecked=0, Total=870 [2018-02-04 14:09:02,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-02-04 14:09:02,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 162. [2018-02-04 14:09:02,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-04 14:09:02,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 172 transitions. [2018-02-04 14:09:02,065 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 172 transitions. Word has length 104 [2018-02-04 14:09:02,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:02,066 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 172 transitions. [2018-02-04 14:09:02,066 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 14:09:02,066 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 172 transitions. [2018-02-04 14:09:02,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-02-04 14:09:02,067 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:02,067 INFO L351 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:02,067 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:02,067 INFO L82 PathProgramCache]: Analyzing trace with hash -63866367, now seen corresponding path program 1 times [2018-02-04 14:09:02,067 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:02,067 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:02,068 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:02,068 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:02,068 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:02,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:02,085 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:02,177 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:09:02,177 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:02,177 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:02,183 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:02,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:02,228 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:02,237 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:09:02,255 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:09:02,255 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2018-02-04 14:09:02,255 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 14:09:02,256 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 14:09:02,256 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-02-04 14:09:02,256 INFO L87 Difference]: Start difference. First operand 162 states and 172 transitions. Second operand 15 states. [2018-02-04 14:09:02,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:02,312 INFO L93 Difference]: Finished difference Result 165 states and 175 transitions. [2018-02-04 14:09:02,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 14:09:02,312 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 104 [2018-02-04 14:09:02,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:02,312 INFO L225 Difference]: With dead ends: 165 [2018-02-04 14:09:02,312 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 14:09:02,313 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=97, Invalid=143, Unknown=0, NotChecked=0, Total=240 [2018-02-04 14:09:02,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 14:09:02,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. [2018-02-04 14:09:02,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-02-04 14:09:02,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 173 transitions. [2018-02-04 14:09:02,315 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 173 transitions. Word has length 104 [2018-02-04 14:09:02,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:02,315 INFO L432 AbstractCegarLoop]: Abstraction has 163 states and 173 transitions. [2018-02-04 14:09:02,315 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 14:09:02,315 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 173 transitions. [2018-02-04 14:09:02,315 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-02-04 14:09:02,316 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:02,316 INFO L351 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:02,316 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:02,316 INFO L82 PathProgramCache]: Analyzing trace with hash -1207457043, now seen corresponding path program 2 times [2018-02-04 14:09:02,316 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:02,316 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:02,316 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:02,316 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:02,316 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:02,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:02,328 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:02,412 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:09:02,412 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:02,412 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:02,423 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 14:09:02,466 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 14:09:02,466 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 14:09:02,470 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:02,473 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 14:09:02,473 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:02,483 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 14:09:02,484 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:02,493 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 14:09:02,493 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:36 [2018-02-04 14:09:03,616 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-02-04 14:09:03,632 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 14:09:03,633 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [24] imperfect sequences [15] total 38 [2018-02-04 14:09:03,633 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-02-04 14:09:03,633 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-02-04 14:09:03,633 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=178, Invalid=1228, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 14:09:03,633 INFO L87 Difference]: Start difference. First operand 163 states and 173 transitions. Second operand 38 states. [2018-02-04 14:09:06,147 WARN L143 SmtUtils]: Spent 2020ms on a formula simplification that was a NOOP. DAG size: 35 [2018-02-04 14:09:07,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:07,366 INFO L93 Difference]: Finished difference Result 164 states and 173 transitions. [2018-02-04 14:09:07,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 14:09:07,366 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 105 [2018-02-04 14:09:07,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:07,367 INFO L225 Difference]: With dead ends: 164 [2018-02-04 14:09:07,367 INFO L226 Difference]: Without dead ends: 162 [2018-02-04 14:09:07,368 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 78 SyntacticMatches, 5 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 833 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=425, Invalid=2997, Unknown=0, NotChecked=0, Total=3422 [2018-02-04 14:09:07,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-04 14:09:07,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-04 14:09:07,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-04 14:09:07,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 171 transitions. [2018-02-04 14:09:07,372 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 171 transitions. Word has length 105 [2018-02-04 14:09:07,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:07,372 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 171 transitions. [2018-02-04 14:09:07,372 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-02-04 14:09:07,372 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 171 transitions. [2018-02-04 14:09:07,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-02-04 14:09:07,373 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:07,373 INFO L351 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:07,373 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:07,373 INFO L82 PathProgramCache]: Analyzing trace with hash 2055534530, now seen corresponding path program 1 times [2018-02-04 14:09:07,373 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:07,373 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:07,374 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:07,374 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 14:09:07,374 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:07,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:07,393 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:07,520 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:09:07,521 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:07,521 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:07,528 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:07,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:07,595 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:07,615 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:09:07,634 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:09:07,635 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2018-02-04 14:09:07,635 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 14:09:07,635 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 14:09:07,635 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-02-04 14:09:07,635 INFO L87 Difference]: Start difference. First operand 162 states and 171 transitions. Second operand 17 states. [2018-02-04 14:09:07,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:07,658 INFO L93 Difference]: Finished difference Result 165 states and 174 transitions. [2018-02-04 14:09:07,659 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 14:09:07,659 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 110 [2018-02-04 14:09:07,659 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:07,659 INFO L225 Difference]: With dead ends: 165 [2018-02-04 14:09:07,659 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 14:09:07,660 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 110 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=126, Invalid=180, Unknown=0, NotChecked=0, Total=306 [2018-02-04 14:09:07,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 14:09:07,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. [2018-02-04 14:09:07,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-02-04 14:09:07,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 172 transitions. [2018-02-04 14:09:07,662 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 172 transitions. Word has length 110 [2018-02-04 14:09:07,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:07,662 INFO L432 AbstractCegarLoop]: Abstraction has 163 states and 172 transitions. [2018-02-04 14:09:07,662 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 14:09:07,662 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 172 transitions. [2018-02-04 14:09:07,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-02-04 14:09:07,663 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:07,663 INFO L351 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:07,663 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:07,663 INFO L82 PathProgramCache]: Analyzing trace with hash 1832241070, now seen corresponding path program 2 times [2018-02-04 14:09:07,663 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:07,663 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:07,664 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:07,664 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:07,664 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:07,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:07,682 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:07,825 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 14:09:07,825 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:07,826 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:07,833 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 14:09:07,883 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 14:09:07,883 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 14:09:07,894 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:07,999 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 14:09:08,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 14:09:08,000 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,001 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,001 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,001 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:11, output treesize:7 [2018-02-04 14:09:08,062 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:08,064 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:08,067 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:08,067 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:26 [2018-02-04 14:09:08,069 WARN L1033 $PredicateComparison]: unable to prove that (exists ((LDV_INIT_LIST_HEAD_~list.offset Int) (v_DerPreprocessor_2 Int)) (and (= |c_#memory_int| (store |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base| (let ((.cse0 (+ LDV_INIT_LIST_HEAD_~list.offset 4))) (store (store (select |c_old(#memory_int)| |c_LDV_INIT_LIST_HEAD_#in~list.base|) LDV_INIT_LIST_HEAD_~list.offset v_DerPreprocessor_2) .cse0 (select (select |c_#memory_int| |c_LDV_INIT_LIST_HEAD_#in~list.base|) .cse0))))) (<= LDV_INIT_LIST_HEAD_~list.offset |c_LDV_INIT_LIST_HEAD_#in~list.offset|))) is different from true [2018-02-04 14:09:08,074 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 27 [2018-02-04 14:09:08,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:08,078 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 35 [2018-02-04 14:09:08,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:08,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:08,083 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 37 [2018-02-04 14:09:08,083 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,087 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,089 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,092 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,092 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 3 variables, input treesize:37, output treesize:9 [2018-02-04 14:09:08,377 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:08,378 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 36 [2018-02-04 14:09:08,379 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 14:09:08,380 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:08,380 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 15 [2018-02-04 14:09:08,380 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,382 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,385 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,385 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:32, output treesize:13 [2018-02-04 14:09:08,704 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 13 [2018-02-04 14:09:08,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 5 [2018-02-04 14:09:08,705 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,705 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,706 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:08,706 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:17, output treesize:5 [2018-02-04 14:09:08,738 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-02-04 14:09:08,755 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 14:09:08,755 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [41] imperfect sequences [17] total 56 [2018-02-04 14:09:08,755 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-02-04 14:09:08,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-02-04 14:09:08,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=2761, Unknown=1, NotChecked=106, Total=3080 [2018-02-04 14:09:08,756 INFO L87 Difference]: Start difference. First operand 163 states and 172 transitions. Second operand 56 states. [2018-02-04 14:09:10,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:10,719 INFO L93 Difference]: Finished difference Result 159 states and 162 transitions. [2018-02-04 14:09:10,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-02-04 14:09:10,720 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 111 [2018-02-04 14:09:10,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:10,720 INFO L225 Difference]: With dead ends: 159 [2018-02-04 14:09:10,720 INFO L226 Difference]: Without dead ends: 157 [2018-02-04 14:09:10,721 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 1026 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=325, Invalid=5530, Unknown=1, NotChecked=150, Total=6006 [2018-02-04 14:09:10,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-02-04 14:09:10,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-02-04 14:09:10,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-02-04 14:09:10,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 160 transitions. [2018-02-04 14:09:10,723 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 160 transitions. Word has length 111 [2018-02-04 14:09:10,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:10,723 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 160 transitions. [2018-02-04 14:09:10,724 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-02-04 14:09:10,724 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 160 transitions. [2018-02-04 14:09:10,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-02-04 14:09:10,724 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:10,724 INFO L351 BasicCegarLoop]: trace histogram [14, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:10,724 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:10,724 INFO L82 PathProgramCache]: Analyzing trace with hash 1142789455, now seen corresponding path program 1 times [2018-02-04 14:09:10,724 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:10,724 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:10,725 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:10,725 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 14:09:10,725 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:10,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:10,741 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:10,951 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2018-02-04 14:09:10,951 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:10,951 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:10,957 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:11,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:11,025 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:11,275 INFO L134 CoverageAnalysis]: Checked inductivity of 114 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 14:09:11,304 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:09:11,304 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 35 [2018-02-04 14:09:11,304 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-02-04 14:09:11,304 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-02-04 14:09:11,305 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=174, Invalid=1016, Unknown=0, NotChecked=0, Total=1190 [2018-02-04 14:09:11,305 INFO L87 Difference]: Start difference. First operand 157 states and 160 transitions. Second operand 35 states. [2018-02-04 14:09:12,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:12,149 INFO L93 Difference]: Finished difference Result 169 states and 172 transitions. [2018-02-04 14:09:12,150 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-04 14:09:12,150 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 119 [2018-02-04 14:09:12,150 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:12,150 INFO L225 Difference]: With dead ends: 169 [2018-02-04 14:09:12,150 INFO L226 Difference]: Without dead ends: 167 [2018-02-04 14:09:12,151 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 526 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=521, Invalid=3639, Unknown=0, NotChecked=0, Total=4160 [2018-02-04 14:09:12,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-02-04 14:09:12,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 165. [2018-02-04 14:09:12,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 14:09:12,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 168 transitions. [2018-02-04 14:09:12,153 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 168 transitions. Word has length 119 [2018-02-04 14:09:12,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:12,153 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 168 transitions. [2018-02-04 14:09:12,153 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-02-04 14:09:12,153 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 168 transitions. [2018-02-04 14:09:12,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-02-04 14:09:12,154 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:12,154 INFO L351 BasicCegarLoop]: trace histogram [15, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:12,154 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:12,154 INFO L82 PathProgramCache]: Analyzing trace with hash -577478985, now seen corresponding path program 1 times [2018-02-04 14:09:12,154 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:12,154 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:12,155 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:12,155 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:12,155 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:12,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:12,167 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:12,409 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 127 trivial. 0 not checked. [2018-02-04 14:09:12,409 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:12,409 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:12,415 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:12,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:12,477 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:12,744 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-04 14:09:12,761 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 14:09:12,761 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 19] total 39 [2018-02-04 14:09:12,762 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-02-04 14:09:12,762 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-02-04 14:09:12,762 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=195, Invalid=1287, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 14:09:12,762 INFO L87 Difference]: Start difference. First operand 165 states and 168 transitions. Second operand 39 states. [2018-02-04 14:09:13,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 14:09:13,860 INFO L93 Difference]: Finished difference Result 169 states and 172 transitions. [2018-02-04 14:09:13,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-02-04 14:09:13,860 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 134 [2018-02-04 14:09:13,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 14:09:13,861 INFO L225 Difference]: With dead ends: 169 [2018-02-04 14:09:13,861 INFO L226 Difference]: Without dead ends: 167 [2018-02-04 14:09:13,862 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 194 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 600 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=595, Invalid=4807, Unknown=0, NotChecked=0, Total=5402 [2018-02-04 14:09:13,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-02-04 14:09:13,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 165. [2018-02-04 14:09:13,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 14:09:13,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 168 transitions. [2018-02-04 14:09:13,864 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 168 transitions. Word has length 134 [2018-02-04 14:09:13,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 14:09:13,864 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 168 transitions. [2018-02-04 14:09:13,864 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-02-04 14:09:13,864 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 168 transitions. [2018-02-04 14:09:13,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 140 [2018-02-04 14:09:13,865 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 14:09:13,865 INFO L351 BasicCegarLoop]: trace histogram [16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 14:09:13,865 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_atomic_add_returnErr0RequiresViolation, ldv_atomic_add_returnErr1RequiresViolation, ldv_atomic_add_returnErr2RequiresViolation, ldv_atomic_add_returnErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 14:09:13,865 INFO L82 PathProgramCache]: Analyzing trace with hash -460832411, now seen corresponding path program 1 times [2018-02-04 14:09:13,865 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 14:09:13,865 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 14:09:13,866 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:13,866 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:13,866 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 14:09:13,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:13,970 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 14:09:18,353 INFO L134 CoverageAnalysis]: Checked inductivity of 152 backedges. 22 proven. 129 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 14:09:18,353 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 14:09:18,353 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 14:09:18,358 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 14:09:18,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 14:09:18,412 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 14:09:18,523 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 14:09:18,524 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 14:09:18,524 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,525 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,528 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,528 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:20, output treesize:16 [2018-02-04 14:09:18,580 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-02-04 14:09:18,581 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,582 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-02-04 14:09:18,582 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,586 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,591 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:18,592 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:36, output treesize:32 [2018-02-04 14:09:18,665 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-02-04 14:09:18,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,670 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 52 [2018-02-04 14:09:18,670 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,677 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,686 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:18,686 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:52, output treesize:48 [2018-02-04 14:09:18,774 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-02-04 14:09:18,776 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,777 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,778 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,778 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,779 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,780 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,781 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 85 [2018-02-04 14:09:18,781 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,792 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,802 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:18,802 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:68, output treesize:64 [2018-02-04 14:09:18,901 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 47 [2018-02-04 14:09:18,904 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,905 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,905 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,907 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,908 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,908 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,909 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,910 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,910 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,911 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:18,912 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 126 [2018-02-04 14:09:18,912 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,929 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:18,942 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:18,943 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:84, output treesize:80 [2018-02-04 14:09:19,049 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-02-04 14:09:19,052 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,055 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,055 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,060 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,061 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,061 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 175 [2018-02-04 14:09:19,062 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:19,086 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:19,102 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 1 dim-2 vars, End of recursive call: 5 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:19,102 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:100, output treesize:96 [2018-02-04 14:09:19,243 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 65 [2018-02-04 14:09:19,247 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,248 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,249 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,250 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,251 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,252 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,253 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,254 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,255 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,255 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,256 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,257 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,257 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,258 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,259 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,259 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,260 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,260 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,261 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,262 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,262 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,263 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 21 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 232 [2018-02-04 14:09:19,264 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:19,297 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:19,316 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 1 dim-2 vars, End of recursive call: 6 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:19,316 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 7 variables, input treesize:116, output treesize:112 [2018-02-04 14:09:19,728 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 74 [2018-02-04 14:09:19,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,753 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,754 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,756 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,757 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,758 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,758 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,759 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,760 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,761 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,761 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,762 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,764 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,764 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,766 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,767 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,767 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,768 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,770 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,770 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,771 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,772 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,780 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,781 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:19,782 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 28 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 297 [2018-02-04 14:09:19,782 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:19,829 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:19,853 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-2 vars, End of recursive call: 7 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:19,853 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 8 variables, input treesize:132, output treesize:128 [2018-02-04 14:09:24,559 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 83 [2018-02-04 14:09:24,578 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,579 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,580 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,581 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,584 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,586 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,587 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,588 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,589 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,590 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,590 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,591 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,594 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,596 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,599 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,600 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,608 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:24,611 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 36 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 370 [2018-02-04 14:09:24,612 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:24,682 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:24,714 INFO L267 ElimStorePlain]: Start of recursive call 1: 8 dim-0 vars, 1 dim-2 vars, End of recursive call: 8 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:24,715 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 9 variables, input treesize:148, output treesize:144 [2018-02-04 14:09:37,488 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 92 [2018-02-04 14:09:37,496 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,497 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,498 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,499 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,500 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,501 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,502 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,503 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,504 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,505 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,506 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,507 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,508 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,509 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,510 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,510 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,511 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,512 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,513 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,514 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,521 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,522 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,523 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,524 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,525 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,525 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,526 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,527 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,528 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,529 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,530 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,530 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,531 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,532 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,533 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,533 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,534 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,535 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,536 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,537 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,538 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,538 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,539 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,540 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,541 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:37,542 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 45 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 451 [2018-02-04 14:09:37,543 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:37,643 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:37,675 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: 9 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:37,675 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 10 variables, input treesize:164, output treesize:160 [2018-02-04 14:09:58,879 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 124 treesize of output 101 [2018-02-04 14:09:58,906 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,907 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,908 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,909 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,910 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,910 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,911 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,912 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,913 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,914 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,914 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,915 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,916 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,917 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,917 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,918 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,919 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,920 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,921 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,921 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,922 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,923 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,924 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,924 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,925 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,926 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,927 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,927 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,928 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,929 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,930 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,930 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,931 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,932 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,933 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,933 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,934 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,935 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,936 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,936 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,937 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,938 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,939 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,939 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,940 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,941 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,942 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,942 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,943 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,944 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,945 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,946 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,946 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,947 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,949 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:09:58,950 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 55 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 540 [2018-02-04 14:09:58,951 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:09:59,074 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:09:59,125 INFO L267 ElimStorePlain]: Start of recursive call 1: 10 dim-0 vars, 1 dim-2 vars, End of recursive call: 10 dim-0 vars, and 1 xjuncts. [2018-02-04 14:09:59,125 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 11 variables, input treesize:180, output treesize:176 [2018-02-04 14:10:27,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 135 treesize of output 110 [2018-02-04 14:10:27,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,599 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,600 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,600 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,608 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,612 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,612 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,617 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,617 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,618 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,619 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,619 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,622 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,622 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,626 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,627 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,627 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,628 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,628 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,629 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,630 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,630 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,631 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,631 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,632 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,633 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,633 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,635 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,638 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:10:27,639 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 66 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 637 [2018-02-04 14:10:27,640 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:10:27,782 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:10:27,820 INFO L267 ElimStorePlain]: Start of recursive call 1: 11 dim-0 vars, 1 dim-2 vars, End of recursive call: 11 dim-0 vars, and 1 xjuncts. [2018-02-04 14:10:27,820 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 12 variables, input treesize:196, output treesize:192 [2018-02-04 14:11:04,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 146 treesize of output 119 [2018-02-04 14:11:04,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,111 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,116 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,116 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,119 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,122 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,122 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,123 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,124 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,124 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,126 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,126 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,127 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,129 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,130 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,130 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,131 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,133 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,133 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,134 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,136 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,137 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,137 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,138 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,139 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,139 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,140 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,141 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,141 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,142 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,142 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,144 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,144 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,145 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,146 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,146 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,147 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,148 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,148 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,149 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,150 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,150 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,151 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,151 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,154 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,154 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,155 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,156 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,156 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,157 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,158 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,158 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,159 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,160 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,160 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,161 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,161 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,162 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,163 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:04,164 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 12 select indices, 12 select index equivalence classes, 78 disjoint index pairs (out of 66 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 742 [2018-02-04 14:11:04,165 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:11:04,348 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:11:04,394 INFO L267 ElimStorePlain]: Start of recursive call 1: 12 dim-0 vars, 1 dim-2 vars, End of recursive call: 12 dim-0 vars, and 1 xjuncts. [2018-02-04 14:11:04,394 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 13 variables, input treesize:212, output treesize:208 [2018-02-04 14:11:47,280 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 128 [2018-02-04 14:11:47,286 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,287 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,289 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,291 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,292 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,292 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,294 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,295 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,296 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,297 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,298 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,299 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,300 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,301 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,302 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,303 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,304 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,305 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,306 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,307 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,308 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,309 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,310 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,311 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,312 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,313 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,313 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,314 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,315 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,316 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,317 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,318 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,319 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,320 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,321 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,322 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,323 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,324 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,325 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,326 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,327 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,327 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,328 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,331 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,332 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,333 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,334 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,335 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,336 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,337 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,338 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,339 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,340 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,342 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,343 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,344 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,345 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,346 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,347 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,347 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,348 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,349 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,350 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,351 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,352 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,353 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,354 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,355 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,356 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,357 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,358 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,359 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,360 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,361 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,362 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,363 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,364 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,364 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,365 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,366 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,367 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,368 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,369 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,370 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,371 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,372 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 14:11:47,373 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 13 select indices, 13 select index equivalence classes, 91 disjoint index pairs (out of 78 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 855 [2018-02-04 14:11:47,374 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 14:11:47,610 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 14:11:47,661 INFO L267 ElimStorePlain]: Start of recursive call 1: 13 dim-0 vars, 1 dim-2 vars, End of recursive call: 13 dim-0 vars, and 1 xjuncts. [2018-02-04 14:11:47,661 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 14 variables, input treesize:228, output treesize:224 Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown