java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 15:02:45,297 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 15:02:45,298 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 15:02:45,311 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 15:02:45,311 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 15:02:45,312 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 15:02:45,312 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 15:02:45,314 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 15:02:45,315 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 15:02:45,316 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 15:02:45,317 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 15:02:45,317 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 15:02:45,318 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 15:02:45,319 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 15:02:45,319 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 15:02:45,321 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 15:02:45,323 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 15:02:45,324 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 15:02:45,325 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 15:02:45,326 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 15:02:45,328 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-02-04 15:02:45,332 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 15:02:45,332 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 15:02:45,332 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-04 15:02:45,342 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 15:02:45,342 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 15:02:45,343 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 15:02:45,343 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 15:02:45,344 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 15:02:45,344 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 15:02:45,345 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 15:02:45,345 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 15:02:45,345 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-04 15:02:45,374 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 15:02:45,384 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 15:02:45,388 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 15:02:45,389 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 15:02:45,389 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 15:02:45,390 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-02-04 15:02:45,559 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 15:02:45,560 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 15:02:45,560 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 15:02:45,561 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 15:02:45,565 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 15:02:45,566 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,568 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@131cb6fc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45, skipping insertion in model container [2018-02-04 15:02:45,568 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,577 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 15:02:45,603 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 15:02:45,693 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 15:02:45,705 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 15:02:45,709 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45 WrapperNode [2018-02-04 15:02:45,710 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 15:02:45,710 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 15:02:45,710 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 15:02:45,710 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 15:02:45,723 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,723 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,731 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,731 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,734 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,736 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,736 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... [2018-02-04 15:02:45,737 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 15:02:45,738 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 15:02:45,738 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 15:02:45,738 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 15:02:45,738 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 15:02:45,773 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 15:02:45,773 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 15:02:45,773 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrncat [2018-02-04 15:02:45,773 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 15:02:45,773 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 15:02:45,773 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure cstrncat [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 15:02:45,774 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 15:02:45,925 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 15:02:45,925 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 03:02:45 BoogieIcfgContainer [2018-02-04 15:02:45,925 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 15:02:45,926 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 15:02:45,926 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 15:02:45,928 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 15:02:45,928 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 03:02:45" (1/3) ... [2018-02-04 15:02:45,929 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@49b9c96e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 03:02:45, skipping insertion in model container [2018-02-04 15:02:45,929 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:02:45" (2/3) ... [2018-02-04 15:02:45,929 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@49b9c96e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 03:02:45, skipping insertion in model container [2018-02-04 15:02:45,929 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 03:02:45" (3/3) ... [2018-02-04 15:02:45,930 INFO L107 eAbstractionObserver]: Analyzing ICFG openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i [2018-02-04 15:02:45,935 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-04 15:02:45,940 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 13 error locations. [2018-02-04 15:02:45,971 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 15:02:45,971 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 15:02:45,971 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-04 15:02:45,971 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-04 15:02:45,971 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 15:02:45,971 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 15:02:45,971 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 15:02:45,972 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 15:02:45,972 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 15:02:45,984 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states. [2018-02-04 15:02:45,991 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-02-04 15:02:45,992 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:45,993 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:45,993 INFO L371 AbstractCegarLoop]: === Iteration 1 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:45,997 INFO L82 PathProgramCache]: Analyzing trace with hash 2055638365, now seen corresponding path program 1 times [2018-02-04 15:02:46,044 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,087 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,148 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,149 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 15:02:46,149 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,150 INFO L182 omatonBuilderFactory]: Interpolants [57#true, 58#false, 59#(= |#valid| |old(#valid)|)] [2018-02-04 15:02:46,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,150 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 15:02:46,158 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 15:02:46,158 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 15:02:46,160 INFO L87 Difference]: Start difference. First operand 54 states. Second operand 3 states. [2018-02-04 15:02:46,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:46,210 INFO L93 Difference]: Finished difference Result 55 states and 62 transitions. [2018-02-04 15:02:46,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 15:02:46,268 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-02-04 15:02:46,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:46,279 INFO L225 Difference]: With dead ends: 55 [2018-02-04 15:02:46,279 INFO L226 Difference]: Without dead ends: 51 [2018-02-04 15:02:46,281 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 15:02:46,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-02-04 15:02:46,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-02-04 15:02:46,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-04 15:02:46,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 57 transitions. [2018-02-04 15:02:46,305 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 57 transitions. Word has length 11 [2018-02-04 15:02:46,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:46,305 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 57 transitions. [2018-02-04 15:02:46,305 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 15:02:46,306 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 57 transitions. [2018-02-04 15:02:46,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-04 15:02:46,306 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:46,306 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:46,306 INFO L371 AbstractCegarLoop]: === Iteration 2 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:46,307 INFO L82 PathProgramCache]: Analyzing trace with hash -1872133330, now seen corresponding path program 1 times [2018-02-04 15:02:46,307 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,318 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,354 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,354 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:02:46,354 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,355 INFO L182 omatonBuilderFactory]: Interpolants [166#true, 167#false, 168#(<= main_~length1~0 1), 169#(<= main_~length1~0 main_~length2~0), 170#(<= (+ main_~length1~0 1) (+ main_~n~0 main_~length2~0))] [2018-02-04 15:02:46,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,356 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 15:02:46,356 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 15:02:46,356 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:02:46,356 INFO L87 Difference]: Start difference. First operand 51 states and 57 transitions. Second operand 5 states. [2018-02-04 15:02:46,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:46,395 INFO L93 Difference]: Finished difference Result 54 states and 61 transitions. [2018-02-04 15:02:46,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 15:02:46,396 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 15 [2018-02-04 15:02:46,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:46,396 INFO L225 Difference]: With dead ends: 54 [2018-02-04 15:02:46,397 INFO L226 Difference]: Without dead ends: 51 [2018-02-04 15:02:46,398 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-02-04 15:02:46,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-02-04 15:02:46,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-02-04 15:02:46,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-04 15:02:46,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 56 transitions. [2018-02-04 15:02:46,402 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 56 transitions. Word has length 15 [2018-02-04 15:02:46,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:46,403 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 56 transitions. [2018-02-04 15:02:46,403 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 15:02:46,403 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 56 transitions. [2018-02-04 15:02:46,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-04 15:02:46,403 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:46,403 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:46,403 INFO L371 AbstractCegarLoop]: === Iteration 3 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:46,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1192074960, now seen corresponding path program 1 times [2018-02-04 15:02:46,404 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,420 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,462 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,462 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-04 15:02:46,463 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,463 INFO L182 omatonBuilderFactory]: Interpolants [280#true, 281#false, 282#(= 1 (select |#valid| |main_#t~malloc11.base|)), 283#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-02-04 15:02:46,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,463 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 15:02:46,464 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 15:02:46,464 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 15:02:46,464 INFO L87 Difference]: Start difference. First operand 51 states and 56 transitions. Second operand 4 states. [2018-02-04 15:02:46,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:46,508 INFO L93 Difference]: Finished difference Result 50 states and 55 transitions. [2018-02-04 15:02:46,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 15:02:46,509 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-02-04 15:02:46,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:46,510 INFO L225 Difference]: With dead ends: 50 [2018-02-04 15:02:46,510 INFO L226 Difference]: Without dead ends: 50 [2018-02-04 15:02:46,510 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:02:46,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-02-04 15:02:46,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2018-02-04 15:02:46,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-02-04 15:02:46,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 55 transitions. [2018-02-04 15:02:46,514 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 55 transitions. Word has length 15 [2018-02-04 15:02:46,514 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:46,515 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 55 transitions. [2018-02-04 15:02:46,515 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 15:02:46,515 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 55 transitions. [2018-02-04 15:02:46,515 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-04 15:02:46,515 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:46,515 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:46,516 INFO L371 AbstractCegarLoop]: === Iteration 4 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:46,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1192074959, now seen corresponding path program 1 times [2018-02-04 15:02:46,516 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,528 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,619 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,619 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 15:02:46,619 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,620 INFO L182 omatonBuilderFactory]: Interpolants [386#true, 387#false, 388#(<= 1 main_~length2~0), 389#(and (<= 1 main_~length2~0) (<= 1 main_~n~0)), 390#(and (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0)), 391#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 1) main_~length1~0)), 392#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 393#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0))] [2018-02-04 15:02:46,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,620 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 15:02:46,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 15:02:46,620 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:02:46,620 INFO L87 Difference]: Start difference. First operand 50 states and 55 transitions. Second operand 8 states. [2018-02-04 15:02:46,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:46,722 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-02-04 15:02:46,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 15:02:46,722 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 15 [2018-02-04 15:02:46,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:46,723 INFO L225 Difference]: With dead ends: 49 [2018-02-04 15:02:46,723 INFO L226 Difference]: Without dead ends: 49 [2018-02-04 15:02:46,724 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=84, Unknown=0, NotChecked=0, Total=132 [2018-02-04 15:02:46,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-02-04 15:02:46,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-02-04 15:02:46,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-02-04 15:02:46,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 54 transitions. [2018-02-04 15:02:46,727 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 54 transitions. Word has length 15 [2018-02-04 15:02:46,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:46,728 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 54 transitions. [2018-02-04 15:02:46,728 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 15:02:46,728 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 54 transitions. [2018-02-04 15:02:46,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-04 15:02:46,728 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:46,729 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:46,729 INFO L371 AbstractCegarLoop]: === Iteration 5 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:46,729 INFO L82 PathProgramCache]: Analyzing trace with hash 1700381909, now seen corresponding path program 1 times [2018-02-04 15:02:46,730 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,739 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,762 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,762 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-04 15:02:46,762 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,763 INFO L182 omatonBuilderFactory]: Interpolants [500#true, 501#false, 502#(= 1 (select |#valid| |main_#t~malloc12.base|)), 503#(= 1 (select |#valid| main_~nondetString2~0.base))] [2018-02-04 15:02:46,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,763 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 15:02:46,763 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 15:02:46,763 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 15:02:46,763 INFO L87 Difference]: Start difference. First operand 49 states and 54 transitions. Second operand 4 states. [2018-02-04 15:02:46,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:46,803 INFO L93 Difference]: Finished difference Result 48 states and 53 transitions. [2018-02-04 15:02:46,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 15:02:46,804 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-02-04 15:02:46,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:46,805 INFO L225 Difference]: With dead ends: 48 [2018-02-04 15:02:46,805 INFO L226 Difference]: Without dead ends: 48 [2018-02-04 15:02:46,805 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:02:46,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-02-04 15:02:46,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-02-04 15:02:46,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-02-04 15:02:46,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 53 transitions. [2018-02-04 15:02:46,808 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 53 transitions. Word has length 16 [2018-02-04 15:02:46,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:46,809 INFO L432 AbstractCegarLoop]: Abstraction has 48 states and 53 transitions. [2018-02-04 15:02:46,809 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 15:02:46,809 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 53 transitions. [2018-02-04 15:02:46,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-04 15:02:46,809 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:46,809 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:46,809 INFO L371 AbstractCegarLoop]: === Iteration 6 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:46,810 INFO L82 PathProgramCache]: Analyzing trace with hash 1700381910, now seen corresponding path program 1 times [2018-02-04 15:02:46,810 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,819 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,867 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,868 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 15:02:46,868 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,868 INFO L182 omatonBuilderFactory]: Interpolants [602#true, 603#false, 604#(<= 1 main_~length2~0), 605#(and (= 0 |main_#t~malloc12.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 606#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))] [2018-02-04 15:02:46,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,869 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 15:02:46,869 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 15:02:46,869 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:02:46,869 INFO L87 Difference]: Start difference. First operand 48 states and 53 transitions. Second operand 5 states. [2018-02-04 15:02:46,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:46,893 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-02-04 15:02:46,894 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 15:02:46,894 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 16 [2018-02-04 15:02:46,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:46,894 INFO L225 Difference]: With dead ends: 47 [2018-02-04 15:02:46,894 INFO L226 Difference]: Without dead ends: 47 [2018-02-04 15:02:46,895 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=16, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:02:46,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-04 15:02:46,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-02-04 15:02:46,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-02-04 15:02:46,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 52 transitions. [2018-02-04 15:02:46,896 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 52 transitions. Word has length 16 [2018-02-04 15:02:46,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:46,897 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 52 transitions. [2018-02-04 15:02:46,897 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 15:02:46,897 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 52 transitions. [2018-02-04 15:02:46,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 15:02:46,897 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:46,897 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:46,897 INFO L371 AbstractCegarLoop]: === Iteration 7 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:46,897 INFO L82 PathProgramCache]: Analyzing trace with hash -275307336, now seen corresponding path program 1 times [2018-02-04 15:02:46,898 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:46,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:46,905 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:46,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,942 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:46,942 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:02:46,943 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:46,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,943 INFO L182 omatonBuilderFactory]: Interpolants [704#false, 705#(= 1 (select |#valid| main_~nondetString1~0.base)), 706#(= 1 (select |#valid| |cstrncat_#in~dst.base|)), 707#(= 1 (select |#valid| cstrncat_~dst.base)), 708#(= 1 (select |#valid| cstrncat_~d~0.base)), 703#true] [2018-02-04 15:02:46,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:46,943 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:02:46,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:02:46,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:02:46,944 INFO L87 Difference]: Start difference. First operand 47 states and 52 transitions. Second operand 6 states. [2018-02-04 15:02:47,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:47,066 INFO L93 Difference]: Finished difference Result 47 states and 52 transitions. [2018-02-04 15:02:47,066 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 15:02:47,066 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-04 15:02:47,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:47,068 INFO L225 Difference]: With dead ends: 47 [2018-02-04 15:02:47,068 INFO L226 Difference]: Without dead ends: 47 [2018-02-04 15:02:47,068 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:02:47,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-04 15:02:47,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 44. [2018-02-04 15:02:47,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-04 15:02:47,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 49 transitions. [2018-02-04 15:02:47,070 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 49 transitions. Word has length 21 [2018-02-04 15:02:47,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:47,070 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 49 transitions. [2018-02-04 15:02:47,070 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:02:47,071 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 49 transitions. [2018-02-04 15:02:47,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 15:02:47,071 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:47,071 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:47,071 INFO L371 AbstractCegarLoop]: === Iteration 8 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:47,071 INFO L82 PathProgramCache]: Analyzing trace with hash -275307335, now seen corresponding path program 1 times [2018-02-04 15:02:47,072 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:47,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:47,079 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:47,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,166 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:47,166 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 15:02:47,166 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:47,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,166 INFO L182 omatonBuilderFactory]: Interpolants [804#true, 805#false, 806#(<= 1 main_~length2~0), 807#(<= (+ main_~n~0 1) main_~length1~0), 808#(and (= 0 |main_#t~malloc11.offset|) (<= (+ main_~n~0 1) main_~length1~0)), 809#(and (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 1) main_~length1~0)), 810#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 811#(and (<= 1 (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 812#(and (= 0 cstrncat_~dst.offset) (<= 1 (select |#length| cstrncat_~dst.base))), 813#(and (<= 1 (select |#length| cstrncat_~d~0.base)) (= cstrncat_~d~0.offset 0))] [2018-02-04 15:02:47,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,166 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 15:02:47,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 15:02:47,167 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-02-04 15:02:47,167 INFO L87 Difference]: Start difference. First operand 44 states and 49 transitions. Second operand 10 states. [2018-02-04 15:02:47,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:47,299 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2018-02-04 15:02:47,299 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 15:02:47,299 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 21 [2018-02-04 15:02:47,299 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:47,300 INFO L225 Difference]: With dead ends: 57 [2018-02-04 15:02:47,300 INFO L226 Difference]: Without dead ends: 57 [2018-02-04 15:02:47,300 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=65, Invalid=207, Unknown=0, NotChecked=0, Total=272 [2018-02-04 15:02:47,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-02-04 15:02:47,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 52. [2018-02-04 15:02:47,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-02-04 15:02:47,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 61 transitions. [2018-02-04 15:02:47,303 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 61 transitions. Word has length 21 [2018-02-04 15:02:47,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:47,304 INFO L432 AbstractCegarLoop]: Abstraction has 52 states and 61 transitions. [2018-02-04 15:02:47,304 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 15:02:47,304 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 61 transitions. [2018-02-04 15:02:47,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 15:02:47,304 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:47,304 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:47,305 INFO L371 AbstractCegarLoop]: === Iteration 9 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:47,305 INFO L82 PathProgramCache]: Analyzing trace with hash 1706718631, now seen corresponding path program 1 times [2018-02-04 15:02:47,305 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:47,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:47,318 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:47,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,368 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:47,368 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 15:02:47,369 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:47,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,369 INFO L182 omatonBuilderFactory]: Interpolants [937#true, 938#false, 939#(= 1 (select |#valid| main_~nondetString2~0.base)), 940#(= 1 (select |#valid| |cstrncat_#in~src.base|)), 941#(= 1 (select |#valid| cstrncat_~src.base)), 942#(= 1 (select |#valid| cstrncat_~s~0.base)), 943#(= 1 (select |#valid| |cstrncat_#t~post3.base|))] [2018-02-04 15:02:47,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,369 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 15:02:47,369 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 15:02:47,370 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 15:02:47,370 INFO L87 Difference]: Start difference. First operand 52 states and 61 transitions. Second operand 7 states. [2018-02-04 15:02:47,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:47,439 INFO L93 Difference]: Finished difference Result 54 states and 62 transitions. [2018-02-04 15:02:47,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 15:02:47,439 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 24 [2018-02-04 15:02:47,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:47,440 INFO L225 Difference]: With dead ends: 54 [2018-02-04 15:02:47,440 INFO L226 Difference]: Without dead ends: 54 [2018-02-04 15:02:47,440 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=61, Unknown=0, NotChecked=0, Total=90 [2018-02-04 15:02:47,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-02-04 15:02:47,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 51. [2018-02-04 15:02:47,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-04 15:02:47,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 59 transitions. [2018-02-04 15:02:47,443 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 59 transitions. Word has length 24 [2018-02-04 15:02:47,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:47,443 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 59 transitions. [2018-02-04 15:02:47,443 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 15:02:47,443 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 59 transitions. [2018-02-04 15:02:47,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 15:02:47,444 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:47,444 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:47,444 INFO L371 AbstractCegarLoop]: === Iteration 10 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:47,444 INFO L82 PathProgramCache]: Analyzing trace with hash 1706718632, now seen corresponding path program 1 times [2018-02-04 15:02:47,445 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:47,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:47,454 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:47,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,553 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:47,554 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 15:02:47,554 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:47,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,554 INFO L182 omatonBuilderFactory]: Interpolants [1056#false, 1057#(<= 1 main_~length2~0), 1058#(and (= 0 |main_#t~malloc12.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 1059#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 1060#(and (= 0 main_~nondetString2~0.offset) (<= 1 (select |#length| main_~nondetString2~0.base))), 1061#(and (<= 1 (select |#length| |cstrncat_#in~src.base|)) (= 0 |cstrncat_#in~src.offset|)), 1062#(and (= 0 cstrncat_~src.offset) (<= 1 (select |#length| cstrncat_~src.base))), 1063#(and (= 0 cstrncat_~s~0.offset) (<= 1 (select |#length| cstrncat_~s~0.base))), 1064#(and (<= 1 (select |#length| |cstrncat_#t~post3.base|)) (= |cstrncat_#t~post3.offset| 0)), 1055#true] [2018-02-04 15:02:47,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,555 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 15:02:47,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 15:02:47,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-04 15:02:47,555 INFO L87 Difference]: Start difference. First operand 51 states and 59 transitions. Second operand 10 states. [2018-02-04 15:02:47,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:47,681 INFO L93 Difference]: Finished difference Result 56 states and 64 transitions. [2018-02-04 15:02:47,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 15:02:47,682 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 24 [2018-02-04 15:02:47,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:47,682 INFO L225 Difference]: With dead ends: 56 [2018-02-04 15:02:47,682 INFO L226 Difference]: Without dead ends: 56 [2018-02-04 15:02:47,683 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=140, Unknown=0, NotChecked=0, Total=182 [2018-02-04 15:02:47,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states. [2018-02-04 15:02:47,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 53. [2018-02-04 15:02:47,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-02-04 15:02:47,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 60 transitions. [2018-02-04 15:02:47,686 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 60 transitions. Word has length 24 [2018-02-04 15:02:47,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:47,686 INFO L432 AbstractCegarLoop]: Abstraction has 53 states and 60 transitions. [2018-02-04 15:02:47,686 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 15:02:47,687 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 60 transitions. [2018-02-04 15:02:47,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 15:02:47,687 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:47,687 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:47,687 INFO L371 AbstractCegarLoop]: === Iteration 11 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:47,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1706720075, now seen corresponding path program 1 times [2018-02-04 15:02:47,688 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:47,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:47,698 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:47,808 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,808 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:47,808 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 15:02:47,808 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:47,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,808 INFO L182 omatonBuilderFactory]: Interpolants [1184#(<= 1 main_~length2~0), 1185#(<= 2 (+ main_~n~0 main_~length2~0)), 1186#(<= 2 main_~length1~0), 1187#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 2 main_~length1~0)), 1188#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 2 main_~length1~0)), 1189#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 2 main_~length1~0)), 1190#(and (= 0 main_~nondetString1~0.offset) (<= 2 (select |#length| main_~nondetString1~0.base))), 1191#(and (<= 2 (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 1192#(and (= 0 cstrncat_~dst.offset) (<= 2 (select |#length| cstrncat_~dst.base))), 1193#(and (<= 2 (select |#length| cstrncat_~d~0.base)) (= cstrncat_~d~0.offset 0)), 1194#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 1182#true, 1183#false] [2018-02-04 15:02:47,809 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:47,809 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 15:02:47,809 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 15:02:47,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 15:02:47,809 INFO L87 Difference]: Start difference. First operand 53 states and 60 transitions. Second operand 13 states. [2018-02-04 15:02:47,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:47,989 INFO L93 Difference]: Finished difference Result 72 states and 82 transitions. [2018-02-04 15:02:47,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 15:02:47,989 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 24 [2018-02-04 15:02:47,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:47,990 INFO L225 Difference]: With dead ends: 72 [2018-02-04 15:02:47,990 INFO L226 Difference]: Without dead ends: 72 [2018-02-04 15:02:47,990 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=85, Invalid=335, Unknown=0, NotChecked=0, Total=420 [2018-02-04 15:02:47,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-02-04 15:02:47,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 64. [2018-02-04 15:02:47,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-02-04 15:02:47,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 75 transitions. [2018-02-04 15:02:47,993 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 75 transitions. Word has length 24 [2018-02-04 15:02:47,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:47,993 INFO L432 AbstractCegarLoop]: Abstraction has 64 states and 75 transitions. [2018-02-04 15:02:47,993 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 15:02:47,993 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 75 transitions. [2018-02-04 15:02:47,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 15:02:47,993 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:47,993 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:47,993 INFO L371 AbstractCegarLoop]: === Iteration 12 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:47,994 INFO L82 PathProgramCache]: Analyzing trace with hash 1074905977, now seen corresponding path program 2 times [2018-02-04 15:02:47,994 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:48,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:48,004 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:48,204 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,205 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:48,205 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 15:02:48,205 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:48,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,205 INFO L182 omatonBuilderFactory]: Interpolants [1347#true, 1348#false, 1349#(<= 1 main_~n~0), 1350#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 1351#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1352#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1353#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (= main_~nondetString1~0.offset 0)), 1354#(and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (<= 3 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 1355#(and (or (<= 3 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 1356#(and (or (<= 3 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))) (= 0 cstrncat_~dst.offset)), 1357#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= 3 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 1358#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= 3 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 1359#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 1360#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:02:48,205 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,205 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 15:02:48,206 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 15:02:48,206 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=155, Unknown=0, NotChecked=0, Total=182 [2018-02-04 15:02:48,206 INFO L87 Difference]: Start difference. First operand 64 states and 75 transitions. Second operand 14 states. [2018-02-04 15:02:48,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:48,644 INFO L93 Difference]: Finished difference Result 105 states and 120 transitions. [2018-02-04 15:02:48,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 15:02:48,644 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 27 [2018-02-04 15:02:48,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:48,645 INFO L225 Difference]: With dead ends: 105 [2018-02-04 15:02:48,645 INFO L226 Difference]: Without dead ends: 105 [2018-02-04 15:02:48,645 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=582, Unknown=0, NotChecked=0, Total=702 [2018-02-04 15:02:48,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-02-04 15:02:48,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 67. [2018-02-04 15:02:48,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-02-04 15:02:48,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 79 transitions. [2018-02-04 15:02:48,648 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 79 transitions. Word has length 27 [2018-02-04 15:02:48,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:48,648 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 79 transitions. [2018-02-04 15:02:48,648 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 15:02:48,648 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 79 transitions. [2018-02-04 15:02:48,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 15:02:48,648 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:48,648 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:48,648 INFO L371 AbstractCegarLoop]: === Iteration 13 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:48,649 INFO L82 PathProgramCache]: Analyzing trace with hash 94248296, now seen corresponding path program 1 times [2018-02-04 15:02:48,649 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:48,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:48,656 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:48,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,699 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:48,699 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:02:48,699 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:48,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,700 INFO L182 omatonBuilderFactory]: Interpolants [1559#true, 1560#false, 1561#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 1562#(and (or (<= cstrncat_~n |cstrncat_#in~n|) (<= (div cstrncat_~n 4294967296) 0)) (or (< 0 (div cstrncat_~n 4294967296)) (<= |cstrncat_#in~n| cstrncat_~n))), 1563#(or (<= 4294967296 |cstrncat_#in~n|) (<= |cstrncat_#in~n| 0))] [2018-02-04 15:02:48,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,700 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 15:02:48,700 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 15:02:48,701 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:02:48,701 INFO L87 Difference]: Start difference. First operand 67 states and 79 transitions. Second operand 5 states. [2018-02-04 15:02:48,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:48,729 INFO L93 Difference]: Finished difference Result 97 states and 112 transitions. [2018-02-04 15:02:48,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 15:02:48,730 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 28 [2018-02-04 15:02:48,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:48,732 INFO L225 Difference]: With dead ends: 97 [2018-02-04 15:02:48,732 INFO L226 Difference]: Without dead ends: 97 [2018-02-04 15:02:48,732 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:02:48,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-02-04 15:02:48,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 78. [2018-02-04 15:02:48,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-02-04 15:02:48,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 91 transitions. [2018-02-04 15:02:48,740 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 91 transitions. Word has length 28 [2018-02-04 15:02:48,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:48,740 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 91 transitions. [2018-02-04 15:02:48,741 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 15:02:48,741 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 91 transitions. [2018-02-04 15:02:48,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 15:02:48,741 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:48,741 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:48,742 INFO L371 AbstractCegarLoop]: === Iteration 14 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:48,742 INFO L82 PathProgramCache]: Analyzing trace with hash -723400154, now seen corresponding path program 1 times [2018-02-04 15:02:48,742 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:48,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:48,753 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:48,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,805 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:48,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:02:48,805 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:48,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,806 INFO L182 omatonBuilderFactory]: Interpolants [1744#(and (= |old(#valid)| (store |#valid| |main_#t~malloc11.base| 0)) (= (select |#valid| |main_#t~malloc11.base|) 1)), 1745#(and (not (= |main_#t~malloc11.base| |main_#t~malloc12.base|)) (= (store (store |#valid| |main_#t~malloc11.base| (select (store |#valid| |main_#t~malloc11.base| 0) |main_#t~malloc11.base|)) |main_#t~malloc12.base| 0) |old(#valid)|)), 1746#(= |old(#valid)| (store |#valid| |main_#t~malloc12.base| (select (store |#valid| |main_#t~malloc12.base| 0) |main_#t~malloc12.base|))), 1741#true, 1742#false, 1743#(= |#valid| |old(#valid)|)] [2018-02-04 15:02:48,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:48,806 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:02:48,806 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:02:48,806 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:02:48,806 INFO L87 Difference]: Start difference. First operand 78 states and 91 transitions. Second operand 6 states. [2018-02-04 15:02:48,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:48,911 INFO L93 Difference]: Finished difference Result 77 states and 90 transitions. [2018-02-04 15:02:48,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 15:02:48,911 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-04 15:02:48,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:48,911 INFO L225 Difference]: With dead ends: 77 [2018-02-04 15:02:48,912 INFO L226 Difference]: Without dead ends: 64 [2018-02-04 15:02:48,912 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:02:48,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-02-04 15:02:48,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 56. [2018-02-04 15:02:48,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-02-04 15:02:48,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 64 transitions. [2018-02-04 15:02:48,914 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 64 transitions. Word has length 28 [2018-02-04 15:02:48,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:48,914 INFO L432 AbstractCegarLoop]: Abstraction has 56 states and 64 transitions. [2018-02-04 15:02:48,914 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:02:48,914 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 64 transitions. [2018-02-04 15:02:48,914 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-04 15:02:48,914 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:48,914 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:48,915 INFO L371 AbstractCegarLoop]: === Iteration 15 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:48,915 INFO L82 PathProgramCache]: Analyzing trace with hash -1208652779, now seen corresponding path program 1 times [2018-02-04 15:02:48,915 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:48,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:48,926 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:49,034 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:49,034 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:02:49,034 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 15:02:49,034 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:49,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:49,035 INFO L182 omatonBuilderFactory]: Interpolants [1888#(and (or (<= cstrncat_~n (* 4294967296 (div cstrncat_~n 4294967296))) (<= cstrncat_~n 1)) (< 0 (+ (div cstrncat_~n 4294967296) 1))), 1889#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 1)), 1890#(<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))), 1884#true, 1885#false, 1886#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 1887#(and (<= |cstrncat_#in~n| 1) (<= 1 |cstrncat_#in~n|))] [2018-02-04 15:02:49,035 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:49,035 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 15:02:49,035 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 15:02:49,035 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-04 15:02:49,036 INFO L87 Difference]: Start difference. First operand 56 states and 64 transitions. Second operand 7 states. [2018-02-04 15:02:49,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:49,104 INFO L93 Difference]: Finished difference Result 100 states and 110 transitions. [2018-02-04 15:02:49,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 15:02:49,105 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 30 [2018-02-04 15:02:49,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:49,105 INFO L225 Difference]: With dead ends: 100 [2018-02-04 15:02:49,105 INFO L226 Difference]: Without dead ends: 94 [2018-02-04 15:02:49,106 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2018-02-04 15:02:49,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-02-04 15:02:49,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 88. [2018-02-04 15:02:49,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-02-04 15:02:49,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 101 transitions. [2018-02-04 15:02:49,109 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 101 transitions. Word has length 30 [2018-02-04 15:02:49,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:49,109 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 101 transitions. [2018-02-04 15:02:49,109 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 15:02:49,109 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 101 transitions. [2018-02-04 15:02:49,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-04 15:02:49,110 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:49,110 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:49,110 INFO L371 AbstractCegarLoop]: === Iteration 16 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:49,110 INFO L82 PathProgramCache]: Analyzing trace with hash -752196469, now seen corresponding path program 3 times [2018-02-04 15:02:49,111 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:49,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:49,122 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:49,408 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:49,408 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:49,408 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 15:02:49,408 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:49,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:49,408 INFO L182 omatonBuilderFactory]: Interpolants [2085#true, 2086#false, 2087#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 2088#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= main_~n~0 1)), 2089#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 2090#(and (= 0 main_~nondetString1~0.offset) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base |main_#t~malloc12.base|))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 2091#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (or (and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1))) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= main_~n~0 1))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 2092#(and (= 0 main_~nondetString1~0.offset) (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 2))), 2093#(and (or (<= (select |#length| |cstrncat_#in~dst.base|) 2) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 |cstrncat_#in~dst.offset|)), 2094#(and (or (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (<= (select |#length| cstrncat_~dst.base) 2)) (= 0 cstrncat_~dst.offset)), 2095#(and (or (<= (select |#length| cstrncat_~d~0.base) 2) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (<= 4 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 2096#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 2097#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1))), 2098#(or (<= (select |#length| cstrncat_~d~0.base) cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 2099#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 2100#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:02:49,409 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:49,409 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 15:02:49,409 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 15:02:49,409 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=208, Unknown=0, NotChecked=0, Total=240 [2018-02-04 15:02:49,409 INFO L87 Difference]: Start difference. First operand 88 states and 101 transitions. Second operand 16 states. [2018-02-04 15:02:50,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:50,028 INFO L93 Difference]: Finished difference Result 100 states and 112 transitions. [2018-02-04 15:02:50,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 15:02:50,028 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 30 [2018-02-04 15:02:50,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:50,029 INFO L225 Difference]: With dead ends: 100 [2018-02-04 15:02:50,029 INFO L226 Difference]: Without dead ends: 93 [2018-02-04 15:02:50,030 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=108, Invalid=594, Unknown=0, NotChecked=0, Total=702 [2018-02-04 15:02:50,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-02-04 15:02:50,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 91. [2018-02-04 15:02:50,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-02-04 15:02:50,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 104 transitions. [2018-02-04 15:02:50,032 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 104 transitions. Word has length 30 [2018-02-04 15:02:50,032 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:50,032 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 104 transitions. [2018-02-04 15:02:50,032 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 15:02:50,032 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 104 transitions. [2018-02-04 15:02:50,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-04 15:02:50,034 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:50,034 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:50,034 INFO L371 AbstractCegarLoop]: === Iteration 17 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:50,034 INFO L82 PathProgramCache]: Analyzing trace with hash -989798061, now seen corresponding path program 1 times [2018-02-04 15:02:50,034 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:50,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:50,042 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:50,177 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,178 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:50,178 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 15:02:50,178 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:50,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,179 INFO L182 omatonBuilderFactory]: Interpolants [2314#true, 2315#false, 2316#(<= 1 main_~length2~0), 2317#(and (= 0 |main_#t~malloc12.offset|) (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 2318#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length2~0) 1) (and (<= 1 main_~length2~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))))), 2319#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 2 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 2320#(and (or (= 0 (select (select |#memory_int| |cstrncat_#in~src.base|) |cstrncat_#in~src.offset|)) (<= 2 (select |#length| |cstrncat_#in~src.base|))) (= 0 |cstrncat_#in~src.offset|)), 2321#(and (or (= 0 (select (select |#memory_int| cstrncat_~src.base) cstrncat_~src.offset)) (<= 2 (select |#length| cstrncat_~src.base))) (= 0 cstrncat_~src.offset)), 2322#(and (= 0 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~s~0.base) cstrncat_~s~0.offset)) (<= 2 (select |#length| cstrncat_~s~0.base)))), 2323#(and (or (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|)))) (= |cstrncat_#t~post3.offset| 0)), 2324#(or (= 0 |cstrncat_#t~mem5|) (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 2325#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 2326#(and (<= 1 |cstrncat_#t~post3.offset|) (<= (+ |cstrncat_#t~post3.offset| 1) (select |#length| |cstrncat_#t~post3.base|)))] [2018-02-04 15:02:50,179 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,179 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 15:02:50,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 15:02:50,179 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2018-02-04 15:02:50,180 INFO L87 Difference]: Start difference. First operand 91 states and 104 transitions. Second operand 13 states. [2018-02-04 15:02:50,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:50,392 INFO L93 Difference]: Finished difference Result 105 states and 119 transitions. [2018-02-04 15:02:50,481 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 15:02:50,481 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 30 [2018-02-04 15:02:50,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:50,482 INFO L225 Difference]: With dead ends: 105 [2018-02-04 15:02:50,482 INFO L226 Difference]: Without dead ends: 105 [2018-02-04 15:02:50,482 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=67, Invalid=313, Unknown=0, NotChecked=0, Total=380 [2018-02-04 15:02:50,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-02-04 15:02:50,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 99. [2018-02-04 15:02:50,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-02-04 15:02:50,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 114 transitions. [2018-02-04 15:02:50,484 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 114 transitions. Word has length 30 [2018-02-04 15:02:50,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:50,485 INFO L432 AbstractCegarLoop]: Abstraction has 99 states and 114 transitions. [2018-02-04 15:02:50,485 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 15:02:50,485 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 114 transitions. [2018-02-04 15:02:50,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-02-04 15:02:50,485 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:50,485 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:50,485 INFO L371 AbstractCegarLoop]: === Iteration 18 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:50,485 INFO L82 PathProgramCache]: Analyzing trace with hash -533341751, now seen corresponding path program 1 times [2018-02-04 15:02:50,486 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:50,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:50,498 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:50,811 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,811 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:50,811 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-04 15:02:50,811 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:50,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,811 INFO L182 omatonBuilderFactory]: Interpolants [2560#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 2561#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 2545#true, 2546#false, 2547#(<= 1 main_~n~0), 2548#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 2549#(and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 2550#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 2551#(and (or (<= 1 main_~n~0) (<= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2552#(and (or (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2553#(and (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (<= 4 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 2554#(and (= 0 cstrncat_~dst.offset) (or (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 2555#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (<= 4 (select |#length| cstrncat_~d~0.base))) (= cstrncat_~d~0.offset 0)), 2556#(and (= cstrncat_~d~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (<= 4 (select |#length| cstrncat_~d~0.base)))), 2557#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 2558#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 2559#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))] [2018-02-04 15:02:50,812 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,812 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 15:02:50,812 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 15:02:50,812 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-02-04 15:02:50,812 INFO L87 Difference]: Start difference. First operand 99 states and 114 transitions. Second operand 17 states. [2018-02-04 15:02:51,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:51,274 INFO L93 Difference]: Finished difference Result 117 states and 134 transitions. [2018-02-04 15:02:51,274 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 15:02:51,274 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 30 [2018-02-04 15:02:51,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:51,275 INFO L225 Difference]: With dead ends: 117 [2018-02-04 15:02:51,275 INFO L226 Difference]: Without dead ends: 116 [2018-02-04 15:02:51,275 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=119, Invalid=693, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:02:51,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2018-02-04 15:02:51,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 102. [2018-02-04 15:02:51,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-02-04 15:02:51,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 118 transitions. [2018-02-04 15:02:51,277 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 118 transitions. Word has length 30 [2018-02-04 15:02:51,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:51,277 INFO L432 AbstractCegarLoop]: Abstraction has 102 states and 118 transitions. [2018-02-04 15:02:51,277 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 15:02:51,278 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 118 transitions. [2018-02-04 15:02:51,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-04 15:02:51,278 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:51,278 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:51,278 INFO L371 AbstractCegarLoop]: === Iteration 19 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:51,278 INFO L82 PathProgramCache]: Analyzing trace with hash -1840623047, now seen corresponding path program 4 times [2018-02-04 15:02:51,279 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:51,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:51,285 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:51,490 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:51,490 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:51,490 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-04 15:02:51,490 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:51,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:51,490 INFO L182 omatonBuilderFactory]: Interpolants [2816#(and (<= 1 cstrncat_~d~0.offset) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))), 2817#(and (or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1))) (<= 2 cstrncat_~d~0.offset)), 2818#(and (or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset 1))) (<= 2 cstrncat_~d~0.offset)), 2819#(and (<= 3 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~d~0.base) cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)))), 2820#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 2821#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 2805#true, 2806#false, 2807#(and (<= 1 main_~n~0) (<= main_~n~0 1)), 2808#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= main_~n~0 1)), 2809#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2810#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2811#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~n~0 1) (= main_~nondetString1~0.offset 0)), 2812#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ main_~n~0 (- 1))) (+ main_~nondetString1~0.offset (+ (- main_~n~0) (- 1)))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2813#(and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (= 0 |cstrncat_#in~dst.offset|)), 2814#(and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)))) (= 0 cstrncat_~dst.offset)), 2815#(and (= cstrncat_~d~0.offset 0) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))] [2018-02-04 15:02:51,490 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:51,491 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 15:02:51,491 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 15:02:51,491 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-02-04 15:02:51,491 INFO L87 Difference]: Start difference. First operand 102 states and 118 transitions. Second operand 17 states. [2018-02-04 15:02:51,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:51,906 INFO L93 Difference]: Finished difference Result 104 states and 116 transitions. [2018-02-04 15:02:51,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 15:02:51,906 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 33 [2018-02-04 15:02:51,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:51,906 INFO L225 Difference]: With dead ends: 104 [2018-02-04 15:02:51,906 INFO L226 Difference]: Without dead ends: 67 [2018-02-04 15:02:51,907 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 178 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=179, Invalid=813, Unknown=0, NotChecked=0, Total=992 [2018-02-04 15:02:51,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-02-04 15:02:51,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-02-04 15:02:51,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-02-04 15:02:51,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 77 transitions. [2018-02-04 15:02:51,908 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 77 transitions. Word has length 33 [2018-02-04 15:02:51,908 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:51,908 INFO L432 AbstractCegarLoop]: Abstraction has 67 states and 77 transitions. [2018-02-04 15:02:51,908 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 15:02:51,908 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 77 transitions. [2018-02-04 15:02:51,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-04 15:02:51,908 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:51,908 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:51,908 INFO L371 AbstractCegarLoop]: === Iteration 20 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:51,908 INFO L82 PathProgramCache]: Analyzing trace with hash -1700074437, now seen corresponding path program 2 times [2018-02-04 15:02:51,909 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:51,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:51,926 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:52,325 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:52,325 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:52,325 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-04 15:02:52,325 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:52,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:52,326 INFO L182 omatonBuilderFactory]: Interpolants [3040#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 3023#true, 3024#false, 3025#(<= 1 main_~n~0), 3026#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 3027#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3028#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3029#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 3030#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))))) (= main_~nondetString1~0.offset 0)), 3031#(and (or (and (or (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 3032#(and (= 0 cstrncat_~dst.offset) (or (and (<= 4 (select |#length| cstrncat_~dst.base)) (or (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 3033#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (or (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))) (= cstrncat_~d~0.offset 0)), 3034#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (or (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))) (= cstrncat_~d~0.offset 0)), 3035#(and (<= 1 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))))), 3036#(and (<= 1 cstrncat_~d~0.offset) (or (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 3037#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 2 cstrncat_~d~0.offset))), 3038#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 2 cstrncat_~d~0.offset))), 3039#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:02:52,326 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:52,326 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 15:02:52,326 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 15:02:52,326 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=266, Unknown=0, NotChecked=0, Total=306 [2018-02-04 15:02:52,327 INFO L87 Difference]: Start difference. First operand 67 states and 77 transitions. Second operand 18 states. [2018-02-04 15:02:52,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:52,830 INFO L93 Difference]: Finished difference Result 100 states and 114 transitions. [2018-02-04 15:02:52,830 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 15:02:52,830 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 33 [2018-02-04 15:02:52,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:52,830 INFO L225 Difference]: With dead ends: 100 [2018-02-04 15:02:52,830 INFO L226 Difference]: Without dead ends: 99 [2018-02-04 15:02:52,830 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 190 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=130, Invalid=800, Unknown=0, NotChecked=0, Total=930 [2018-02-04 15:02:52,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-02-04 15:02:52,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 70. [2018-02-04 15:02:52,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 70 states. [2018-02-04 15:02:52,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 81 transitions. [2018-02-04 15:02:52,832 INFO L78 Accepts]: Start accepts. Automaton has 70 states and 81 transitions. Word has length 33 [2018-02-04 15:02:52,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:52,832 INFO L432 AbstractCegarLoop]: Abstraction has 70 states and 81 transitions. [2018-02-04 15:02:52,832 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 15:02:52,832 INFO L276 IsEmpty]: Start isEmpty. Operand 70 states and 81 transitions. [2018-02-04 15:02:52,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 15:02:52,833 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:52,833 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:52,833 INFO L371 AbstractCegarLoop]: === Iteration 21 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:52,833 INFO L82 PathProgramCache]: Analyzing trace with hash -608695935, now seen corresponding path program 1 times [2018-02-04 15:02:52,834 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:52,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:52,843 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:53,026 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:53,027 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:53,027 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-04 15:02:53,027 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:53,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:53,027 INFO L182 omatonBuilderFactory]: Interpolants [3237#true, 3238#false, 3239#(<= 1 main_~n~0), 3240#(<= (+ main_~length2~0 1) main_~length1~0), 3241#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|)), 3242#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| main_~nondetString1~0.base) 1)), 3243#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 3244#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 3245#(and (<= (+ main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 3246#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))), 3247#(and (= 0 |cstrncat_#in~src.offset|) (<= (+ (select |#length| |cstrncat_#in~src.base|) 1) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 3248#(and (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset) (<= (+ (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base))), 3249#(and (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (select |#length| cstrncat_~d~0.base))), 3250#(and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset| 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (= cstrncat_~d~0.offset 0) (= |cstrncat_#t~post3.offset| 0)), 3251#(and (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3252#(and (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3253#(and (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|))), 3254#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 3255#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:02:53,027 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:53,027 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 15:02:53,027 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 15:02:53,028 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=299, Unknown=0, NotChecked=0, Total=342 [2018-02-04 15:02:53,028 INFO L87 Difference]: Start difference. First operand 70 states and 81 transitions. Second operand 19 states. [2018-02-04 15:02:53,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:53,357 INFO L93 Difference]: Finished difference Result 88 states and 100 transitions. [2018-02-04 15:02:53,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 15:02:53,357 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 35 [2018-02-04 15:02:53,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:53,358 INFO L225 Difference]: With dead ends: 88 [2018-02-04 15:02:53,358 INFO L226 Difference]: Without dead ends: 87 [2018-02-04 15:02:53,358 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 141 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=132, Invalid=798, Unknown=0, NotChecked=0, Total=930 [2018-02-04 15:02:53,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-02-04 15:02:53,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 84. [2018-02-04 15:02:53,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-02-04 15:02:53,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2018-02-04 15:02:53,360 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 96 transitions. Word has length 35 [2018-02-04 15:02:53,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:53,360 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 96 transitions. [2018-02-04 15:02:53,360 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 15:02:53,360 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 96 transitions. [2018-02-04 15:02:53,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 15:02:53,361 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:53,361 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:53,361 INFO L371 AbstractCegarLoop]: === Iteration 22 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:53,361 INFO L82 PathProgramCache]: Analyzing trace with hash -1689703552, now seen corresponding path program 2 times [2018-02-04 15:02:53,362 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:53,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:53,373 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:53,632 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:53,632 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:53,632 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-04 15:02:53,632 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:53,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:53,633 INFO L182 omatonBuilderFactory]: Interpolants [3456#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 3457#(and (= 0 main_~nondetString2~0.offset) (or (not (= (+ main_~nondetString2~0.offset main_~length2~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 3458#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)) 1) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 3459#(and (= 0 |cstrncat_#in~src.offset|) (or (and (not (= |cstrncat_#in~dst.base| |cstrncat_#in~src.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~src.base|) 1))) (<= 3 (select |#length| |cstrncat_#in~src.base|)) (<= (select |#length| |cstrncat_#in~src.base|) 1))), 3460#(and (or (<= (select |#length| cstrncat_~src.base) 1) (<= 3 (select |#length| cstrncat_~src.base)) (and (not (= cstrncat_~dst.base cstrncat_~src.base)) (= 0 (select (select |#memory_int| cstrncat_~src.base) 1)))) (= 0 cstrncat_~src.offset)), 3461#(and (or (<= 3 (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) 1) (and (not (= cstrncat_~d~0.base cstrncat_~s~0.base)) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 3462#(and (or (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|)) (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) cstrncat_~s~0.offset))) (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (= |cstrncat_#t~post3.base| cstrncat_~s~0.base) (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) 1)) (<= cstrncat_~s~0.offset (+ |cstrncat_#t~post3.offset| 1)) (not (= |cstrncat_#t~post3.base| cstrncat_~d~0.base)))) (= |cstrncat_#t~post3.offset| 0)), 3463#(or (and (<= 1 cstrncat_~s~0.offset) (= 0 (select (select (store |#memory_int| cstrncat_~d~0.base (store (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset |cstrncat_#t~mem5|)) cstrncat_~s~0.base) 1)) (<= cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)))), 3464#(or (and (<= 1 cstrncat_~s~0.offset) (or (<= (+ cstrncat_~s~0.offset 2) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset))) (and (<= 1 cstrncat_~s~0.offset) (= 0 (select (select |#memory_int| cstrncat_~s~0.base) 1)) (<= cstrncat_~s~0.offset 1))), 3465#(or (and (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (= 1 |cstrncat_#t~post3.offset|)) (and (or (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (<= 2 cstrncat_~s~0.offset))), 3466#(or (= 0 |cstrncat_#t~mem5|) (and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset))), 3467#(and (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)) (<= 2 cstrncat_~s~0.offset)), 3468#(and (<= (+ |cstrncat_#t~post3.offset| 1) (select |#length| |cstrncat_#t~post3.base|)) (<= 2 |cstrncat_#t~post3.offset|)), 3452#true, 3453#false, 3454#(= (select |#valid| |main_#t~malloc11.base|) 1), 3455#(= (select |#valid| main_~nondetString1~0.base) 1)] [2018-02-04 15:02:53,633 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:53,633 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 15:02:53,633 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 15:02:53,633 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-02-04 15:02:53,633 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. Second operand 17 states. [2018-02-04 15:02:53,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:53,995 INFO L93 Difference]: Finished difference Result 101 states and 112 transitions. [2018-02-04 15:02:53,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 15:02:53,995 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 36 [2018-02-04 15:02:53,995 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:53,996 INFO L225 Difference]: With dead ends: 101 [2018-02-04 15:02:53,996 INFO L226 Difference]: Without dead ends: 101 [2018-02-04 15:02:53,996 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=92, Invalid=558, Unknown=0, NotChecked=0, Total=650 [2018-02-04 15:02:53,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-02-04 15:02:53,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 92. [2018-02-04 15:02:53,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-02-04 15:02:53,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 106 transitions. [2018-02-04 15:02:53,997 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 106 transitions. Word has length 36 [2018-02-04 15:02:53,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:53,997 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 106 transitions. [2018-02-04 15:02:53,997 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 15:02:53,998 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 106 transitions. [2018-02-04 15:02:53,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 15:02:53,998 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:53,998 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:53,998 INFO L371 AbstractCegarLoop]: === Iteration 23 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:53,998 INFO L82 PathProgramCache]: Analyzing trace with hash -663196535, now seen corresponding path program 3 times [2018-02-04 15:02:53,999 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:54,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:54,010 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:54,496 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:54,496 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:54,496 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-04 15:02:54,496 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:54,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:54,497 INFO L182 omatonBuilderFactory]: Interpolants [3680#true, 3681#false, 3682#(<= 1 main_~n~0), 3683#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 3684#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3685#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 3686#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 3687#(and (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 3688#(and (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 6 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 3689#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (or (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)))))) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 3690#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (or (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1))) (= cstrncat_~d~0.offset 0)), 3691#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (or (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1))) (= cstrncat_~d~0.offset 0)), 3692#(or (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 3693#(or (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 3694#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 3695#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 3696#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 3697#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 3698#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 3699#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 3700#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:02:54,497 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:54,497 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 15:02:54,497 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 15:02:54,498 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=363, Unknown=0, NotChecked=0, Total=420 [2018-02-04 15:02:54,498 INFO L87 Difference]: Start difference. First operand 92 states and 106 transitions. Second operand 21 states. [2018-02-04 15:02:55,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:55,394 INFO L93 Difference]: Finished difference Result 121 states and 137 transitions. [2018-02-04 15:02:55,555 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 15:02:55,555 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 36 [2018-02-04 15:02:55,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:55,556 INFO L225 Difference]: With dead ends: 121 [2018-02-04 15:02:55,556 INFO L226 Difference]: Without dead ends: 120 [2018-02-04 15:02:55,556 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 334 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=205, Invalid=1201, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 15:02:55,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-02-04 15:02:55,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 95. [2018-02-04 15:02:55,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-02-04 15:02:55,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 110 transitions. [2018-02-04 15:02:55,558 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 110 transitions. Word has length 36 [2018-02-04 15:02:55,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:55,558 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 110 transitions. [2018-02-04 15:02:55,558 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 15:02:55,558 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 110 transitions. [2018-02-04 15:02:55,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 15:02:55,559 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:55,559 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:55,559 INFO L371 AbstractCegarLoop]: === Iteration 24 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:55,559 INFO L82 PathProgramCache]: Analyzing trace with hash -601444785, now seen corresponding path program 1 times [2018-02-04 15:02:55,560 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:55,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:55,567 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:55,896 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:55,896 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:55,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-04 15:02:55,897 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:55,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:55,897 INFO L182 omatonBuilderFactory]: Interpolants [3968#(and (or (<= (+ |cstrncat_#t~pre2| (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)), 3969#(<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)), 3970#(<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|)), 3971#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 3972#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 3973#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 3951#true, 3952#false, 3953#(<= 1 main_~n~0), 3954#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3955#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3956#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3957#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 3958#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 3959#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 3960#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 3961#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 3962#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 3963#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 3964#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) 1)) (= 0 cstrncat_~s~0.offset)), 3965#(and (<= 1 cstrncat_~n) (= |cstrncat_#t~post3.offset| 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset |cstrncat_#t~post3.offset|) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3966#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 3967#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset 1)))] [2018-02-04 15:02:55,897 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:55,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 15:02:55,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 15:02:55,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=438, Unknown=0, NotChecked=0, Total=506 [2018-02-04 15:02:55,898 INFO L87 Difference]: Start difference. First operand 95 states and 110 transitions. Second operand 23 states. [2018-02-04 15:02:56,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:56,413 INFO L93 Difference]: Finished difference Result 115 states and 129 transitions. [2018-02-04 15:02:56,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-04 15:02:56,413 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 38 [2018-02-04 15:02:56,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:56,413 INFO L225 Difference]: With dead ends: 115 [2018-02-04 15:02:56,413 INFO L226 Difference]: Without dead ends: 114 [2018-02-04 15:02:56,414 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 519 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=271, Invalid=1709, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 15:02:56,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-02-04 15:02:56,416 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 95. [2018-02-04 15:02:56,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 95 states. [2018-02-04 15:02:56,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 110 transitions. [2018-02-04 15:02:56,417 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 110 transitions. Word has length 38 [2018-02-04 15:02:56,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:56,417 INFO L432 AbstractCegarLoop]: Abstraction has 95 states and 110 transitions. [2018-02-04 15:02:56,417 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 15:02:56,417 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 110 transitions. [2018-02-04 15:02:56,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 15:02:56,418 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:56,418 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:56,418 INFO L371 AbstractCegarLoop]: === Iteration 25 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:56,418 INFO L82 PathProgramCache]: Analyzing trace with hash -438410885, now seen corresponding path program 4 times [2018-02-04 15:02:56,418 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:56,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:56,431 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:57,322 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:57,322 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:57,322 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-04 15:02:57,322 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:57,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:57,323 INFO L182 omatonBuilderFactory]: Interpolants [4228#true, 4229#false, 4230#(<= 1 main_~n~0), 4231#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 4232#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1)), 4233#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset)), 4234#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4235#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 4236#(and (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (or (<= 7 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1))))) (<= 6 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|))) (= 0 |cstrncat_#in~dst.offset|)), 4237#(and (= 0 cstrncat_~dst.offset) (or (and (<= 6 (select |#length| cstrncat_~dst.base)) (or (<= 7 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)))))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 4238#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (<= 6 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))))), 4239#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (<= 6 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (= cstrncat_~d~0.offset 0)), 4240#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 4241#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 4242#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 4243#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 4244#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 4245#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 4246#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 4247#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))), 4248#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 4249#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:02:57,323 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:57,323 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 15:02:57,323 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 15:02:57,323 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=400, Unknown=0, NotChecked=0, Total=462 [2018-02-04 15:02:57,324 INFO L87 Difference]: Start difference. First operand 95 states and 110 transitions. Second operand 22 states. [2018-02-04 15:02:57,998 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 105 DAG size of output 104 [2018-02-04 15:02:58,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:58,828 INFO L93 Difference]: Finished difference Result 120 states and 137 transitions. [2018-02-04 15:02:58,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-04 15:02:58,828 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 39 [2018-02-04 15:02:58,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:58,828 INFO L225 Difference]: With dead ends: 120 [2018-02-04 15:02:58,828 INFO L226 Difference]: Without dead ends: 119 [2018-02-04 15:02:58,829 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 291 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=230, Invalid=1330, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 15:02:58,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-04 15:02:58,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 98. [2018-02-04 15:02:58,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-02-04 15:02:58,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 114 transitions. [2018-02-04 15:02:58,830 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 114 transitions. Word has length 39 [2018-02-04 15:02:58,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:58,830 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 114 transitions. [2018-02-04 15:02:58,830 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 15:02:58,830 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 114 transitions. [2018-02-04 15:02:58,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-04 15:02:58,831 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:58,831 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:58,831 INFO L371 AbstractCegarLoop]: === Iteration 26 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:58,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1171788660, now seen corresponding path program 2 times [2018-02-04 15:02:58,831 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:58,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:58,838 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:59,045 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:02:59,045 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:59,045 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-04 15:02:59,045 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:59,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:59,046 INFO L182 omatonBuilderFactory]: Interpolants [4512#(and (<= (+ main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 4513#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))), 4514#(and (= 0 |cstrncat_#in~src.offset|) (<= (+ (select |#length| |cstrncat_#in~src.base|) 1) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~dst.offset|)), 4515#(and (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset) (<= (+ (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base))), 4516#(and (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 1) (select |#length| cstrncat_~d~0.base))), 4517#(and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset| 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (= cstrncat_~d~0.offset 0) (= |cstrncat_#t~post3.offset| 0)), 4518#(and (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 4519#(<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)), 4520#(<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)), 4521#(<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|)), 4522#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 4523#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 4524#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 4504#true, 4505#false, 4506#(<= 1 main_~n~0), 4507#(<= (+ main_~length2~0 1) main_~length1~0), 4508#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|)), 4509#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= (select |#valid| main_~nondetString1~0.base) 1)), 4510#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 4511#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length2~0 1) main_~length1~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)))] [2018-02-04 15:02:59,046 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:02:59,046 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 15:02:59,046 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 15:02:59,046 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=366, Unknown=0, NotChecked=0, Total=420 [2018-02-04 15:02:59,047 INFO L87 Difference]: Start difference. First operand 98 states and 114 transitions. Second operand 21 states. [2018-02-04 15:02:59,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:59,417 INFO L93 Difference]: Finished difference Result 123 states and 139 transitions. [2018-02-04 15:02:59,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 15:02:59,417 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 41 [2018-02-04 15:02:59,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:59,418 INFO L225 Difference]: With dead ends: 123 [2018-02-04 15:02:59,418 INFO L226 Difference]: Without dead ends: 121 [2018-02-04 15:02:59,418 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=172, Invalid=950, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 15:02:59,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-02-04 15:02:59,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 118. [2018-02-04 15:02:59,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-04 15:02:59,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 135 transitions. [2018-02-04 15:02:59,420 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 135 transitions. Word has length 41 [2018-02-04 15:02:59,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:59,420 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 135 transitions. [2018-02-04 15:02:59,420 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 15:02:59,420 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 135 transitions. [2018-02-04 15:02:59,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-02-04 15:02:59,421 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:59,421 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:59,421 INFO L371 AbstractCegarLoop]: === Iteration 27 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:02:59,421 INFO L82 PathProgramCache]: Analyzing trace with hash 669200065, now seen corresponding path program 2 times [2018-02-04 15:02:59,422 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:59,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:59,431 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:00,140 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:00,141 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:00,141 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-04 15:03:00,141 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:00,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:00,141 INFO L182 omatonBuilderFactory]: Interpolants [4800#(and (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ main_~length2~0 main_~nondetString1~0.offset) 1)) (<= 1 main_~n~0))) (= main_~nondetString1~0.offset 0)), 4801#(and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) 1)) (and (<= 1 main_~n~0) (or (<= (+ main_~n~0 3) (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (<= (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset) 1)))) (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 4802#(and (= 0 |cstrncat_#in~src.offset|) (or (and (or (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)) (<= (select |#length| |cstrncat_#in~src.base|) 1)) (<= 1 |cstrncat_#in~n|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1))) (= 0 |cstrncat_#in~dst.offset|)), 4803#(and (= 0 cstrncat_~dst.offset) (or (and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~src.base) 1) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~dst.base)))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1))) (= 0 cstrncat_~src.offset)), 4804#(and (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 1) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))))), 4805#(and (or (and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (or (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) 1))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 1 cstrncat_~d~0.offset))) (= 0 cstrncat_~s~0.offset)), 4806#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 1 cstrncat_~d~0.offset)) (and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (or (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 4807#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 1) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset) (<= 2 cstrncat_~d~0.offset)), 4808#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) cstrncat_~s~0.offset)) (= |cstrncat_#t~post3.offset| 0) (<= 2 cstrncat_~d~0.offset)), 4809#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~d~0.offset)), 4810#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= 3 cstrncat_~d~0.offset)), 4811#(and (<= 3 cstrncat_~d~0.offset) (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)), 4812#(and (<= 3 cstrncat_~d~0.offset) (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset))), 4813#(and (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (<= 3 cstrncat_~d~0.offset)), 4814#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 4815#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 4792#true, 4793#false, 4794#(<= 1 main_~n~0), 4795#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 4796#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 4797#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 4798#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 |main_#t~malloc12.offset|) (= main_~nondetString1~0.offset 0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 4799#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (or (< (+ main_~n~0 1) (+ main_~nondetString1~0.offset main_~length1~0)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString2~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0))] [2018-02-04 15:03:00,142 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:00,142 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 15:03:00,142 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 15:03:00,142 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=499, Unknown=0, NotChecked=0, Total=552 [2018-02-04 15:03:00,142 INFO L87 Difference]: Start difference. First operand 118 states and 135 transitions. Second operand 24 states. [2018-02-04 15:03:01,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:01,054 INFO L93 Difference]: Finished difference Result 145 states and 162 transitions. [2018-02-04 15:03:01,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 15:03:01,055 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 41 [2018-02-04 15:03:01,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:01,055 INFO L225 Difference]: With dead ends: 145 [2018-02-04 15:03:01,055 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 15:03:01,056 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=159, Invalid=1401, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 15:03:01,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 15:03:01,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 118. [2018-02-04 15:03:01,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-04 15:03:01,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 135 transitions. [2018-02-04 15:03:01,057 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 135 transitions. Word has length 41 [2018-02-04 15:03:01,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:01,058 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 135 transitions. [2018-02-04 15:03:01,058 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 15:03:01,058 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 135 transitions. [2018-02-04 15:03:01,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 15:03:01,058 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:01,058 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:01,058 INFO L371 AbstractCegarLoop]: === Iteration 28 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:01,058 INFO L82 PathProgramCache]: Analyzing trace with hash 1965711341, now seen corresponding path program 3 times [2018-02-04 15:03:01,058 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:01,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:01,066 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:01,231 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 15:03:01,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:01,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-04 15:03:01,232 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:01,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:01,232 INFO L182 omatonBuilderFactory]: Interpolants [5120#(and (= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (not (= cstrncat_~d~0.base cstrncat_~s~0.base))), 5121#(and (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (= |cstrncat_#t~post3.base| cstrncat_~s~0.base) (not (= cstrncat_~d~0.base |cstrncat_#t~post3.base|))), 5122#(= 0 (select (select (store |#memory_int| cstrncat_~d~0.base (store (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset |cstrncat_#t~mem5|)) cstrncat_~s~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))), 5123#(= 0 (select (select |#memory_int| cstrncat_~s~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))), 5124#(or (= 0 (select (select |#memory_int| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)) (and (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 5125#(or (= 0 |cstrncat_#t~mem5|) (and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base)))), 5126#(and (<= 1 cstrncat_~s~0.offset) (<= (+ cstrncat_~s~0.offset 1) (select |#length| cstrncat_~s~0.base))), 5127#(and (<= 1 |cstrncat_#t~post3.offset|) (<= (+ |cstrncat_#t~post3.offset| 1) (select |#length| |cstrncat_#t~post3.base|))), 5111#true, 5112#false, 5113#(= (select |#valid| |main_#t~malloc11.base|) 1), 5114#(= (select |#valid| main_~nondetString1~0.base) 1), 5115#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 |main_#t~malloc12.offset|) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 5116#(and (= main_~nondetString2~0.offset 0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~length2~0 (select |#length| main_~nondetString2~0.base))), 5117#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5118#(and (= 0 (select (select |#memory_int| |cstrncat_#in~src.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (not (= |cstrncat_#in~dst.base| |cstrncat_#in~src.base|))), 5119#(and (not (= cstrncat_~dst.base cstrncat_~src.base)) (= 0 (select (select |#memory_int| cstrncat_~src.base) (+ (select |#length| cstrncat_~src.base) (- 1)))))] [2018-02-04 15:03:01,232 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 15:03:01,232 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 15:03:01,232 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 15:03:01,233 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-02-04 15:03:01,233 INFO L87 Difference]: Start difference. First operand 118 states and 135 transitions. Second operand 17 states. [2018-02-04 15:03:01,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:01,509 INFO L93 Difference]: Finished difference Result 120 states and 134 transitions. [2018-02-04 15:03:01,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 15:03:01,509 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 42 [2018-02-04 15:03:01,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:01,510 INFO L225 Difference]: With dead ends: 120 [2018-02-04 15:03:01,510 INFO L226 Difference]: Without dead ends: 100 [2018-02-04 15:03:01,510 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=136, Invalid=676, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:03:01,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-02-04 15:03:01,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 69. [2018-02-04 15:03:01,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-02-04 15:03:01,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 78 transitions. [2018-02-04 15:03:01,512 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 78 transitions. Word has length 42 [2018-02-04 15:03:01,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:01,512 INFO L432 AbstractCegarLoop]: Abstraction has 69 states and 78 transitions. [2018-02-04 15:03:01,512 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 15:03:01,512 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 78 transitions. [2018-02-04 15:03:01,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 15:03:01,513 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:01,513 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:01,513 INFO L371 AbstractCegarLoop]: === Iteration 29 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:01,513 INFO L82 PathProgramCache]: Analyzing trace with hash 296873801, now seen corresponding path program 5 times [2018-02-04 15:03:01,514 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:01,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:01,523 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:02,128 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 84 DAG size of output 69 [2018-02-04 15:03:02,346 WARN L146 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 58 DAG size of output 45 [2018-02-04 15:03:02,837 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 74 DAG size of output 52 [2018-02-04 15:03:03,195 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:03,196 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:03,196 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-04 15:03:03,196 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:03,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:03,196 INFO L182 omatonBuilderFactory]: Interpolants [5341#true, 5342#false, 5343#(<= 1 main_~n~0), 5344#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 5345#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 5346#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 5347#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5348#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 5349#(and (or (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1))))) (and (or (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 7 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 |cstrncat_#in~dst.offset|)), 5350#(and (or (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~dst.base))) (<= 7 (select |#length| cstrncat_~dst.base))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))) (= 0 cstrncat_~dst.offset)), 5351#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))))) (= cstrncat_~d~0.offset 0)), 5352#(and (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))))) (= cstrncat_~d~0.offset 0)), 5353#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 5354#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 5355#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 5356#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 5357#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 5358#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 5359#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 5360#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 5361#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 5362#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 5363#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 5364#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 5365#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:03,196 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:03,196 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-04 15:03:03,197 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-04 15:03:03,197 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=515, Unknown=0, NotChecked=0, Total=600 [2018-02-04 15:03:03,197 INFO L87 Difference]: Start difference. First operand 69 states and 78 transitions. Second operand 25 states. [2018-02-04 15:03:04,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:04,978 INFO L93 Difference]: Finished difference Result 116 states and 127 transitions. [2018-02-04 15:03:04,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-04 15:03:04,979 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 42 [2018-02-04 15:03:04,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:04,979 INFO L225 Difference]: With dead ends: 116 [2018-02-04 15:03:04,979 INFO L226 Difference]: Without dead ends: 115 [2018-02-04 15:03:04,980 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 422 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=317, Invalid=1753, Unknown=0, NotChecked=0, Total=2070 [2018-02-04 15:03:04,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-02-04 15:03:04,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 72. [2018-02-04 15:03:04,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-02-04 15:03:04,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 82 transitions. [2018-02-04 15:03:04,981 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 82 transitions. Word has length 42 [2018-02-04 15:03:04,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:04,982 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 82 transitions. [2018-02-04 15:03:04,982 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-04 15:03:04,982 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 82 transitions. [2018-02-04 15:03:04,982 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-04 15:03:04,982 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:04,982 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:04,982 INFO L371 AbstractCegarLoop]: === Iteration 30 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:04,982 INFO L82 PathProgramCache]: Analyzing trace with hash -889231934, now seen corresponding path program 3 times [2018-02-04 15:03:04,983 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:04,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:04,988 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:05,326 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:05,326 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:05,326 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-04 15:03:05,327 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:05,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:05,327 INFO L182 omatonBuilderFactory]: Interpolants [5600#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 5601#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 5602#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 5603#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 5604#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))), 5605#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)), 5606#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 5607#(and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 5608#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 5609#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) 1)) (= 0 cstrncat_~s~0.offset)), 5610#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (= |cstrncat_#t~post3.offset| 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset |cstrncat_#t~post3.offset|) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5611#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5612#(and (<= 1 cstrncat_~n) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset 1)) (<= 2 cstrncat_~d~0.offset)), 5613#(and (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (and (<= 0 |cstrncat_#t~pre2|) (<= (+ |cstrncat_#t~pre2| (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)))) (<= 2 cstrncat_~d~0.offset)), 5614#(and (<= 2 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5615#(and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 2) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset)) (<= 2 cstrncat_~d~0.offset)), 5616#(and (<= 3 cstrncat_~d~0.offset) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) cstrncat_~s~0.offset))), 5617#(and (<= 3 cstrncat_~d~0.offset) (<= (+ (select |#length| |cstrncat_#t~post3.base|) cstrncat_~d~0.offset 1) (+ (select |#length| cstrncat_~d~0.base) |cstrncat_#t~post3.offset|))), 5618#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 5619#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 5596#true, 5597#false, 5598#(<= 1 main_~n~0), 5599#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))] [2018-02-04 15:03:05,327 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 1 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:05,327 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 15:03:05,327 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 15:03:05,327 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=490, Unknown=0, NotChecked=0, Total=552 [2018-02-04 15:03:05,328 INFO L87 Difference]: Start difference. First operand 72 states and 82 transitions. Second operand 24 states. [2018-02-04 15:03:05,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:05,926 INFO L93 Difference]: Finished difference Result 113 states and 123 transitions. [2018-02-04 15:03:05,926 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 15:03:05,926 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 44 [2018-02-04 15:03:05,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:05,926 INFO L225 Difference]: With dead ends: 113 [2018-02-04 15:03:05,927 INFO L226 Difference]: Without dead ends: 89 [2018-02-04 15:03:05,927 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 390 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=209, Invalid=1513, Unknown=0, NotChecked=0, Total=1722 [2018-02-04 15:03:05,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-02-04 15:03:05,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 72. [2018-02-04 15:03:05,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-02-04 15:03:05,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 81 transitions. [2018-02-04 15:03:05,928 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 81 transitions. Word has length 44 [2018-02-04 15:03:05,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:05,928 INFO L432 AbstractCegarLoop]: Abstraction has 72 states and 81 transitions. [2018-02-04 15:03:05,928 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 15:03:05,929 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 81 transitions. [2018-02-04 15:03:05,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-04 15:03:05,929 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:05,929 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:05,929 INFO L371 AbstractCegarLoop]: === Iteration 31 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:05,929 INFO L82 PathProgramCache]: Analyzing trace with hash -1391820529, now seen corresponding path program 4 times [2018-02-04 15:03:05,929 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:05,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:05,936 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:06,345 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:03:06,345 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:06,345 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-04 15:03:06,345 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:06,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:06,346 INFO L182 omatonBuilderFactory]: Interpolants [5856#(and (<= cstrncat_~n 2147483647) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~d~0.offset cstrncat_~n)))), 5857#(and (<= cstrncat_~n 2147483646) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)) (and (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)))), 5858#(and (<= cstrncat_~n 2147483646) (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)))), 5859#(and (or (<= 2 cstrncat_~n) (and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))) (<= cstrncat_~n 2147483646)), 5860#(and (<= cstrncat_~n 2147483646) (or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~n))), 5861#(and (or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= 1 |cstrncat_#t~pre2|)) (<= (div |cstrncat_#t~pre2| 4294967296) 0)), 5862#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 5841#true, 5842#false, 5843#(<= main_~n~0 2147483647), 5844#(and (<= main_~n~0 2147483647) (<= 1 main_~n~0)), 5845#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 5846#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 5847#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 5848#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5849#(and (<= main_~n~0 2147483647) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5850#(and (<= |cstrncat_#in~n| 2147483647) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)))) (<= 1 |cstrncat_#in~n|)), 5851#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 5852#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 5853#(and (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n))) (<= cstrncat_~n 2147483647)), 5854#(and (<= cstrncat_~n 2147483647) (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n)))), 5855#(and (or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n))) (<= cstrncat_~n 2147483647))] [2018-02-04 15:03:06,346 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:03:06,346 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 15:03:06,346 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 15:03:06,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=407, Unknown=0, NotChecked=0, Total=462 [2018-02-04 15:03:06,347 INFO L87 Difference]: Start difference. First operand 72 states and 81 transitions. Second operand 22 states. [2018-02-04 15:03:06,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:06,828 INFO L93 Difference]: Finished difference Result 105 states and 115 transitions. [2018-02-04 15:03:06,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 15:03:06,828 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 44 [2018-02-04 15:03:06,828 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:06,829 INFO L225 Difference]: With dead ends: 105 [2018-02-04 15:03:06,829 INFO L226 Difference]: Without dead ends: 104 [2018-02-04 15:03:06,829 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 226 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=169, Invalid=1021, Unknown=0, NotChecked=0, Total=1190 [2018-02-04 15:03:06,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-02-04 15:03:06,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 98. [2018-02-04 15:03:06,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-02-04 15:03:06,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 112 transitions. [2018-02-04 15:03:06,830 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 112 transitions. Word has length 44 [2018-02-04 15:03:06,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:06,831 INFO L432 AbstractCegarLoop]: Abstraction has 98 states and 112 transitions. [2018-02-04 15:03:06,831 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 15:03:06,831 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 112 transitions. [2018-02-04 15:03:06,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-02-04 15:03:06,831 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:06,831 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:06,831 INFO L371 AbstractCegarLoop]: === Iteration 32 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:06,831 INFO L82 PathProgramCache]: Analyzing trace with hash 829744827, now seen corresponding path program 6 times [2018-02-04 15:03:06,831 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:06,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:06,840 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:07,376 WARN L146 SmtUtils]: Spent 263ms on a formula simplification. DAG size of input: 99 DAG size of output 76 [2018-02-04 15:03:07,553 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 73 DAG size of output 51 [2018-02-04 15:03:07,698 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 73 DAG size of output 51 [2018-02-04 15:03:07,816 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 73 DAG size of output 51 [2018-02-04 15:03:07,940 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 76 DAG size of output 54 [2018-02-04 15:03:08,108 WARN L146 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 88 DAG size of output 58 [2018-02-04 15:03:08,310 WARN L146 SmtUtils]: Spent 152ms on a formula simplification. DAG size of input: 91 DAG size of output 61 [2018-02-04 15:03:08,436 WARN L146 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 61 DAG size of output 48 [2018-02-04 15:03:08,558 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 64 DAG size of output 51 [2018-02-04 15:03:08,887 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:08,887 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:08,887 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-02-04 15:03:08,887 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:08,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:08,888 INFO L182 omatonBuilderFactory]: Interpolants [6092#true, 6093#false, 6094#(<= 1 main_~n~0), 6095#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 6096#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 6097#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 6098#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 6099#(and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (or (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= main_~nondetString1~0.offset 0)), 6100#(and (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 9 (select |#length| |cstrncat_#in~dst.base|))) (<= 8 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 6101#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (or (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~dst.base))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 6102#(and (or (and (or (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (= cstrncat_~d~0.offset 0)), 6103#(and (or (and (or (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))))) (= cstrncat_~d~0.offset 0)), 6104#(and (<= 1 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))))), 6105#(and (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))) (<= 1 cstrncat_~d~0.offset)), 6106#(and (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))) (<= 2 cstrncat_~d~0.offset)), 6107#(and (<= 2 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 6108#(and (<= 3 cstrncat_~d~0.offset) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 6109#(and (<= 3 cstrncat_~d~0.offset) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 6110#(and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))) (<= 4 cstrncat_~d~0.offset)), 6111#(and (<= 4 cstrncat_~d~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))))), 6112#(and (<= 5 cstrncat_~d~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 6113#(and (<= 5 cstrncat_~d~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 6114#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 6 cstrncat_~d~0.offset))), 6115#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 6 cstrncat_~d~0.offset))), 6116#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 7 cstrncat_~d~0.offset)), 6117#(and (<= 8 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:08,888 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:08,888 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-02-04 15:03:08,888 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-02-04 15:03:08,888 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=590, Unknown=0, NotChecked=0, Total=650 [2018-02-04 15:03:08,888 INFO L87 Difference]: Start difference. First operand 98 states and 112 transitions. Second operand 26 states. [2018-02-04 15:03:10,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:10,641 INFO L93 Difference]: Finished difference Result 134 states and 152 transitions. [2018-02-04 15:03:10,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 15:03:10,641 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 45 [2018-02-04 15:03:10,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:10,642 INFO L225 Difference]: With dead ends: 134 [2018-02-04 15:03:10,642 INFO L226 Difference]: Without dead ends: 133 [2018-02-04 15:03:10,642 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 518 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=206, Invalid=1956, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 15:03:10,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-02-04 15:03:10,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 101. [2018-02-04 15:03:10,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 101 states. [2018-02-04 15:03:10,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 116 transitions. [2018-02-04 15:03:10,644 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 116 transitions. Word has length 45 [2018-02-04 15:03:10,644 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:10,644 INFO L432 AbstractCegarLoop]: Abstraction has 101 states and 116 transitions. [2018-02-04 15:03:10,644 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-02-04 15:03:10,644 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 116 transitions. [2018-02-04 15:03:10,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-04 15:03:10,644 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:10,644 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:10,644 INFO L371 AbstractCegarLoop]: === Iteration 33 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:10,644 INFO L82 PathProgramCache]: Analyzing trace with hash -1804660582, now seen corresponding path program 1 times [2018-02-04 15:03:10,645 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:10,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:10,651 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:11,163 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:11,163 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:11,163 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-04 15:03:11,164 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:11,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:11,164 INFO L182 omatonBuilderFactory]: Interpolants [6400#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6401#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0))) (or (and (= 0 |main_#t~malloc12.offset|) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))) (< (+ main_~n~0 2) main_~length1~0))), 6402#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (< (+ main_~n~0 2) main_~length1~0) (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6403#(or (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= main_~length2~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6404#(or (and (= 0 main_~nondetString2~0.offset) (<= (select |#length| main_~nondetString2~0.base) 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6405#(or (and (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)) (and (= 0 |cstrncat_#in~src.offset|) (<= (select |#length| |cstrncat_#in~src.base|) 2))), 6406#(or (and (<= (select |#length| cstrncat_~src.base) 2) (= 0 cstrncat_~src.offset)) (and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~dst.base)))), 6407#(or (and (<= 1 cstrncat_~n) (= cstrncat_~d~0.offset 0) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6408#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6409#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6410#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6411#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6412#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6413#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 6414#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (and (<= |cstrncat_#t~pre2| cstrncat_~n) (<= 0 |cstrncat_#t~pre2|) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6415#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)), 6416#(or (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6417#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 0 cstrncat_~d~0.offset))), 6418#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6419#(or (and (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6420#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6421#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 6422#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 6395#true, 6396#false, 6397#(or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)), 6398#(and (or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))), 6399#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0))))] [2018-02-04 15:03:11,164 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:11,164 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 15:03:11,164 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 15:03:11,164 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=675, Unknown=0, NotChecked=0, Total=756 [2018-02-04 15:03:11,164 INFO L87 Difference]: Start difference. First operand 101 states and 116 transitions. Second operand 28 states. [2018-02-04 15:03:12,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:12,172 INFO L93 Difference]: Finished difference Result 123 states and 137 transitions. [2018-02-04 15:03:12,172 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-04 15:03:12,173 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 46 [2018-02-04 15:03:12,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:12,173 INFO L225 Difference]: With dead ends: 123 [2018-02-04 15:03:12,173 INFO L226 Difference]: Without dead ends: 122 [2018-02-04 15:03:12,174 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 475 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=245, Invalid=1917, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 15:03:12,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-02-04 15:03:12,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 103. [2018-02-04 15:03:12,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-02-04 15:03:12,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 119 transitions. [2018-02-04 15:03:12,175 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 119 transitions. Word has length 46 [2018-02-04 15:03:12,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:12,175 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 119 transitions. [2018-02-04 15:03:12,175 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 15:03:12,175 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 119 transitions. [2018-02-04 15:03:12,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 15:03:12,176 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:12,176 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:12,176 INFO L371 AbstractCegarLoop]: === Iteration 34 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:12,176 INFO L82 PathProgramCache]: Analyzing trace with hash 98715828, now seen corresponding path program 5 times [2018-02-04 15:03:12,176 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:12,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:12,182 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:12,711 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:12,711 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:12,711 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-04 15:03:12,711 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:12,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:12,712 INFO L182 omatonBuilderFactory]: Interpolants [6687#true, 6688#false, 6689#(or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)), 6690#(and (or (<= main_~length1~0 (+ main_~n~0 2)) (<= 1 main_~n~0)) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))), 6691#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)))), 6692#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (or (< (+ main_~n~0 2) main_~length1~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6693#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0))) (or (and (= 0 |main_#t~malloc12.offset|) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))) (< (+ main_~n~0 2) main_~length1~0))), 6694#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (< (+ main_~n~0 2) main_~length1~0) (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))) (or (<= main_~length1~0 (+ main_~n~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0)))), 6695#(or (and (= 0 main_~nondetString2~0.offset) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= main_~length2~0 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6696#(or (and (= 0 main_~nondetString2~0.offset) (<= (select |#length| main_~nondetString2~0.base) 2)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~n~0) (<= (+ main_~n~0 3) (select |#length| main_~nondetString1~0.base)))), 6697#(or (and (<= (+ |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)) (and (= 0 |cstrncat_#in~src.offset|) (<= (select |#length| |cstrncat_#in~src.base|) 2))), 6698#(or (and (<= (select |#length| cstrncat_~src.base) 2) (= 0 cstrncat_~src.offset)) (and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~dst.base)))), 6699#(or (and (<= 1 cstrncat_~n) (= cstrncat_~d~0.offset 0) (<= (+ cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6700#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6701#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 6702#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))), 6703#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 6704#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 6705#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (and (<= |cstrncat_#t~pre2| cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)) (<= 0 |cstrncat_#t~pre2|))), 6706#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967296))) 4294967296)) 1) cstrncat_~n)), 6707#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967296))) 4294967296)) 1) cstrncat_~n)), 6708#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= (+ (* 4294967296 (div (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)), 6709#(or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))), 6710#(or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 6711#(or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 6712#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 6713#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 6714#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:12,712 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:12,712 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 15:03:12,713 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 15:03:12,713 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=675, Unknown=0, NotChecked=0, Total=756 [2018-02-04 15:03:12,713 INFO L87 Difference]: Start difference. First operand 103 states and 119 transitions. Second operand 28 states. [2018-02-04 15:03:13,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:13,807 INFO L93 Difference]: Finished difference Result 129 states and 143 transitions. [2018-02-04 15:03:13,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-04 15:03:13,807 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 47 [2018-02-04 15:03:13,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:13,808 INFO L225 Difference]: With dead ends: 129 [2018-02-04 15:03:13,808 INFO L226 Difference]: Without dead ends: 106 [2018-02-04 15:03:13,808 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 602 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=316, Invalid=2336, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 15:03:13,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-02-04 15:03:13,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 103. [2018-02-04 15:03:13,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 103 states. [2018-02-04 15:03:13,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 118 transitions. [2018-02-04 15:03:13,810 INFO L78 Accepts]: Start accepts. Automaton has 103 states and 118 transitions. Word has length 47 [2018-02-04 15:03:13,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:13,810 INFO L432 AbstractCegarLoop]: Abstraction has 103 states and 118 transitions. [2018-02-04 15:03:13,810 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 15:03:13,810 INFO L276 IsEmpty]: Start isEmpty. Operand 103 states and 118 transitions. [2018-02-04 15:03:13,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 15:03:13,810 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:13,810 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:13,810 INFO L371 AbstractCegarLoop]: === Iteration 35 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:13,810 INFO L82 PathProgramCache]: Analyzing trace with hash 1391354377, now seen corresponding path program 7 times [2018-02-04 15:03:13,811 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:13,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:13,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:14,553 WARN L146 SmtUtils]: Spent 359ms on a formula simplification. DAG size of input: 120 DAG size of output 85 [2018-02-04 15:03:14,799 WARN L146 SmtUtils]: Spent 202ms on a formula simplification. DAG size of input: 90 DAG size of output 57 [2018-02-04 15:03:14,992 WARN L146 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 90 DAG size of output 57 [2018-02-04 15:03:15,178 WARN L146 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 90 DAG size of output 57 [2018-02-04 15:03:15,364 WARN L146 SmtUtils]: Spent 164ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:03:15,594 WARN L146 SmtUtils]: Spent 202ms on a formula simplification. DAG size of input: 105 DAG size of output 63 [2018-02-04 15:03:15,846 WARN L146 SmtUtils]: Spent 218ms on a formula simplification. DAG size of input: 108 DAG size of output 66 [2018-02-04 15:03:15,999 WARN L146 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:03:16,148 WARN L146 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:03:16,723 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:16,723 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:16,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-04 15:03:16,723 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:16,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:16,724 INFO L182 omatonBuilderFactory]: Interpolants [6995#true, 6996#false, 6997#(<= 1 main_~n~0), 6998#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 6999#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 7000#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 7001#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7002#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7003#(and (or (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (or (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 7004#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))) (<= 8 (select |#length| cstrncat_~dst.base))) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (or (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 7005#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (or (<= 10 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))))), 7006#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (or (<= 10 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))))), 7007#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 7008#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7009#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7010#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7011#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7012#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7013#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7014#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7015#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7016#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7017#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7018#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7019#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 7020#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 7021#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 7022#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 7023#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:16,724 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:16,724 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 15:03:16,724 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 15:03:16,724 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=684, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:03:16,724 INFO L87 Difference]: Start difference. First operand 103 states and 118 transitions. Second operand 29 states. [2018-02-04 15:03:17,602 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 143 DAG size of output 140 [2018-02-04 15:03:17,859 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 141 DAG size of output 135 [2018-02-04 15:03:18,031 WARN L146 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 144 DAG size of output 141 [2018-02-04 15:03:18,205 WARN L146 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 135 DAG size of output 129 [2018-02-04 15:03:18,368 WARN L146 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 138 DAG size of output 135 [2018-02-04 15:03:18,549 WARN L146 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 128 DAG size of output 125 [2018-02-04 15:03:18,704 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 131 DAG size of output 128 [2018-02-04 15:03:18,845 WARN L146 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 122 DAG size of output 119 [2018-02-04 15:03:18,989 WARN L146 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 125 DAG size of output 122 [2018-02-04 15:03:19,254 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 118 DAG size of output 115 [2018-02-04 15:03:19,396 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 109 DAG size of output 106 [2018-02-04 15:03:19,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:19,543 INFO L93 Difference]: Finished difference Result 127 states and 144 transitions. [2018-02-04 15:03:19,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-04 15:03:19,543 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 48 [2018-02-04 15:03:19,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:19,543 INFO L225 Difference]: With dead ends: 127 [2018-02-04 15:03:19,543 INFO L226 Difference]: Without dead ends: 126 [2018-02-04 15:03:19,544 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 608 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=453, Invalid=2303, Unknown=0, NotChecked=0, Total=2756 [2018-02-04 15:03:19,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-02-04 15:03:19,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 106. [2018-02-04 15:03:19,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-04 15:03:19,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-02-04 15:03:19,546 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 48 [2018-02-04 15:03:19,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:19,546 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-02-04 15:03:19,546 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 15:03:19,546 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-02-04 15:03:19,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-02-04 15:03:19,547 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:19,547 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:19,547 INFO L371 AbstractCegarLoop]: === Iteration 36 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:19,547 INFO L82 PathProgramCache]: Analyzing trace with hash -1574633716, now seen corresponding path program 2 times [2018-02-04 15:03:19,548 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:19,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:19,559 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:20,925 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:20,925 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:20,925 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-04 15:03:20,925 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:20,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:20,926 INFO L182 omatonBuilderFactory]: Interpolants [7305#true, 7306#false, 7307#(<= 1 main_~n~0), 7308#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7309#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7310#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7311#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 7312#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7313#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 7314#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 7315#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 7316#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 7317#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 7318#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))), 7319#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7320#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7321#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7322#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7323#(and (<= 1 cstrncat_~n) (<= 0 cstrncat_~d~0.offset) (= 0 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7324#(and (<= 1 cstrncat_~n) (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (<= 0 cstrncat_~d~0.offset) (= |cstrncat_#t~post3.offset| 0) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7325#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (<= 0 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7326#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= 1 cstrncat_~d~0.offset)), 7327#(and (<= 1 cstrncat_~s~0.offset) (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7328#(and (<= 1 cstrncat_~s~0.offset) (<= 1 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n))), 7329#(and (<= 1 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)) (<= 2 cstrncat_~s~0.offset)), 7330#(and (<= 2 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= 2 cstrncat_~s~0.offset)), 7331#(and (<= 2 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base)))) (<= 2 cstrncat_~s~0.offset)), 7332#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~d~0.offset) (<= 2 cstrncat_~s~0.offset)), 7333#(and (or (< 2 (select |#length| |cstrncat_#t~post3.base|)) (<= 2 |cstrncat_#t~post3.offset|)) (or (<= (select |#length| |cstrncat_#t~post3.base|) 2) (and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))))), 7334#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:20,926 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:20,926 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-04 15:03:20,926 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-04 15:03:20,926 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=786, Unknown=0, NotChecked=0, Total=870 [2018-02-04 15:03:20,927 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 30 states. [2018-02-04 15:03:21,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:21,889 INFO L93 Difference]: Finished difference Result 126 states and 142 transitions. [2018-02-04 15:03:21,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 15:03:21,889 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 49 [2018-02-04 15:03:21,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:21,890 INFO L225 Difference]: With dead ends: 126 [2018-02-04 15:03:21,890 INFO L226 Difference]: Without dead ends: 125 [2018-02-04 15:03:21,891 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 594 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=277, Invalid=2173, Unknown=0, NotChecked=0, Total=2450 [2018-02-04 15:03:21,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-02-04 15:03:21,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 106. [2018-02-04 15:03:21,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-04 15:03:21,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 122 transitions. [2018-02-04 15:03:21,892 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 122 transitions. Word has length 49 [2018-02-04 15:03:21,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:21,892 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 122 transitions. [2018-02-04 15:03:21,892 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-04 15:03:21,893 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 122 transitions. [2018-02-04 15:03:21,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-04 15:03:21,893 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:21,893 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:21,893 INFO L371 AbstractCegarLoop]: === Iteration 37 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:21,893 INFO L82 PathProgramCache]: Analyzing trace with hash -1360385918, now seen corresponding path program 6 times [2018-02-04 15:03:21,893 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:21,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:21,903 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:22,477 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:22,477 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:22,477 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-04 15:03:22,478 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:22,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:22,478 INFO L182 omatonBuilderFactory]: Interpolants [7616#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 7617#(and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 |cstrncat_#in~src.offset|) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 7618#(and (<= 1 cstrncat_~n) (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 7619#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))), 7620#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))), 7621#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7622#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7623#(and (<= 1 cstrncat_~n) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= 0 cstrncat_~s~0.offset)), 7624#(and (<= 1 cstrncat_~n) (<= (+ |cstrncat_#t~post3.offset| 1) cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (= |cstrncat_#t~post3.offset| 0)), 7625#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))), 7626#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 7627#(and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|)), 7628#(and (<= 1 cstrncat_~s~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n))), 7629#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n)) (<= 2 cstrncat_~s~0.offset)), 7630#(and (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n)) (<= 0 cstrncat_~d~0.offset) (<= 2 cstrncat_~s~0.offset)), 7631#(and (<= 1 cstrncat_~d~0.offset) (or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) 2)) (<= 2 cstrncat_~s~0.offset)), 7632#(and (<= 1 cstrncat_~d~0.offset) (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) 2) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 2 cstrncat_~s~0.offset)), 7633#(and (<= 1 cstrncat_~d~0.offset) (or (<= (select |#length| cstrncat_~s~0.base) 2) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (<= 2 cstrncat_~s~0.offset)), 7634#(and (or (<= (select |#length| |cstrncat_#t~post3.base|) 2) (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)))) (or (< 2 (select |#length| |cstrncat_#t~post3.base|)) (<= 2 |cstrncat_#t~post3.offset|))), 7635#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 7636#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 7607#true, 7608#false, 7609#(<= 1 main_~n~0), 7610#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7611#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7612#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7613#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 7614#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 7615#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0))] [2018-02-04 15:03:22,478 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:22,478 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-04 15:03:22,478 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-04 15:03:22,479 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=785, Unknown=0, NotChecked=0, Total=870 [2018-02-04 15:03:22,479 INFO L87 Difference]: Start difference. First operand 106 states and 122 transitions. Second operand 30 states. [2018-02-04 15:03:23,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:23,483 INFO L93 Difference]: Finished difference Result 130 states and 145 transitions. [2018-02-04 15:03:23,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-04 15:03:23,484 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 50 [2018-02-04 15:03:23,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:23,484 INFO L225 Difference]: With dead ends: 130 [2018-02-04 15:03:23,484 INFO L226 Difference]: Without dead ends: 107 [2018-02-04 15:03:23,485 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 658 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=315, Invalid=2441, Unknown=0, NotChecked=0, Total=2756 [2018-02-04 15:03:23,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-02-04 15:03:23,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 106. [2018-02-04 15:03:23,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-02-04 15:03:23,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 121 transitions. [2018-02-04 15:03:23,486 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 121 transitions. Word has length 50 [2018-02-04 15:03:23,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:23,486 INFO L432 AbstractCegarLoop]: Abstraction has 106 states and 121 transitions. [2018-02-04 15:03:23,486 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-04 15:03:23,486 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 121 transitions. [2018-02-04 15:03:23,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-04 15:03:23,487 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:23,487 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:23,487 INFO L371 AbstractCegarLoop]: === Iteration 38 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:23,487 INFO L82 PathProgramCache]: Analyzing trace with hash -891126789, now seen corresponding path program 8 times [2018-02-04 15:03:23,488 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:23,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:23,499 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:24,777 WARN L146 SmtUtils]: Spent 339ms on a formula simplification. DAG size of input: 141 DAG size of output 93 [2018-02-04 15:03:25,080 WARN L146 SmtUtils]: Spent 266ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-04 15:03:25,341 WARN L146 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-04 15:03:25,601 WARN L146 SmtUtils]: Spent 237ms on a formula simplification. DAG size of input: 109 DAG size of output 63 [2018-02-04 15:03:25,927 WARN L146 SmtUtils]: Spent 300ms on a formula simplification. DAG size of input: 112 DAG size of output 66 [2018-02-04 15:03:26,237 WARN L146 SmtUtils]: Spent 280ms on a formula simplification. DAG size of input: 125 DAG size of output 70 [2018-02-04 15:03:26,537 WARN L146 SmtUtils]: Spent 266ms on a formula simplification. DAG size of input: 128 DAG size of output 73 [2018-02-04 15:03:26,737 WARN L146 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:03:26,955 WARN L146 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-04 15:03:27,101 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:03:27,267 WARN L146 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:03:27,865 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:27,865 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:27,865 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-04 15:03:27,866 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:27,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:27,867 INFO L182 omatonBuilderFactory]: Interpolants [7936#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7937#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7938#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7939#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7940#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7941#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7942#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 7943#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7944#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 7945#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 7946#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))), 7947#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 7948#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 7919#true, 7920#false, 7921#(<= 1 main_~n~0), 7922#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 7923#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 7924#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 7925#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7926#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 7927#(and (or (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (or (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 10 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 7928#(and (= 0 cstrncat_~dst.offset) (or (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (or (<= 11 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 7929#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 10 (select |#length| cstrncat_~d~0.base)) (or (<= 11 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))), 7930#(and (= cstrncat_~d~0.offset 0) (or (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 10 (select |#length| cstrncat_~d~0.base)) (or (<= 11 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))), 7931#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 7932#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7933#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7934#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 7935#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))] [2018-02-04 15:03:27,867 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:27,867 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-04 15:03:27,868 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-04 15:03:27,868 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=726, Unknown=0, NotChecked=0, Total=870 [2018-02-04 15:03:27,868 INFO L87 Difference]: Start difference. First operand 106 states and 121 transitions. Second operand 30 states. [2018-02-04 15:03:28,774 WARN L146 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 173 DAG size of output 172 [2018-02-04 15:03:28,964 WARN L146 SmtUtils]: Spent 152ms on a formula simplification. DAG size of input: 161 DAG size of output 158 [2018-02-04 15:03:29,164 WARN L146 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 167 DAG size of output 161 [2018-02-04 15:03:29,351 WARN L146 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 158 DAG size of output 152 [2018-02-04 15:03:29,543 WARN L146 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 164 DAG size of output 155 [2018-02-04 15:03:29,726 WARN L146 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 152 DAG size of output 146 [2018-02-04 15:03:29,914 WARN L146 SmtUtils]: Spent 162ms on a formula simplification. DAG size of input: 158 DAG size of output 149 [2018-02-04 15:03:30,135 WARN L146 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 146 DAG size of output 141 [2018-02-04 15:03:30,334 WARN L146 SmtUtils]: Spent 155ms on a formula simplification. DAG size of input: 152 DAG size of output 143 [2018-02-04 15:03:30,544 WARN L146 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 140 DAG size of output 134 [2018-02-04 15:03:30,739 WARN L146 SmtUtils]: Spent 146ms on a formula simplification. DAG size of input: 146 DAG size of output 137 [2018-02-04 15:03:30,903 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 134 DAG size of output 128 [2018-02-04 15:03:31,081 WARN L146 SmtUtils]: Spent 140ms on a formula simplification. DAG size of input: 140 DAG size of output 134 [2018-02-04 15:03:31,230 WARN L146 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 126 DAG size of output 123 [2018-02-04 15:03:31,388 WARN L146 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 131 DAG size of output 126 [2018-02-04 15:03:31,541 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 120 DAG size of output 117 [2018-02-04 15:03:31,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:31,694 INFO L93 Difference]: Finished difference Result 130 states and 147 transitions. [2018-02-04 15:03:31,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 15:03:31,694 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 51 [2018-02-04 15:03:31,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:31,695 INFO L225 Difference]: With dead ends: 130 [2018-02-04 15:03:31,695 INFO L226 Difference]: Without dead ends: 129 [2018-02-04 15:03:31,696 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 700 ImplicationChecksByTransitivity, 6.9s TimeCoverageRelationStatistics Valid=516, Invalid=2564, Unknown=0, NotChecked=0, Total=3080 [2018-02-04 15:03:31,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-02-04 15:03:31,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 109. [2018-02-04 15:03:31,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-04 15:03:31,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 125 transitions. [2018-02-04 15:03:31,698 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 125 transitions. Word has length 51 [2018-02-04 15:03:31,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:31,699 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 125 transitions. [2018-02-04 15:03:31,699 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-04 15:03:31,699 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 125 transitions. [2018-02-04 15:03:31,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-04 15:03:31,699 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:31,699 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:31,699 INFO L371 AbstractCegarLoop]: === Iteration 39 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:31,700 INFO L82 PathProgramCache]: Analyzing trace with hash 682894170, now seen corresponding path program 3 times [2018-02-04 15:03:31,700 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:31,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:31,719 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:32,587 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:32,587 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:32,587 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-04 15:03:32,587 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:32,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:32,588 INFO L182 omatonBuilderFactory]: Interpolants [8256#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8257#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8258#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8259#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 8260#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0))), 8261#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 8262#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 8263#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base)) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|))), 8264#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n)), 8265#(or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8266#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 0 cstrncat_~d~0.offset))), 8267#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8268#(or (and (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8269#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 8270#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 8271#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8240#true, 8241#false, 8242#(<= 1 main_~n~0), 8243#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8244#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8245#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8246#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 8247#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 8248#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8249#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (or (and (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 8250#(and (or (and (or (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1))))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))))) (= 0 |cstrncat_#in~src.offset|) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 8251#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (or (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 2) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1)))))) (= 0 cstrncat_~src.offset)), 8252#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))))), 8253#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (or (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))))), 8254#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 8255#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))))] [2018-02-04 15:03:32,588 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:32,588 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-04 15:03:32,588 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-04 15:03:32,588 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=881, Unknown=0, NotChecked=0, Total=992 [2018-02-04 15:03:32,589 INFO L87 Difference]: Start difference. First operand 109 states and 125 transitions. Second operand 32 states. [2018-02-04 15:03:33,128 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 113 DAG size of output 108 [2018-02-04 15:03:33,267 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 120 DAG size of output 117 [2018-02-04 15:03:34,027 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 52 DAG size of output 39 [2018-02-04 15:03:34,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:34,126 INFO L93 Difference]: Finished difference Result 129 states and 145 transitions. [2018-02-04 15:03:34,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-04 15:03:34,126 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 52 [2018-02-04 15:03:34,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:34,127 INFO L225 Difference]: With dead ends: 129 [2018-02-04 15:03:34,127 INFO L226 Difference]: Without dead ends: 128 [2018-02-04 15:03:34,128 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 719 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=353, Invalid=2403, Unknown=0, NotChecked=0, Total=2756 [2018-02-04 15:03:34,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-02-04 15:03:34,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 109. [2018-02-04 15:03:34,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-02-04 15:03:34,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 125 transitions. [2018-02-04 15:03:34,130 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 125 transitions. Word has length 52 [2018-02-04 15:03:34,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:34,130 INFO L432 AbstractCegarLoop]: Abstraction has 109 states and 125 transitions. [2018-02-04 15:03:34,130 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-04 15:03:34,131 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 125 transitions. [2018-02-04 15:03:34,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-04 15:03:34,131 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:34,131 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:34,131 INFO L371 AbstractCegarLoop]: === Iteration 40 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:34,131 INFO L82 PathProgramCache]: Analyzing trace with hash -96498188, now seen corresponding path program 7 times [2018-02-04 15:03:34,132 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:34,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:34,142 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:34,679 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 15:03:34,680 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:34,680 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-04 15:03:34,680 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:34,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:34,680 INFO L182 omatonBuilderFactory]: Interpolants [8576#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8552#true, 8553#false, 8554#(<= main_~n~0 2147483647), 8555#(and (<= main_~n~0 2147483647) (<= 1 main_~n~0)), 8556#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 8557#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 8558#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 8559#(and (<= main_~n~0 2147483647) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8560#(and (<= main_~n~0 2147483647) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 8561#(and (<= |cstrncat_#in~n| 2147483647) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)))) (<= 1 |cstrncat_#in~n|)), 8562#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 8563#(and (<= 1 cstrncat_~n) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= cstrncat_~n 2147483647)), 8564#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 2147483647) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)))), 8565#(and (<= 1 cstrncat_~n) (<= cstrncat_~n 2147483647) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (<= (select |#length| cstrncat_~d~0.base) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)))), 8566#(and (<= 1 cstrncat_~n) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483647)), 8567#(and (<= 1 cstrncat_~n) (or (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483647)), 8568#(and (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483646) (<= 0 |cstrncat_#t~pre2|)), 8569#(and (or (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967296))) 4294967296)) 1) cstrncat_~n) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~d~0.offset cstrncat_~n))) (<= cstrncat_~n 2147483646)), 8570#(and (<= cstrncat_~n 2147483646) (or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~n cstrncat_~d~0.offset)))), 8571#(and (or (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset 1) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~n cstrncat_~d~0.offset)) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= cstrncat_~n 2147483645)), 8572#(and (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~n cstrncat_~d~0.offset))) (<= cstrncat_~n 2147483645)), 8573#(and (or (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ cstrncat_~n cstrncat_~d~0.offset))) (<= cstrncat_~n 2147483645) (<= 0 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8574#(and (or (<= (+ (select |#length| cstrncat_~d~0.base) 2) (+ cstrncat_~d~0.offset cstrncat_~n)) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~n 2147483645) (<= 1 cstrncat_~d~0.offset) (<= cstrncat_~d~0.offset (select |#length| cstrncat_~d~0.base))), 8575#(and (<= 1 cstrncat_~d~0.offset) (<= (div |cstrncat_#t~pre2| 4294967296) 0) (or (<= (+ (select |#length| cstrncat_~d~0.base) 1) (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset)) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= cstrncat_~d~0.offset (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:34,681 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 39 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 15:03:34,681 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-04 15:03:34,681 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-04 15:03:34,681 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=539, Unknown=0, NotChecked=0, Total=600 [2018-02-04 15:03:34,681 INFO L87 Difference]: Start difference. First operand 109 states and 125 transitions. Second operand 25 states. [2018-02-04 15:03:35,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:35,395 INFO L93 Difference]: Finished difference Result 117 states and 127 transitions. [2018-02-04 15:03:35,395 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-04 15:03:35,395 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 53 [2018-02-04 15:03:35,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:35,396 INFO L225 Difference]: With dead ends: 117 [2018-02-04 15:03:35,396 INFO L226 Difference]: Without dead ends: 97 [2018-02-04 15:03:35,396 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 47 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 412 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=212, Invalid=1768, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 15:03:35,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-02-04 15:03:35,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 88. [2018-02-04 15:03:35,397 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-02-04 15:03:35,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 99 transitions. [2018-02-04 15:03:35,397 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 99 transitions. Word has length 53 [2018-02-04 15:03:35,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:35,398 INFO L432 AbstractCegarLoop]: Abstraction has 88 states and 99 transitions. [2018-02-04 15:03:35,398 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-04 15:03:35,398 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 99 transitions. [2018-02-04 15:03:35,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-04 15:03:35,398 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:35,398 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:35,398 INFO L371 AbstractCegarLoop]: === Iteration 41 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:35,398 INFO L82 PathProgramCache]: Analyzing trace with hash -365312823, now seen corresponding path program 9 times [2018-02-04 15:03:35,399 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:35,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:35,411 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:37,209 WARN L146 SmtUtils]: Spent 427ms on a formula simplification. DAG size of input: 168 DAG size of output 101 [2018-02-04 15:03:37,568 WARN L146 SmtUtils]: Spent 315ms on a formula simplification. DAG size of input: 130 DAG size of output 69 [2018-02-04 15:03:37,899 WARN L146 SmtUtils]: Spent 306ms on a formula simplification. DAG size of input: 130 DAG size of output 69 [2018-02-04 15:03:38,322 WARN L146 SmtUtils]: Spent 397ms on a formula simplification. DAG size of input: 130 DAG size of output 69 [2018-02-04 15:03:38,667 WARN L146 SmtUtils]: Spent 315ms on a formula simplification. DAG size of input: 133 DAG size of output 72 [2018-02-04 15:03:39,044 WARN L146 SmtUtils]: Spent 335ms on a formula simplification. DAG size of input: 147 DAG size of output 77 [2018-02-04 15:03:39,429 WARN L146 SmtUtils]: Spent 346ms on a formula simplification. DAG size of input: 150 DAG size of output 80 [2018-02-04 15:03:39,703 WARN L146 SmtUtils]: Spent 243ms on a formula simplification. DAG size of input: 113 DAG size of output 67 [2018-02-04 15:03:39,988 WARN L146 SmtUtils]: Spent 250ms on a formula simplification. DAG size of input: 116 DAG size of output 70 [2018-02-04 15:03:40,192 WARN L146 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:03:40,411 WARN L146 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-04 15:03:40,559 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:03:40,719 WARN L146 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:03:41,331 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:41,331 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:41,331 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-04 15:03:41,331 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:41,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:41,332 INFO L182 omatonBuilderFactory]: Interpolants [8832#(and (= cstrncat_~d~0.offset 0) (or (and (<= 11 (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 12 (select |#length| cstrncat_~d~0.base)))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 10 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))))), 8833#(and (or (and (<= 11 (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 12 (select |#length| cstrncat_~d~0.base)))) (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 10 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))))) (= cstrncat_~d~0.offset 0)), 8834#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base)))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 8835#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))))), 8836#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8837#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8838#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8839#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8840#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8841#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8842#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8843#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8844#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8845#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 8846#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 8847#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 8848#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 8849#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 8850#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 8851#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 8852#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 8853#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 8854#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 8822#true, 8823#false, 8824#(<= 1 main_~n~0), 8825#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 8826#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (= (select |#valid| main_~nondetString1~0.base) 1)), 8827#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset)), 8828#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 8829#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (<= 12 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ main_~nondetString1~0.offset (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)))))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 8830#(and (or (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 12 (select |#length| |cstrncat_#in~dst.base|)))) (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 8831#(and (= 0 cstrncat_~dst.offset) (or (and (<= 11 (select |#length| cstrncat_~dst.base)) (or (<= 12 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))))] [2018-02-04 15:03:41,332 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:41,332 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 15:03:41,332 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 15:03:41,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=183, Invalid=873, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 15:03:41,332 INFO L87 Difference]: Start difference. First operand 88 states and 99 transitions. Second operand 33 states. [2018-02-04 15:03:41,941 WARN L143 SmtUtils]: Spent 114ms on a formula simplification that was a NOOP. DAG size: 173 [2018-02-04 15:03:42,236 WARN L143 SmtUtils]: Spent 108ms on a formula simplification that was a NOOP. DAG size: 184 [2018-02-04 15:03:42,600 WARN L146 SmtUtils]: Spent 185ms on a formula simplification. DAG size of input: 177 DAG size of output 174 [2018-02-04 15:03:42,957 WARN L146 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 175 DAG size of output 169 [2018-02-04 15:03:43,179 WARN L146 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 178 DAG size of output 175 [2018-02-04 15:03:43,410 WARN L146 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 169 DAG size of output 163 [2018-02-04 15:03:43,611 WARN L146 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 172 DAG size of output 169 [2018-02-04 15:03:43,816 WARN L146 SmtUtils]: Spent 161ms on a formula simplification. DAG size of input: 163 DAG size of output 158 [2018-02-04 15:03:44,025 WARN L146 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 166 DAG size of output 163 [2018-02-04 15:03:44,222 WARN L146 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 157 DAG size of output 151 [2018-02-04 15:03:44,419 WARN L146 SmtUtils]: Spent 163ms on a formula simplification. DAG size of input: 160 DAG size of output 157 [2018-02-04 15:03:44,629 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 151 DAG size of output 145 [2018-02-04 15:03:44,838 WARN L146 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 154 DAG size of output 151 [2018-02-04 15:03:45,080 WARN L146 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 145 DAG size of output 139 [2018-02-04 15:03:45,290 WARN L146 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 148 DAG size of output 145 [2018-02-04 15:03:45,472 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 137 DAG size of output 134 [2018-02-04 15:03:45,668 WARN L146 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 140 DAG size of output 137 [2018-02-04 15:03:45,876 WARN L146 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 131 DAG size of output 128 [2018-02-04 15:03:46,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:46,064 INFO L93 Difference]: Finished difference Result 113 states and 126 transitions. [2018-02-04 15:03:46,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-04 15:03:46,064 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 54 [2018-02-04 15:03:46,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:46,065 INFO L225 Difference]: With dead ends: 113 [2018-02-04 15:03:46,065 INFO L226 Difference]: Without dead ends: 112 [2018-02-04 15:03:46,066 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 868 ImplicationChecksByTransitivity, 8.9s TimeCoverageRelationStatistics Valid=638, Invalid=3022, Unknown=0, NotChecked=0, Total=3660 [2018-02-04 15:03:46,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-02-04 15:03:46,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 91. [2018-02-04 15:03:46,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-02-04 15:03:46,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 103 transitions. [2018-02-04 15:03:46,068 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 103 transitions. Word has length 54 [2018-02-04 15:03:46,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:46,068 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 103 transitions. [2018-02-04 15:03:46,068 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 15:03:46,068 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 103 transitions. [2018-02-04 15:03:46,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-02-04 15:03:46,068 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:46,068 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:46,069 INFO L371 AbstractCegarLoop]: === Iteration 42 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:46,069 INFO L82 PathProgramCache]: Analyzing trace with hash -196742068, now seen corresponding path program 4 times [2018-02-04 15:03:46,069 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:46,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:46,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:47,611 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:47,612 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:47,612 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-04 15:03:47,612 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:47,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:47,612 INFO L182 omatonBuilderFactory]: Interpolants [9115#true, 9116#false, 9117#(<= 1 main_~n~0), 9118#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9119#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9120#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9121#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 9122#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9123#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base))) (and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 3) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 9124#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (or (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 3) (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 9125#(and (= 0 |cstrncat_#in~src.offset|) (or (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~dst.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)))))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 9126#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset) (or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)) (- 1)))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 3) (select |#length| cstrncat_~dst.base))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 2) (select |#length| cstrncat_~dst.base))))), 9127#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1))))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0)), 9128#(and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (or (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (or (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 9129#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))) (<= 2 cstrncat_~d~0.offset)), 9130#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))) (<= 2 cstrncat_~d~0.offset)), 9131#(and (<= 1 cstrncat_~n) (<= 3 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9132#(and (<= 1 cstrncat_~n) (<= 3 cstrncat_~d~0.offset) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9133#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 4 cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9134#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 4 cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9135#(or (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (<= 5 cstrncat_~d~0.offset) (<= (+ cstrncat_~n cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))), 9136#(or (and (<= 1 cstrncat_~n) (<= 6 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9137#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= 6 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 9138#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= 6 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 9139#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (+ (select |#length| cstrncat_~d~0.base) 1)) (<= 7 cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 9140#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base)) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|) (<= 7 cstrncat_~d~0.offset))), 9141#(or (and (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 7 cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 9142#(or (and (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 7 cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9143#(or (and (<= (+ (* 4294967296 (div (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n (+ cstrncat_~d~0.offset 4294967294))) 4294967296)) 1) cstrncat_~n) (<= 8 cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9144#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= 8 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base)))))), 9145#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= 8 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))), 9146#(or (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|) (and (<= 8 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))), 9147#(and (<= 8 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:03:47,612 INFO L134 CoverageAnalysis]: Checked inductivity of 75 backedges. 0 proven. 75 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:47,613 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 15:03:47,613 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 15:03:47,613 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=974, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 15:03:47,613 INFO L87 Difference]: Start difference. First operand 91 states and 103 transitions. Second operand 33 states. [2018-02-04 15:03:49,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:49,426 INFO L93 Difference]: Finished difference Result 108 states and 119 transitions. [2018-02-04 15:03:49,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 15:03:49,426 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 55 [2018-02-04 15:03:49,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:49,427 INFO L225 Difference]: With dead ends: 108 [2018-02-04 15:03:49,427 INFO L226 Difference]: Without dead ends: 92 [2018-02-04 15:03:49,427 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 708 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=251, Invalid=2829, Unknown=0, NotChecked=0, Total=3080 [2018-02-04 15:03:49,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2018-02-04 15:03:49,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 91. [2018-02-04 15:03:49,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-02-04 15:03:49,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 102 transitions. [2018-02-04 15:03:49,428 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 102 transitions. Word has length 55 [2018-02-04 15:03:49,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:49,429 INFO L432 AbstractCegarLoop]: Abstraction has 91 states and 102 transitions. [2018-02-04 15:03:49,429 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 15:03:49,429 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 102 transitions. [2018-02-04 15:03:49,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-04 15:03:49,429 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:49,429 INFO L351 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:49,429 INFO L371 AbstractCegarLoop]: === Iteration 43 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:03:49,429 INFO L82 PathProgramCache]: Analyzing trace with hash 412819771, now seen corresponding path program 10 times [2018-02-04 15:03:49,430 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:49,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:49,442 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:52,388 WARN L146 SmtUtils]: Spent 646ms on a formula simplification. DAG size of input: 197 DAG size of output 109 [2018-02-04 15:03:52,896 WARN L146 SmtUtils]: Spent 454ms on a formula simplification. DAG size of input: 153 DAG size of output 75 [2018-02-04 15:03:53,396 WARN L146 SmtUtils]: Spent 471ms on a formula simplification. DAG size of input: 153 DAG size of output 75 [2018-02-04 15:03:53,911 WARN L146 SmtUtils]: Spent 478ms on a formula simplification. DAG size of input: 153 DAG size of output 75 [2018-02-04 15:03:54,402 WARN L146 SmtUtils]: Spent 456ms on a formula simplification. DAG size of input: 156 DAG size of output 78 [2018-02-04 15:03:54,910 WARN L146 SmtUtils]: Spent 465ms on a formula simplification. DAG size of input: 171 DAG size of output 84 [2018-02-04 15:03:55,408 WARN L146 SmtUtils]: Spent 452ms on a formula simplification. DAG size of input: 174 DAG size of output 87 [2018-02-04 15:03:55,782 WARN L146 SmtUtils]: Spent 331ms on a formula simplification. DAG size of input: 135 DAG size of output 74 [2018-02-04 15:03:56,168 WARN L146 SmtUtils]: Spent 347ms on a formula simplification. DAG size of input: 138 DAG size of output 77 [2018-02-04 15:03:56,464 WARN L146 SmtUtils]: Spent 263ms on a formula simplification. DAG size of input: 113 DAG size of output 67 [2018-02-04 15:03:56,778 WARN L146 SmtUtils]: Spent 261ms on a formula simplification. DAG size of input: 116 DAG size of output 70 [2018-02-04 15:03:56,994 WARN L146 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:03:57,198 WARN L146 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-04 15:03:57,350 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:03:57,528 WARN L146 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:03:58,175 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:58,175 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:58,175 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-02-04 15:03:58,175 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:58,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:58,176 INFO L182 omatonBuilderFactory]: Interpolants [9408#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))))), 9409#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9410#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9411#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9412#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9413#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9414#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9415#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9416#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9417#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9418#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 9419#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 9420#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 0 cstrncat_~d~0.offset) (or (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))))), 9421#(and (<= 1 cstrncat_~d~0.offset) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 9422#(and (<= 1 cstrncat_~d~0.offset) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))))), 9423#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 2 cstrncat_~d~0.offset))), 9424#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 2 cstrncat_~d~0.offset))), 9425#(and (<= 3 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 9426#(and (<= 4 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 9393#true, 9394#false, 9395#(<= 1 main_~n~0), 9396#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0)), 9397#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= (select |#valid| main_~nondetString1~0.base) 1)), 9398#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2)))), 9399#(and (= 0 main_~nondetString1~0.offset) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 9400#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 13 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (<= 12 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 9401#(and (or (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (or (<= 13 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 12 (select |#length| |cstrncat_#in~dst.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 9402#(and (or (and (or (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~dst.base))) (<= 12 (select |#length| cstrncat_~dst.base))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))) (<= 11 (select |#length| cstrncat_~dst.base))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))) (= 0 cstrncat_~dst.offset)), 9403#(and (= cstrncat_~d~0.offset 0) (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~d~0.base))) (<= 12 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 11 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))))), 9404#(and (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~d~0.base))) (<= 12 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= 11 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base)))) (= cstrncat_~d~0.offset 0)), 9405#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 9406#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 9407#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base)))))] [2018-02-04 15:03:58,176 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:58,176 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-02-04 15:03:58,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-02-04 15:03:58,176 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=968, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 15:03:58,177 INFO L87 Difference]: Start difference. First operand 91 states and 102 transitions. Second operand 34 states. [2018-02-04 15:03:58,484 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 130 DAG size of output 129 [2018-02-04 15:03:58,772 WARN L143 SmtUtils]: Spent 113ms on a formula simplification that was a NOOP. DAG size: 189 [2018-02-04 15:03:58,938 WARN L143 SmtUtils]: Spent 117ms on a formula simplification that was a NOOP. DAG size: 192 [2018-02-04 15:03:59,246 WARN L146 SmtUtils]: Spent 246ms on a formula simplification. DAG size of input: 205 DAG size of output 202 [2018-02-04 15:03:59,534 WARN L146 SmtUtils]: Spent 255ms on a formula simplification. DAG size of input: 215 DAG size of output 204 [2018-02-04 15:03:59,848 WARN L146 SmtUtils]: Spent 255ms on a formula simplification. DAG size of input: 200 DAG size of output 191 [2018-02-04 15:04:00,172 WARN L146 SmtUtils]: Spent 287ms on a formula simplification. DAG size of input: 210 DAG size of output 195 [2018-02-04 15:04:00,477 WARN L146 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 196 DAG size of output 181 [2018-02-04 15:04:00,761 WARN L146 SmtUtils]: Spent 247ms on a formula simplification. DAG size of input: 206 DAG size of output 189 [2018-02-04 15:04:01,080 WARN L146 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 193 DAG size of output 175 [2018-02-04 15:04:01,459 WARN L146 SmtUtils]: Spent 343ms on a formula simplification. DAG size of input: 203 DAG size of output 185 [2018-02-04 15:04:01,852 WARN L146 SmtUtils]: Spent 311ms on a formula simplification. DAG size of input: 187 DAG size of output 167 [2018-02-04 15:04:02,123 WARN L146 SmtUtils]: Spent 231ms on a formula simplification. DAG size of input: 197 DAG size of output 176 [2018-02-04 15:04:02,479 WARN L146 SmtUtils]: Spent 297ms on a formula simplification. DAG size of input: 181 DAG size of output 163 [2018-02-04 15:04:02,839 WARN L146 SmtUtils]: Spent 271ms on a formula simplification. DAG size of input: 191 DAG size of output 173 [2018-02-04 15:04:03,116 WARN L146 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 175 DAG size of output 160 [2018-02-04 15:04:03,364 WARN L146 SmtUtils]: Spent 208ms on a formula simplification. DAG size of input: 185 DAG size of output 166 [2018-02-04 15:04:03,625 WARN L146 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 169 DAG size of output 157 [2018-02-04 15:04:03,880 WARN L146 SmtUtils]: Spent 203ms on a formula simplification. DAG size of input: 175 DAG size of output 160 [2018-02-04 15:04:04,132 WARN L146 SmtUtils]: Spent 166ms on a formula simplification. DAG size of input: 160 DAG size of output 150 [2018-02-04 15:04:04,377 WARN L146 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 163 DAG size of output 156 [2018-02-04 15:04:04,586 WARN L146 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 150 DAG size of output 145 [2018-02-04 15:04:04,847 WARN L146 SmtUtils]: Spent 205ms on a formula simplification. DAG size of input: 153 DAG size of output 148 [2018-02-04 15:04:05,058 WARN L146 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 142 DAG size of output 139 [2018-02-04 15:04:05,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:04:05,249 INFO L93 Difference]: Finished difference Result 116 states and 129 transitions. [2018-02-04 15:04:05,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 15:04:05,249 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 57 [2018-02-04 15:04:05,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:04:05,250 INFO L225 Difference]: With dead ends: 116 [2018-02-04 15:04:05,250 INFO L226 Difference]: Without dead ends: 115 [2018-02-04 15:04:05,250 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 978 ImplicationChecksByTransitivity, 13.1s TimeCoverageRelationStatistics Valid=630, Invalid=3402, Unknown=0, NotChecked=0, Total=4032 [2018-02-04 15:04:05,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-02-04 15:04:05,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 94. [2018-02-04 15:04:05,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-02-04 15:04:05,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 106 transitions. [2018-02-04 15:04:05,252 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 106 transitions. Word has length 57 [2018-02-04 15:04:05,252 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:04:05,252 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 106 transitions. [2018-02-04 15:04:05,252 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-02-04 15:04:05,252 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 106 transitions. [2018-02-04 15:04:05,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-04 15:04:05,252 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:04:05,253 INFO L351 BasicCegarLoop]: trace histogram [8, 8, 7, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:04:05,253 INFO L371 AbstractCegarLoop]: === Iteration 44 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:04:05,253 INFO L82 PathProgramCache]: Analyzing trace with hash -1844435430, now seen corresponding path program 5 times [2018-02-04 15:04:05,253 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:04:05,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:04:05,268 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:04:05,703 WARN L146 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 78 DAG size of output 62 [2018-02-04 15:04:05,866 WARN L146 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 72 DAG size of output 56 [2018-02-04 15:04:05,992 WARN L146 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 63 DAG size of output 50 [2018-02-04 15:04:06,142 WARN L146 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 63 DAG size of output 50 [2018-02-04 15:04:06,370 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 63 DAG size of output 50 [2018-02-04 15:04:06,985 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 0 proven. 96 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:06,986 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:04:06,986 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-04 15:04:06,986 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:04:06,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:06,986 INFO L182 omatonBuilderFactory]: Interpolants [9728#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967294))) 4294967296)) 1) cstrncat_~n)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9729#(or (and (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9730#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9731#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 9732#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 9697#true, 9698#false, 9699#(<= 1 main_~n~0), 9700#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9701#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9702#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9703#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 9704#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 9705#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))) (and (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 4) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 main_~length2~0 3) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base))))), 9706#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (and (or (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 4) (select |#length| main_~nondetString1~0.base))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 9707#(and (= 0 |cstrncat_#in~src.offset|) (or (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)) (- 1))))) (and (or (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 4) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)) (- 1)) (- 1))))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 9708#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 2) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 4) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 3) (select |#length| cstrncat_~dst.base)))) (= 0 cstrncat_~src.offset)), 9709#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0) (or (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1))))))), 9710#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1)))))) (= 0 cstrncat_~s~0.offset)), 9711#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base)))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9712#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base)))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9713#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9714#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9715#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9716#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 9717#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9718#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~n cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9719#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9720#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 9721#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 9722#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 9723#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 9724#(or (and (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 9725#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n)), 9726#(or (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 9727#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= (+ (* 4294967296 (div (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 0 cstrncat_~d~0.offset)))] [2018-02-04 15:04:06,986 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 0 proven. 96 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:06,987 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 15:04:06,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 15:04:06,987 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=144, Invalid=1116, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 15:04:06,987 INFO L87 Difference]: Start difference. First operand 94 states and 106 transitions. Second operand 36 states. [2018-02-04 15:04:07,573 WARN L146 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 159 DAG size of output 133 [2018-02-04 15:04:07,763 WARN L146 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 152 DAG size of output 147 [2018-02-04 15:04:07,977 WARN L146 SmtUtils]: Spent 191ms on a formula simplification. DAG size of input: 159 DAG size of output 156 [2018-02-04 15:04:08,140 WARN L146 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 132 DAG size of output 127 [2018-02-04 15:04:08,300 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 135 DAG size of output 133 [2018-02-04 15:04:08,450 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 118 DAG size of output 114 [2018-02-04 15:04:08,616 WARN L146 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 121 DAG size of output 120 [2018-02-04 15:04:11,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:04:11,798 INFO L93 Difference]: Finished difference Result 111 states and 122 transitions. [2018-02-04 15:04:11,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-04 15:04:11,798 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 58 [2018-02-04 15:04:11,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:04:11,798 INFO L225 Difference]: With dead ends: 111 [2018-02-04 15:04:11,798 INFO L226 Difference]: Without dead ends: 95 [2018-02-04 15:04:11,799 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=476, Invalid=3184, Unknown=0, NotChecked=0, Total=3660 [2018-02-04 15:04:11,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2018-02-04 15:04:11,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 94. [2018-02-04 15:04:11,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 94 states. [2018-02-04 15:04:11,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 105 transitions. [2018-02-04 15:04:11,800 INFO L78 Accepts]: Start accepts. Automaton has 94 states and 105 transitions. Word has length 58 [2018-02-04 15:04:11,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:04:11,800 INFO L432 AbstractCegarLoop]: Abstraction has 94 states and 105 transitions. [2018-02-04 15:04:11,800 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 15:04:11,800 INFO L276 IsEmpty]: Start isEmpty. Operand 94 states and 105 transitions. [2018-02-04 15:04:11,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-02-04 15:04:11,800 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:04:11,800 INFO L351 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:04:11,800 INFO L371 AbstractCegarLoop]: === Iteration 45 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:04:11,801 INFO L82 PathProgramCache]: Analyzing trace with hash 1822431113, now seen corresponding path program 11 times [2018-02-04 15:04:11,801 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:04:11,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:04:11,816 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:04:17,492 WARN L146 SmtUtils]: Spent 825ms on a formula simplification. DAG size of input: 228 DAG size of output 117 [2018-02-04 15:04:18,199 WARN L146 SmtUtils]: Spent 620ms on a formula simplification. DAG size of input: 178 DAG size of output 81 [2018-02-04 15:04:18,821 WARN L146 SmtUtils]: Spent 590ms on a formula simplification. DAG size of input: 178 DAG size of output 81 [2018-02-04 15:04:19,432 WARN L146 SmtUtils]: Spent 566ms on a formula simplification. DAG size of input: 178 DAG size of output 81 [2018-02-04 15:04:20,048 WARN L146 SmtUtils]: Spent 575ms on a formula simplification. DAG size of input: 181 DAG size of output 84 [2018-02-04 15:04:20,725 WARN L146 SmtUtils]: Spent 618ms on a formula simplification. DAG size of input: 197 DAG size of output 91 [2018-02-04 15:04:21,444 WARN L146 SmtUtils]: Spent 667ms on a formula simplification. DAG size of input: 200 DAG size of output 94 [2018-02-04 15:04:21,964 WARN L146 SmtUtils]: Spent 472ms on a formula simplification. DAG size of input: 159 DAG size of output 81 [2018-02-04 15:04:22,455 WARN L146 SmtUtils]: Spent 441ms on a formula simplification. DAG size of input: 162 DAG size of output 84 [2018-02-04 15:04:22,841 WARN L146 SmtUtils]: Spent 344ms on a formula simplification. DAG size of input: 135 DAG size of output 74 [2018-02-04 15:04:23,233 WARN L146 SmtUtils]: Spent 344ms on a formula simplification. DAG size of input: 138 DAG size of output 77 [2018-02-04 15:04:23,513 WARN L146 SmtUtils]: Spent 240ms on a formula simplification. DAG size of input: 113 DAG size of output 67 [2018-02-04 15:04:23,814 WARN L146 SmtUtils]: Spent 261ms on a formula simplification. DAG size of input: 116 DAG size of output 70 [2018-02-04 15:04:24,021 WARN L146 SmtUtils]: Spent 168ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:04:24,245 WARN L146 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-04 15:04:24,411 WARN L146 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:04:24,573 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:04:25,263 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:25,263 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:04:25,263 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-02-04 15:04:25,263 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:04:25,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:25,264 INFO L182 omatonBuilderFactory]: Interpolants [9988#true, 9989#false, 9990#(<= 1 main_~n~0), 9991#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (= 1 (select |#valid| |main_#t~malloc11.base|))), 9992#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (= 1 (select |#valid| main_~nondetString1~0.base))), 9993#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset)), 9994#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 9995#(and (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (or (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 12 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 13 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 14 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))))), 9996#(and (or (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1)))) (<= 12 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 13 (select |#length| |cstrncat_#in~dst.base|)) (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 14 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)))))) (= 0 |cstrncat_#in~dst.offset|)), 9997#(and (= 0 cstrncat_~dst.offset) (or (and (or (<= 14 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 13 (select |#length| cstrncat_~dst.base))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 12 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 9998#(and (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 14 (select |#length| cstrncat_~d~0.base))) (<= 13 (select |#length| cstrncat_~d~0.base))) (and (<= 12 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~d~0.base)))) (= cstrncat_~d~0.offset 0)), 9999#(and (= cstrncat_~d~0.offset 0) (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 14 (select |#length| cstrncat_~d~0.base))) (<= 13 (select |#length| cstrncat_~d~0.base))) (and (<= 12 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~d~0.base))))), 10000#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10001#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10002#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10003#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10004#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))))), 10005#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))))), 10006#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10007#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10008#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10009#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10010#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10011#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10012#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10013#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10014#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10015#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10016#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 10017#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 10018#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 10019#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 10020#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 10021#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 10022#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 10023#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 10024#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:04:25,264 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:25,264 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-02-04 15:04:25,265 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-02-04 15:04:25,265 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=250, Invalid=1082, Unknown=0, NotChecked=0, Total=1332 [2018-02-04 15:04:25,265 INFO L87 Difference]: Start difference. First operand 94 states and 105 transitions. Second operand 37 states. [2018-02-04 15:04:25,595 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 140 DAG size of output 139 [2018-02-04 15:04:25,932 WARN L143 SmtUtils]: Spent 122ms on a formula simplification that was a NOOP. DAG size: 205 [2018-02-04 15:04:26,130 WARN L143 SmtUtils]: Spent 140ms on a formula simplification that was a NOOP. DAG size: 208 [2018-02-04 15:04:26,331 WARN L143 SmtUtils]: Spent 135ms on a formula simplification that was a NOOP. DAG size: 218 [2018-02-04 15:04:26,500 WARN L143 SmtUtils]: Spent 136ms on a formula simplification that was a NOOP. DAG size: 220 [2018-02-04 15:04:26,837 WARN L146 SmtUtils]: Spent 277ms on a formula simplification. DAG size of input: 211 DAG size of output 208 [2018-02-04 15:04:27,056 WARN L143 SmtUtils]: Spent 172ms on a formula simplification that was a NOOP. DAG size: 215 [2018-02-04 15:04:27,381 WARN L146 SmtUtils]: Spent 253ms on a formula simplification. DAG size of input: 209 DAG size of output 203 [2018-02-04 15:04:27,664 WARN L146 SmtUtils]: Spent 245ms on a formula simplification. DAG size of input: 212 DAG size of output 209 [2018-02-04 15:04:27,952 WARN L146 SmtUtils]: Spent 229ms on a formula simplification. DAG size of input: 203 DAG size of output 197 [2018-02-04 15:04:28,220 WARN L146 SmtUtils]: Spent 231ms on a formula simplification. DAG size of input: 206 DAG size of output 203 [2018-02-04 15:04:28,474 WARN L146 SmtUtils]: Spent 208ms on a formula simplification. DAG size of input: 197 DAG size of output 192 [2018-02-04 15:04:28,732 WARN L146 SmtUtils]: Spent 223ms on a formula simplification. DAG size of input: 200 DAG size of output 197 [2018-02-04 15:04:28,994 WARN L146 SmtUtils]: Spent 211ms on a formula simplification. DAG size of input: 191 DAG size of output 185 [2018-02-04 15:04:29,247 WARN L146 SmtUtils]: Spent 216ms on a formula simplification. DAG size of input: 194 DAG size of output 191 [2018-02-04 15:04:29,488 WARN L146 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 185 DAG size of output 179 [2018-02-04 15:04:29,755 WARN L146 SmtUtils]: Spent 225ms on a formula simplification. DAG size of input: 188 DAG size of output 185 [2018-02-04 15:04:29,996 WARN L146 SmtUtils]: Spent 188ms on a formula simplification. DAG size of input: 179 DAG size of output 173 [2018-02-04 15:04:30,240 WARN L146 SmtUtils]: Spent 203ms on a formula simplification. DAG size of input: 182 DAG size of output 179 [2018-02-04 15:04:30,505 WARN L146 SmtUtils]: Spent 196ms on a formula simplification. DAG size of input: 172 DAG size of output 169 [2018-02-04 15:04:30,755 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 175 DAG size of output 172 [2018-02-04 15:04:31,050 WARN L146 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 166 DAG size of output 163 [2018-02-04 15:04:31,309 WARN L146 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 169 DAG size of output 166 [2018-02-04 15:04:31,548 WARN L146 SmtUtils]: Spent 182ms on a formula simplification. DAG size of input: 159 DAG size of output 156 [2018-02-04 15:04:31,789 WARN L146 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 162 DAG size of output 159 [2018-02-04 15:04:32,025 WARN L146 SmtUtils]: Spent 182ms on a formula simplification. DAG size of input: 153 DAG size of output 150 [2018-02-04 15:04:32,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:04:32,232 INFO L93 Difference]: Finished difference Result 119 states and 132 transitions. [2018-02-04 15:04:32,233 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 15:04:32,233 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 60 [2018-02-04 15:04:32,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:04:32,233 INFO L225 Difference]: With dead ends: 119 [2018-02-04 15:04:32,233 INFO L226 Difference]: Without dead ends: 118 [2018-02-04 15:04:32,234 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1169 ImplicationChecksByTransitivity, 15.1s TimeCoverageRelationStatistics Valid=859, Invalid=3833, Unknown=0, NotChecked=0, Total=4692 [2018-02-04 15:04:32,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-02-04 15:04:32,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 97. [2018-02-04 15:04:32,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-04 15:04:32,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 109 transitions. [2018-02-04 15:04:32,235 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 109 transitions. Word has length 60 [2018-02-04 15:04:32,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:04:32,235 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 109 transitions. [2018-02-04 15:04:32,235 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-02-04 15:04:32,235 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 109 transitions. [2018-02-04 15:04:32,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-04 15:04:32,235 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:04:32,236 INFO L351 BasicCegarLoop]: trace histogram [9, 9, 8, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:04:32,236 INFO L371 AbstractCegarLoop]: === Iteration 46 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:04:32,236 INFO L82 PathProgramCache]: Analyzing trace with hash -1096156788, now seen corresponding path program 6 times [2018-02-04 15:04:32,236 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:04:32,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:04:32,247 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:04:32,808 WARN L146 SmtUtils]: Spent 221ms on a formula simplification. DAG size of input: 96 DAG size of output 71 [2018-02-04 15:04:33,062 WARN L146 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 90 DAG size of output 65 [2018-02-04 15:04:33,254 WARN L146 SmtUtils]: Spent 180ms on a formula simplification. DAG size of input: 79 DAG size of output 57 [2018-02-04 15:04:33,425 WARN L146 SmtUtils]: Spent 158ms on a formula simplification. DAG size of input: 79 DAG size of output 57 [2018-02-04 15:04:33,603 WARN L146 SmtUtils]: Spent 161ms on a formula simplification. DAG size of input: 79 DAG size of output 57 [2018-02-04 15:04:33,780 WARN L146 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 79 DAG size of output 57 [2018-02-04 15:04:34,655 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:34,655 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:04:34,655 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37] total 37 [2018-02-04 15:04:34,655 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:04:34,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:34,656 INFO L182 omatonBuilderFactory]: Interpolants [10305#true, 10306#false, 10307#(<= 1 main_~n~0), 10308#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10309#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10310#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10311#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 10312#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10313#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))) (and (or (<= (+ main_~n~0 main_~length2~0 5) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 main_~length2~0 4) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 10314#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 4) (select |#length| main_~nondetString1~0.base)) (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 5) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base)))) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 10315#(and (= 0 |cstrncat_#in~src.offset|) (or (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)) (- 1)) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 5) (select |#length| |cstrncat_#in~dst.base|))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 4) (select |#length| |cstrncat_#in~dst.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 10316#(and (<= 1 cstrncat_~n) (= 0 cstrncat_~dst.offset) (or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 3) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 2) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 5) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 4) (select |#length| cstrncat_~dst.base)))) (= 0 cstrncat_~src.offset)), 10317#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0)), 10318#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 10319#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 6) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))))), 10320#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 6) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))))), 10321#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base)))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 10322#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base)))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 10323#(and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 10324#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 10325#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 10326#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)))), 10327#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10328#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10329#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10330#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10331#(or (and (<= 1 cstrncat_~n) (<= 0 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10332#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= 0 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 10333#(or (and (<= 1 cstrncat_~n) (<= 0 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 10334#(or (and (<= 1 cstrncat_~n) (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 10335#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base)) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|))), 10336#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n))), 10337#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= 1 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~d~0.offset (+ cstrncat_~n 4294967295))) 4294967296)) 1) cstrncat_~n))), 10338#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= 2 cstrncat_~d~0.offset) (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n 4294967294))) 4294967296)) 1) cstrncat_~n))), 10339#(or (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset) (and (<= 2 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base)))))), 10340#(or (and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 10341#(or (and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 10342#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base)))] [2018-02-04 15:04:34,656 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:04:34,656 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-02-04 15:04:34,656 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-02-04 15:04:34,656 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=1253, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 15:04:34,656 INFO L87 Difference]: Start difference. First operand 97 states and 109 transitions. Second operand 38 states. [2018-02-04 15:04:35,333 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 176 DAG size of output 152 [2018-02-04 15:04:35,604 WARN L146 SmtUtils]: Spent 216ms on a formula simplification. DAG size of input: 188 DAG size of output 169 [2018-02-04 15:04:35,899 WARN L146 SmtUtils]: Spent 258ms on a formula simplification. DAG size of input: 195 DAG size of output 178 [2018-02-04 15:04:36,123 WARN L146 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 156 DAG size of output 150 [2018-02-04 15:04:36,333 WARN L146 SmtUtils]: Spent 178ms on a formula simplification. DAG size of input: 159 DAG size of output 156 [2018-02-04 15:04:36,544 WARN L146 SmtUtils]: Spent 168ms on a formula simplification. DAG size of input: 143 DAG size of output 136 [2018-02-04 15:04:36,748 WARN L146 SmtUtils]: Spent 165ms on a formula simplification. DAG size of input: 146 DAG size of output 142 [2018-02-04 15:04:36,920 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 136 DAG size of output 129 [2018-02-04 15:04:37,095 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 139 DAG size of output 135 [2018-02-04 15:04:37,259 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 129 DAG size of output 124 [2018-02-04 15:04:37,420 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 132 DAG size of output 127 [2018-02-04 15:04:37,573 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 122 DAG size of output 118 [2018-02-04 15:04:37,746 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 118 DAG size of output 118 [2018-02-04 15:04:37,920 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 121 DAG size of output 121 [2018-02-04 15:04:38,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:04:38,455 INFO L93 Difference]: Finished difference Result 114 states and 125 transitions. [2018-02-04 15:04:38,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 15:04:38,455 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 61 [2018-02-04 15:04:38,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:04:38,456 INFO L225 Difference]: With dead ends: 114 [2018-02-04 15:04:38,456 INFO L226 Difference]: Without dead ends: 98 [2018-02-04 15:04:38,456 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1196 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=532, Invalid=3628, Unknown=0, NotChecked=0, Total=4160 [2018-02-04 15:04:38,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-02-04 15:04:38,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 97. [2018-02-04 15:04:38,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-04 15:04:38,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 108 transitions. [2018-02-04 15:04:38,457 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 108 transitions. Word has length 61 [2018-02-04 15:04:38,457 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:04:38,457 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 108 transitions. [2018-02-04 15:04:38,457 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-02-04 15:04:38,457 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 108 transitions. [2018-02-04 15:04:38,458 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 64 [2018-02-04 15:04:38,458 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:04:38,458 INFO L351 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:04:38,458 INFO L371 AbstractCegarLoop]: === Iteration 47 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:04:38,458 INFO L82 PathProgramCache]: Analyzing trace with hash -636299653, now seen corresponding path program 12 times [2018-02-04 15:04:38,458 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:04:38,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:04:38,469 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:04:50,162 WARN L146 SmtUtils]: Spent 944ms on a formula simplification. DAG size of input: 261 DAG size of output 125 [2018-02-04 15:04:50,997 WARN L146 SmtUtils]: Spent 763ms on a formula simplification. DAG size of input: 205 DAG size of output 87 [2018-02-04 15:04:51,792 WARN L146 SmtUtils]: Spent 756ms on a formula simplification. DAG size of input: 205 DAG size of output 87 [2018-02-04 15:04:52,568 WARN L146 SmtUtils]: Spent 730ms on a formula simplification. DAG size of input: 205 DAG size of output 87 [2018-02-04 15:04:53,358 WARN L146 SmtUtils]: Spent 744ms on a formula simplification. DAG size of input: 208 DAG size of output 90 [2018-02-04 15:04:54,204 WARN L146 SmtUtils]: Spent 795ms on a formula simplification. DAG size of input: 225 DAG size of output 98 [2018-02-04 15:04:55,085 WARN L146 SmtUtils]: Spent 813ms on a formula simplification. DAG size of input: 228 DAG size of output 101 [2018-02-04 15:04:55,728 WARN L146 SmtUtils]: Spent 594ms on a formula simplification. DAG size of input: 185 DAG size of output 88 [2018-02-04 15:04:56,371 WARN L146 SmtUtils]: Spent 592ms on a formula simplification. DAG size of input: 188 DAG size of output 91 [2018-02-04 15:04:56,882 WARN L146 SmtUtils]: Spent 467ms on a formula simplification. DAG size of input: 159 DAG size of output 81 [2018-02-04 15:04:57,380 WARN L146 SmtUtils]: Spent 452ms on a formula simplification. DAG size of input: 162 DAG size of output 84 [2018-02-04 15:04:57,747 WARN L146 SmtUtils]: Spent 324ms on a formula simplification. DAG size of input: 135 DAG size of output 74 [2018-02-04 15:04:58,140 WARN L146 SmtUtils]: Spent 345ms on a formula simplification. DAG size of input: 138 DAG size of output 77 [2018-02-04 15:04:58,453 WARN L146 SmtUtils]: Spent 264ms on a formula simplification. DAG size of input: 113 DAG size of output 67 [2018-02-04 15:04:58,752 WARN L146 SmtUtils]: Spent 254ms on a formula simplification. DAG size of input: 116 DAG size of output 70 [2018-02-04 15:04:58,965 WARN L146 SmtUtils]: Spent 173ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:04:59,192 WARN L146 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-04 15:04:59,346 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:04:59,536 WARN L146 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:04:59,676 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 59 DAG size of output 46 [2018-02-04 15:05:00,232 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:00,233 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:05:00,233 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37] total 37 [2018-02-04 15:05:00,233 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:05:00,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:00,234 INFO L182 omatonBuilderFactory]: Interpolants [10624#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10625#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10626#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))))), 10627#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))))), 10628#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1))))))), 10629#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1))))))), 10630#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10631#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10632#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10633#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10634#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10635#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10636#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10637#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 10638#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 10639#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 10640#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 10641#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 10642#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 10643#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset))), 10644#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base))), 10645#(and (<= 2 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 10608#true, 10609#false, 10610#(<= 1 main_~n~0), 10611#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (= 1 (select |#valid| |main_#t~malloc11.base|))), 10612#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (= 1 (select |#valid| main_~nondetString1~0.base))), 10613#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset)), 10614#(and (or (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 1)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~n~0 2))) (= 0 main_~nondetString1~0.offset) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 10615#(and (= 0 main_~nondetString1~0.offset) (or (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 13 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 12 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 14 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (<= 15 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))), 10616#(and (or (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (or (<= 15 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= 14 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1))))) (and (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 13 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 12 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 |cstrncat_#in~dst.offset|)), 10617#(and (= 0 cstrncat_~dst.offset) (or (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 14 (select |#length| cstrncat_~dst.base)) (or (<= 15 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (<= 12 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1)))) (<= 13 (select |#length| cstrncat_~dst.base))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~dst.base))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset)))), 10618#(and (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 13 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 15 (select |#length| cstrncat_~d~0.base))) (<= 14 (select |#length| cstrncat_~d~0.base))) (and (<= 12 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~d~0.base)))) (= cstrncat_~d~0.offset 0)), 10619#(and (= cstrncat_~d~0.offset 0) (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 13 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 15 (select |#length| cstrncat_~d~0.base))) (<= 14 (select |#length| cstrncat_~d~0.base))) (and (<= 12 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~d~0.base))))), 10620#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 14) (select |#length| cstrncat_~d~0.base)))) (and (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10621#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 14) (select |#length| cstrncat_~d~0.base)))) (and (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10622#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 10623#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))))] [2018-02-04 15:05:00,234 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:00,234 INFO L409 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-02-04 15:05:00,234 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-02-04 15:05:00,234 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=274, Invalid=1132, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 15:05:00,235 INFO L87 Difference]: Start difference. First operand 97 states and 108 transitions. Second operand 38 states. [2018-02-04 15:05:00,584 WARN L146 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 148 DAG size of output 147 [2018-02-04 15:05:00,925 WARN L143 SmtUtils]: Spent 133ms on a formula simplification that was a NOOP. DAG size: 221 [2018-02-04 15:05:01,123 WARN L143 SmtUtils]: Spent 141ms on a formula simplification that was a NOOP. DAG size: 224 [2018-02-04 15:05:01,346 WARN L143 SmtUtils]: Spent 153ms on a formula simplification that was a NOOP. DAG size: 235 [2018-02-04 15:05:01,721 WARN L146 SmtUtils]: Spent 342ms on a formula simplification. DAG size of input: 241 DAG size of output 240 [2018-02-04 15:05:02,193 WARN L146 SmtUtils]: Spent 371ms on a formula simplification. DAG size of input: 229 DAG size of output 226 [2018-02-04 15:05:02,492 WARN L146 SmtUtils]: Spent 267ms on a formula simplification. DAG size of input: 235 DAG size of output 229 [2018-02-04 15:05:02,910 WARN L146 SmtUtils]: Spent 320ms on a formula simplification. DAG size of input: 226 DAG size of output 220 [2018-02-04 15:05:03,260 WARN L146 SmtUtils]: Spent 311ms on a formula simplification. DAG size of input: 232 DAG size of output 223 [2018-02-04 15:05:03,570 WARN L146 SmtUtils]: Spent 251ms on a formula simplification. DAG size of input: 220 DAG size of output 214 [2018-02-04 15:05:03,874 WARN L146 SmtUtils]: Spent 271ms on a formula simplification. DAG size of input: 226 DAG size of output 217 [2018-02-04 15:05:04,171 WARN L146 SmtUtils]: Spent 246ms on a formula simplification. DAG size of input: 214 DAG size of output 209 [2018-02-04 15:05:04,473 WARN L146 SmtUtils]: Spent 265ms on a formula simplification. DAG size of input: 220 DAG size of output 211 [2018-02-04 15:05:04,755 WARN L146 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 208 DAG size of output 202 [2018-02-04 15:05:05,055 WARN L146 SmtUtils]: Spent 261ms on a formula simplification. DAG size of input: 214 DAG size of output 205 [2018-02-04 15:05:05,325 WARN L146 SmtUtils]: Spent 215ms on a formula simplification. DAG size of input: 202 DAG size of output 196 [2018-02-04 15:05:05,611 WARN L146 SmtUtils]: Spent 240ms on a formula simplification. DAG size of input: 208 DAG size of output 199 [2018-02-04 15:05:05,916 WARN L146 SmtUtils]: Spent 250ms on a formula simplification. DAG size of input: 196 DAG size of output 190 [2018-02-04 15:05:06,186 WARN L146 SmtUtils]: Spent 220ms on a formula simplification. DAG size of input: 202 DAG size of output 193 [2018-02-04 15:05:06,484 WARN L146 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 190 DAG size of output 185 [2018-02-04 15:05:06,774 WARN L146 SmtUtils]: Spent 236ms on a formula simplification. DAG size of input: 196 DAG size of output 187 [2018-02-04 15:05:07,055 WARN L146 SmtUtils]: Spent 208ms on a formula simplification. DAG size of input: 184 DAG size of output 178 [2018-02-04 15:05:07,345 WARN L146 SmtUtils]: Spent 223ms on a formula simplification. DAG size of input: 190 DAG size of output 181 [2018-02-04 15:05:07,655 WARN L146 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 178 DAG size of output 172 [2018-02-04 15:05:07,954 WARN L146 SmtUtils]: Spent 219ms on a formula simplification. DAG size of input: 184 DAG size of output 178 [2018-02-04 15:05:08,206 WARN L146 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 170 DAG size of output 167 [2018-02-04 15:05:08,454 WARN L146 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 175 DAG size of output 170 [2018-02-04 15:05:08,700 WARN L146 SmtUtils]: Spent 183ms on a formula simplification. DAG size of input: 164 DAG size of output 161 [2018-02-04 15:05:08,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:05:08,917 INFO L93 Difference]: Finished difference Result 122 states and 135 transitions. [2018-02-04 15:05:08,918 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-02-04 15:05:08,918 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 63 [2018-02-04 15:05:08,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:05:08,918 INFO L225 Difference]: With dead ends: 122 [2018-02-04 15:05:08,918 INFO L226 Difference]: Without dead ends: 121 [2018-02-04 15:05:08,919 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1297 ImplicationChecksByTransitivity, 19.3s TimeCoverageRelationStatistics Valid=946, Invalid=4166, Unknown=0, NotChecked=0, Total=5112 [2018-02-04 15:05:08,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-02-04 15:05:08,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 100. [2018-02-04 15:05:08,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-02-04 15:05:08,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 112 transitions. [2018-02-04 15:05:08,920 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 112 transitions. Word has length 63 [2018-02-04 15:05:08,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:05:08,920 INFO L432 AbstractCegarLoop]: Abstraction has 100 states and 112 transitions. [2018-02-04 15:05:08,920 INFO L433 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-02-04 15:05:08,920 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 112 transitions. [2018-02-04 15:05:08,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 15:05:08,920 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:05:08,921 INFO L351 BasicCegarLoop]: trace histogram [10, 10, 9, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:05:08,921 INFO L371 AbstractCegarLoop]: === Iteration 48 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:05:08,921 INFO L82 PathProgramCache]: Analyzing trace with hash -7399206, now seen corresponding path program 7 times [2018-02-04 15:05:08,921 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:05:08,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:05:08,938 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:05:09,496 WARN L146 SmtUtils]: Spent 218ms on a formula simplification. DAG size of input: 116 DAG size of output 80 [2018-02-04 15:05:09,721 WARN L146 SmtUtils]: Spent 208ms on a formula simplification. DAG size of input: 110 DAG size of output 74 [2018-02-04 15:05:09,954 WARN L146 SmtUtils]: Spent 217ms on a formula simplification. DAG size of input: 126 DAG size of output 66 [2018-02-04 15:05:10,178 WARN L146 SmtUtils]: Spent 207ms on a formula simplification. DAG size of input: 126 DAG size of output 66 [2018-02-04 15:05:10,377 WARN L146 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 126 DAG size of output 66 [2018-02-04 15:05:10,595 WARN L146 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 126 DAG size of output 66 [2018-02-04 15:05:10,734 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 104 DAG size of output 66 [2018-02-04 15:05:10,880 WARN L146 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 107 DAG size of output 69 [2018-02-04 15:05:11,724 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:11,724 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:05:11,724 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39] total 39 [2018-02-04 15:05:11,724 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:05:11,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:11,725 INFO L182 omatonBuilderFactory]: Interpolants [10944#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 3) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~n~0 main_~length2~0 1) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (or (<= (+ main_~n~0 main_~length2~0 6) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (<= (+ main_~n~0 main_~length2~0 5) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 main_~length2~0) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 4) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 main_~length2~0 2) (select |#length| main_~nondetString1~0.base)))) (= main_~nondetString1~0.offset 0)), 10945#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~n~0) (or (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 2) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 4) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base)) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 1) (select |#length| main_~nondetString1~0.base))) (and (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 3) (select |#length| main_~nondetString1~0.base))) (and (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 5) (select |#length| main_~nondetString1~0.base)) (or (<= (+ main_~n~0 (select |#length| main_~nondetString2~0.base) 6) (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (select |#length| main_~nondetString1~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))))) (= main_~nondetString1~0.offset 0)), 10946#(and (= 0 |cstrncat_#in~src.offset|) (or (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 2) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (- |cstrncat_#in~n|) (+ (select |#length| |cstrncat_#in~dst.base|) (- 1))) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (+ (select |#length| |cstrncat_#in~dst.base|) (- 1))) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 1) (select |#length| |cstrncat_#in~dst.base|))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (- |cstrncat_#in~n|) (select |#length| |cstrncat_#in~dst.base|)) (- 1))))) (and (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 4) (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (select |#length| |cstrncat_#in~src.base|) (- 1))))) (and (or (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (- |cstrncat_#in~n|) (+ (select |#length| |cstrncat_#in~dst.base|) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 6) (select |#length| |cstrncat_#in~dst.base|))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 5) (select |#length| |cstrncat_#in~dst.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (- |cstrncat_#in~n|) (+ (select |#length| |cstrncat_#in~dst.base|) (- 1))) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| |cstrncat_#in~src.base|) |cstrncat_#in~n| 3) (select |#length| |cstrncat_#in~dst.base|)))) (<= 1 |cstrncat_#in~n|) (= 0 |cstrncat_#in~dst.offset|)), 10947#(and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base)) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~dst.base)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 3) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~dst.base) (- 1))) (- 1)) (- 1)) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 2) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~dst.base) (- 1))) (- 1)) (- 1))))) (and (or (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 6) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~dst.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 5) (select |#length| cstrncat_~dst.base))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 1) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~dst.base) (- 1))) (- 1))))) (and (<= (+ cstrncat_~n (select |#length| cstrncat_~src.base) 4) (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (select |#length| cstrncat_~src.base) (- 1)))))) (= 0 cstrncat_~dst.offset) (= 0 cstrncat_~src.offset)), 10948#(and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (select |#length| cstrncat_~s~0.base) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 6) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1)) (- 1)))))) (= 0 cstrncat_~s~0.offset) (= cstrncat_~d~0.offset 0)), 10949#(and (<= 1 cstrncat_~n) (or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1)) (- 1))))) (and (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset (+ (select |#length| cstrncat_~s~0.base) (- 1))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ (select |#length| cstrncat_~s~0.base) cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1)))) (= 0 cstrncat_~s~0.offset)), 10950#(or (and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 6) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10951#(or (and (<= 1 cstrncat_~n) (or (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 6) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10952#(or (and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 6) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base)))) (<= 1 cstrncat_~n)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10953#(or (and (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset cstrncat_~n 6) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base)))) (<= 1 cstrncat_~n)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10954#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))))))), 10955#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset)) (and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 5) (select |#length| cstrncat_~d~0.base))))))), 10956#(or (and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10957#(or (and (<= 1 cstrncat_~n) (or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (select |#length| cstrncat_~d~0.base)) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (- cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) (- 1))) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 4) (select |#length| cstrncat_~d~0.base)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10958#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10959#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 1 cstrncat_~n) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 3) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10960#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10961#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 2) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10962#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n 1) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10963#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base))) (and (<= (select |#length| cstrncat_~s~0.base) 2) (= 0 cstrncat_~s~0.offset))), 10964#(or (and (<= (+ (select |#length| cstrncat_~s~0.base) |cstrncat_#t~post3.offset|) (+ cstrncat_~s~0.offset 1)) (= |cstrncat_#t~post3.offset| 0)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 10965#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (select |#length| cstrncat_~d~0.base)))), 10966#(or (and (<= 1 cstrncat_~n) (<= (+ cstrncat_~d~0.offset cstrncat_~n) (+ (select |#length| cstrncat_~d~0.base) 1))) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 10967#(or (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1)) (and (<= (+ cstrncat_~n cstrncat_~d~0.offset) (select |#length| cstrncat_~d~0.base)) (or (<= |cstrncat_#t~pre2| cstrncat_~n) (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)))) (<= 0 |cstrncat_#t~pre2|))), 10968#(or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) (+ cstrncat_~s~0.offset 1))), 10969#(or (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 10970#(or (and (<= (+ (* 4294967296 (div (+ cstrncat_~d~0.offset (+ cstrncat_~n (+ (- (select |#length| cstrncat_~d~0.base)) 4294967295))) 4294967296)) 1) cstrncat_~n) (<= 0 cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 10971#(or (and (<= (+ (* 4294967296 (div (+ (- (select |#length| cstrncat_~d~0.base)) (+ cstrncat_~n (+ cstrncat_~d~0.offset 4294967294))) 4294967296)) 1) cstrncat_~n) (<= 1 cstrncat_~d~0.offset)) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 10972#(or (and (<= 1 cstrncat_~d~0.offset) (or (<= |cstrncat_#t~pre2| (* 4294967296 (div |cstrncat_#t~pre2| 4294967296))) (<= (+ |cstrncat_#t~pre2| cstrncat_~d~0.offset) (+ (* 4294967296 (div |cstrncat_#t~pre2| 4294967296)) (select |#length| cstrncat_~d~0.base))))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 10973#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| cstrncat_~s~0.base) cstrncat_~s~0.offset)), 10974#(or (and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))) (<= (select |#length| |cstrncat_#t~post3.base|) |cstrncat_#t~post3.offset|)), 10975#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 10936#true, 10937#false, 10938#(<= 1 main_~n~0), 10939#(and (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10940#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= (select |#valid| |main_#t~malloc11.base|) 1) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10941#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0)), 10942#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc12.offset|) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0) (= main_~length2~0 (select |#length| |main_#t~malloc12.base|))), 10943#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~length2~0 (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0) (<= (+ main_~n~0 main_~length2~0) main_~length1~0))] [2018-02-04 15:05:11,725 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 0 proven. 147 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:11,725 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-02-04 15:05:11,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-02-04 15:05:11,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=189, Invalid=1371, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 15:05:11,725 INFO L87 Difference]: Start difference. First operand 100 states and 112 transitions. Second operand 40 states. [2018-02-04 15:05:12,460 WARN L146 SmtUtils]: Spent 181ms on a formula simplification. DAG size of input: 203 DAG size of output 177 [2018-02-04 15:05:12,739 WARN L146 SmtUtils]: Spent 221ms on a formula simplification. DAG size of input: 198 DAG size of output 192 [2018-02-04 15:05:13,041 WARN L146 SmtUtils]: Spent 270ms on a formula simplification. DAG size of input: 205 DAG size of output 201 [2018-02-04 15:05:13,272 WARN L146 SmtUtils]: Spent 183ms on a formula simplification. DAG size of input: 178 DAG size of output 172 [2018-02-04 15:05:13,495 WARN L146 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 181 DAG size of output 178 [2018-02-04 15:05:13,701 WARN L146 SmtUtils]: Spent 159ms on a formula simplification. DAG size of input: 165 DAG size of output 160 [2018-02-04 15:05:13,905 WARN L146 SmtUtils]: Spent 161ms on a formula simplification. DAG size of input: 168 DAG size of output 166 [2018-02-04 15:05:14,092 WARN L146 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 158 DAG size of output 153 [2018-02-04 15:05:14,283 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 161 DAG size of output 159 [2018-02-04 15:05:14,462 WARN L146 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 148 DAG size of output 147 [2018-02-04 15:05:14,645 WARN L146 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 151 DAG size of output 150 [2018-02-04 15:05:14,815 WARN L146 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 141 DAG size of output 139 [2018-02-04 15:05:14,993 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 144 DAG size of output 142 [2018-02-04 15:05:15,143 WARN L146 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 134 DAG size of output 133 [2018-02-04 15:05:15,303 WARN L146 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 134 DAG size of output 133 [2018-02-04 15:05:15,478 WARN L146 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 137 DAG size of output 136 [2018-02-04 15:05:16,047 WARN L146 SmtUtils]: Spent 250ms on a formula simplification. DAG size of input: 52 DAG size of output 39 [2018-02-04 15:05:16,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:05:16,187 INFO L93 Difference]: Finished difference Result 117 states and 128 transitions. [2018-02-04 15:05:16,187 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-02-04 15:05:16,187 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 64 [2018-02-04 15:05:16,187 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:05:16,188 INFO L225 Difference]: With dead ends: 117 [2018-02-04 15:05:16,188 INFO L226 Difference]: Without dead ends: 101 [2018-02-04 15:05:16,188 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1381 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=635, Invalid=4057, Unknown=0, NotChecked=0, Total=4692 [2018-02-04 15:05:16,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2018-02-04 15:05:16,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 100. [2018-02-04 15:05:16,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-02-04 15:05:16,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 111 transitions. [2018-02-04 15:05:16,190 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 111 transitions. Word has length 64 [2018-02-04 15:05:16,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:05:16,190 INFO L432 AbstractCegarLoop]: Abstraction has 100 states and 111 transitions. [2018-02-04 15:05:16,190 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-02-04 15:05:16,190 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 111 transitions. [2018-02-04 15:05:16,190 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-04 15:05:16,190 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:05:16,190 INFO L351 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:05:16,190 INFO L371 AbstractCegarLoop]: === Iteration 49 === [mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation, cstrncatErr7RequiresViolation, cstrncatErr5RequiresViolation, cstrncatErr0RequiresViolation, cstrncatErr3RequiresViolation, cstrncatErr1RequiresViolation, cstrncatErr2RequiresViolation, cstrncatErr6RequiresViolation, cstrncatErr4RequiresViolation]=== [2018-02-04 15:05:16,190 INFO L82 PathProgramCache]: Analyzing trace with hash 1982683721, now seen corresponding path program 13 times [2018-02-04 15:05:16,191 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:05:16,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:05:16,202 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:05:36,816 WARN L146 SmtUtils]: Spent 1279ms on a formula simplification. DAG size of input: 294 DAG size of output 132 [2018-02-04 15:05:37,810 WARN L146 SmtUtils]: Spent 923ms on a formula simplification. DAG size of input: 234 DAG size of output 93 [2018-02-04 15:05:38,790 WARN L146 SmtUtils]: Spent 944ms on a formula simplification. DAG size of input: 234 DAG size of output 93 [2018-02-04 15:05:39,728 WARN L146 SmtUtils]: Spent 896ms on a formula simplification. DAG size of input: 234 DAG size of output 93 [2018-02-04 15:05:40,685 WARN L146 SmtUtils]: Spent 912ms on a formula simplification. DAG size of input: 237 DAG size of output 96 [2018-02-04 15:05:41,736 WARN L146 SmtUtils]: Spent 996ms on a formula simplification. DAG size of input: 255 DAG size of output 105 [2018-02-04 15:05:42,840 WARN L146 SmtUtils]: Spent 1045ms on a formula simplification. DAG size of input: 258 DAG size of output 108 [2018-02-04 15:05:43,628 WARN L146 SmtUtils]: Spent 741ms on a formula simplification. DAG size of input: 213 DAG size of output 95 [2018-02-04 15:05:44,432 WARN L146 SmtUtils]: Spent 751ms on a formula simplification. DAG size of input: 216 DAG size of output 98 [2018-02-04 15:05:45,022 WARN L146 SmtUtils]: Spent 544ms on a formula simplification. DAG size of input: 185 DAG size of output 88 [2018-02-04 15:05:45,653 WARN L146 SmtUtils]: Spent 581ms on a formula simplification. DAG size of input: 188 DAG size of output 91 [2018-02-04 15:05:46,120 WARN L146 SmtUtils]: Spent 423ms on a formula simplification. DAG size of input: 159 DAG size of output 81 [2018-02-04 15:05:46,617 WARN L146 SmtUtils]: Spent 446ms on a formula simplification. DAG size of input: 162 DAG size of output 84 [2018-02-04 15:05:46,994 WARN L146 SmtUtils]: Spent 333ms on a formula simplification. DAG size of input: 135 DAG size of output 74 [2018-02-04 15:05:47,410 WARN L146 SmtUtils]: Spent 366ms on a formula simplification. DAG size of input: 138 DAG size of output 77 [2018-02-04 15:05:47,689 WARN L146 SmtUtils]: Spent 239ms on a formula simplification. DAG size of input: 113 DAG size of output 67 [2018-02-04 15:05:47,968 WARN L146 SmtUtils]: Spent 238ms on a formula simplification. DAG size of input: 116 DAG size of output 70 [2018-02-04 15:05:48,180 WARN L146 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 93 DAG size of output 60 [2018-02-04 15:05:48,403 WARN L146 SmtUtils]: Spent 184ms on a formula simplification. DAG size of input: 96 DAG size of output 63 [2018-02-04 15:05:48,561 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 75 DAG size of output 53 [2018-02-04 15:05:48,738 WARN L146 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 78 DAG size of output 56 [2018-02-04 15:05:49,421 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:49,422 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:05:49,422 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40] total 40 [2018-02-04 15:05:49,422 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:05:49,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:49,423 INFO L182 omatonBuilderFactory]: Interpolants [11264#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 15) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 14) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base)))), 11265#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 14) (select |#length| cstrncat_~d~0.base)))) (and (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 11266#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 14) (select |#length| cstrncat_~d~0.base)))) (and (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 11267#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 11268#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (or (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 11269#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 11270#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base)))), 11271#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11272#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base)))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11273#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11274#(or (and (or (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11275#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11276#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11277#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11278#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (or (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11279#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11280#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (or (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1))))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11281#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11282#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base)))), 11283#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 11284#(or (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 3) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))))), 11285#(or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 11286#(or (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))))), 11287#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))), 11288#(or (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)))), 11289#(<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)), 11290#(and (<= (+ cstrncat_~d~0.offset 2) (select |#length| cstrncat_~d~0.base)) (<= 0 cstrncat_~d~0.offset)), 11291#(and (<= 1 cstrncat_~d~0.offset) (<= (+ cstrncat_~d~0.offset 1) (select |#length| cstrncat_~d~0.base))), 11251#true, 11252#false, 11253#(<= 1 main_~n~0), 11254#(and (= main_~length1~0 (select |#length| |main_#t~malloc11.base|)) (= 0 |main_#t~malloc11.offset|) (<= 1 main_~n~0) (= 1 (select |#valid| |main_#t~malloc11.base|))), 11255#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= 1 (select |#valid| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 11256#(and (not (= main_~nondetString1~0.base |main_#t~malloc12.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (= main_~nondetString1~0.offset 0)), 11257#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~n~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 11258#(and (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (- main_~nondetString1~0.offset) 3)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 14 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 8 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 10 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 11 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 6 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 9 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 12 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1)))))) (<= 4 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 15 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (or (<= 16 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) 1)) (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))) (<= 5 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)))) (and (<= 13 (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base))) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~length2~0 main_~nondetString2~0.offset (- 1)) 0)) main_~nondetString1~0.base) (+ (- main_~n~0) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ main_~n~0 (+ (select |#length| main_~nondetString1~0.base) (- 1))) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (+ main_~nondetString1~0.offset (- 1)))))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 11259#(and (or (and (<= 9 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 15 (select |#length| |cstrncat_#in~dst.base|)) (or (<= 16 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))))) (and (<= 8 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrncat_#in~dst.base|))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) |cstrncat_#in~dst.offset|)) (and (<= 5 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1))))) (and (<= 11 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 12 (select |#length| |cstrncat_#in~dst.base|))) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) 1)) (and (<= 6 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ 3 (- 1)))) (<= 14 (select |#length| |cstrncat_#in~dst.base|))) (and (<= 10 (select |#length| |cstrncat_#in~dst.base|)) (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrncat_#in~dst.base|) (+ (+ (+ (+ (+ (select |#length| |cstrncat_#in~dst.base|) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrncat_#in~dst.base|)))) (= 0 |cstrncat_#in~dst.offset|)), 11260#(and (or (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~dst.base))) (and (<= 6 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 8 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 15 (select |#length| cstrncat_~dst.base)) (or (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 16 (select |#length| cstrncat_~dst.base)))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) 1)) (and (<= 4 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1))))) (and (<= 12 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1))))) (and (<= 10 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 9 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (<= 14 (select |#length| cstrncat_~dst.base)) (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~dst.base))) (and (= 0 (select (select |#memory_int| cstrncat_~dst.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~dst.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 7 (select |#length| cstrncat_~dst.base))) (= 0 (select (select |#memory_int| cstrncat_~dst.base) cstrncat_~dst.offset))) (= 0 cstrncat_~dst.offset)), 11261#(and (= cstrncat_~d~0.offset 0) (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 14 (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 16 (select |#length| cstrncat_~d~0.base))) (<= 15 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (and (<= 12 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~d~0.base))))), 11262#(and (or (and (<= 9 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 13 (select |#length| cstrncat_~d~0.base))) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) 1)) (and (<= 4 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 8 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ 3 (- 1)))) (<= 14 (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 16 (select |#length| cstrncat_~d~0.base))) (<= 15 (select |#length| cstrncat_~d~0.base))) (and (<= 5 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1))))) (and (<= 7 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 10 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset)) (= |cstrncat_#t~mem0| (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (<= 12 (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 6 (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= 11 (select |#length| cstrncat_~d~0.base)))) (= cstrncat_~d~0.offset 0)), 11263#(or (and (<= (+ cstrncat_~d~0.offset 3) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 7) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 12) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 4) (select |#length| cstrncat_~d~0.base))) (and (or (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 15) (select |#length| cstrncat_~d~0.base))) (<= (+ cstrncat_~d~0.offset 14) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 10) (select |#length| cstrncat_~d~0.base))) (and (= cstrncat_~d~0.offset 1) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) cstrncat_~d~0.offset))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 11) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 9) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 6) (select |#length| cstrncat_~d~0.base))) (and (<= (+ cstrncat_~d~0.offset 13) (select |#length| cstrncat_~d~0.base)) (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ cstrncat_~d~0.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 8) (select |#length| cstrncat_~d~0.base))) (and (= 0 (select (select |#memory_int| cstrncat_~d~0.base) (+ (+ (+ (+ (select |#length| cstrncat_~d~0.base) (- 1)) (- 1)) (- 1)) (- 1)))) (<= (+ cstrncat_~d~0.offset 5) (select |#length| cstrncat_~d~0.base))))] [2018-02-04 15:05:49,423 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:05:49,423 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-02-04 15:05:49,423 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-02-04 15:05:49,423 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=332, Invalid=1308, Unknown=0, NotChecked=0, Total=1640 [2018-02-04 15:05:49,423 INFO L87 Difference]: Start difference. First operand 100 states and 111 transitions. Second operand 41 states. [2018-02-04 15:05:50,057 WARN L143 SmtUtils]: Spent 149ms on a formula simplification that was a NOOP. DAG size: 237 [2018-02-04 15:05:50,267 WARN L143 SmtUtils]: Spent 155ms on a formula simplification that was a NOOP. DAG size: 240 [2018-02-04 15:05:50,491 WARN L143 SmtUtils]: Spent 163ms on a formula simplification that was a NOOP. DAG size: 252 [2018-02-04 15:05:50,675 WARN L143 SmtUtils]: Spent 159ms on a formula simplification that was a NOOP. DAG size: 254 [2018-02-04 15:05:51,044 WARN L146 SmtUtils]: Spent 298ms on a formula simplification. DAG size of input: 245 DAG size of output 242 Received shutdown request... [2018-02-04 15:05:51,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 15:05:51,068 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 15:05:51,072 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 15:05:51,072 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 03:05:51 BoogieIcfgContainer [2018-02-04 15:05:51,072 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 15:05:51,072 INFO L168 Benchmark]: Toolchain (without parser) took 185513.12 ms. Allocated memory was 402.7 MB in the beginning and 904.4 MB in the end (delta: 501.7 MB). Free memory was 359.5 MB in the beginning and 632.6 MB in the end (delta: -273.1 MB). Peak memory consumption was 228.6 MB. Max. memory is 5.3 GB. [2018-02-04 15:05:51,073 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 402.7 MB. Free memory is still 366.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 15:05:51,073 INFO L168 Benchmark]: CACSL2BoogieTranslator took 149.50 ms. Allocated memory is still 402.7 MB. Free memory was 359.5 MB in the beginning and 349.0 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-02-04 15:05:51,074 INFO L168 Benchmark]: Boogie Preprocessor took 27.17 ms. Allocated memory is still 402.7 MB. Free memory was 349.0 MB in the beginning and 347.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-04 15:05:51,074 INFO L168 Benchmark]: RCFGBuilder took 187.85 ms. Allocated memory is still 402.7 MB. Free memory was 347.6 MB in the beginning and 327.0 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 5.3 GB. [2018-02-04 15:05:51,074 INFO L168 Benchmark]: TraceAbstraction took 185146.18 ms. Allocated memory was 402.7 MB in the beginning and 904.4 MB in the end (delta: 501.7 MB). Free memory was 325.7 MB in the beginning and 632.6 MB in the end (delta: -307.0 MB). Peak memory consumption was 194.8 MB. Max. memory is 5.3 GB. [2018-02-04 15:05:51,076 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 402.7 MB. Free memory is still 366.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 149.50 ms. Allocated memory is still 402.7 MB. Free memory was 359.5 MB in the beginning and 349.0 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 27.17 ms. Allocated memory is still 402.7 MB. Free memory was 349.0 MB in the beginning and 347.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 187.85 ms. Allocated memory is still 402.7 MB. Free memory was 347.6 MB in the beginning and 327.0 MB in the end (delta: 20.7 MB). Peak memory consumption was 20.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 185146.18 ms. Allocated memory was 402.7 MB in the beginning and 904.4 MB in the end (delta: 501.7 MB). Free memory was 325.7 MB in the beginning and 632.6 MB in the end (delta: -307.0 MB). Peak memory consumption was 194.8 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 574). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 573). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 574). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 573). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 557]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 557). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 553). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 546). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 546). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 553). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 549). Cancelled while BasicCegarLoop was constructing difference of abstraction (100states) and interpolant automaton (currently 15 states, 41 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 51 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 54 locations, 13 error locations. TIMEOUT Result, 185.1s OverallTime, 49 OverallIterations, 16 TraceHistogramMax, 70.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1416 SDtfs, 4553 SDslu, 11184 SDs, 0 SdLazy, 18130 SolverSat, 1601 SolverUnsat, 1 SolverUnknown, 0 SolverNotchecked, 11.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1711 GetRequests, 61 SyntacticMatches, 19 SemanticMatches, 1630 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18376 ImplicationChecksByTransitivity, 128.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=118occurred in iteration=26, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 19/2770 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 48 MinimizatonAttempts, 577 StatesRemovedByMinimization, 41 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 112.9s InterpolantComputationTime, 1888 NumberOfCodeBlocks, 1888 NumberOfCodeBlocksAsserted, 49 NumberOfCheckSat, 1839 ConstructedInterpolants, 0 QuantifiedInterpolants, 4275509 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 49 InterpolantComputations, 13 PerfectInterpolantSequences, 19/2770 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_15-05-51-083.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrncat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_15-05-51-083.csv Completed graceful shutdown